config.ini revision 9265
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=TimingSimpleCPU 33children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload 34checker=Null 35clock=500 36cpu_id=0 37defer_registration=false 38do_checkpoint_insts=true 39do_quiesce=true 40do_statistics_insts=true 41dtb=system.cpu.dtb 42function_trace=false 43function_trace_start=0 44interrupts=system.cpu.interrupts 45itb=system.cpu.itb 46max_insts_all_threads=0 47max_insts_any_thread=0 48max_loads_all_threads=0 49max_loads_any_thread=0 50numThreads=1 51profile=0 52progress_interval=0 53system=system 54tracer=system.cpu.tracer 55workload=system.cpu.workload 56dcache_port=system.cpu.dcache.cpu_side 57icache_port=system.cpu.icache.cpu_side 58 59[system.cpu.dcache] 60type=BaseCache 61addr_ranges=0:18446744073709551615 62assoc=2 63block_size=64 64clock=1 65forward_snoops=true 66hash_delay=1 67hit_latency=1000 68is_top_level=true 69max_miss_count=0 70mshrs=10 71prefetch_on_access=false 72prefetcher=Null 73prioritizeRequests=false 74repl=Null 75response_latency=1000 76size=262144 77subblock_size=0 78system=system 79tgts_per_mshr=5 80trace_addr=0 81two_queue=false 82write_buffers=8 83cpu_side=system.cpu.dcache_port 84mem_side=system.cpu.toL2Bus.slave[1] 85 86[system.cpu.dtb] 87type=ArmTLB 88children=walker 89size=64 90walker=system.cpu.dtb.walker 91 92[system.cpu.dtb.walker] 93type=ArmTableWalker 94clock=1 95num_squash_per_cycle=2 96sys=system 97port=system.cpu.toL2Bus.slave[3] 98 99[system.cpu.icache] 100type=BaseCache 101addr_ranges=0:18446744073709551615 102assoc=2 103block_size=64 104clock=1 105forward_snoops=true 106hash_delay=1 107hit_latency=1000 108is_top_level=true 109max_miss_count=0 110mshrs=10 111prefetch_on_access=false 112prefetcher=Null 113prioritizeRequests=false 114repl=Null 115response_latency=1000 116size=131072 117subblock_size=0 118system=system 119tgts_per_mshr=5 120trace_addr=0 121two_queue=false 122write_buffers=8 123cpu_side=system.cpu.icache_port 124mem_side=system.cpu.toL2Bus.slave[0] 125 126[system.cpu.interrupts] 127type=ArmInterrupts 128 129[system.cpu.itb] 130type=ArmTLB 131children=walker 132size=64 133walker=system.cpu.itb.walker 134 135[system.cpu.itb.walker] 136type=ArmTableWalker 137clock=1 138num_squash_per_cycle=2 139sys=system 140port=system.cpu.toL2Bus.slave[2] 141 142[system.cpu.l2cache] 143type=BaseCache 144addr_ranges=0:18446744073709551615 145assoc=2 146block_size=64 147clock=1 148forward_snoops=true 149hash_delay=1 150hit_latency=10000 151is_top_level=false 152max_miss_count=0 153mshrs=10 154prefetch_on_access=false 155prefetcher=Null 156prioritizeRequests=false 157repl=Null 158response_latency=10000 159size=2097152 160subblock_size=0 161system=system 162tgts_per_mshr=5 163trace_addr=0 164two_queue=false 165write_buffers=8 166cpu_side=system.cpu.toL2Bus.master[0] 167mem_side=system.membus.slave[1] 168 169[system.cpu.toL2Bus] 170type=CoherentBus 171block_size=64 172clock=1000 173header_cycles=1 174use_default_range=false 175width=8 176master=system.cpu.l2cache.cpu_side 177slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 178 179[system.cpu.tracer] 180type=ExeTracer 181 182[system.cpu.workload] 183type=LiveProcess 184cmd=twolf smred 185cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing 186egid=100 187env= 188errout=cerr 189euid=100 190executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf 191gid=100 192input=cin 193max_stack_size=67108864 194output=cout 195pid=100 196ppid=99 197simpoint=0 198system=system 199uid=100 200 201[system.membus] 202type=CoherentBus 203block_size=64 204clock=1000 205header_cycles=1 206use_default_range=false 207width=8 208master=system.physmem.port 209slave=system.system_port system.cpu.l2cache.mem_side 210 211[system.physmem] 212type=SimpleMemory 213bandwidth=73.000000 214clock=1 215conf_table_reported=false 216in_addr_map=true 217latency=30000 218latency_var=0 219null=false 220range=0:134217727 221zero=false 222port=system.membus.master[0] 223 224