config.ini revision 10218:5a45f124a2f7
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu membus monitor physmem 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= 26symbolfile= 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[1] 35 36[system.clk_domain] 37type=SrcClockDomain 38children=voltage_domain 39clock=1000 40eventq_index=0 41voltage_domain=system.clk_domain.voltage_domain 42 43[system.clk_domain.voltage_domain] 44type=VoltageDomain 45eventq_index=0 46voltage=1.000000 47 48[system.cpu] 49type=TrafficGen 50clk_domain=system.clk_domain 51config_file=tests/quick/se/70.tgen/tgen-simple-dram.cfg 52elastic_req=false 53eventq_index=0 54system=system 55port=system.monitor.slave 56 57[system.membus] 58type=NoncoherentBus 59clk_domain=system.clk_domain 60eventq_index=0 61header_cycles=1 62use_default_range=false 63width=16 64master=system.physmem.port 65slave=system.monitor.master system.system_port 66 67[system.monitor] 68type=CommMonitor 69bandwidth_bins=20 70burst_length_bins=20 71clk_domain=system.clk_domain 72disable_addr_dists=true 73disable_bandwidth_hists=false 74disable_burst_length_hists=false 75disable_itt_dists=false 76disable_latency_hists=false 77disable_outstanding_hists=false 78disable_transaction_hists=false 79eventq_index=0 80itt_bins=20 81itt_max_bin=100000 82latency_bins=20 83outstanding_bins=20 84read_addr_mask=18446744073709551615 85sample_period=1000000000 86trace_file= 87transaction_bins=20 88write_addr_mask=18446744073709551615 89master=system.membus.slave[0] 90slave=system.cpu.port 91 92[system.physmem] 93type=SimpleDRAM 94activation_limit=4 95addr_mapping=RaBaChCo 96banks_per_rank=8 97burst_length=8 98channels=1 99clk_domain=system.clk_domain 100conf_table_reported=true 101device_bus_width=8 102device_rowbuffer_size=1024 103devices_per_rank=8 104eventq_index=0 105in_addr_map=true 106mem_sched_policy=frfcfs 107null=false 108page_policy=open 109range=0:134217727 110ranks_per_channel=2 111read_buffer_size=32 112static_backend_latency=10000 113static_frontend_latency=10000 114tBURST=5000 115tCL=13750 116tRAS=35000 117tRCD=13750 118tREFI=7800000 119tRFC=300000 120tRP=13750 121tRRD=6250 122tWTR=7500 123tXAW=40000 124write_buffer_size=32 125write_high_thresh_perc=70 126write_low_thresh_perc=0 127port=system.membus.master[0] 128 129