stats.txt revision 11388:bd4125134e77
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.203116 # Number of seconds simulated 4sim_ticks 203115946500 # Number of ticks simulated 5final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 864116 # Simulator instruction rate (inst/s) 8host_op_rate 875304 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1305930078 # Simulator tick rate (ticks/s) 10host_mem_usage 235576 # Number of bytes of host memory used 11host_seconds 155.53 # Real time elapsed on the host 12sim_insts 134398959 # Number of instructions simulated 13sim_ops 136139187 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 122318 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 130522 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 85270 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 85270 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 2585006 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 38541297 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 41126303 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 2585006 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 2585006 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 26867807 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 26867807 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 26867807 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s) 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.workload.num_syscalls 1946 # Number of system calls 41system.cpu.numCycles 406231893 # number of cpu cycles simulated 42system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 44system.cpu.committedInsts 134398959 # Number of instructions committed 45system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed 46system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses 47system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses 48system.cpu.num_func_calls 1709332 # number of times a function call or return occured 49system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls 50system.cpu.num_int_insts 115187757 # number of integer instructions 51system.cpu.num_fp_insts 2326976 # number of float instructions 52system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read 53system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written 54system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read 55system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written 56system.cpu.num_mem_refs 58160261 # number of memory refs 57system.cpu.num_load_insts 37275864 # Number of load instructions 58system.cpu.num_store_insts 20884397 # Number of store instructions 59system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 60system.cpu.num_busy_cycles 406231892.998000 # Number of busy cycles 61system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 62system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 63system.cpu.Branches 12719094 # Number of branches fetched 64system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction 65system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction 66system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction 67system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction 68system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction 69system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction 70system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction 71system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction 72system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction 73system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction 74system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction 75system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction 76system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction 77system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction 78system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction 79system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction 80system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction 81system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction 82system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction 83system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction 84system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction 85system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction 86system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction 87system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction 88system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction 89system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction 90system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction 91system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction 92system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction 93system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction 94system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction 95system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction 96system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 97system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 98system.cpu.op_class::total 136293808 # Class of executed instruction 99system.cpu.dcache.tags.replacements 146583 # number of replacements 100system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use 101system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. 102system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. 103system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. 104system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit. 105system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268923 # Average occupied blocks per requestor 106system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy 107system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy 108system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 109system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id 110system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id 111system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id 112system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 113system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses 114system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses 115system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits 116system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits 117system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits 118system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits 119system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits 120system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits 121system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits 122system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits 123system.cpu.dcache.overall_hits::cpu.data 57944940 # number of overall hits 124system.cpu.dcache.overall_hits::total 57944940 # number of overall hits 125system.cpu.dcache.ReadReq_misses::cpu.data 45500 # number of ReadReq misses 126system.cpu.dcache.ReadReq_misses::total 45500 # number of ReadReq misses 127system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses 128system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses 129system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses 130system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses 131system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses 132system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses 133system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses 134system.cpu.dcache.overall_misses::total 150664 # number of overall misses 135system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623315500 # number of ReadReq miss cycles 136system.cpu.dcache.ReadReq_miss_latency::total 1623315500 # number of ReadReq miss cycles 137system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554000 # number of WriteReq miss cycles 138system.cpu.dcache.WriteReq_miss_latency::total 6329554000 # number of WriteReq miss cycles 139system.cpu.dcache.SwapReq_miss_latency::cpu.data 441000 # number of SwapReq miss cycles 140system.cpu.dcache.SwapReq_miss_latency::total 441000 # number of SwapReq miss cycles 141system.cpu.dcache.demand_miss_latency::cpu.data 7952869500 # number of demand (read+write) miss cycles 142system.cpu.dcache.demand_miss_latency::total 7952869500 # number of demand (read+write) miss cycles 143system.cpu.dcache.overall_miss_latency::cpu.data 7952869500 # number of overall miss cycles 144system.cpu.dcache.overall_miss_latency::total 7952869500 # number of overall miss cycles 145system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) 146system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) 147system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) 148system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) 149system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) 150system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) 151system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses 152system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses 153system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses 154system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses 155system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses 156system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses 157system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses 158system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses 159system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses 160system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses 161system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses 162system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses 163system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses 164system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses 165system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35677.263736 # average ReadReq miss latency 166system.cpu.dcache.ReadReq_avg_miss_latency::total 35677.263736 # average ReadReq miss latency 167system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.459587 # average WriteReq miss latency 168system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.459587 # average WriteReq miss latency 169system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29400 # average SwapReq miss latency 170system.cpu.dcache.SwapReq_avg_miss_latency::total 29400 # average SwapReq miss latency 171system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency 172system.cpu.dcache.demand_avg_miss_latency::total 52785.466336 # average overall miss latency 173system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency 174system.cpu.dcache.overall_avg_miss_latency::total 52785.466336 # average overall miss latency 175system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 176system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 177system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 178system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 179system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 180system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 181system.cpu.dcache.fast_writes 0 # number of fast writes performed 182system.cpu.dcache.cache_copies 0 # number of cache copies performed 183system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks 184system.cpu.dcache.writebacks::total 123865 # number of writebacks 185system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses 186system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses 187system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses 188system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses 189system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses 190system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses 191system.cpu.dcache.demand_mshr_misses::cpu.data 150664 # number of demand (read+write) MSHR misses 192system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses 193system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses 194system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses 195system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577815500 # number of ReadReq MSHR miss cycles 196system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577815500 # number of ReadReq MSHR miss cycles 197system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390000 # number of WriteReq MSHR miss cycles 198system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390000 # number of WriteReq MSHR miss cycles 199system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 426000 # number of SwapReq MSHR miss cycles 200system.cpu.dcache.SwapReq_mshr_miss_latency::total 426000 # number of SwapReq MSHR miss cycles 201system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802205500 # number of demand (read+write) MSHR miss cycles 202system.cpu.dcache.demand_mshr_miss_latency::total 7802205500 # number of demand (read+write) MSHR miss cycles 203system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802205500 # number of overall MSHR miss cycles 204system.cpu.dcache.overall_mshr_miss_latency::total 7802205500 # number of overall MSHR miss cycles 205system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses 206system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses 207system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses 208system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses 209system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses 210system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses 211system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses 212system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses 213system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses 214system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses 215system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34677.263736 # average ReadReq mshr miss latency 216system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34677.263736 # average ReadReq mshr miss latency 217system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587 # average WriteReq mshr miss latency 218system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587 # average WriteReq mshr miss latency 219system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency 220system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency 221system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency 222system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency 223system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency 224system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency 225system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 226system.cpu.icache.tags.replacements 184976 # number of replacements 227system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use 228system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. 229system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. 230system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. 231system.cpu.icache.tags.warmup_cycle 144582800500 # Cycle when the warmup percentage was hit. 232system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181265 # Average occupied blocks per requestor 233system.cpu.icache.tags.occ_percent::cpu.inst 0.978604 # Average percentage of cache occupancy 234system.cpu.icache.tags.occ_percent::total 0.978604 # Average percentage of cache occupancy 235system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id 236system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 237system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id 238system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 239system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id 240system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id 241system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 242system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses 243system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses 244system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits 245system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits 246system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits 247system.cpu.icache.demand_hits::total 134366557 # number of demand (read+write) hits 248system.cpu.icache.overall_hits::cpu.inst 134366557 # number of overall hits 249system.cpu.icache.overall_hits::total 134366557 # number of overall hits 250system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses 251system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses 252system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses 253system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses 254system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses 255system.cpu.icache.overall_misses::total 187024 # number of overall misses 256system.cpu.icache.ReadReq_miss_latency::cpu.inst 2835239000 # number of ReadReq miss cycles 257system.cpu.icache.ReadReq_miss_latency::total 2835239000 # number of ReadReq miss cycles 258system.cpu.icache.demand_miss_latency::cpu.inst 2835239000 # number of demand (read+write) miss cycles 259system.cpu.icache.demand_miss_latency::total 2835239000 # number of demand (read+write) miss cycles 260system.cpu.icache.overall_miss_latency::cpu.inst 2835239000 # number of overall miss cycles 261system.cpu.icache.overall_miss_latency::total 2835239000 # number of overall miss cycles 262system.cpu.icache.ReadReq_accesses::cpu.inst 134553581 # number of ReadReq accesses(hits+misses) 263system.cpu.icache.ReadReq_accesses::total 134553581 # number of ReadReq accesses(hits+misses) 264system.cpu.icache.demand_accesses::cpu.inst 134553581 # number of demand (read+write) accesses 265system.cpu.icache.demand_accesses::total 134553581 # number of demand (read+write) accesses 266system.cpu.icache.overall_accesses::cpu.inst 134553581 # number of overall (read+write) accesses 267system.cpu.icache.overall_accesses::total 134553581 # number of overall (read+write) accesses 268system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses 269system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses 270system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses 271system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses 272system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses 273system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses 274system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15159.760245 # average ReadReq miss latency 275system.cpu.icache.ReadReq_avg_miss_latency::total 15159.760245 # average ReadReq miss latency 276system.cpu.icache.demand_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency 277system.cpu.icache.demand_avg_miss_latency::total 15159.760245 # average overall miss latency 278system.cpu.icache.overall_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency 279system.cpu.icache.overall_avg_miss_latency::total 15159.760245 # average overall miss latency 280system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 281system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 282system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 283system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 284system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 285system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 286system.cpu.icache.fast_writes 0 # number of fast writes performed 287system.cpu.icache.cache_copies 0 # number of cache copies performed 288system.cpu.icache.writebacks::writebacks 184976 # number of writebacks 289system.cpu.icache.writebacks::total 184976 # number of writebacks 290system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses 291system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses 292system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses 293system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses 294system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses 295system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses 296system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2648215000 # number of ReadReq MSHR miss cycles 297system.cpu.icache.ReadReq_mshr_miss_latency::total 2648215000 # number of ReadReq MSHR miss cycles 298system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2648215000 # number of demand (read+write) MSHR miss cycles 299system.cpu.icache.demand_mshr_miss_latency::total 2648215000 # number of demand (read+write) MSHR miss cycles 300system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2648215000 # number of overall MSHR miss cycles 301system.cpu.icache.overall_mshr_miss_latency::total 2648215000 # number of overall MSHR miss cycles 302system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses 303system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses 304system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses 305system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses 306system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses 307system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses 308system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14159.760245 # average ReadReq mshr miss latency 309system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14159.760245 # average ReadReq mshr miss latency 310system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency 311system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency 312system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency 313system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency 314system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 315system.cpu.l2cache.tags.replacements 99022 # number of replacements 316system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use 317system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks. 318system.cpu.l2cache.tags.sampled_refs 130065 # Sample count of references to valid blocks. 319system.cpu.l2cache.tags.avg_refs 3.335501 # Average number of references to valid blocks. 320system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 321system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168 # Average occupied blocks per requestor 322system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863620 # Average occupied blocks per requestor 323system.cpu.l2cache.tags.occ_blocks::cpu.data 1304.666895 # Average occupied blocks per requestor 324system.cpu.l2cache.tags.occ_percent::writebacks 0.802282 # Average percentage of cache occupancy 325system.cpu.l2cache.tags.occ_percent::cpu.inst 0.099178 # Average percentage of cache occupancy 326system.cpu.l2cache.tags.occ_percent::cpu.data 0.039815 # Average percentage of cache occupancy 327system.cpu.l2cache.tags.occ_percent::total 0.941275 # Average percentage of cache occupancy 328system.cpu.l2cache.tags.occ_task_id_blocks::1024 31043 # Occupied blocks per task id 329system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 330system.cpu.l2cache.tags.age_task_id_blocks_1024::1 566 # Occupied blocks per task id 331system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11257 # Occupied blocks per task id 332system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18470 # Occupied blocks per task id 333system.cpu.l2cache.tags.age_task_id_blocks_1024::4 557 # Occupied blocks per task id 334system.cpu.l2cache.tags.occ_task_id_percent::1024 0.947357 # Percentage of cache occupancy per task id 335system.cpu.l2cache.tags.tag_accesses 5588812 # Number of tag accesses 336system.cpu.l2cache.tags.data_accesses 5588812 # Number of data accesses 337system.cpu.l2cache.WritebackDirty_hits::writebacks 123865 # number of WritebackDirty hits 338system.cpu.l2cache.WritebackDirty_hits::total 123865 # number of WritebackDirty hits 339system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits 340system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits 341system.cpu.l2cache.ReadExReq_hits::cpu.data 3915 # number of ReadExReq hits 342system.cpu.l2cache.ReadExReq_hits::total 3915 # number of ReadExReq hits 343system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178820 # number of ReadCleanReq hits 344system.cpu.l2cache.ReadCleanReq_hits::total 178820 # number of ReadCleanReq hits 345system.cpu.l2cache.ReadSharedReq_hits::cpu.data 24446 # number of ReadSharedReq hits 346system.cpu.l2cache.ReadSharedReq_hits::total 24446 # number of ReadSharedReq hits 347system.cpu.l2cache.demand_hits::cpu.inst 178820 # number of demand (read+write) hits 348system.cpu.l2cache.demand_hits::cpu.data 28361 # number of demand (read+write) hits 349system.cpu.l2cache.demand_hits::total 207181 # number of demand (read+write) hits 350system.cpu.l2cache.overall_hits::cpu.inst 178820 # number of overall hits 351system.cpu.l2cache.overall_hits::cpu.data 28361 # number of overall hits 352system.cpu.l2cache.overall_hits::total 207181 # number of overall hits 353system.cpu.l2cache.ReadExReq_misses::cpu.data 101264 # number of ReadExReq misses 354system.cpu.l2cache.ReadExReq_misses::total 101264 # number of ReadExReq misses 355system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8204 # number of ReadCleanReq misses 356system.cpu.l2cache.ReadCleanReq_misses::total 8204 # number of ReadCleanReq misses 357system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21054 # number of ReadSharedReq misses 358system.cpu.l2cache.ReadSharedReq_misses::total 21054 # number of ReadSharedReq misses 359system.cpu.l2cache.demand_misses::cpu.inst 8204 # number of demand (read+write) misses 360system.cpu.l2cache.demand_misses::cpu.data 122318 # number of demand (read+write) misses 361system.cpu.l2cache.demand_misses::total 130522 # number of demand (read+write) misses 362system.cpu.l2cache.overall_misses::cpu.inst 8204 # number of overall misses 363system.cpu.l2cache.overall_misses::cpu.data 122318 # number of overall misses 364system.cpu.l2cache.overall_misses::total 130522 # number of overall misses 365system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6025890000 # number of ReadExReq miss cycles 366system.cpu.l2cache.ReadExReq_miss_latency::total 6025890000 # number of ReadExReq miss cycles 367system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 488461500 # number of ReadCleanReq miss cycles 368system.cpu.l2cache.ReadCleanReq_miss_latency::total 488461500 # number of ReadCleanReq miss cycles 369system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1252834000 # number of ReadSharedReq miss cycles 370system.cpu.l2cache.ReadSharedReq_miss_latency::total 1252834000 # number of ReadSharedReq miss cycles 371system.cpu.l2cache.demand_miss_latency::cpu.inst 488461500 # number of demand (read+write) miss cycles 372system.cpu.l2cache.demand_miss_latency::cpu.data 7278724000 # number of demand (read+write) miss cycles 373system.cpu.l2cache.demand_miss_latency::total 7767185500 # number of demand (read+write) miss cycles 374system.cpu.l2cache.overall_miss_latency::cpu.inst 488461500 # number of overall miss cycles 375system.cpu.l2cache.overall_miss_latency::cpu.data 7278724000 # number of overall miss cycles 376system.cpu.l2cache.overall_miss_latency::total 7767185500 # number of overall miss cycles 377system.cpu.l2cache.WritebackDirty_accesses::writebacks 123865 # number of WritebackDirty accesses(hits+misses) 378system.cpu.l2cache.WritebackDirty_accesses::total 123865 # number of WritebackDirty accesses(hits+misses) 379system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses) 380system.cpu.l2cache.WritebackClean_accesses::total 184923 # number of WritebackClean accesses(hits+misses) 381system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) 382system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) 383system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses) 384system.cpu.l2cache.ReadCleanReq_accesses::total 187024 # number of ReadCleanReq accesses(hits+misses) 385system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45500 # number of ReadSharedReq accesses(hits+misses) 386system.cpu.l2cache.ReadSharedReq_accesses::total 45500 # number of ReadSharedReq accesses(hits+misses) 387system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses 388system.cpu.l2cache.demand_accesses::cpu.data 150679 # number of demand (read+write) accesses 389system.cpu.l2cache.demand_accesses::total 337703 # number of demand (read+write) accesses 390system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses 391system.cpu.l2cache.overall_accesses::cpu.data 150679 # number of overall (read+write) accesses 392system.cpu.l2cache.overall_accesses::total 337703 # number of overall (read+write) accesses 393system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962778 # miss rate for ReadExReq accesses 394system.cpu.l2cache.ReadExReq_miss_rate::total 0.962778 # miss rate for ReadExReq accesses 395system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043866 # miss rate for ReadCleanReq accesses 396system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043866 # miss rate for ReadCleanReq accesses 397system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.462725 # miss rate for ReadSharedReq accesses 398system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.462725 # miss rate for ReadSharedReq accesses 399system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043866 # miss rate for demand accesses 400system.cpu.l2cache.demand_miss_rate::cpu.data 0.811779 # miss rate for demand accesses 401system.cpu.l2cache.demand_miss_rate::total 0.386499 # miss rate for demand accesses 402system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043866 # miss rate for overall accesses 403system.cpu.l2cache.overall_miss_rate::cpu.data 0.811779 # miss rate for overall accesses 404system.cpu.l2cache.overall_miss_rate::total 0.386499 # miss rate for overall accesses 405system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59506.734871 # average ReadExReq miss latency 406system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59506.734871 # average ReadExReq miss latency 407system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59539.431984 # average ReadCleanReq miss latency 408system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59539.431984 # average ReadCleanReq miss latency 409system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.747126 # average ReadSharedReq miss latency 410system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.747126 # average ReadSharedReq miss latency 411system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency 412system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency 413system.cpu.l2cache.demand_avg_miss_latency::total 59508.630729 # average overall miss latency 414system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency 415system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency 416system.cpu.l2cache.overall_avg_miss_latency::total 59508.630729 # average overall miss latency 417system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 418system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 419system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 420system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 421system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 422system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 423system.cpu.l2cache.fast_writes 0 # number of fast writes performed 424system.cpu.l2cache.cache_copies 0 # number of cache copies performed 425system.cpu.l2cache.writebacks::writebacks 85270 # number of writebacks 426system.cpu.l2cache.writebacks::total 85270 # number of writebacks 427system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses 428system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses 429system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101264 # number of ReadExReq MSHR misses 430system.cpu.l2cache.ReadExReq_mshr_misses::total 101264 # number of ReadExReq MSHR misses 431system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8204 # number of ReadCleanReq MSHR misses 432system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8204 # number of ReadCleanReq MSHR misses 433system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21054 # number of ReadSharedReq MSHR misses 434system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21054 # number of ReadSharedReq MSHR misses 435system.cpu.l2cache.demand_mshr_misses::cpu.inst 8204 # number of demand (read+write) MSHR misses 436system.cpu.l2cache.demand_mshr_misses::cpu.data 122318 # number of demand (read+write) MSHR misses 437system.cpu.l2cache.demand_mshr_misses::total 130522 # number of demand (read+write) MSHR misses 438system.cpu.l2cache.overall_mshr_misses::cpu.inst 8204 # number of overall MSHR misses 439system.cpu.l2cache.overall_mshr_misses::cpu.data 122318 # number of overall MSHR misses 440system.cpu.l2cache.overall_mshr_misses::total 130522 # number of overall MSHR misses 441system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250000 # number of ReadExReq MSHR miss cycles 442system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250000 # number of ReadExReq MSHR miss cycles 443system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 406421500 # number of ReadCleanReq MSHR miss cycles 444system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 406421500 # number of ReadCleanReq MSHR miss cycles 445system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1042294000 # number of ReadSharedReq MSHR miss cycles 446system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1042294000 # number of ReadSharedReq MSHR miss cycles 447system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 406421500 # number of demand (read+write) MSHR miss cycles 448system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6055544000 # number of demand (read+write) MSHR miss cycles 449system.cpu.l2cache.demand_mshr_miss_latency::total 6461965500 # number of demand (read+write) MSHR miss cycles 450system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 406421500 # number of overall MSHR miss cycles 451system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6055544000 # number of overall MSHR miss cycles 452system.cpu.l2cache.overall_mshr_miss_latency::total 6461965500 # number of overall MSHR miss cycles 453system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 454system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 455system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962778 # mshr miss rate for ReadExReq accesses 456system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962778 # mshr miss rate for ReadExReq accesses 457system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for ReadCleanReq accesses 458system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadCleanReq accesses 459system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462725 # mshr miss rate for ReadSharedReq accesses 460system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462725 # mshr miss rate for ReadSharedReq accesses 461system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for demand accesses 462system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for demand accesses 463system.cpu.l2cache.demand_mshr_miss_rate::total 0.386499 # mshr miss rate for demand accesses 464system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for overall accesses 465system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for overall accesses 466system.cpu.l2cache.overall_mshr_miss_rate::total 0.386499 # mshr miss rate for overall accesses 467system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49506.734871 # average ReadExReq mshr miss latency 468system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49506.734871 # average ReadExReq mshr miss latency 469system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49539.431984 # average ReadCleanReq mshr miss latency 470system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49539.431984 # average ReadCleanReq mshr miss latency 471system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747126 # average ReadSharedReq mshr miss latency 472system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747126 # average ReadSharedReq mshr miss latency 473system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency 474system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency 475system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency 476system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency 477system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency 478system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency 479system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 480system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. 481system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. 482system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 483system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter. 484system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 485system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 486system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution 487system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution 488system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution 489system.cpu.toL2Bus.trans_dist::CleanEvict 36470 # Transaction distribution 490system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution 491system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution 492system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution 493system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution 494system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes) 495system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes) 496system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes) 497system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) 498system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570816 # Cumulative packet size per connected master and slave (bytes) 499system.cpu.toL2Bus.pkt_size::total 41378816 # Cumulative packet size per connected master and slave (bytes) 500system.cpu.toL2Bus.snoops 99022 # Total snoops (count) 501system.cpu.toL2Bus.snoop_fanout::samples 436725 # Request fanout histogram 502system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram 503system.cpu.toL2Bus.snoop_fanout::stdev 0.090579 # Request fanout histogram 504system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 505system.cpu.toL2Bus.snoop_fanout::0 433112 99.17% 99.17% # Request fanout histogram 506system.cpu.toL2Bus.snoop_fanout::1 3613 0.83% 100.00% # Request fanout histogram 507system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 508system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 509system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 510system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 511system.cpu.toL2Bus.snoop_fanout::total 436725 # Request fanout histogram 512system.cpu.toL2Bus.reqLayer0.occupancy 643472000 # Layer occupancy (ticks) 513system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 514system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) 515system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 516system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) 517system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 518system.membus.trans_dist::ReadResp 29258 # Transaction distribution 519system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution 520system.membus.trans_dist::CleanEvict 10301 # Transaction distribution 521system.membus.trans_dist::ReadExReq 101264 # Transaction distribution 522system.membus.trans_dist::ReadExResp 101264 # Transaction distribution 523system.membus.trans_dist::ReadSharedReq 29258 # Transaction distribution 524system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356615 # Packet count per connected master and slave (bytes) 525system.membus.pkt_count::total 356615 # Packet count per connected master and slave (bytes) 526system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810688 # Cumulative packet size per connected master and slave (bytes) 527system.membus.pkt_size::total 13810688 # Cumulative packet size per connected master and slave (bytes) 528system.membus.snoops 0 # Total snoops (count) 529system.membus.snoop_fanout::samples 226093 # Request fanout histogram 530system.membus.snoop_fanout::mean 0 # Request fanout histogram 531system.membus.snoop_fanout::stdev 0 # Request fanout histogram 532system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 533system.membus.snoop_fanout::0 226093 100.00% 100.00% # Request fanout histogram 534system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 535system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 536system.membus.snoop_fanout::min_value 0 # Request fanout histogram 537system.membus.snoop_fanout::max_value 0 # Request fanout histogram 538system.membus.snoop_fanout::total 226093 # Request fanout histogram 539system.membus.reqLayer0.occupancy 568574500 # Layer occupancy (ticks) 540system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 541system.membus.respLayer1.occupancy 652610000 # Layer occupancy (ticks) 542system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 543 544---------- End Simulation Statistics ---------- 545