stats.txt revision 10752:62b24818c8c6
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.127293 # Number of seconds simulated 4sim_ticks 127293405500 # Number of ticks simulated 5final_tick 127293405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 802256 # Simulator instruction rate (inst/s) 8host_op_rate 1024256 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1451138855 # Simulator tick rate (ticks/s) 10host_mem_usage 317568 # Number of bytes of host memory used 11host_seconds 87.72 # Real time elapsed on the host 12sim_insts 70373628 # Number of instructions simulated 13sim_ops 89847362 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8179968 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 255488 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 255488 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5370176 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5370176 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3992 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 62253657 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 64260737 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 42187386 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 42187386 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 42187386 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 62253657 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 106448122 # Total bandwidth to/from this memory (bytes/s) 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 53system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 58system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 59system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 60system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69system.cpu.dtb.walker.walks 0 # Table walker walks requested 70system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses 98system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 107system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 108system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 109system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 110system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 111system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 115system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 116system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 117system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 118system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 127system.cpu.itb.walker.walks 0 # Table walker walks requested 128system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.inst_hits 0 # ITB inst hits 136system.cpu.itb.inst_misses 0 # ITB inst misses 137system.cpu.itb.read_hits 0 # DTB read hits 138system.cpu.itb.read_misses 0 # DTB read misses 139system.cpu.itb.write_hits 0 # DTB write hits 140system.cpu.itb.write_misses 0 # DTB write misses 141system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 142system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 143system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 144system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 145system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 146system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 147system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 148system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 1946 # Number of system calls 157system.cpu.numCycles 254586811 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 70373628 # Number of instructions committed 161system.cpu.committedOps 89847362 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses 164system.cpu.num_func_calls 3311620 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls 166system.cpu.num_int_insts 81528488 # number of integer instructions 167system.cpu.num_fp_insts 56 # number of float instructions 168system.cpu.num_int_register_reads 141328474 # number of times the integer registers were read 169system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written 170system.cpu.num_fp_register_reads 36 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 20 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 334802003 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written 174system.cpu.num_mem_refs 43422001 # number of memory refs 175system.cpu.num_load_insts 22866262 # Number of load instructions 176system.cpu.num_store_insts 20555739 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 178system.cpu.num_busy_cycles 254586810.998000 # Number of busy cycles 179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 181system.cpu.Branches 13741485 # Number of branches fetched 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction 184system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction 187system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction 188system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction 189system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction 190system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction 191system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction 192system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction 193system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction 194system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction 195system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction 196system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction 197system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction 198system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction 199system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction 200system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction 201system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction 202system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction 203system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction 204system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction 205system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction 206system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction 207system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction 208system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction 209system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction 212system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction 213system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 90690083 # Class of executed instruction 217system.cpu.dcache.tags.replacements 155902 # number of replacements 218system.cpu.dcache.tags.tagsinuse 4076.389361 # Cycle average of tags in use 219system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks. 222system.cpu.dcache.tags.warmup_cycle 1061070000 # Cycle when the warmup percentage was hit. 223system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389361 # Average occupied blocks per requestor 224system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id 230system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 231system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses 232system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses 233system.cpu.dcache.ReadReq_hits::cpu.data 22749839 # number of ReadReq hits 234system.cpu.dcache.ReadReq_hits::total 22749839 # number of ReadReq hits 235system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits 236system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits 237system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits 238system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits 239system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 240system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 241system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 242system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 243system.cpu.dcache.demand_hits::cpu.data 42492708 # number of demand (read+write) hits 244system.cpu.dcache.demand_hits::total 42492708 # number of demand (read+write) hits 245system.cpu.dcache.overall_hits::cpu.data 42576331 # number of overall hits 246system.cpu.dcache.overall_hits::total 42576331 # number of overall hits 247system.cpu.dcache.ReadReq_misses::cpu.data 30228 # number of ReadReq misses 248system.cpu.dcache.ReadReq_misses::total 30228 # number of ReadReq misses 249system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses 250system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses 251system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses 252system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses 253system.cpu.dcache.demand_misses::cpu.data 137260 # number of demand (read+write) misses 254system.cpu.dcache.demand_misses::total 137260 # number of demand (read+write) misses 255system.cpu.dcache.overall_misses::cpu.data 177381 # number of overall misses 256system.cpu.dcache.overall_misses::total 177381 # number of overall misses 257system.cpu.dcache.ReadReq_miss_latency::cpu.data 517066000 # number of ReadReq miss cycles 258system.cpu.dcache.ReadReq_miss_latency::total 517066000 # number of ReadReq miss cycles 259system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689116000 # number of WriteReq miss cycles 260system.cpu.dcache.WriteReq_miss_latency::total 5689116000 # number of WriteReq miss cycles 261system.cpu.dcache.demand_miss_latency::cpu.data 6206182000 # number of demand (read+write) miss cycles 262system.cpu.dcache.demand_miss_latency::total 6206182000 # number of demand (read+write) miss cycles 263system.cpu.dcache.overall_miss_latency::cpu.data 6206182000 # number of overall miss cycles 264system.cpu.dcache.overall_miss_latency::total 6206182000 # number of overall miss cycles 265system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) 266system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) 267system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 268system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 269system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) 270system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) 271system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 272system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 273system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 274system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 275system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses 276system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses 277system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses 278system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses 279system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 # miss rate for ReadReq accesses 280system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses 281system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses 282system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses 283system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses 284system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses 285system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses 286system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses 287system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses 288system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses 289system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17105.531295 # average ReadReq miss latency 290system.cpu.dcache.ReadReq_avg_miss_latency::total 17105.531295 # average ReadReq miss latency 291system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.412064 # average WriteReq miss latency 292system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.412064 # average WriteReq miss latency 293system.cpu.dcache.demand_avg_miss_latency::cpu.data 45214.789451 # average overall miss latency 294system.cpu.dcache.demand_avg_miss_latency::total 45214.789451 # average overall miss latency 295system.cpu.dcache.overall_avg_miss_latency::cpu.data 34987.862285 # average overall miss latency 296system.cpu.dcache.overall_avg_miss_latency::total 34987.862285 # average overall miss latency 297system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 298system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 299system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 302system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 303system.cpu.dcache.fast_writes 0 # number of fast writes performed 304system.cpu.dcache.cache_copies 0 # number of cache copies performed 305system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks 306system.cpu.dcache.writebacks::total 128239 # number of writebacks 307system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1120 # number of ReadReq MSHR hits 308system.cpu.dcache.ReadReq_mshr_hits::total 1120 # number of ReadReq MSHR hits 309system.cpu.dcache.demand_mshr_hits::cpu.data 1120 # number of demand (read+write) MSHR hits 310system.cpu.dcache.demand_mshr_hits::total 1120 # number of demand (read+write) MSHR hits 311system.cpu.dcache.overall_mshr_hits::cpu.data 1120 # number of overall MSHR hits 312system.cpu.dcache.overall_mshr_hits::total 1120 # number of overall MSHR hits 313system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses 314system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses 315system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses 316system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses 317system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses 318system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses 319system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses 320system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses 321system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses 322system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses 323system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 457995500 # number of ReadReq MSHR miss cycles 324system.cpu.dcache.ReadReq_mshr_miss_latency::total 457995500 # number of ReadReq MSHR miss cycles 325system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5528568000 # number of WriteReq MSHR miss cycles 326system.cpu.dcache.WriteReq_mshr_miss_latency::total 5528568000 # number of WriteReq MSHR miss cycles 327system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1058278000 # number of SoftPFReq MSHR miss cycles 328system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1058278000 # number of SoftPFReq MSHR miss cycles 329system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5986563500 # number of demand (read+write) MSHR miss cycles 330system.cpu.dcache.demand_mshr_miss_latency::total 5986563500 # number of demand (read+write) MSHR miss cycles 331system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7044841500 # number of overall MSHR miss cycles 332system.cpu.dcache.overall_mshr_miss_latency::total 7044841500 # number of overall MSHR miss cycles 333system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses 334system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses 335system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 336system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 337system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses 338system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses 339system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses 340system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses 341system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 342system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses 343system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15734.351381 # average ReadReq mshr miss latency 344system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15734.351381 # average ReadReq mshr miss latency 345system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51653.412064 # average WriteReq mshr miss latency 346system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51653.412064 # average WriteReq mshr miss latency 347system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44357.364406 # average SoftPFReq mshr miss latency 348system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44357.364406 # average SoftPFReq mshr miss latency 349system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43973.582342 # average overall mshr miss latency 350system.cpu.dcache.demand_avg_mshr_miss_latency::total 43973.582342 # average overall mshr miss latency 351system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44030.809760 # average overall mshr miss latency 352system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760 # average overall mshr miss latency 353system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 354system.cpu.icache.tags.replacements 16890 # number of replacements 355system.cpu.icache.tags.tagsinuse 1733.672975 # Cycle average of tags in use 356system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. 357system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. 358system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks. 359system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 360system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672975 # Average occupied blocks per requestor 361system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy 362system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy 363system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id 364system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 365system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id 368system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id 369system.cpu.icache.tags.tag_accesses 156309046 # Number of tag accesses 370system.cpu.icache.tags.data_accesses 156309046 # Number of data accesses 371system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits 372system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits 373system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits 374system.cpu.icache.demand_hits::total 78126161 # number of demand (read+write) hits 375system.cpu.icache.overall_hits::cpu.inst 78126161 # number of overall hits 376system.cpu.icache.overall_hits::total 78126161 # number of overall hits 377system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses 378system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses 379system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses 380system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses 381system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses 382system.cpu.icache.overall_misses::total 18908 # number of overall misses 383system.cpu.icache.ReadReq_miss_latency::cpu.inst 413935000 # number of ReadReq miss cycles 384system.cpu.icache.ReadReq_miss_latency::total 413935000 # number of ReadReq miss cycles 385system.cpu.icache.demand_miss_latency::cpu.inst 413935000 # number of demand (read+write) miss cycles 386system.cpu.icache.demand_miss_latency::total 413935000 # number of demand (read+write) miss cycles 387system.cpu.icache.overall_miss_latency::cpu.inst 413935000 # number of overall miss cycles 388system.cpu.icache.overall_miss_latency::total 413935000 # number of overall miss cycles 389system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) 390system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) 391system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses 392system.cpu.icache.demand_accesses::total 78145069 # number of demand (read+write) accesses 393system.cpu.icache.overall_accesses::cpu.inst 78145069 # number of overall (read+write) accesses 394system.cpu.icache.overall_accesses::total 78145069 # number of overall (read+write) accesses 395system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses 396system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses 397system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses 398system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses 399system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses 400system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses 401system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21892.056272 # average ReadReq miss latency 402system.cpu.icache.ReadReq_avg_miss_latency::total 21892.056272 # average ReadReq miss latency 403system.cpu.icache.demand_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency 404system.cpu.icache.demand_avg_miss_latency::total 21892.056272 # average overall miss latency 405system.cpu.icache.overall_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency 406system.cpu.icache.overall_avg_miss_latency::total 21892.056272 # average overall miss latency 407system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 408system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 409system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 410system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 411system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 412system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 413system.cpu.icache.fast_writes 0 # number of fast writes performed 414system.cpu.icache.cache_copies 0 # number of cache copies performed 415system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses 416system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses 417system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses 418system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses 419system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses 420system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses 421system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 385573000 # number of ReadReq MSHR miss cycles 422system.cpu.icache.ReadReq_mshr_miss_latency::total 385573000 # number of ReadReq MSHR miss cycles 423system.cpu.icache.demand_mshr_miss_latency::cpu.inst 385573000 # number of demand (read+write) MSHR miss cycles 424system.cpu.icache.demand_mshr_miss_latency::total 385573000 # number of demand (read+write) MSHR miss cycles 425system.cpu.icache.overall_mshr_miss_latency::cpu.inst 385573000 # number of overall MSHR miss cycles 426system.cpu.icache.overall_mshr_miss_latency::total 385573000 # number of overall MSHR miss cycles 427system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses 428system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses 429system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses 430system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses 431system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses 432system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses 433system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20392.056272 # average ReadReq mshr miss latency 434system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20392.056272 # average ReadReq mshr miss latency 435system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency 436system.cpu.icache.demand_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency 437system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency 438system.cpu.icache.overall_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency 439system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 440system.cpu.l2cache.tags.replacements 94693 # number of replacements 441system.cpu.l2cache.tags.tagsinuse 30351.006010 # Cycle average of tags in use 442system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. 443system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. 444system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. 445system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 446system.cpu.l2cache.tags.occ_blocks::writebacks 27796.868072 # Average occupied blocks per requestor 447system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.768401 # Average occupied blocks per requestor 448system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.369537 # Average occupied blocks per requestor 449system.cpu.l2cache.tags.occ_percent::writebacks 0.848293 # Average percentage of cache occupancy 450system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035149 # Average percentage of cache occupancy 451system.cpu.l2cache.tags.occ_percent::cpu.data 0.042797 # Average percentage of cache occupancy 452system.cpu.l2cache.tags.occ_percent::total 0.926239 # Average percentage of cache occupancy 453system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id 454system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 455system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id 456system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15103 # Occupied blocks per task id 457system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13917 # Occupied blocks per task id 458system.cpu.l2cache.tags.age_task_id_blocks_1024::4 607 # Occupied blocks per task id 459system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id 460system.cpu.l2cache.tags.tag_accesses 2689980 # Number of tag accesses 461system.cpu.l2cache.tags.data_accesses 2689980 # Number of data accesses 462system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits 463system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits 464system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits 465system.cpu.l2cache.Writeback_hits::writebacks 128239 # number of Writeback hits 466system.cpu.l2cache.Writeback_hits::total 128239 # number of Writeback hits 467system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits 468system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits 469system.cpu.l2cache.demand_hits::cpu.inst 14916 # number of demand (read+write) hits 470system.cpu.l2cache.demand_hits::cpu.data 36178 # number of demand (read+write) hits 471system.cpu.l2cache.demand_hits::total 51094 # number of demand (read+write) hits 472system.cpu.l2cache.overall_hits::cpu.inst 14916 # number of overall hits 473system.cpu.l2cache.overall_hits::cpu.data 36178 # number of overall hits 474system.cpu.l2cache.overall_hits::total 51094 # number of overall hits 475system.cpu.l2cache.ReadReq_misses::cpu.inst 3992 # number of ReadReq misses 476system.cpu.l2cache.ReadReq_misses::cpu.data 21540 # number of ReadReq misses 477system.cpu.l2cache.ReadReq_misses::total 25532 # number of ReadReq misses 478system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses 479system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses 480system.cpu.l2cache.demand_misses::cpu.inst 3992 # number of demand (read+write) misses 481system.cpu.l2cache.demand_misses::cpu.data 123820 # number of demand (read+write) misses 482system.cpu.l2cache.demand_misses::total 127812 # number of demand (read+write) misses 483system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses 484system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses 485system.cpu.l2cache.overall_misses::total 127812 # number of overall misses 486system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210047000 # number of ReadReq miss cycles 487system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1133331500 # number of ReadReq miss cycles 488system.cpu.l2cache.ReadReq_miss_latency::total 1343378500 # number of ReadReq miss cycles 489system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371640000 # number of ReadExReq miss cycles 490system.cpu.l2cache.ReadExReq_miss_latency::total 5371640000 # number of ReadExReq miss cycles 491system.cpu.l2cache.demand_miss_latency::cpu.inst 210047000 # number of demand (read+write) miss cycles 492system.cpu.l2cache.demand_miss_latency::cpu.data 6504971500 # number of demand (read+write) miss cycles 493system.cpu.l2cache.demand_miss_latency::total 6715018500 # number of demand (read+write) miss cycles 494system.cpu.l2cache.overall_miss_latency::cpu.inst 210047000 # number of overall miss cycles 495system.cpu.l2cache.overall_miss_latency::cpu.data 6504971500 # number of overall miss cycles 496system.cpu.l2cache.overall_miss_latency::total 6715018500 # number of overall miss cycles 497system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) 498system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) 499system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) 500system.cpu.l2cache.Writeback_accesses::writebacks 128239 # number of Writeback accesses(hits+misses) 501system.cpu.l2cache.Writeback_accesses::total 128239 # number of Writeback accesses(hits+misses) 502system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) 503system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) 504system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses 505system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses 506system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses 507system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses 508system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses 509system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses 510system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.211128 # miss rate for ReadReq accesses 511system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.406676 # miss rate for ReadReq accesses 512system.cpu.l2cache.ReadReq_miss_rate::total 0.355233 # miss rate for ReadReq accesses 513system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955602 # miss rate for ReadExReq accesses 514system.cpu.l2cache.ReadExReq_miss_rate::total 0.955602 # miss rate for ReadExReq accesses 515system.cpu.l2cache.demand_miss_rate::cpu.inst 0.211128 # miss rate for demand accesses 516system.cpu.l2cache.demand_miss_rate::cpu.data 0.773885 # miss rate for demand accesses 517system.cpu.l2cache.demand_miss_rate::total 0.714409 # miss rate for demand accesses 518system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses 519system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses 520system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses 521system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52616.983968 # average ReadReq miss latency 522system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52615.204271 # average ReadReq miss latency 523system.cpu.l2cache.ReadReq_avg_miss_latency::total 52615.482532 # average ReadReq miss latency 524system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52518.967540 # average ReadExReq miss latency 525system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52518.967540 # average ReadExReq miss latency 526system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency 527system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency 528system.cpu.l2cache.demand_avg_miss_latency::total 52538.247582 # average overall miss latency 529system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency 530system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency 531system.cpu.l2cache.overall_avg_miss_latency::total 52538.247582 # average overall miss latency 532system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 533system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 534system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 535system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 536system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 537system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 538system.cpu.l2cache.fast_writes 0 # number of fast writes performed 539system.cpu.l2cache.cache_copies 0 # number of cache copies performed 540system.cpu.l2cache.writebacks::writebacks 83909 # number of writebacks 541system.cpu.l2cache.writebacks::total 83909 # number of writebacks 542system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3992 # number of ReadReq MSHR misses 543system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21540 # number of ReadReq MSHR misses 544system.cpu.l2cache.ReadReq_mshr_misses::total 25532 # number of ReadReq MSHR misses 545system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses 546system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses 547system.cpu.l2cache.demand_mshr_misses::cpu.inst 3992 # number of demand (read+write) MSHR misses 548system.cpu.l2cache.demand_mshr_misses::cpu.data 123820 # number of demand (read+write) MSHR misses 549system.cpu.l2cache.demand_mshr_misses::total 127812 # number of demand (read+write) MSHR misses 550system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses 551system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses 552system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses 553system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 161778000 # number of ReadReq MSHR miss cycles 554system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 873989500 # number of ReadReq MSHR miss cycles 555system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1035767500 # number of ReadReq MSHR miss cycles 556system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4142346500 # number of ReadExReq MSHR miss cycles 557system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4142346500 # number of ReadExReq MSHR miss cycles 558system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161778000 # number of demand (read+write) MSHR miss cycles 559system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5016336000 # number of demand (read+write) MSHR miss cycles 560system.cpu.l2cache.demand_mshr_miss_latency::total 5178114000 # number of demand (read+write) MSHR miss cycles 561system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161778000 # number of overall MSHR miss cycles 562system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5016336000 # number of overall MSHR miss cycles 563system.cpu.l2cache.overall_mshr_miss_latency::total 5178114000 # number of overall MSHR miss cycles 564system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses 565system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses 566system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses 567system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses 568system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses 569system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for demand accesses 570system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses 571system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 # mshr miss rate for demand accesses 572system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses 573system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses 574system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses 575system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40525.551102 # average ReadReq mshr miss latency 576system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40575.185701 # average ReadReq mshr miss latency 577system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40567.425192 # average ReadReq mshr miss latency 578system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.063551 # average ReadExReq mshr miss latency 579system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.063551 # average ReadExReq mshr miss latency 580system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency 581system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency 582system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency 583system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency 584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency 585system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency 586system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 587system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution 588system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution 589system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution 590system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution 591system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution 592system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37816 # Packet count per connected master and slave (bytes) 593system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 448235 # Packet count per connected master and slave (bytes) 594system.cpu.toL2Bus.pkt_count::total 486051 # Packet count per connected master and slave (bytes) 595system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes) 596system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes) 597system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes) 598system.cpu.toL2Bus.snoops 0 # Total snoops (count) 599system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram 600system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 601system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 602system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 603system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 604system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 605system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 606system.cpu.toL2Bus.snoop_fanout::3 307145 100.00% 100.00% # Request fanout histogram 607system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 608system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 609system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 610system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 611system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram 612system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks) 613system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 614system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) 615system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 616system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) 617system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 618system.membus.trans_dist::ReadReq 25532 # Transaction distribution 619system.membus.trans_dist::ReadResp 25532 # Transaction distribution 620system.membus.trans_dist::Writeback 83909 # Transaction distribution 621system.membus.trans_dist::ReadExReq 102280 # Transaction distribution 622system.membus.trans_dist::ReadExResp 102280 # Transaction distribution 623system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes) 624system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes) 625system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) 626system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) 627system.membus.snoops 0 # Total snoops (count) 628system.membus.snoop_fanout::samples 214640 # Request fanout histogram 629system.membus.snoop_fanout::mean 0 # Request fanout histogram 630system.membus.snoop_fanout::stdev 0 # Request fanout histogram 631system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 632system.membus.snoop_fanout::0 214640 100.00% 100.00% # Request fanout histogram 633system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 634system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 635system.membus.snoop_fanout::min_value 0 # Request fanout histogram 636system.membus.snoop_fanout::max_value 0 # Request fanout histogram 637system.membus.snoop_fanout::total 214640 # Request fanout histogram 638system.membus.reqLayer0.occupancy 566253984 # Layer occupancy (ticks) 639system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) 640system.membus.respLayer1.occupancy 642220500 # Layer occupancy (ticks) 641system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 642 643---------- End Simulation Statistics ---------- 644