stats.txt revision 9348:44d31345e360
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000262 # Number of seconds simulated 4sim_ticks 261623500 # Number of ticks simulated 5final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 114971 # Simulator instruction rate (inst/s) 8host_op_rate 114971 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 45557694 # Simulator tick rate (ticks/s) 10host_mem_usage 232524 # Number of bytes of host memory used 11host_seconds 5.74 # Real time elapsed on the host 12sim_insts 660239 # Number of instructions simulated 13sim_ops 660239 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu3.inst 3392 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu3.data 1408 # Number of bytes read from this memory 22system.physmem.bytes_read::total 36608 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 3392 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu3.inst 53 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu3.data 22 # Number of read requests responded to by this memory 36system.physmem.num_reads::total 572 # Number of read requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 69718508 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 40363347 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 1712384 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 3669395 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 2201637 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 3914021 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 12965196 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 5381780 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 139926268 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 69718508 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 1712384 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 2201637 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 12965196 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 86597725 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 69718508 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 40363347 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 1712384 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 3669395 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 2201637 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 3914021 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 12965196 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 5381780 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 139926268 # Total bandwidth to/from this memory (bytes/s) 60system.cpu0.workload.num_syscalls 89 # Number of system calls 61system.cpu0.numCycles 523247 # number of cpu cycles simulated 62system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 63system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 64system.cpu0.committedInsts 158010 # Number of instructions committed 65system.cpu0.committedOps 158010 # Number of ops (including micro ops) committed 66system.cpu0.num_int_alu_accesses 108832 # Number of integer alu accesses 67system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 68system.cpu0.num_func_calls 390 # number of times a function call or return occured 69system.cpu0.num_conditional_control_insts 25938 # number of instructions that are conditional controls 70system.cpu0.num_int_insts 108832 # number of integer instructions 71system.cpu0.num_fp_insts 0 # number of float instructions 72system.cpu0.num_int_register_reads 314654 # number of times the integer registers were read 73system.cpu0.num_int_register_writes 110438 # number of times the integer registers were written 74system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 75system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 76system.cpu0.num_mem_refs 73739 # number of memory refs 77system.cpu0.num_load_insts 48819 # Number of load instructions 78system.cpu0.num_store_insts 24920 # Number of store instructions 79system.cpu0.num_idle_cycles 0 # Number of idle cycles 80system.cpu0.num_busy_cycles 523247 # Number of busy cycles 81system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 82system.cpu0.idle_fraction 0 # Percentage of idle cycles 83system.cpu0.icache.replacements 215 # number of replacements 84system.cpu0.icache.tagsinuse 212.464540 # Cycle average of tags in use 85system.cpu0.icache.total_refs 157606 # Total number of references to valid blocks. 86system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. 87system.cpu0.icache.avg_refs 337.486081 # Average number of references to valid blocks. 88system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 89system.cpu0.icache.occ_blocks::cpu0.inst 212.464540 # Average occupied blocks per requestor 90system.cpu0.icache.occ_percent::cpu0.inst 0.414970 # Average percentage of cache occupancy 91system.cpu0.icache.occ_percent::total 0.414970 # Average percentage of cache occupancy 92system.cpu0.icache.ReadReq_hits::cpu0.inst 157606 # number of ReadReq hits 93system.cpu0.icache.ReadReq_hits::total 157606 # number of ReadReq hits 94system.cpu0.icache.demand_hits::cpu0.inst 157606 # number of demand (read+write) hits 95system.cpu0.icache.demand_hits::total 157606 # number of demand (read+write) hits 96system.cpu0.icache.overall_hits::cpu0.inst 157606 # number of overall hits 97system.cpu0.icache.overall_hits::total 157606 # number of overall hits 98system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 99system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 100system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 101system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 102system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 103system.cpu0.icache.overall_misses::total 467 # number of overall misses 104system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18144000 # number of ReadReq miss cycles 105system.cpu0.icache.ReadReq_miss_latency::total 18144000 # number of ReadReq miss cycles 106system.cpu0.icache.demand_miss_latency::cpu0.inst 18144000 # number of demand (read+write) miss cycles 107system.cpu0.icache.demand_miss_latency::total 18144000 # number of demand (read+write) miss cycles 108system.cpu0.icache.overall_miss_latency::cpu0.inst 18144000 # number of overall miss cycles 109system.cpu0.icache.overall_miss_latency::total 18144000 # number of overall miss cycles 110system.cpu0.icache.ReadReq_accesses::cpu0.inst 158073 # number of ReadReq accesses(hits+misses) 111system.cpu0.icache.ReadReq_accesses::total 158073 # number of ReadReq accesses(hits+misses) 112system.cpu0.icache.demand_accesses::cpu0.inst 158073 # number of demand (read+write) accesses 113system.cpu0.icache.demand_accesses::total 158073 # number of demand (read+write) accesses 114system.cpu0.icache.overall_accesses::cpu0.inst 158073 # number of overall (read+write) accesses 115system.cpu0.icache.overall_accesses::total 158073 # number of overall (read+write) accesses 116system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002954 # miss rate for ReadReq accesses 117system.cpu0.icache.ReadReq_miss_rate::total 0.002954 # miss rate for ReadReq accesses 118system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002954 # miss rate for demand accesses 119system.cpu0.icache.demand_miss_rate::total 0.002954 # miss rate for demand accesses 120system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002954 # miss rate for overall accesses 121system.cpu0.icache.overall_miss_rate::total 0.002954 # miss rate for overall accesses 122system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38852.248394 # average ReadReq miss latency 123system.cpu0.icache.ReadReq_avg_miss_latency::total 38852.248394 # average ReadReq miss latency 124system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency 125system.cpu0.icache.demand_avg_miss_latency::total 38852.248394 # average overall miss latency 126system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency 127system.cpu0.icache.overall_avg_miss_latency::total 38852.248394 # average overall miss latency 128system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 129system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 130system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 131system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 132system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 133system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 134system.cpu0.icache.fast_writes 0 # number of fast writes performed 135system.cpu0.icache.cache_copies 0 # number of cache copies performed 136system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 137system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 138system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 139system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 140system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 141system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses 142system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17210000 # number of ReadReq MSHR miss cycles 143system.cpu0.icache.ReadReq_mshr_miss_latency::total 17210000 # number of ReadReq MSHR miss cycles 144system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17210000 # number of demand (read+write) MSHR miss cycles 145system.cpu0.icache.demand_mshr_miss_latency::total 17210000 # number of demand (read+write) MSHR miss cycles 146system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17210000 # number of overall MSHR miss cycles 147system.cpu0.icache.overall_mshr_miss_latency::total 17210000 # number of overall MSHR miss cycles 148system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for ReadReq accesses 149system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002954 # mshr miss rate for ReadReq accesses 150system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for demand accesses 151system.cpu0.icache.demand_mshr_miss_rate::total 0.002954 # mshr miss rate for demand accesses 152system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for overall accesses 153system.cpu0.icache.overall_mshr_miss_rate::total 0.002954 # mshr miss rate for overall accesses 154system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average ReadReq mshr miss latency 155system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36852.248394 # average ReadReq mshr miss latency 156system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency 157system.cpu0.icache.demand_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency 158system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency 159system.cpu0.icache.overall_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency 160system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 161system.cpu0.dcache.replacements 2 # number of replacements 162system.cpu0.dcache.tagsinuse 145.601248 # Cycle average of tags in use 163system.cpu0.dcache.total_refs 73215 # Total number of references to valid blocks. 164system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. 165system.cpu0.dcache.avg_refs 438.413174 # Average number of references to valid blocks. 166system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 167system.cpu0.dcache.occ_blocks::cpu0.data 145.601248 # Average occupied blocks per requestor 168system.cpu0.dcache.occ_percent::cpu0.data 0.284377 # Average percentage of cache occupancy 169system.cpu0.dcache.occ_percent::total 0.284377 # Average percentage of cache occupancy 170system.cpu0.dcache.ReadReq_hits::cpu0.data 48647 # number of ReadReq hits 171system.cpu0.dcache.ReadReq_hits::total 48647 # number of ReadReq hits 172system.cpu0.dcache.WriteReq_hits::cpu0.data 24686 # number of WriteReq hits 173system.cpu0.dcache.WriteReq_hits::total 24686 # number of WriteReq hits 174system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 175system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits 176system.cpu0.dcache.demand_hits::cpu0.data 73333 # number of demand (read+write) hits 177system.cpu0.dcache.demand_hits::total 73333 # number of demand (read+write) hits 178system.cpu0.dcache.overall_hits::cpu0.data 73333 # number of overall hits 179system.cpu0.dcache.overall_hits::total 73333 # number of overall hits 180system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses 181system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses 182system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 183system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 184system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 185system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 186system.cpu0.dcache.demand_misses::cpu0.data 345 # number of demand (read+write) misses 187system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses 188system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses 189system.cpu0.dcache.overall_misses::total 345 # number of overall misses 190system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4649500 # number of ReadReq miss cycles 191system.cpu0.dcache.ReadReq_miss_latency::total 4649500 # number of ReadReq miss cycles 192system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7005000 # number of WriteReq miss cycles 193system.cpu0.dcache.WriteReq_miss_latency::total 7005000 # number of WriteReq miss cycles 194system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 363500 # number of SwapReq miss cycles 195system.cpu0.dcache.SwapReq_miss_latency::total 363500 # number of SwapReq miss cycles 196system.cpu0.dcache.demand_miss_latency::cpu0.data 11654500 # number of demand (read+write) miss cycles 197system.cpu0.dcache.demand_miss_latency::total 11654500 # number of demand (read+write) miss cycles 198system.cpu0.dcache.overall_miss_latency::cpu0.data 11654500 # number of overall miss cycles 199system.cpu0.dcache.overall_miss_latency::total 11654500 # number of overall miss cycles 200system.cpu0.dcache.ReadReq_accesses::cpu0.data 48809 # number of ReadReq accesses(hits+misses) 201system.cpu0.dcache.ReadReq_accesses::total 48809 # number of ReadReq accesses(hits+misses) 202system.cpu0.dcache.WriteReq_accesses::cpu0.data 24869 # number of WriteReq accesses(hits+misses) 203system.cpu0.dcache.WriteReq_accesses::total 24869 # number of WriteReq accesses(hits+misses) 204system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 205system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 206system.cpu0.dcache.demand_accesses::cpu0.data 73678 # number of demand (read+write) accesses 207system.cpu0.dcache.demand_accesses::total 73678 # number of demand (read+write) accesses 208system.cpu0.dcache.overall_accesses::cpu0.data 73678 # number of overall (read+write) accesses 209system.cpu0.dcache.overall_accesses::total 73678 # number of overall (read+write) accesses 210system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003319 # miss rate for ReadReq accesses 211system.cpu0.dcache.ReadReq_miss_rate::total 0.003319 # miss rate for ReadReq accesses 212system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007359 # miss rate for WriteReq accesses 213system.cpu0.dcache.WriteReq_miss_rate::total 0.007359 # miss rate for WriteReq accesses 214system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 215system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses 216system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004683 # miss rate for demand accesses 217system.cpu0.dcache.demand_miss_rate::total 0.004683 # miss rate for demand accesses 218system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004683 # miss rate for overall accesses 219system.cpu0.dcache.overall_miss_rate::total 0.004683 # miss rate for overall accesses 220system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28700.617284 # average ReadReq miss latency 221system.cpu0.dcache.ReadReq_avg_miss_latency::total 28700.617284 # average ReadReq miss latency 222system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38278.688525 # average WriteReq miss latency 223system.cpu0.dcache.WriteReq_avg_miss_latency::total 38278.688525 # average WriteReq miss latency 224system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13980.769231 # average SwapReq miss latency 225system.cpu0.dcache.SwapReq_avg_miss_latency::total 13980.769231 # average SwapReq miss latency 226system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency 227system.cpu0.dcache.demand_avg_miss_latency::total 33781.159420 # average overall miss latency 228system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency 229system.cpu0.dcache.overall_avg_miss_latency::total 33781.159420 # average overall miss latency 230system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 231system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 232system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 233system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 234system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 235system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 236system.cpu0.dcache.fast_writes 0 # number of fast writes performed 237system.cpu0.dcache.cache_copies 0 # number of cache copies performed 238system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 239system.cpu0.dcache.writebacks::total 1 # number of writebacks 240system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses 241system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses 242system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 243system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 244system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 245system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 246system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 # number of demand (read+write) MSHR misses 247system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses 248system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses 249system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses 250system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4325500 # number of ReadReq MSHR miss cycles 251system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4325500 # number of ReadReq MSHR miss cycles 252system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6639000 # number of WriteReq MSHR miss cycles 253system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6639000 # number of WriteReq MSHR miss cycles 254system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311500 # number of SwapReq MSHR miss cycles 255system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311500 # number of SwapReq MSHR miss cycles 256system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10964500 # number of demand (read+write) MSHR miss cycles 257system.cpu0.dcache.demand_mshr_miss_latency::total 10964500 # number of demand (read+write) MSHR miss cycles 258system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10964500 # number of overall MSHR miss cycles 259system.cpu0.dcache.overall_mshr_miss_latency::total 10964500 # number of overall MSHR miss cycles 260system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003319 # mshr miss rate for ReadReq accesses 261system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003319 # mshr miss rate for ReadReq accesses 262system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007359 # mshr miss rate for WriteReq accesses 263system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007359 # mshr miss rate for WriteReq accesses 264system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 265system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses 266system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for demand accesses 267system.cpu0.dcache.demand_mshr_miss_rate::total 0.004683 # mshr miss rate for demand accesses 268system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for overall accesses 269system.cpu0.dcache.overall_mshr_miss_rate::total 0.004683 # mshr miss rate for overall accesses 270system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26700.617284 # average ReadReq mshr miss latency 271system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26700.617284 # average ReadReq mshr miss latency 272system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36278.688525 # average WriteReq mshr miss latency 273system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36278.688525 # average WriteReq mshr miss latency 274system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11980.769231 # average SwapReq mshr miss latency 275system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11980.769231 # average SwapReq mshr miss latency 276system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency 277system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency 278system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency 279system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency 280system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 281system.cpu1.numCycles 523247 # number of cpu cycles simulated 282system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 283system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 284system.cpu1.committedInsts 173283 # Number of instructions committed 285system.cpu1.committedOps 173283 # Number of ops (including micro ops) committed 286system.cpu1.num_int_alu_accesses 108736 # Number of integer alu accesses 287system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 288system.cpu1.num_func_calls 637 # number of times a function call or return occured 289system.cpu1.num_conditional_control_insts 36284 # number of instructions that are conditional controls 290system.cpu1.num_int_insts 108736 # number of integer instructions 291system.cpu1.num_fp_insts 0 # number of float instructions 292system.cpu1.num_int_register_reads 252002 # number of times the integer registers were read 293system.cpu1.num_int_register_writes 93825 # number of times the integer registers were written 294system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 295system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 296system.cpu1.num_mem_refs 48621 # number of memory refs 297system.cpu1.num_load_insts 40031 # Number of load instructions 298system.cpu1.num_store_insts 8590 # Number of store instructions 299system.cpu1.num_idle_cycles 68750.001737 # Number of idle cycles 300system.cpu1.num_busy_cycles 454496.998263 # Number of busy cycles 301system.cpu1.not_idle_fraction 0.868609 # Percentage of non-idle cycles 302system.cpu1.idle_fraction 0.131391 # Percentage of idle cycles 303system.cpu1.icache.replacements 280 # number of replacements 304system.cpu1.icache.tagsinuse 65.593035 # Cycle average of tags in use 305system.cpu1.icache.total_refs 172950 # Total number of references to valid blocks. 306system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. 307system.cpu1.icache.avg_refs 472.540984 # Average number of references to valid blocks. 308system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 309system.cpu1.icache.occ_blocks::cpu1.inst 65.593035 # Average occupied blocks per requestor 310system.cpu1.icache.occ_percent::cpu1.inst 0.128111 # Average percentage of cache occupancy 311system.cpu1.icache.occ_percent::total 0.128111 # Average percentage of cache occupancy 312system.cpu1.icache.ReadReq_hits::cpu1.inst 172950 # number of ReadReq hits 313system.cpu1.icache.ReadReq_hits::total 172950 # number of ReadReq hits 314system.cpu1.icache.demand_hits::cpu1.inst 172950 # number of demand (read+write) hits 315system.cpu1.icache.demand_hits::total 172950 # number of demand (read+write) hits 316system.cpu1.icache.overall_hits::cpu1.inst 172950 # number of overall hits 317system.cpu1.icache.overall_hits::total 172950 # number of overall hits 318system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 319system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 320system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 321system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 322system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 323system.cpu1.icache.overall_misses::total 366 # number of overall misses 324system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5373500 # number of ReadReq miss cycles 325system.cpu1.icache.ReadReq_miss_latency::total 5373500 # number of ReadReq miss cycles 326system.cpu1.icache.demand_miss_latency::cpu1.inst 5373500 # number of demand (read+write) miss cycles 327system.cpu1.icache.demand_miss_latency::total 5373500 # number of demand (read+write) miss cycles 328system.cpu1.icache.overall_miss_latency::cpu1.inst 5373500 # number of overall miss cycles 329system.cpu1.icache.overall_miss_latency::total 5373500 # number of overall miss cycles 330system.cpu1.icache.ReadReq_accesses::cpu1.inst 173316 # number of ReadReq accesses(hits+misses) 331system.cpu1.icache.ReadReq_accesses::total 173316 # number of ReadReq accesses(hits+misses) 332system.cpu1.icache.demand_accesses::cpu1.inst 173316 # number of demand (read+write) accesses 333system.cpu1.icache.demand_accesses::total 173316 # number of demand (read+write) accesses 334system.cpu1.icache.overall_accesses::cpu1.inst 173316 # number of overall (read+write) accesses 335system.cpu1.icache.overall_accesses::total 173316 # number of overall (read+write) accesses 336system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002112 # miss rate for ReadReq accesses 337system.cpu1.icache.ReadReq_miss_rate::total 0.002112 # miss rate for ReadReq accesses 338system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002112 # miss rate for demand accesses 339system.cpu1.icache.demand_miss_rate::total 0.002112 # miss rate for demand accesses 340system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002112 # miss rate for overall accesses 341system.cpu1.icache.overall_miss_rate::total 0.002112 # miss rate for overall accesses 342system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14681.693989 # average ReadReq miss latency 343system.cpu1.icache.ReadReq_avg_miss_latency::total 14681.693989 # average ReadReq miss latency 344system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency 345system.cpu1.icache.demand_avg_miss_latency::total 14681.693989 # average overall miss latency 346system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency 347system.cpu1.icache.overall_avg_miss_latency::total 14681.693989 # average overall miss latency 348system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 349system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 350system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 351system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 352system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 353system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 354system.cpu1.icache.fast_writes 0 # number of fast writes performed 355system.cpu1.icache.cache_copies 0 # number of cache copies performed 356system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 357system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 358system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 359system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 360system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 361system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 362system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4641500 # number of ReadReq MSHR miss cycles 363system.cpu1.icache.ReadReq_mshr_miss_latency::total 4641500 # number of ReadReq MSHR miss cycles 364system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4641500 # number of demand (read+write) MSHR miss cycles 365system.cpu1.icache.demand_mshr_miss_latency::total 4641500 # number of demand (read+write) MSHR miss cycles 366system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4641500 # number of overall MSHR miss cycles 367system.cpu1.icache.overall_mshr_miss_latency::total 4641500 # number of overall MSHR miss cycles 368system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for ReadReq accesses 369system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses 370system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for demand accesses 371system.cpu1.icache.demand_mshr_miss_rate::total 0.002112 # mshr miss rate for demand accesses 372system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for overall accesses 373system.cpu1.icache.overall_mshr_miss_rate::total 0.002112 # mshr miss rate for overall accesses 374system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average ReadReq mshr miss latency 375system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12681.693989 # average ReadReq mshr miss latency 376system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average overall mshr miss latency 377system.cpu1.icache.demand_avg_mshr_miss_latency::total 12681.693989 # average overall mshr miss latency 378system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average overall mshr miss latency 379system.cpu1.icache.overall_avg_mshr_miss_latency::total 12681.693989 # average overall mshr miss latency 380system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 381system.cpu1.dcache.replacements 0 # number of replacements 382system.cpu1.dcache.tagsinuse 25.918058 # Cycle average of tags in use 383system.cpu1.dcache.total_refs 19532 # Total number of references to valid blocks. 384system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. 385system.cpu1.dcache.avg_refs 651.066667 # Average number of references to valid blocks. 386system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 387system.cpu1.dcache.occ_blocks::cpu1.data 25.918058 # Average occupied blocks per requestor 388system.cpu1.dcache.occ_percent::cpu1.data 0.050621 # Average percentage of cache occupancy 389system.cpu1.dcache.occ_percent::total 0.050621 # Average percentage of cache occupancy 390system.cpu1.dcache.ReadReq_hits::cpu1.data 39847 # number of ReadReq hits 391system.cpu1.dcache.ReadReq_hits::total 39847 # number of ReadReq hits 392system.cpu1.dcache.WriteReq_hits::cpu1.data 8412 # number of WriteReq hits 393system.cpu1.dcache.WriteReq_hits::total 8412 # number of WriteReq hits 394system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits 395system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits 396system.cpu1.dcache.demand_hits::cpu1.data 48259 # number of demand (read+write) hits 397system.cpu1.dcache.demand_hits::total 48259 # number of demand (read+write) hits 398system.cpu1.dcache.overall_hits::cpu1.data 48259 # number of overall hits 399system.cpu1.dcache.overall_hits::total 48259 # number of overall hits 400system.cpu1.dcache.ReadReq_misses::cpu1.data 177 # number of ReadReq misses 401system.cpu1.dcache.ReadReq_misses::total 177 # number of ReadReq misses 402system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses 403system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses 404system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses 405system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses 406system.cpu1.dcache.demand_misses::cpu1.data 282 # number of demand (read+write) misses 407system.cpu1.dcache.demand_misses::total 282 # number of demand (read+write) misses 408system.cpu1.dcache.overall_misses::cpu1.data 282 # number of overall misses 409system.cpu1.dcache.overall_misses::total 282 # number of overall misses 410system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3316000 # number of ReadReq miss cycles 411system.cpu1.dcache.ReadReq_miss_latency::total 3316000 # number of ReadReq miss cycles 412system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1875500 # number of WriteReq miss cycles 413system.cpu1.dcache.WriteReq_miss_latency::total 1875500 # number of WriteReq miss cycles 414system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 659500 # number of SwapReq miss cycles 415system.cpu1.dcache.SwapReq_miss_latency::total 659500 # number of SwapReq miss cycles 416system.cpu1.dcache.demand_miss_latency::cpu1.data 5191500 # number of demand (read+write) miss cycles 417system.cpu1.dcache.demand_miss_latency::total 5191500 # number of demand (read+write) miss cycles 418system.cpu1.dcache.overall_miss_latency::cpu1.data 5191500 # number of overall miss cycles 419system.cpu1.dcache.overall_miss_latency::total 5191500 # number of overall miss cycles 420system.cpu1.dcache.ReadReq_accesses::cpu1.data 40024 # number of ReadReq accesses(hits+misses) 421system.cpu1.dcache.ReadReq_accesses::total 40024 # number of ReadReq accesses(hits+misses) 422system.cpu1.dcache.WriteReq_accesses::cpu1.data 8517 # number of WriteReq accesses(hits+misses) 423system.cpu1.dcache.WriteReq_accesses::total 8517 # number of WriteReq accesses(hits+misses) 424system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 425system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 426system.cpu1.dcache.demand_accesses::cpu1.data 48541 # number of demand (read+write) accesses 427system.cpu1.dcache.demand_accesses::total 48541 # number of demand (read+write) accesses 428system.cpu1.dcache.overall_accesses::cpu1.data 48541 # number of overall (read+write) accesses 429system.cpu1.dcache.overall_accesses::total 48541 # number of overall (read+write) accesses 430system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004422 # miss rate for ReadReq accesses 431system.cpu1.dcache.ReadReq_miss_rate::total 0.004422 # miss rate for ReadReq accesses 432system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012328 # miss rate for WriteReq accesses 433system.cpu1.dcache.WriteReq_miss_rate::total 0.012328 # miss rate for WriteReq accesses 434system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.774648 # miss rate for SwapReq accesses 435system.cpu1.dcache.SwapReq_miss_rate::total 0.774648 # miss rate for SwapReq accesses 436system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005810 # miss rate for demand accesses 437system.cpu1.dcache.demand_miss_rate::total 0.005810 # miss rate for demand accesses 438system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005810 # miss rate for overall accesses 439system.cpu1.dcache.overall_miss_rate::total 0.005810 # miss rate for overall accesses 440system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18734.463277 # average ReadReq miss latency 441system.cpu1.dcache.ReadReq_avg_miss_latency::total 18734.463277 # average ReadReq miss latency 442system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17861.904762 # average WriteReq miss latency 443system.cpu1.dcache.WriteReq_avg_miss_latency::total 17861.904762 # average WriteReq miss latency 444system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11990.909091 # average SwapReq miss latency 445system.cpu1.dcache.SwapReq_avg_miss_latency::total 11990.909091 # average SwapReq miss latency 446system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18409.574468 # average overall miss latency 447system.cpu1.dcache.demand_avg_miss_latency::total 18409.574468 # average overall miss latency 448system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18409.574468 # average overall miss latency 449system.cpu1.dcache.overall_avg_miss_latency::total 18409.574468 # average overall miss latency 450system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 451system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 452system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 453system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 454system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 455system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 456system.cpu1.dcache.fast_writes 0 # number of fast writes performed 457system.cpu1.dcache.cache_copies 0 # number of cache copies performed 458system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 177 # number of ReadReq MSHR misses 459system.cpu1.dcache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses 460system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses 461system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 462system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses 463system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses 464system.cpu1.dcache.demand_mshr_misses::cpu1.data 282 # number of demand (read+write) MSHR misses 465system.cpu1.dcache.demand_mshr_misses::total 282 # number of demand (read+write) MSHR misses 466system.cpu1.dcache.overall_mshr_misses::cpu1.data 282 # number of overall MSHR misses 467system.cpu1.dcache.overall_mshr_misses::total 282 # number of overall MSHR misses 468system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2962000 # number of ReadReq MSHR miss cycles 469system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2962000 # number of ReadReq MSHR miss cycles 470system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1665500 # number of WriteReq MSHR miss cycles 471system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1665500 # number of WriteReq MSHR miss cycles 472system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 549500 # number of SwapReq MSHR miss cycles 473system.cpu1.dcache.SwapReq_mshr_miss_latency::total 549500 # number of SwapReq MSHR miss cycles 474system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4627500 # number of demand (read+write) MSHR miss cycles 475system.cpu1.dcache.demand_mshr_miss_latency::total 4627500 # number of demand (read+write) MSHR miss cycles 476system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4627500 # number of overall MSHR miss cycles 477system.cpu1.dcache.overall_mshr_miss_latency::total 4627500 # number of overall MSHR miss cycles 478system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004422 # mshr miss rate for ReadReq accesses 479system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004422 # mshr miss rate for ReadReq accesses 480system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012328 # mshr miss rate for WriteReq accesses 481system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012328 # mshr miss rate for WriteReq accesses 482system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.774648 # mshr miss rate for SwapReq accesses 483system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.774648 # mshr miss rate for SwapReq accesses 484system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for demand accesses 485system.cpu1.dcache.demand_mshr_miss_rate::total 0.005810 # mshr miss rate for demand accesses 486system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for overall accesses 487system.cpu1.dcache.overall_mshr_miss_rate::total 0.005810 # mshr miss rate for overall accesses 488system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16734.463277 # average ReadReq mshr miss latency 489system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16734.463277 # average ReadReq mshr miss latency 490system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15861.904762 # average WriteReq mshr miss latency 491system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15861.904762 # average WriteReq mshr miss latency 492system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 9990.909091 # average SwapReq mshr miss latency 493system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 9990.909091 # average SwapReq mshr miss latency 494system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency 495system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency 496system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency 497system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency 498system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 499system.cpu2.numCycles 523246 # number of cpu cycles simulated 500system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 501system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 502system.cpu2.committedInsts 160665 # Number of instructions committed 503system.cpu2.committedOps 160665 # Number of ops (including micro ops) committed 504system.cpu2.num_int_alu_accesses 113639 # Number of integer alu accesses 505system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 506system.cpu2.num_func_calls 637 # number of times a function call or return occured 507system.cpu2.num_conditional_control_insts 27518 # number of instructions that are conditional controls 508system.cpu2.num_int_insts 113639 # number of integer instructions 509system.cpu2.num_fp_insts 0 # number of float instructions 510system.cpu2.num_int_register_reads 306682 # number of times the integer registers were read 511system.cpu2.num_int_register_writes 118721 # number of times the integer registers were written 512system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 513system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 514system.cpu2.num_mem_refs 62290 # number of memory refs 515system.cpu2.num_load_insts 42488 # Number of load instructions 516system.cpu2.num_store_insts 19802 # Number of store instructions 517system.cpu2.num_idle_cycles 69015.869837 # Number of idle cycles 518system.cpu2.num_busy_cycles 454230.130163 # Number of busy cycles 519system.cpu2.not_idle_fraction 0.868101 # Percentage of non-idle cycles 520system.cpu2.idle_fraction 0.131899 # Percentage of idle cycles 521system.cpu2.icache.replacements 281 # number of replacements 522system.cpu2.icache.tagsinuse 67.731754 # Cycle average of tags in use 523system.cpu2.icache.total_refs 160331 # Total number of references to valid blocks. 524system.cpu2.icache.sampled_refs 367 # Sample count of references to valid blocks. 525system.cpu2.icache.avg_refs 436.869210 # Average number of references to valid blocks. 526system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 527system.cpu2.icache.occ_blocks::cpu2.inst 67.731754 # Average occupied blocks per requestor 528system.cpu2.icache.occ_percent::cpu2.inst 0.132289 # Average percentage of cache occupancy 529system.cpu2.icache.occ_percent::total 0.132289 # Average percentage of cache occupancy 530system.cpu2.icache.ReadReq_hits::cpu2.inst 160331 # number of ReadReq hits 531system.cpu2.icache.ReadReq_hits::total 160331 # number of ReadReq hits 532system.cpu2.icache.demand_hits::cpu2.inst 160331 # number of demand (read+write) hits 533system.cpu2.icache.demand_hits::total 160331 # number of demand (read+write) hits 534system.cpu2.icache.overall_hits::cpu2.inst 160331 # number of overall hits 535system.cpu2.icache.overall_hits::total 160331 # number of overall hits 536system.cpu2.icache.ReadReq_misses::cpu2.inst 367 # number of ReadReq misses 537system.cpu2.icache.ReadReq_misses::total 367 # number of ReadReq misses 538system.cpu2.icache.demand_misses::cpu2.inst 367 # number of demand (read+write) misses 539system.cpu2.icache.demand_misses::total 367 # number of demand (read+write) misses 540system.cpu2.icache.overall_misses::cpu2.inst 367 # number of overall misses 541system.cpu2.icache.overall_misses::total 367 # number of overall misses 542system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5321500 # number of ReadReq miss cycles 543system.cpu2.icache.ReadReq_miss_latency::total 5321500 # number of ReadReq miss cycles 544system.cpu2.icache.demand_miss_latency::cpu2.inst 5321500 # number of demand (read+write) miss cycles 545system.cpu2.icache.demand_miss_latency::total 5321500 # number of demand (read+write) miss cycles 546system.cpu2.icache.overall_miss_latency::cpu2.inst 5321500 # number of overall miss cycles 547system.cpu2.icache.overall_miss_latency::total 5321500 # number of overall miss cycles 548system.cpu2.icache.ReadReq_accesses::cpu2.inst 160698 # number of ReadReq accesses(hits+misses) 549system.cpu2.icache.ReadReq_accesses::total 160698 # number of ReadReq accesses(hits+misses) 550system.cpu2.icache.demand_accesses::cpu2.inst 160698 # number of demand (read+write) accesses 551system.cpu2.icache.demand_accesses::total 160698 # number of demand (read+write) accesses 552system.cpu2.icache.overall_accesses::cpu2.inst 160698 # number of overall (read+write) accesses 553system.cpu2.icache.overall_accesses::total 160698 # number of overall (read+write) accesses 554system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002284 # miss rate for ReadReq accesses 555system.cpu2.icache.ReadReq_miss_rate::total 0.002284 # miss rate for ReadReq accesses 556system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002284 # miss rate for demand accesses 557system.cpu2.icache.demand_miss_rate::total 0.002284 # miss rate for demand accesses 558system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002284 # miss rate for overall accesses 559system.cpu2.icache.overall_miss_rate::total 0.002284 # miss rate for overall accesses 560system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14500 # average ReadReq miss latency 561system.cpu2.icache.ReadReq_avg_miss_latency::total 14500 # average ReadReq miss latency 562system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14500 # average overall miss latency 563system.cpu2.icache.demand_avg_miss_latency::total 14500 # average overall miss latency 564system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14500 # average overall miss latency 565system.cpu2.icache.overall_avg_miss_latency::total 14500 # average overall miss latency 566system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 567system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 568system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 569system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 570system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 571system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 572system.cpu2.icache.fast_writes 0 # number of fast writes performed 573system.cpu2.icache.cache_copies 0 # number of cache copies performed 574system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 367 # number of ReadReq MSHR misses 575system.cpu2.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 576system.cpu2.icache.demand_mshr_misses::cpu2.inst 367 # number of demand (read+write) MSHR misses 577system.cpu2.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 578system.cpu2.icache.overall_mshr_misses::cpu2.inst 367 # number of overall MSHR misses 579system.cpu2.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 580system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4587500 # number of ReadReq MSHR miss cycles 581system.cpu2.icache.ReadReq_mshr_miss_latency::total 4587500 # number of ReadReq MSHR miss cycles 582system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4587500 # number of demand (read+write) MSHR miss cycles 583system.cpu2.icache.demand_mshr_miss_latency::total 4587500 # number of demand (read+write) MSHR miss cycles 584system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4587500 # number of overall MSHR miss cycles 585system.cpu2.icache.overall_mshr_miss_latency::total 4587500 # number of overall MSHR miss cycles 586system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for ReadReq accesses 587system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002284 # mshr miss rate for ReadReq accesses 588system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for demand accesses 589system.cpu2.icache.demand_mshr_miss_rate::total 0.002284 # mshr miss rate for demand accesses 590system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for overall accesses 591system.cpu2.icache.overall_mshr_miss_rate::total 0.002284 # mshr miss rate for overall accesses 592system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12500 # average ReadReq mshr miss latency 593system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12500 # average ReadReq mshr miss latency 594system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency 595system.cpu2.icache.demand_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency 596system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency 597system.cpu2.icache.overall_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency 598system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 599system.cpu2.dcache.replacements 0 # number of replacements 600system.cpu2.dcache.tagsinuse 26.833050 # Cycle average of tags in use 601system.cpu2.dcache.total_refs 41851 # Total number of references to valid blocks. 602system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. 603system.cpu2.dcache.avg_refs 1443.137931 # Average number of references to valid blocks. 604system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 605system.cpu2.dcache.occ_blocks::cpu2.data 26.833050 # Average occupied blocks per requestor 606system.cpu2.dcache.occ_percent::cpu2.data 0.052408 # Average percentage of cache occupancy 607system.cpu2.dcache.occ_percent::total 0.052408 # Average percentage of cache occupancy 608system.cpu2.dcache.ReadReq_hits::cpu2.data 42328 # number of ReadReq hits 609system.cpu2.dcache.ReadReq_hits::total 42328 # number of ReadReq hits 610system.cpu2.dcache.WriteReq_hits::cpu2.data 19626 # number of WriteReq hits 611system.cpu2.dcache.WriteReq_hits::total 19626 # number of WriteReq hits 612system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits 613system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits 614system.cpu2.dcache.demand_hits::cpu2.data 61954 # number of demand (read+write) hits 615system.cpu2.dcache.demand_hits::total 61954 # number of demand (read+write) hits 616system.cpu2.dcache.overall_hits::cpu2.data 61954 # number of overall hits 617system.cpu2.dcache.overall_hits::total 61954 # number of overall hits 618system.cpu2.dcache.ReadReq_misses::cpu2.data 152 # number of ReadReq misses 619system.cpu2.dcache.ReadReq_misses::total 152 # number of ReadReq misses 620system.cpu2.dcache.WriteReq_misses::cpu2.data 106 # number of WriteReq misses 621system.cpu2.dcache.WriteReq_misses::total 106 # number of WriteReq misses 622system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses 623system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses 624system.cpu2.dcache.demand_misses::cpu2.data 258 # number of demand (read+write) misses 625system.cpu2.dcache.demand_misses::total 258 # number of demand (read+write) misses 626system.cpu2.dcache.overall_misses::cpu2.data 258 # number of overall misses 627system.cpu2.dcache.overall_misses::total 258 # number of overall misses 628system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1938000 # number of ReadReq miss cycles 629system.cpu2.dcache.ReadReq_miss_latency::total 1938000 # number of ReadReq miss cycles 630system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2155000 # number of WriteReq miss cycles 631system.cpu2.dcache.WriteReq_miss_latency::total 2155000 # number of WriteReq miss cycles 632system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 612500 # number of SwapReq miss cycles 633system.cpu2.dcache.SwapReq_miss_latency::total 612500 # number of SwapReq miss cycles 634system.cpu2.dcache.demand_miss_latency::cpu2.data 4093000 # number of demand (read+write) miss cycles 635system.cpu2.dcache.demand_miss_latency::total 4093000 # number of demand (read+write) miss cycles 636system.cpu2.dcache.overall_miss_latency::cpu2.data 4093000 # number of overall miss cycles 637system.cpu2.dcache.overall_miss_latency::total 4093000 # number of overall miss cycles 638system.cpu2.dcache.ReadReq_accesses::cpu2.data 42480 # number of ReadReq accesses(hits+misses) 639system.cpu2.dcache.ReadReq_accesses::total 42480 # number of ReadReq accesses(hits+misses) 640system.cpu2.dcache.WriteReq_accesses::cpu2.data 19732 # number of WriteReq accesses(hits+misses) 641system.cpu2.dcache.WriteReq_accesses::total 19732 # number of WriteReq accesses(hits+misses) 642system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) 643system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) 644system.cpu2.dcache.demand_accesses::cpu2.data 62212 # number of demand (read+write) accesses 645system.cpu2.dcache.demand_accesses::total 62212 # number of demand (read+write) accesses 646system.cpu2.dcache.overall_accesses::cpu2.data 62212 # number of overall (read+write) accesses 647system.cpu2.dcache.overall_accesses::total 62212 # number of overall (read+write) accesses 648system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003578 # miss rate for ReadReq accesses 649system.cpu2.dcache.ReadReq_miss_rate::total 0.003578 # miss rate for ReadReq accesses 650system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005372 # miss rate for WriteReq accesses 651system.cpu2.dcache.WriteReq_miss_rate::total 0.005372 # miss rate for WriteReq accesses 652system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.852941 # miss rate for SwapReq accesses 653system.cpu2.dcache.SwapReq_miss_rate::total 0.852941 # miss rate for SwapReq accesses 654system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004147 # miss rate for demand accesses 655system.cpu2.dcache.demand_miss_rate::total 0.004147 # miss rate for demand accesses 656system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004147 # miss rate for overall accesses 657system.cpu2.dcache.overall_miss_rate::total 0.004147 # miss rate for overall accesses 658system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12750 # average ReadReq miss latency 659system.cpu2.dcache.ReadReq_avg_miss_latency::total 12750 # average ReadReq miss latency 660system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20330.188679 # average WriteReq miss latency 661system.cpu2.dcache.WriteReq_avg_miss_latency::total 20330.188679 # average WriteReq miss latency 662system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10560.344828 # average SwapReq miss latency 663system.cpu2.dcache.SwapReq_avg_miss_latency::total 10560.344828 # average SwapReq miss latency 664system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency 665system.cpu2.dcache.demand_avg_miss_latency::total 15864.341085 # average overall miss latency 666system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency 667system.cpu2.dcache.overall_avg_miss_latency::total 15864.341085 # average overall miss latency 668system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 669system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 670system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 671system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 672system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 673system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 674system.cpu2.dcache.fast_writes 0 # number of fast writes performed 675system.cpu2.dcache.cache_copies 0 # number of cache copies performed 676system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses 677system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses 678system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses 679system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 680system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses 681system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses 682system.cpu2.dcache.demand_mshr_misses::cpu2.data 258 # number of demand (read+write) MSHR misses 683system.cpu2.dcache.demand_mshr_misses::total 258 # number of demand (read+write) MSHR misses 684system.cpu2.dcache.overall_mshr_misses::cpu2.data 258 # number of overall MSHR misses 685system.cpu2.dcache.overall_mshr_misses::total 258 # number of overall MSHR misses 686system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1634000 # number of ReadReq MSHR miss cycles 687system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1634000 # number of ReadReq MSHR miss cycles 688system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1943000 # number of WriteReq MSHR miss cycles 689system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1943000 # number of WriteReq MSHR miss cycles 690system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 496500 # number of SwapReq MSHR miss cycles 691system.cpu2.dcache.SwapReq_mshr_miss_latency::total 496500 # number of SwapReq MSHR miss cycles 692system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3577000 # number of demand (read+write) MSHR miss cycles 693system.cpu2.dcache.demand_mshr_miss_latency::total 3577000 # number of demand (read+write) MSHR miss cycles 694system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3577000 # number of overall MSHR miss cycles 695system.cpu2.dcache.overall_mshr_miss_latency::total 3577000 # number of overall MSHR miss cycles 696system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003578 # mshr miss rate for ReadReq accesses 697system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003578 # mshr miss rate for ReadReq accesses 698system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.005372 # mshr miss rate for WriteReq accesses 699system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.005372 # mshr miss rate for WriteReq accesses 700system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.852941 # mshr miss rate for SwapReq accesses 701system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.852941 # mshr miss rate for SwapReq accesses 702system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for demand accesses 703system.cpu2.dcache.demand_mshr_miss_rate::total 0.004147 # mshr miss rate for demand accesses 704system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for overall accesses 705system.cpu2.dcache.overall_mshr_miss_rate::total 0.004147 # mshr miss rate for overall accesses 706system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10750 # average ReadReq mshr miss latency 707system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10750 # average ReadReq mshr miss latency 708system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 18330.188679 # average WriteReq mshr miss latency 709system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 18330.188679 # average WriteReq mshr miss latency 710system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8560.344828 # average SwapReq mshr miss latency 711system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8560.344828 # average SwapReq mshr miss latency 712system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency 713system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency 714system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency 715system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency 716system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 717system.cpu3.numCycles 523246 # number of cpu cycles simulated 718system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 719system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 720system.cpu3.committedInsts 168281 # Number of instructions committed 721system.cpu3.committedOps 168281 # Number of ops (including micro ops) committed 722system.cpu3.num_int_alu_accesses 108796 # Number of integer alu accesses 723system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 724system.cpu3.num_func_calls 637 # number of times a function call or return occured 725system.cpu3.num_conditional_control_insts 33752 # number of instructions that are conditional controls 726system.cpu3.num_int_insts 108796 # number of integer instructions 727system.cpu3.num_fp_insts 0 # number of float instructions 728system.cpu3.num_int_register_reads 262371 # number of times the integer registers were read 729system.cpu3.num_int_register_writes 98980 # number of times the integer registers were written 730system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 731system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 732system.cpu3.num_mem_refs 51213 # number of memory refs 733system.cpu3.num_load_insts 40064 # Number of load instructions 734system.cpu3.num_store_insts 11149 # Number of store instructions 735system.cpu3.num_idle_cycles 69253.869381 # Number of idle cycles 736system.cpu3.num_busy_cycles 453992.130619 # Number of busy cycles 737system.cpu3.not_idle_fraction 0.867646 # Percentage of non-idle cycles 738system.cpu3.idle_fraction 0.132354 # Percentage of idle cycles 739system.cpu3.icache.replacements 280 # number of replacements 740system.cpu3.icache.tagsinuse 70.063196 # Cycle average of tags in use 741system.cpu3.icache.total_refs 167948 # Total number of references to valid blocks. 742system.cpu3.icache.sampled_refs 366 # Sample count of references to valid blocks. 743system.cpu3.icache.avg_refs 458.874317 # Average number of references to valid blocks. 744system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 745system.cpu3.icache.occ_blocks::cpu3.inst 70.063196 # Average occupied blocks per requestor 746system.cpu3.icache.occ_percent::cpu3.inst 0.136842 # Average percentage of cache occupancy 747system.cpu3.icache.occ_percent::total 0.136842 # Average percentage of cache occupancy 748system.cpu3.icache.ReadReq_hits::cpu3.inst 167948 # number of ReadReq hits 749system.cpu3.icache.ReadReq_hits::total 167948 # number of ReadReq hits 750system.cpu3.icache.demand_hits::cpu3.inst 167948 # number of demand (read+write) hits 751system.cpu3.icache.demand_hits::total 167948 # number of demand (read+write) hits 752system.cpu3.icache.overall_hits::cpu3.inst 167948 # number of overall hits 753system.cpu3.icache.overall_hits::total 167948 # number of overall hits 754system.cpu3.icache.ReadReq_misses::cpu3.inst 366 # number of ReadReq misses 755system.cpu3.icache.ReadReq_misses::total 366 # number of ReadReq misses 756system.cpu3.icache.demand_misses::cpu3.inst 366 # number of demand (read+write) misses 757system.cpu3.icache.demand_misses::total 366 # number of demand (read+write) misses 758system.cpu3.icache.overall_misses::cpu3.inst 366 # number of overall misses 759system.cpu3.icache.overall_misses::total 366 # number of overall misses 760system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7343000 # number of ReadReq miss cycles 761system.cpu3.icache.ReadReq_miss_latency::total 7343000 # number of ReadReq miss cycles 762system.cpu3.icache.demand_miss_latency::cpu3.inst 7343000 # number of demand (read+write) miss cycles 763system.cpu3.icache.demand_miss_latency::total 7343000 # number of demand (read+write) miss cycles 764system.cpu3.icache.overall_miss_latency::cpu3.inst 7343000 # number of overall miss cycles 765system.cpu3.icache.overall_miss_latency::total 7343000 # number of overall miss cycles 766system.cpu3.icache.ReadReq_accesses::cpu3.inst 168314 # number of ReadReq accesses(hits+misses) 767system.cpu3.icache.ReadReq_accesses::total 168314 # number of ReadReq accesses(hits+misses) 768system.cpu3.icache.demand_accesses::cpu3.inst 168314 # number of demand (read+write) accesses 769system.cpu3.icache.demand_accesses::total 168314 # number of demand (read+write) accesses 770system.cpu3.icache.overall_accesses::cpu3.inst 168314 # number of overall (read+write) accesses 771system.cpu3.icache.overall_accesses::total 168314 # number of overall (read+write) accesses 772system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002175 # miss rate for ReadReq accesses 773system.cpu3.icache.ReadReq_miss_rate::total 0.002175 # miss rate for ReadReq accesses 774system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002175 # miss rate for demand accesses 775system.cpu3.icache.demand_miss_rate::total 0.002175 # miss rate for demand accesses 776system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002175 # miss rate for overall accesses 777system.cpu3.icache.overall_miss_rate::total 0.002175 # miss rate for overall accesses 778system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 20062.841530 # average ReadReq miss latency 779system.cpu3.icache.ReadReq_avg_miss_latency::total 20062.841530 # average ReadReq miss latency 780system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 20062.841530 # average overall miss latency 781system.cpu3.icache.demand_avg_miss_latency::total 20062.841530 # average overall miss latency 782system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 20062.841530 # average overall miss latency 783system.cpu3.icache.overall_avg_miss_latency::total 20062.841530 # average overall miss latency 784system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 785system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 786system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 787system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 788system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 789system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 790system.cpu3.icache.fast_writes 0 # number of fast writes performed 791system.cpu3.icache.cache_copies 0 # number of cache copies performed 792system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 366 # number of ReadReq MSHR misses 793system.cpu3.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 794system.cpu3.icache.demand_mshr_misses::cpu3.inst 366 # number of demand (read+write) MSHR misses 795system.cpu3.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 796system.cpu3.icache.overall_mshr_misses::cpu3.inst 366 # number of overall MSHR misses 797system.cpu3.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 798system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6611000 # number of ReadReq MSHR miss cycles 799system.cpu3.icache.ReadReq_mshr_miss_latency::total 6611000 # number of ReadReq MSHR miss cycles 800system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6611000 # number of demand (read+write) MSHR miss cycles 801system.cpu3.icache.demand_mshr_miss_latency::total 6611000 # number of demand (read+write) MSHR miss cycles 802system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6611000 # number of overall MSHR miss cycles 803system.cpu3.icache.overall_mshr_miss_latency::total 6611000 # number of overall MSHR miss cycles 804system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for ReadReq accesses 805system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002175 # mshr miss rate for ReadReq accesses 806system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for demand accesses 807system.cpu3.icache.demand_mshr_miss_rate::total 0.002175 # mshr miss rate for demand accesses 808system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for overall accesses 809system.cpu3.icache.overall_mshr_miss_rate::total 0.002175 # mshr miss rate for overall accesses 810system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average ReadReq mshr miss latency 811system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 18062.841530 # average ReadReq mshr miss latency 812system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average overall mshr miss latency 813system.cpu3.icache.demand_avg_mshr_miss_latency::total 18062.841530 # average overall mshr miss latency 814system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average overall mshr miss latency 815system.cpu3.icache.overall_avg_mshr_miss_latency::total 18062.841530 # average overall mshr miss latency 816system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 817system.cpu3.dcache.replacements 0 # number of replacements 818system.cpu3.dcache.tagsinuse 27.713697 # Cycle average of tags in use 819system.cpu3.dcache.total_refs 24536 # Total number of references to valid blocks. 820system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. 821system.cpu3.dcache.avg_refs 846.068966 # Average number of references to valid blocks. 822system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 823system.cpu3.dcache.occ_blocks::cpu3.data 27.713697 # Average occupied blocks per requestor 824system.cpu3.dcache.occ_percent::cpu3.data 0.054128 # Average percentage of cache occupancy 825system.cpu3.dcache.occ_percent::total 0.054128 # Average percentage of cache occupancy 826system.cpu3.dcache.ReadReq_hits::cpu3.data 39885 # number of ReadReq hits 827system.cpu3.dcache.ReadReq_hits::total 39885 # number of ReadReq hits 828system.cpu3.dcache.WriteReq_hits::cpu3.data 10974 # number of WriteReq hits 829system.cpu3.dcache.WriteReq_hits::total 10974 # number of WriteReq hits 830system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits 831system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits 832system.cpu3.dcache.demand_hits::cpu3.data 50859 # number of demand (read+write) hits 833system.cpu3.dcache.demand_hits::total 50859 # number of demand (read+write) hits 834system.cpu3.dcache.overall_hits::cpu3.data 50859 # number of overall hits 835system.cpu3.dcache.overall_hits::total 50859 # number of overall hits 836system.cpu3.dcache.ReadReq_misses::cpu3.data 172 # number of ReadReq misses 837system.cpu3.dcache.ReadReq_misses::total 172 # number of ReadReq misses 838system.cpu3.dcache.WriteReq_misses::cpu3.data 104 # number of WriteReq misses 839system.cpu3.dcache.WriteReq_misses::total 104 # number of WriteReq misses 840system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses 841system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses 842system.cpu3.dcache.demand_misses::cpu3.data 276 # number of demand (read+write) misses 843system.cpu3.dcache.demand_misses::total 276 # number of demand (read+write) misses 844system.cpu3.dcache.overall_misses::cpu3.data 276 # number of overall misses 845system.cpu3.dcache.overall_misses::total 276 # number of overall misses 846system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3405000 # number of ReadReq miss cycles 847system.cpu3.dcache.ReadReq_miss_latency::total 3405000 # number of ReadReq miss cycles 848system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1971500 # number of WriteReq miss cycles 849system.cpu3.dcache.WriteReq_miss_latency::total 1971500 # number of WriteReq miss cycles 850system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 653500 # number of SwapReq miss cycles 851system.cpu3.dcache.SwapReq_miss_latency::total 653500 # number of SwapReq miss cycles 852system.cpu3.dcache.demand_miss_latency::cpu3.data 5376500 # number of demand (read+write) miss cycles 853system.cpu3.dcache.demand_miss_latency::total 5376500 # number of demand (read+write) miss cycles 854system.cpu3.dcache.overall_miss_latency::cpu3.data 5376500 # number of overall miss cycles 855system.cpu3.dcache.overall_miss_latency::total 5376500 # number of overall miss cycles 856system.cpu3.dcache.ReadReq_accesses::cpu3.data 40057 # number of ReadReq accesses(hits+misses) 857system.cpu3.dcache.ReadReq_accesses::total 40057 # number of ReadReq accesses(hits+misses) 858system.cpu3.dcache.WriteReq_accesses::cpu3.data 11078 # number of WriteReq accesses(hits+misses) 859system.cpu3.dcache.WriteReq_accesses::total 11078 # number of WriteReq accesses(hits+misses) 860system.cpu3.dcache.SwapReq_accesses::cpu3.data 69 # number of SwapReq accesses(hits+misses) 861system.cpu3.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) 862system.cpu3.dcache.demand_accesses::cpu3.data 51135 # number of demand (read+write) accesses 863system.cpu3.dcache.demand_accesses::total 51135 # number of demand (read+write) accesses 864system.cpu3.dcache.overall_accesses::cpu3.data 51135 # number of overall (read+write) accesses 865system.cpu3.dcache.overall_accesses::total 51135 # number of overall (read+write) accesses 866system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004294 # miss rate for ReadReq accesses 867system.cpu3.dcache.ReadReq_miss_rate::total 0.004294 # miss rate for ReadReq accesses 868system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.009388 # miss rate for WriteReq accesses 869system.cpu3.dcache.WriteReq_miss_rate::total 0.009388 # miss rate for WriteReq accesses 870system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.797101 # miss rate for SwapReq accesses 871system.cpu3.dcache.SwapReq_miss_rate::total 0.797101 # miss rate for SwapReq accesses 872system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005397 # miss rate for demand accesses 873system.cpu3.dcache.demand_miss_rate::total 0.005397 # miss rate for demand accesses 874system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005397 # miss rate for overall accesses 875system.cpu3.dcache.overall_miss_rate::total 0.005397 # miss rate for overall accesses 876system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 19796.511628 # average ReadReq miss latency 877system.cpu3.dcache.ReadReq_avg_miss_latency::total 19796.511628 # average ReadReq miss latency 878system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18956.730769 # average WriteReq miss latency 879system.cpu3.dcache.WriteReq_avg_miss_latency::total 18956.730769 # average WriteReq miss latency 880system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11881.818182 # average SwapReq miss latency 881system.cpu3.dcache.SwapReq_avg_miss_latency::total 11881.818182 # average SwapReq miss latency 882system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19480.072464 # average overall miss latency 883system.cpu3.dcache.demand_avg_miss_latency::total 19480.072464 # average overall miss latency 884system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19480.072464 # average overall miss latency 885system.cpu3.dcache.overall_avg_miss_latency::total 19480.072464 # average overall miss latency 886system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 887system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 888system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 889system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 890system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 891system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 892system.cpu3.dcache.fast_writes 0 # number of fast writes performed 893system.cpu3.dcache.cache_copies 0 # number of cache copies performed 894system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 172 # number of ReadReq MSHR misses 895system.cpu3.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses 896system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses 897system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses 898system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 55 # number of SwapReq MSHR misses 899system.cpu3.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses 900system.cpu3.dcache.demand_mshr_misses::cpu3.data 276 # number of demand (read+write) MSHR misses 901system.cpu3.dcache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses 902system.cpu3.dcache.overall_mshr_misses::cpu3.data 276 # number of overall MSHR misses 903system.cpu3.dcache.overall_mshr_misses::total 276 # number of overall MSHR misses 904system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3061000 # number of ReadReq MSHR miss cycles 905system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3061000 # number of ReadReq MSHR miss cycles 906system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1763500 # number of WriteReq MSHR miss cycles 907system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1763500 # number of WriteReq MSHR miss cycles 908system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 543500 # number of SwapReq MSHR miss cycles 909system.cpu3.dcache.SwapReq_mshr_miss_latency::total 543500 # number of SwapReq MSHR miss cycles 910system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4824500 # number of demand (read+write) MSHR miss cycles 911system.cpu3.dcache.demand_mshr_miss_latency::total 4824500 # number of demand (read+write) MSHR miss cycles 912system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4824500 # number of overall MSHR miss cycles 913system.cpu3.dcache.overall_mshr_miss_latency::total 4824500 # number of overall MSHR miss cycles 914system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004294 # mshr miss rate for ReadReq accesses 915system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004294 # mshr miss rate for ReadReq accesses 916system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.009388 # mshr miss rate for WriteReq accesses 917system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.009388 # mshr miss rate for WriteReq accesses 918system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.797101 # mshr miss rate for SwapReq accesses 919system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.797101 # mshr miss rate for SwapReq accesses 920system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005397 # mshr miss rate for demand accesses 921system.cpu3.dcache.demand_mshr_miss_rate::total 0.005397 # mshr miss rate for demand accesses 922system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005397 # mshr miss rate for overall accesses 923system.cpu3.dcache.overall_mshr_miss_rate::total 0.005397 # mshr miss rate for overall accesses 924system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17796.511628 # average ReadReq mshr miss latency 925system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 17796.511628 # average ReadReq mshr miss latency 926system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16956.730769 # average WriteReq mshr miss latency 927system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16956.730769 # average WriteReq mshr miss latency 928system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9881.818182 # average SwapReq mshr miss latency 929system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9881.818182 # average SwapReq mshr miss latency 930system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 17480.072464 # average overall mshr miss latency 931system.cpu3.dcache.demand_avg_mshr_miss_latency::total 17480.072464 # average overall mshr miss latency 932system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 17480.072464 # average overall mshr miss latency 933system.cpu3.dcache.overall_avg_mshr_miss_latency::total 17480.072464 # average overall mshr miss latency 934system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 935system.l2c.replacements 0 # number of replacements 936system.l2c.tagsinuse 349.154335 # Cycle average of tags in use 937system.l2c.total_refs 1221 # Total number of references to valid blocks. 938system.l2c.sampled_refs 429 # Sample count of references to valid blocks. 939system.l2c.avg_refs 2.846154 # Average number of references to valid blocks. 940system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 941system.l2c.occ_blocks::writebacks 0.889459 # Average occupied blocks per requestor 942system.l2c.occ_blocks::cpu0.inst 231.842883 # Average occupied blocks per requestor 943system.l2c.occ_blocks::cpu0.data 54.217473 # Average occupied blocks per requestor 944system.l2c.occ_blocks::cpu1.inst 6.219466 # Average occupied blocks per requestor 945system.l2c.occ_blocks::cpu1.data 0.812784 # Average occupied blocks per requestor 946system.l2c.occ_blocks::cpu2.inst 1.917796 # Average occupied blocks per requestor 947system.l2c.occ_blocks::cpu2.data 0.863537 # Average occupied blocks per requestor 948system.l2c.occ_blocks::cpu3.inst 46.262373 # Average occupied blocks per requestor 949system.l2c.occ_blocks::cpu3.data 6.128563 # Average occupied blocks per requestor 950system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy 951system.l2c.occ_percent::cpu0.inst 0.003538 # Average percentage of cache occupancy 952system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy 953system.l2c.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy 954system.l2c.occ_percent::cpu1.data 0.000012 # Average percentage of cache occupancy 955system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy 956system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy 957system.l2c.occ_percent::cpu3.inst 0.000706 # Average percentage of cache occupancy 958system.l2c.occ_percent::cpu3.data 0.000094 # Average percentage of cache occupancy 959system.l2c.occ_percent::total 0.005328 # Average percentage of cache occupancy 960system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits 961system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 962system.l2c.ReadReq_hits::cpu1.inst 352 # number of ReadReq hits 963system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits 964system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits 965system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits 966system.l2c.ReadReq_hits::cpu3.inst 306 # number of ReadReq hits 967system.l2c.ReadReq_hits::cpu3.data 3 # number of ReadReq hits 968system.l2c.ReadReq_hits::total 1221 # number of ReadReq hits 969system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 970system.l2c.Writeback_hits::total 1 # number of Writeback hits 971system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 972system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 973system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits 974system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 975system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits 976system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits 977system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits 978system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 979system.l2c.demand_hits::cpu3.inst 306 # number of demand (read+write) hits 980system.l2c.demand_hits::cpu3.data 3 # number of demand (read+write) hits 981system.l2c.demand_hits::total 1221 # number of demand (read+write) hits 982system.l2c.overall_hits::cpu0.inst 182 # number of overall hits 983system.l2c.overall_hits::cpu0.data 5 # number of overall hits 984system.l2c.overall_hits::cpu1.inst 352 # number of overall hits 985system.l2c.overall_hits::cpu1.data 9 # number of overall hits 986system.l2c.overall_hits::cpu2.inst 355 # number of overall hits 987system.l2c.overall_hits::cpu2.data 9 # number of overall hits 988system.l2c.overall_hits::cpu3.inst 306 # number of overall hits 989system.l2c.overall_hits::cpu3.data 3 # number of overall hits 990system.l2c.overall_hits::total 1221 # number of overall hits 991system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses 992system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 993system.l2c.ReadReq_misses::cpu1.inst 14 # number of ReadReq misses 994system.l2c.ReadReq_misses::cpu1.data 2 # number of ReadReq misses 995system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses 996system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses 997system.l2c.ReadReq_misses::cpu3.inst 60 # number of ReadReq misses 998system.l2c.ReadReq_misses::cpu3.data 8 # number of ReadReq misses 999system.l2c.ReadReq_misses::total 449 # number of ReadReq misses 1000system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses 1001system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses 1002system.l2c.UpgradeReq_misses::cpu2.data 20 # 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number of overall MSHR miss cycles 1265system.l2c.overall_mshr_miss_latency::cpu3.inst 2120000 # number of overall MSHR miss cycles 1266system.l2c.overall_mshr_miss_latency::cpu3.data 889500 # number of overall MSHR miss cycles 1267system.l2c.overall_mshr_miss_latency::total 22910000 # number of overall MSHR miss cycles 1268system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses 1269system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses 1270system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadReq accesses 1271system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadReq accesses 1272system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024523 # mshr miss rate for ReadReq accesses 1273system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for ReadReq accesses 1274system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.144809 # mshr miss rate for ReadReq accesses 1275system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.636364 # mshr miss rate for ReadReq accesses 1276system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses 1277system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 1278system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 1279system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 1280system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 1281system.l2c.UpgradeReq_mshr_miss_rate::total 0.977011 # mshr miss rate for UpgradeReq accesses 1282system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 1283system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 1284system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 1285system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 1286system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1287system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 1288system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses 1289system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for demand accesses 1290system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses 1291system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024523 # mshr miss rate for demand accesses 1292system.l2c.demand_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for demand accesses 1293system.l2c.demand_mshr_miss_rate::cpu3.inst 0.144809 # mshr miss rate for demand accesses 1294system.l2c.demand_mshr_miss_rate::cpu3.data 0.846154 # mshr miss rate for demand accesses 1295system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses 1296system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 1297system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 1298system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses 1299system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses 1300system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024523 # mshr miss rate for overall accesses 1301system.l2c.overall_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for overall accesses 1302system.l2c.overall_mshr_miss_rate::cpu3.inst 0.144809 # mshr miss rate for overall accesses 1303system.l2c.overall_mshr_miss_rate::cpu3.data 0.846154 # mshr miss rate for overall accesses 1304system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses 1305system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average ReadReq mshr miss latency 1306system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency 1307system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average ReadReq mshr miss latency 1308system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency 1309system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency 1310system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency 1311system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency 1312system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency 1313system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.930233 # average ReadReq mshr miss latency 1314system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40160.392857 # average UpgradeReq mshr miss latency 1315system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40138.611111 # average UpgradeReq mshr miss latency 1316system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency 1317system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40105.052632 # average UpgradeReq mshr miss latency 1318system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40105.670588 # average UpgradeReq mshr miss latency 1319system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency 1320system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40357.142857 # average ReadExReq mshr miss latency 1321system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40464.285714 # average ReadExReq mshr miss latency 1322system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40633.333333 # average ReadExReq mshr miss latency 1323system.l2c.ReadExReq_avg_mshr_miss_latency::total 40147.887324 # average ReadExReq mshr miss latency 1324system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency 1325system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency 1326system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency 1327system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency 1328system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency 1329system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency 1330system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 1331system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency 1332system.l2c.demand_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency 1333system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency 1334system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency 1335system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency 1336system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency 1337system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency 1338system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency 1339system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 1340system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency 1341system.l2c.overall_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency 1342system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1343 1344---------- End Simulation Statistics ---------- 1345