xref: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000269                       # Number of seconds simulated
sim_ticks                                   268898000                       # Number of ticks simulated
final_tick                                  268898000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1131883                       # Simulator instruction rate (inst/s)
host_op_rate                                  1131850                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              454173870                       # Simulator tick rate (ticks/s)
host_mem_usage                                 240368                       # Number of bytes of host memory used
host_seconds                                     0.59                       # Real time elapsed on the host
sim_insts                                      670104                       # Number of instructions simulated
sim_ops                                        670104                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst            18240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst             3776                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data             1408                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst              128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data              960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data             1024                       # Number of bytes read from this memory
system.physmem.bytes_read::total                36608                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        18240                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst         3776                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst          128                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          512                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           22656                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               285                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               165                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                59                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                22                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                 2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                 8                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                16                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   572                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst            67832412                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            39271397                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst            14042499                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             5236186                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst              476017                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             3570127                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             1904068                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             3808135                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               136140842                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst       67832412                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst       14042499                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst         476017                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        1904068                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           84254996                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst           67832412                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           39271397                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst           14042499                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            5236186                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst             476017                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            3570127                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            1904068                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            3808135                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              136140842                       # Total bandwidth to/from this memory (bytes/s)
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          537796                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                     160914                       # Number of instructions committed
system.cpu0.committedOps                       160914                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses               110768                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts        26422                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                      110768                       # number of integer instructions
system.cpu0.num_fp_insts                            0                       # number of float instructions
system.cpu0.num_int_register_reads             320462                       # number of times the integer registers were read
system.cpu0.num_int_register_writes            112374                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu0.num_mem_refs                        75191                       # number of memory refs
system.cpu0.num_load_insts                      49787                       # Number of load instructions
system.cpu0.num_store_insts                     25404                       # Number of store instructions
system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
system.cpu0.num_busy_cycles                    537796                       # Number of busy cycles
system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
system.cpu0.icache.replacements                   215                       # number of replacements
system.cpu0.icache.tagsinuse               212.263647                       # Cycle average of tags in use
system.cpu0.icache.total_refs                  160510                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                   467                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                343.704497                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   212.263647                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.414577                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.414577                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst       160510                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total         160510                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst       160510                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total          160510                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst       160510                       # number of overall hits
system.cpu0.icache.overall_hits::total         160510                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
system.cpu0.icache.overall_misses::total          467                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     18554000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     18554000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     18554000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     18554000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     18554000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     18554000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst       160977                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total       160977                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst       160977                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total       160977                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst       160977                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total       160977                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002901                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.002901                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002901                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.002901                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002901                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.002901                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39730.192719                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 39730.192719                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39730.192719                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 39730.192719                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39730.192719                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 39730.192719                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          467                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          467                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          467                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          467                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          467                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          467                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     17153000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     17153000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     17153000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     17153000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     17153000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     17153000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.002901                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.002901                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.002901                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.002901                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.002901                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.002901                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36730.192719                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36730.192719                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36730.192719                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 36730.192719                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36730.192719                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 36730.192719                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                     2                       # number of replacements
system.cpu0.dcache.tagsinuse               145.520681                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                   74667                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                   167                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                447.107784                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   145.520681                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.284220                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.284220                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data        49615                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          49615                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        25170                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         25170                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           16                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data        74785                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total           74785                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data        74785                       # number of overall hits
system.cpu0.dcache.overall_hits::total          74785                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          162                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          162                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          183                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          183                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           26                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           26                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data          345                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total           345                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data          345                       # number of overall misses
system.cpu0.dcache.overall_misses::total          345                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data      5171000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total      5171000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      7310000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total      7310000                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       522000                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       522000                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     12481000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     12481000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     12481000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     12481000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        49777                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        49777                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        25353                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        25353                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data        75130                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total        75130                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data        75130                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total        75130                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003255                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.003255                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007218                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.007218                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.619048                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.619048                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.004592                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.004592                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.004592                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.004592                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31919.753086                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 31919.753086                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39945.355191                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 39945.355191                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20076.923077                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 20076.923077                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36176.811594                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 36176.811594                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36176.811594                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 36176.811594                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          162                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          162                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          183                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          183                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           26                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           26                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          345                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          345                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          345                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          345                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4684001                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4684001                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6761000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6761000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       444000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       444000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     11445001                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     11445001                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     11445001                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     11445001                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003255                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003255                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007218                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007218                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.619048                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.619048                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.004592                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.004592                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.004592                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.004592                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28913.586420                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28913.586420                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36945.355191                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36945.355191                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17076.923077                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17076.923077                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33173.915942                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33173.915942                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33173.915942                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33173.915942                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                          537796                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                     159902                       # Number of instructions committed
system.cpu1.committedOps                       159902                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses               114536                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                        637                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts        26689                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                      114536                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads             313629                       # number of times the integer registers were read
system.cpu1.num_int_register_writes            121810                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_mem_refs                        64016                       # number of memory refs
system.cpu1.num_load_insts                      42937                       # Number of load instructions
system.cpu1.num_store_insts                     21079                       # Number of store instructions
system.cpu1.num_idle_cycles              71578.001734                       # Number of idle cycles
system.cpu1.num_busy_cycles              466217.998266                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.866905                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.133095                       # Percentage of idle cycles
system.cpu1.icache.replacements                   280                       # number of replacements
system.cpu1.icache.tagsinuse                69.905818                       # Cycle average of tags in use
system.cpu1.icache.total_refs                  159569                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                   366                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                435.980874                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst    69.905818                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.136535                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.136535                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst       159569                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total         159569                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst       159569                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total          159569                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst       159569                       # number of overall hits
system.cpu1.icache.overall_hits::total         159569                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          366                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          366                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          366                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           366                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          366                       # number of overall misses
system.cpu1.icache.overall_misses::total          366                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7984500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total      7984500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst      7984500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total      7984500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst      7984500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total      7984500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst       159935                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total       159935                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst       159935                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total       159935                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst       159935                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total       159935                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002288                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.002288                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002288                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.002288                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002288                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.002288                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21815.573770                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 21815.573770                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21815.573770                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 21815.573770                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21815.573770                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 21815.573770                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          366                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          366                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          366                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      6886000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total      6886000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      6886000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total      6886000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      6886000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total      6886000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.002288                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.002288                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.002288                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.002288                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.002288                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.002288                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18814.207650                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18814.207650                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18814.207650                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 18814.207650                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18814.207650                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 18814.207650                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                     0                       # number of replacements
system.cpu1.dcache.tagsinuse                27.731515                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                   44449                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs               1532.724138                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data    27.731515                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.054163                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.054163                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data        42776                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          42776                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        20903                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         20903                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           10                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             10                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        63679                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           63679                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        63679                       # number of overall hits
system.cpu1.dcache.overall_hits::total          63679                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          153                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          153                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          106                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          106                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           58                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          259                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           259                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          259                       # number of overall misses
system.cpu1.dcache.overall_misses::total          259                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      3030000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      3030000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2410000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      2410000                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       772000                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       772000                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data      5440000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total      5440000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data      5440000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total      5440000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        42929                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        42929                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        21009                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        21009                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           68                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        63938                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        63938                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        63938                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        63938                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.003564                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.003564                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.005045                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.005045                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.852941                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.852941                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.004051                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.004051                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.004051                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.004051                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19803.921569                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 19803.921569                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22735.849057                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 22735.849057                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13310.344828                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total 13310.344828                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21003.861004                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 21003.861004                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21003.861004                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 21003.861004                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          153                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          153                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          106                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           58                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          259                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          259                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          259                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          259                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2570001                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2570001                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      2092000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      2092000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       598000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       598000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      4662001                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      4662001                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      4662001                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      4662001                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003564                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003564                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.005045                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.005045                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.852941                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.852941                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.004051                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.004051                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.004051                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.004051                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16797.392157                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16797.392157                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19735.849057                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19735.849057                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10310.344828                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10310.344828                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18000.003861                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18000.003861                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18000.003861                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18000.003861                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.numCycles                          537796                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.committedInsts                     177221                       # Number of instructions committed
system.cpu2.committedOps                       177221                       # Number of ops (including micro ops) committed
system.cpu2.num_int_alu_accesses               109567                       # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu2.num_func_calls                        637                       # number of times a function call or return occured
system.cpu2.num_conditional_control_insts        37840                       # number of instructions that are conditional controls
system.cpu2.num_int_insts                      109567                       # number of integer instructions
system.cpu2.num_fp_insts                            0                       # number of float instructions
system.cpu2.num_int_register_reads             249142                       # number of times the integer registers were read
system.cpu2.num_int_register_writes             92045                       # number of times the integer registers were written
system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu2.num_mem_refs                        47896                       # number of memory refs
system.cpu2.num_load_insts                      40447                       # Number of load instructions
system.cpu2.num_store_insts                      7449                       # Number of store instructions
system.cpu2.num_idle_cycles              71854.001733                       # Number of idle cycles
system.cpu2.num_busy_cycles              465941.998267                       # Number of busy cycles
system.cpu2.not_idle_fraction                0.866392                       # Percentage of non-idle cycles
system.cpu2.idle_fraction                    0.133608                       # Percentage of idle cycles
system.cpu2.icache.replacements                   281                       # number of replacements
system.cpu2.icache.tagsinuse                67.534984                       # Cycle average of tags in use
system.cpu2.icache.total_refs                  176887                       # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs                   367                       # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs                481.980926                       # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.occ_blocks::cpu2.inst    67.534984                       # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst     0.131904                       # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total        0.131904                       # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst       176887                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total         176887                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst       176887                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total          176887                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst       176887                       # number of overall hits
system.cpu2.icache.overall_hits::total         176887                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          367                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          367                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          367                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           367                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          367                       # number of overall misses
system.cpu2.icache.overall_misses::total          367                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      5709500                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total      5709500                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst      5709500                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total      5709500                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst      5709500                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total      5709500                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst       177254                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total       177254                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst       177254                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total       177254                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst       177254                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total       177254                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002070                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.002070                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002070                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.002070                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002070                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.002070                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15557.220708                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 15557.220708                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15557.220708                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 15557.220708                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15557.220708                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 15557.220708                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          367                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          367                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          367                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          367                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          367                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          367                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      4608500                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total      4608500                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      4608500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total      4608500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      4608500                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total      4608500                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.002070                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.002070                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.002070                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.002070                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.002070                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.002070                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12557.220708                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12557.220708                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12557.220708                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 12557.220708                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12557.220708                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 12557.220708                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.replacements                     0                       # number of replacements
system.cpu2.dcache.tagsinuse                26.638398                       # Cycle average of tags in use
system.cpu2.dcache.total_refs                   17171                       # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs                592.103448                       # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.occ_blocks::cpu2.data    26.638398                       # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data     0.052028                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total        0.052028                       # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data        40266                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          40266                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data         7273                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total          7273                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           18                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             18                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        47539                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           47539                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        47539                       # number of overall hits
system.cpu2.dcache.overall_hits::total          47539                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          173                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          173                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          105                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          105                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           51                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           51                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          278                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           278                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          278                       # number of overall misses
system.cpu2.dcache.overall_misses::total          278                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      3995000                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      3995000                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2318000                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      2318000                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       814000                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       814000                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data      6313000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total      6313000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data      6313000                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total      6313000                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        40439                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        40439                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data         7378                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total         7378                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           69                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        47817                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        47817                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        47817                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        47817                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.004278                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.004278                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.014231                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.014231                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.739130                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.739130                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.005814                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.005814                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.005814                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.005814                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23092.485549                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 23092.485549                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22076.190476                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 22076.190476                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 15960.784314                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total 15960.784314                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22708.633094                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 22708.633094                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22708.633094                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 22708.633094                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          173                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          105                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           51                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           51                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          278                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          278                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          278                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          278                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      3476000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      3476000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      2003000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      2003000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       661000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       661000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      5479000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      5479000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      5479000                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      5479000                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.004278                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.004278                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.014231                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.014231                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.739130                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.739130                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.005814                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.005814                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.005814                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.005814                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 20092.485549                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 20092.485549                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19076.190476                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19076.190476                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 12960.784314                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 12960.784314                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19708.633094                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19708.633094                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19708.633094                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19708.633094                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.numCycles                          537796                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.committedInsts                     172067                       # Number of instructions committed
system.cpu3.committedOps                       172067                       # Number of ops (including micro ops) committed
system.cpu3.num_int_alu_accesses               111206                       # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu3.num_func_calls                        637                       # number of times a function call or return occured
system.cpu3.num_conditional_control_insts        34437                       # number of instructions that are conditional controls
system.cpu3.num_int_insts                      111206                       # number of integer instructions
system.cpu3.num_fp_insts                            0                       # number of float instructions
system.cpu3.num_int_register_reads             269314                       # number of times the integer registers were read
system.cpu3.num_int_register_writes            101322                       # number of times the integer registers were written
system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu3.num_mem_refs                        52937                       # number of memory refs
system.cpu3.num_load_insts                      41268                       # Number of load instructions
system.cpu3.num_store_insts                     11669                       # Number of store instructions
system.cpu3.num_idle_cycles              72130.001732                       # Number of idle cycles
system.cpu3.num_busy_cycles              465665.998268                       # Number of busy cycles
system.cpu3.not_idle_fraction                0.865879                       # Percentage of non-idle cycles
system.cpu3.idle_fraction                    0.134121                       # Percentage of idle cycles
system.cpu3.icache.replacements                   280                       # number of replacements
system.cpu3.icache.tagsinuse                65.345482                       # Cycle average of tags in use
system.cpu3.icache.total_refs                  171734                       # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs                   366                       # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs                469.218579                       # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.occ_blocks::cpu3.inst    65.345482                       # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst     0.127628                       # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total        0.127628                       # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst       171734                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total         171734                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst       171734                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total          171734                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst       171734                       # number of overall hits
system.cpu3.icache.overall_hits::total         171734                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          366                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          366                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          366                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           366                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          366                       # number of overall misses
system.cpu3.icache.overall_misses::total          366                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      5645500                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total      5645500                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst      5645500                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total      5645500                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst      5645500                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total      5645500                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst       172100                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total       172100                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst       172100                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total       172100                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst       172100                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total       172100                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002127                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.002127                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002127                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.002127                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002127                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.002127                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15424.863388                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 15424.863388                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15424.863388                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 15424.863388                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15424.863388                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 15424.863388                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          366                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          366                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          366                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4547000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total      4547000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4547000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total      4547000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4547000                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total      4547000                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.002127                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.002127                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.002127                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.002127                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.002127                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.002127                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12423.497268                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12423.497268                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12423.497268                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 12423.497268                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12423.497268                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 12423.497268                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.replacements                     0                       # number of replacements
system.cpu3.dcache.tagsinuse                25.850163                       # Cycle average of tags in use
system.cpu3.dcache.total_refs                   25744                       # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs                858.133333                       # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.occ_blocks::cpu3.data    25.850163                       # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data     0.050489                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total        0.050489                       # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data        41084                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          41084                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        11491                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         11491                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           12                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        52575                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           52575                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        52575                       # number of overall hits
system.cpu3.dcache.overall_hits::total          52575                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          176                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          176                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          105                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          105                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           59                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           59                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          281                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           281                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          281                       # number of overall misses
system.cpu3.dcache.overall_misses::total          281                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      4401000                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      4401000                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      1861000                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      1861000                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       928000                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       928000                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data      6262000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total      6262000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data      6262000                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total      6262000                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        41260                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        41260                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        11596                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        11596                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           71                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        52856                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        52856                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        52856                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        52856                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.004266                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.004266                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.009055                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.009055                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.830986                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.830986                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.005316                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.005316                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.005316                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.005316                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 25005.681818                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 25005.681818                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 17723.809524                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 17723.809524                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 15728.813559                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total 15728.813559                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 22284.697509                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 22284.697509                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 22284.697509                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 22284.697509                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          176                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          176                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          105                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           59                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           59                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          281                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          281                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          281                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          281                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      3873000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      3873000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1546000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1546000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       751000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       751000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      5419000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      5419000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      5419000                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      5419000                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.004266                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.004266                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.009055                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.009055                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.830986                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.830986                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.005316                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.005316                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.005316                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.005316                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 22005.681818                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 22005.681818                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14723.809524                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14723.809524                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 12728.813559                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 12728.813559                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 19284.697509                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 19284.697509                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 19284.697509                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 19284.697509                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.l2c.replacements                             0                       # number of replacements
system.l2c.tagsinuse                       348.825789                       # Cycle average of tags in use
system.l2c.total_refs                            1221                       # Total number of references to valid blocks.
system.l2c.sampled_refs                           429                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          2.846154                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks            0.888106                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst           231.689332                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data            54.189752                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst            51.472071                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data             6.113701                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst             1.771073                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data             0.842159                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst             1.030424                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data             0.829169                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.000014                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.003535                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.000827                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.000785                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.000093                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst            0.000027                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data            0.000013                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst            0.000016                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data            0.000013                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.005323                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst                182                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst                300                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data                  3                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst                355                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst                358                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1221                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst                 182                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 300                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                   3                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 355                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 358                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1221                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                182                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                300                       # number of overall hits
system.l2c.overall_hits::cpu1.data                  3                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                355                       # number of overall hits
system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                358                       # number of overall hits
system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
system.l2c.overall_hits::total                   1221                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst              285                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data               66                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst               66                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data                8                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst               12                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data                2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst                8                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data                2                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  449                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data            28                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            20                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            27                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            11                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                86                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             15                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             14                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             14                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                142                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst               285                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                66                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                23                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                12                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                16                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                 8                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                16                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   591                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              285                       # number of overall misses
system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               66                       # number of overall misses
system.l2c.overall_misses::cpu1.data               23                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               12                       # number of overall misses
system.l2c.overall_misses::cpu2.data               16                       # number of overall misses
system.l2c.overall_misses::cpu3.inst                8                       # number of overall misses
system.l2c.overall_misses::cpu3.data               16                       # number of overall misses
system.l2c.overall_misses::total                  591                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst     14828000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data      3432000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst      3308000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data       398000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst       529000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data        95000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst       418000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data       104000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       23112000                       # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data      5148000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data       780000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data       728000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       728000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total      7384000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     14828000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data      8580000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      3308000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data      1178000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst       529000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data       823000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst       418000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data       832000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        30496000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     14828000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data      8580000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      3308000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data      1178000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst       529000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data       823000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst       418000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data       832000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       30496000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst            467                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data             71                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst            366                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data             11                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst            367                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data             11                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst            366                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data             11                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               1670                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           20                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           27                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           11                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              88                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           15                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           14                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           14                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              142                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             366                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              26                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             367                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             366                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                1812                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            366                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             26                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            367                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            366                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               1812                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.610278                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.929577                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.180328                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.727273                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.032698                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.181818                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst      0.021858                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data      0.181818                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.268862                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.933333                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.977273                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.610278                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.180328                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.884615                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.032698                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.640000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.021858                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.640000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.326159                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.610278                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.180328                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.884615                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.032698                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.640000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.021858                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.640000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.326159                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52028.070175                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data        52000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 50121.212121                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data        49750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 44083.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data        47500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst        52250                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data        52000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 51474.387528                       # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data        52000                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data        52000                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data        52000                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data        52000                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52028.070175                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data        52000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 50121.212121                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 51217.391304                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 44083.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 51437.500000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst        52250                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data        52000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 51600.676819                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52028.070175                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data        52000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 50121.212121                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 51217.391304                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 44083.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 51437.500000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst        52250                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data        52000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 51600.676819                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst            10                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                19                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst             10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 19                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst            10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                19                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst          285                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data           66                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst           59                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst            8                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             430                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data           28                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           20                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           27                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           11                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           86                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           99                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           15                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           14                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           14                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           142                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          285                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          165                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           59                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           22                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           15                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            8                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           16                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              572                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          285                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          165                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           59                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           22                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           15                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            8                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           16                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             572                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     11408000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data      2640000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst      2360000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data       280000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst        80000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       322000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data        80000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     17210000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data      1120000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       800000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      1080000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       440000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      3440000                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      3960000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       600000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       560000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       560000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      5680000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     11408000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data      6600000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst      2360000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data       880000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst        80000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data       600000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst       322000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data       640000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     22890000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     11408000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data      6600000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst      2360000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data       880000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst        80000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data       600000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst       322000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data       640000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     22890000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.929577                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.161202                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.636364                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.005450                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.090909                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.021858                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.181818                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.257485                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.933333                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.977273                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.161202                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.846154                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.005450                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.600000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.021858                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.640000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.315673                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.161202                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.846154                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.005450                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.600000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.021858                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.640000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.315673                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40028.070175                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        40250                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40023.255814                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total        40000                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data        40000                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data        40000                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data        40000                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40028.070175                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        40250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40017.482517                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40028.070175                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40017.482517                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------