stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000262 # Number of seconds simulated 4sim_ticks 262298000 # Number of ticks simulated 5final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1158712 # Simulator instruction rate (inst/s) 8host_tick_rate 458877844 # Simulator tick rate (ticks/s) 9host_mem_usage 222944 # Number of bytes of host memory used 10host_seconds 0.57 # Real time elapsed on the host 11sim_insts 662307 # Number of instructions simulated 12system.physmem.bytes_read 36608 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 22656 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 0 # Number of bytes written to this memory 15system.physmem.num_reads 572 # Number of read requests responded to by this memory 16system.physmem.num_writes 0 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 139566447 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 86375039 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_total 139566447 # Total bandwidth to/from this memory (bytes/s) 21system.cpu0.workload.num_syscalls 89 # Number of system calls 22system.cpu0.numCycles 524596 # number of cpu cycles simulated 23system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 24system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 25system.cpu0.num_insts 158353 # Number of instructions executed 26system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses 27system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 28system.cpu0.num_func_calls 390 # number of times a function call or return occured 29system.cpu0.num_conditional_control_insts 25994 # number of instructions that are conditional controls 30system.cpu0.num_int_insts 109064 # number of integer instructions 31system.cpu0.num_fp_insts 0 # number of float instructions 32system.cpu0.num_int_register_reads 315336 # number of times the integer registers were read 33system.cpu0.num_int_register_writes 110671 # number of times the integer registers were written 34system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 35system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 36system.cpu0.num_mem_refs 73905 # number of memory refs 37system.cpu0.num_load_insts 48930 # Number of load instructions 38system.cpu0.num_store_insts 24975 # Number of store instructions 39system.cpu0.num_idle_cycles 0 # Number of idle cycles 40system.cpu0.num_busy_cycles 524596 # Number of busy cycles 41system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 42system.cpu0.idle_fraction 0 # Percentage of idle cycles 43system.cpu0.icache.replacements 215 # number of replacements 44system.cpu0.icache.tagsinuse 212.479188 # Cycle average of tags in use 45system.cpu0.icache.total_refs 157949 # Total number of references to valid blocks. 46system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. 47system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks. 48system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 49system.cpu0.icache.occ_blocks::0 212.479188 # Average occupied blocks per context 50system.cpu0.icache.occ_percent::0 0.414998 # Average percentage of cache occupancy 51system.cpu0.icache.ReadReq_hits 157949 # number of ReadReq hits 52system.cpu0.icache.demand_hits 157949 # number of demand (read+write) hits 53system.cpu0.icache.overall_hits 157949 # number of overall hits 54system.cpu0.icache.ReadReq_misses 467 # number of ReadReq misses 55system.cpu0.icache.demand_misses 467 # number of demand (read+write) misses 56system.cpu0.icache.overall_misses 467 # number of overall misses 57system.cpu0.icache.ReadReq_miss_latency 18524000 # number of ReadReq miss cycles 58system.cpu0.icache.demand_miss_latency 18524000 # number of demand (read+write) miss cycles 59system.cpu0.icache.overall_miss_latency 18524000 # number of overall miss cycles 60system.cpu0.icache.ReadReq_accesses 158416 # number of ReadReq accesses(hits+misses) 61system.cpu0.icache.demand_accesses 158416 # number of demand (read+write) accesses 62system.cpu0.icache.overall_accesses 158416 # number of overall (read+write) accesses 63system.cpu0.icache.ReadReq_miss_rate 0.002948 # miss rate for ReadReq accesses 64system.cpu0.icache.demand_miss_rate 0.002948 # miss rate for demand accesses 65system.cpu0.icache.overall_miss_rate 0.002948 # miss rate for overall accesses 66system.cpu0.icache.ReadReq_avg_miss_latency 39665.952891 # average ReadReq miss latency 67system.cpu0.icache.demand_avg_miss_latency 39665.952891 # average overall miss latency 68system.cpu0.icache.overall_avg_miss_latency 39665.952891 # average overall miss latency 69system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 70system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 71system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 72system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 73system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 74system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 75system.cpu0.icache.fast_writes 0 # number of fast writes performed 76system.cpu0.icache.cache_copies 0 # number of cache copies performed 77system.cpu0.icache.writebacks 0 # number of writebacks 78system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 79system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits 80system.cpu0.icache.ReadReq_mshr_misses 467 # number of ReadReq MSHR misses 81system.cpu0.icache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses 82system.cpu0.icache.overall_mshr_misses 467 # number of overall MSHR misses 83system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 84system.cpu0.icache.ReadReq_mshr_miss_latency 17123000 # number of ReadReq MSHR miss cycles 85system.cpu0.icache.demand_mshr_miss_latency 17123000 # number of demand (read+write) MSHR miss cycles 86system.cpu0.icache.overall_mshr_miss_latency 17123000 # number of overall MSHR miss cycles 87system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 88system.cpu0.icache.ReadReq_mshr_miss_rate 0.002948 # mshr miss rate for ReadReq accesses 89system.cpu0.icache.demand_mshr_miss_rate 0.002948 # mshr miss rate for demand accesses 90system.cpu0.icache.overall_mshr_miss_rate 0.002948 # mshr miss rate for overall accesses 91system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36665.952891 # average ReadReq mshr miss latency 92system.cpu0.icache.demand_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency 93system.cpu0.icache.overall_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency 94system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 95system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated 96system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 97system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 98system.cpu0.dcache.replacements 9 # number of replacements 99system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use 100system.cpu0.dcache.total_refs 56009 # Total number of references to valid blocks. 101system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. 102system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks. 103system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 104system.cpu0.dcache.occ_blocks::0 141.233342 # Average occupied blocks per context 105system.cpu0.dcache.occ_percent::0 0.275846 # Average percentage of cache occupancy 106system.cpu0.dcache.ReadReq_hits 48758 # number of ReadReq hits 107system.cpu0.dcache.WriteReq_hits 24741 # number of WriteReq hits 108system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits 109system.cpu0.dcache.demand_hits 73499 # number of demand (read+write) hits 110system.cpu0.dcache.overall_hits 73499 # number of overall hits 111system.cpu0.dcache.ReadReq_misses 162 # number of ReadReq misses 112system.cpu0.dcache.WriteReq_misses 183 # number of WriteReq misses 113system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses 114system.cpu0.dcache.demand_misses 345 # number of demand (read+write) misses 115system.cpu0.dcache.overall_misses 345 # number of overall misses 116system.cpu0.dcache.ReadReq_miss_latency 4749000 # number of ReadReq miss cycles 117system.cpu0.dcache.WriteReq_miss_latency 7175000 # number of WriteReq miss cycles 118system.cpu0.dcache.SwapReq_miss_latency 387000 # number of SwapReq miss cycles 119system.cpu0.dcache.demand_miss_latency 11924000 # number of demand (read+write) miss cycles 120system.cpu0.dcache.overall_miss_latency 11924000 # number of overall miss cycles 121system.cpu0.dcache.ReadReq_accesses 48920 # number of ReadReq accesses(hits+misses) 122system.cpu0.dcache.WriteReq_accesses 24924 # number of WriteReq accesses(hits+misses) 123system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) 124system.cpu0.dcache.demand_accesses 73844 # number of demand (read+write) accesses 125system.cpu0.dcache.overall_accesses 73844 # number of overall (read+write) accesses 126system.cpu0.dcache.ReadReq_miss_rate 0.003312 # miss rate for ReadReq accesses 127system.cpu0.dcache.WriteReq_miss_rate 0.007342 # miss rate for WriteReq accesses 128system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses 129system.cpu0.dcache.demand_miss_rate 0.004672 # miss rate for demand accesses 130system.cpu0.dcache.overall_miss_rate 0.004672 # miss rate for overall accesses 131system.cpu0.dcache.ReadReq_avg_miss_latency 29314.814815 # average ReadReq miss latency 132system.cpu0.dcache.WriteReq_avg_miss_latency 39207.650273 # average WriteReq miss latency 133system.cpu0.dcache.SwapReq_avg_miss_latency 14884.615385 # average SwapReq miss latency 134system.cpu0.dcache.demand_avg_miss_latency 34562.318841 # average overall miss latency 135system.cpu0.dcache.overall_avg_miss_latency 34562.318841 # average overall miss latency 136system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 137system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 138system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 139system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 140system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 141system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 142system.cpu0.dcache.fast_writes 0 # number of fast writes performed 143system.cpu0.dcache.cache_copies 0 # number of cache copies performed 144system.cpu0.dcache.writebacks 6 # number of writebacks 145system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 146system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits 147system.cpu0.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses 148system.cpu0.dcache.WriteReq_mshr_misses 183 # number of WriteReq MSHR misses 149system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses 150system.cpu0.dcache.demand_mshr_misses 345 # number of demand (read+write) MSHR misses 151system.cpu0.dcache.overall_mshr_misses 345 # number of overall MSHR misses 152system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 153system.cpu0.dcache.ReadReq_mshr_miss_latency 4263000 # number of ReadReq MSHR miss cycles 154system.cpu0.dcache.WriteReq_mshr_miss_latency 6626000 # number of WriteReq MSHR miss cycles 155system.cpu0.dcache.SwapReq_mshr_miss_latency 309000 # number of SwapReq MSHR miss cycles 156system.cpu0.dcache.demand_mshr_miss_latency 10889000 # number of demand (read+write) MSHR miss cycles 157system.cpu0.dcache.overall_mshr_miss_latency 10889000 # number of overall MSHR miss cycles 158system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 159system.cpu0.dcache.ReadReq_mshr_miss_rate 0.003312 # mshr miss rate for ReadReq accesses 160system.cpu0.dcache.WriteReq_mshr_miss_rate 0.007342 # mshr miss rate for WriteReq accesses 161system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses 162system.cpu0.dcache.demand_mshr_miss_rate 0.004672 # mshr miss rate for demand accesses 163system.cpu0.dcache.overall_mshr_miss_rate 0.004672 # mshr miss rate for overall accesses 164system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 26314.814815 # average ReadReq mshr miss latency 165system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36207.650273 # average WriteReq mshr miss latency 166system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 11884.615385 # average SwapReq mshr miss latency 167system.cpu0.dcache.demand_avg_mshr_miss_latency 31562.318841 # average overall mshr miss latency 168system.cpu0.dcache.overall_avg_mshr_miss_latency 31562.318841 # average overall mshr miss latency 169system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 170system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 171system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 172system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 173system.cpu1.numCycles 524596 # number of cpu cycles simulated 174system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 175system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 176system.cpu1.num_insts 172325 # Number of instructions executed 177system.cpu1.num_int_alu_accesses 107932 # Number of integer alu accesses 178system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 179system.cpu1.num_func_calls 637 # number of times a function call or return occured 180system.cpu1.num_conditional_control_insts 36203 # number of instructions that are conditional controls 181system.cpu1.num_int_insts 107932 # number of integer instructions 182system.cpu1.num_fp_insts 0 # number of float instructions 183system.cpu1.num_int_register_reads 249091 # number of times the integer registers were read 184system.cpu1.num_int_register_writes 92744 # number of times the integer registers were written 185system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 186system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 187system.cpu1.num_mem_refs 47898 # number of memory refs 188system.cpu1.num_load_insts 39616 # Number of load instructions 189system.cpu1.num_store_insts 8282 # Number of store instructions 190system.cpu1.num_idle_cycles 68578.001739 # Number of idle cycles 191system.cpu1.num_busy_cycles 456017.998261 # Number of busy cycles 192system.cpu1.not_idle_fraction 0.869275 # Percentage of non-idle cycles 193system.cpu1.idle_fraction 0.130725 # Percentage of idle cycles 194system.cpu1.icache.replacements 280 # number of replacements 195system.cpu1.icache.tagsinuse 70.076133 # Cycle average of tags in use 196system.cpu1.icache.total_refs 171992 # Total number of references to valid blocks. 197system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. 198system.cpu1.icache.avg_refs 469.923497 # Average number of references to valid blocks. 199system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 200system.cpu1.icache.occ_blocks::0 70.076133 # Average occupied blocks per context 201system.cpu1.icache.occ_percent::0 0.136867 # Average percentage of cache occupancy 202system.cpu1.icache.ReadReq_hits 171992 # number of ReadReq hits 203system.cpu1.icache.demand_hits 171992 # number of demand (read+write) hits 204system.cpu1.icache.overall_hits 171992 # number of overall hits 205system.cpu1.icache.ReadReq_misses 366 # number of ReadReq misses 206system.cpu1.icache.demand_misses 366 # number of demand (read+write) misses 207system.cpu1.icache.overall_misses 366 # number of overall misses 208system.cpu1.icache.ReadReq_miss_latency 7920500 # number of ReadReq miss cycles 209system.cpu1.icache.demand_miss_latency 7920500 # number of demand (read+write) miss cycles 210system.cpu1.icache.overall_miss_latency 7920500 # number of overall miss cycles 211system.cpu1.icache.ReadReq_accesses 172358 # number of ReadReq accesses(hits+misses) 212system.cpu1.icache.demand_accesses 172358 # number of demand (read+write) accesses 213system.cpu1.icache.overall_accesses 172358 # number of overall (read+write) accesses 214system.cpu1.icache.ReadReq_miss_rate 0.002123 # miss rate for ReadReq accesses 215system.cpu1.icache.demand_miss_rate 0.002123 # miss rate for demand accesses 216system.cpu1.icache.overall_miss_rate 0.002123 # miss rate for overall accesses 217system.cpu1.icache.ReadReq_avg_miss_latency 21640.710383 # average ReadReq miss latency 218system.cpu1.icache.demand_avg_miss_latency 21640.710383 # average overall miss latency 219system.cpu1.icache.overall_avg_miss_latency 21640.710383 # average overall miss latency 220system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 221system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 222system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 223system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 224system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 225system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 226system.cpu1.icache.fast_writes 0 # number of fast writes performed 227system.cpu1.icache.cache_copies 0 # number of cache copies performed 228system.cpu1.icache.writebacks 0 # number of writebacks 229system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 230system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits 231system.cpu1.icache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses 232system.cpu1.icache.demand_mshr_misses 366 # number of demand (read+write) MSHR misses 233system.cpu1.icache.overall_mshr_misses 366 # number of overall MSHR misses 234system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 235system.cpu1.icache.ReadReq_mshr_miss_latency 6822000 # number of ReadReq MSHR miss cycles 236system.cpu1.icache.demand_mshr_miss_latency 6822000 # number of demand (read+write) MSHR miss cycles 237system.cpu1.icache.overall_mshr_miss_latency 6822000 # number of overall MSHR miss cycles 238system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 239system.cpu1.icache.ReadReq_mshr_miss_rate 0.002123 # mshr miss rate for ReadReq accesses 240system.cpu1.icache.demand_mshr_miss_rate 0.002123 # mshr miss rate for demand accesses 241system.cpu1.icache.overall_mshr_miss_rate 0.002123 # mshr miss rate for overall accesses 242system.cpu1.icache.ReadReq_avg_mshr_miss_latency 18639.344262 # average ReadReq mshr miss latency 243system.cpu1.icache.demand_avg_mshr_miss_latency 18639.344262 # average overall mshr miss latency 244system.cpu1.icache.overall_avg_mshr_miss_latency 18639.344262 # average overall mshr miss latency 245system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 246system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated 247system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 248system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 249system.cpu1.dcache.replacements 2 # number of replacements 250system.cpu1.dcache.tagsinuse 22.703917 # Cycle average of tags in use 251system.cpu1.dcache.total_refs 18908 # Total number of references to valid blocks. 252system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks. 253system.cpu1.dcache.avg_refs 609.935484 # Average number of references to valid blocks. 254system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 255system.cpu1.dcache.occ_blocks::0 26.693562 # Average occupied blocks per context 256system.cpu1.dcache.occ_blocks::1 -3.989645 # Average occupied blocks per context 257system.cpu1.dcache.occ_percent::0 0.052136 # Average percentage of cache occupancy 258system.cpu1.dcache.occ_percent::1 -0.007792 # Average percentage of cache occupancy 259system.cpu1.dcache.ReadReq_hits 39428 # number of ReadReq hits 260system.cpu1.dcache.WriteReq_hits 8099 # number of WriteReq hits 261system.cpu1.dcache.SwapReq_hits 18 # number of SwapReq hits 262system.cpu1.dcache.demand_hits 47527 # number of demand (read+write) hits 263system.cpu1.dcache.overall_hits 47527 # number of overall hits 264system.cpu1.dcache.ReadReq_misses 181 # number of ReadReq misses 265system.cpu1.dcache.WriteReq_misses 98 # number of WriteReq misses 266system.cpu1.dcache.SwapReq_misses 65 # number of SwapReq misses 267system.cpu1.dcache.demand_misses 279 # number of demand (read+write) misses 268system.cpu1.dcache.overall_misses 279 # number of overall misses 269system.cpu1.dcache.ReadReq_miss_latency 3713000 # number of ReadReq miss cycles 270system.cpu1.dcache.WriteReq_miss_latency 1889000 # number of WriteReq miss cycles 271system.cpu1.dcache.SwapReq_miss_latency 415000 # number of SwapReq miss cycles 272system.cpu1.dcache.demand_miss_latency 5602000 # number of demand (read+write) miss cycles 273system.cpu1.dcache.overall_miss_latency 5602000 # number of overall miss cycles 274system.cpu1.dcache.ReadReq_accesses 39609 # number of ReadReq accesses(hits+misses) 275system.cpu1.dcache.WriteReq_accesses 8197 # number of WriteReq accesses(hits+misses) 276system.cpu1.dcache.SwapReq_accesses 83 # number of SwapReq accesses(hits+misses) 277system.cpu1.dcache.demand_accesses 47806 # number of demand (read+write) accesses 278system.cpu1.dcache.overall_accesses 47806 # number of overall (read+write) accesses 279system.cpu1.dcache.ReadReq_miss_rate 0.004570 # miss rate for ReadReq accesses 280system.cpu1.dcache.WriteReq_miss_rate 0.011956 # miss rate for WriteReq accesses 281system.cpu1.dcache.SwapReq_miss_rate 0.783133 # miss rate for SwapReq accesses 282system.cpu1.dcache.demand_miss_rate 0.005836 # miss rate for demand accesses 283system.cpu1.dcache.overall_miss_rate 0.005836 # miss rate for overall accesses 284system.cpu1.dcache.ReadReq_avg_miss_latency 20513.812155 # average ReadReq miss latency 285system.cpu1.dcache.WriteReq_avg_miss_latency 19275.510204 # average WriteReq miss latency 286system.cpu1.dcache.SwapReq_avg_miss_latency 6384.615385 # average SwapReq miss latency 287system.cpu1.dcache.demand_avg_miss_latency 20078.853047 # average overall miss latency 288system.cpu1.dcache.overall_avg_miss_latency 20078.853047 # average overall miss latency 289system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 290system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 291system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 292system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 293system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 294system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 295system.cpu1.dcache.fast_writes 0 # number of fast writes performed 296system.cpu1.dcache.cache_copies 0 # number of cache copies performed 297system.cpu1.dcache.writebacks 1 # number of writebacks 298system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 299system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits 300system.cpu1.dcache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses 301system.cpu1.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses 302system.cpu1.dcache.SwapReq_mshr_misses 65 # number of SwapReq MSHR misses 303system.cpu1.dcache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses 304system.cpu1.dcache.overall_mshr_misses 279 # number of overall MSHR misses 305system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 306system.cpu1.dcache.ReadReq_mshr_miss_latency 3170000 # number of ReadReq MSHR miss cycles 307system.cpu1.dcache.WriteReq_mshr_miss_latency 1595000 # number of WriteReq MSHR miss cycles 308system.cpu1.dcache.SwapReq_mshr_miss_latency 220000 # number of SwapReq MSHR miss cycles 309system.cpu1.dcache.demand_mshr_miss_latency 4765000 # number of demand (read+write) MSHR miss cycles 310system.cpu1.dcache.overall_mshr_miss_latency 4765000 # number of overall MSHR miss cycles 311system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 312system.cpu1.dcache.ReadReq_mshr_miss_rate 0.004570 # mshr miss rate for ReadReq accesses 313system.cpu1.dcache.WriteReq_mshr_miss_rate 0.011956 # mshr miss rate for WriteReq accesses 314system.cpu1.dcache.SwapReq_mshr_miss_rate 0.783133 # mshr miss rate for SwapReq accesses 315system.cpu1.dcache.demand_mshr_miss_rate 0.005836 # mshr miss rate for demand accesses 316system.cpu1.dcache.overall_mshr_miss_rate 0.005836 # mshr miss rate for overall accesses 317system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 17513.812155 # average ReadReq mshr miss latency 318system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 16275.510204 # average WriteReq mshr miss latency 319system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 3384.615385 # average SwapReq mshr miss latency 320system.cpu1.dcache.demand_avg_mshr_miss_latency 17078.853047 # average overall mshr miss latency 321system.cpu1.dcache.overall_avg_mshr_miss_latency 17078.853047 # average overall mshr miss latency 322system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 323system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 324system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 325system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 326system.cpu2.numCycles 524596 # number of cpu cycles simulated 327system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 328system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 329system.cpu2.num_insts 165499 # Number of instructions executed 330system.cpu2.num_int_alu_accesses 112355 # Number of integer alu accesses 331system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 332system.cpu2.num_func_calls 637 # number of times a function call or return occured 333system.cpu2.num_conditional_control_insts 30582 # number of instructions that are conditional controls 334system.cpu2.num_int_insts 112355 # number of integer instructions 335system.cpu2.num_fp_insts 0 # number of float instructions 336system.cpu2.num_int_register_reads 289268 # number of times the integer registers were read 337system.cpu2.num_int_register_writes 110631 # number of times the integer registers were written 338system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 339system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 340system.cpu2.num_mem_refs 57941 # number of memory refs 341system.cpu2.num_load_insts 41852 # Number of load instructions 342system.cpu2.num_store_insts 16089 # Number of store instructions 343system.cpu2.num_idle_cycles 68840.001738 # Number of idle cycles 344system.cpu2.num_busy_cycles 455755.998262 # Number of busy cycles 345system.cpu2.not_idle_fraction 0.868775 # Percentage of non-idle cycles 346system.cpu2.idle_fraction 0.131225 # Percentage of idle cycles 347system.cpu2.icache.replacements 280 # number of replacements 348system.cpu2.icache.tagsinuse 65.601019 # Cycle average of tags in use 349system.cpu2.icache.total_refs 165166 # Total number of references to valid blocks. 350system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. 351system.cpu2.icache.avg_refs 451.273224 # Average number of references to valid blocks. 352system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 353system.cpu2.icache.occ_blocks::0 65.601019 # Average occupied blocks per context 354system.cpu2.icache.occ_percent::0 0.128127 # Average percentage of cache occupancy 355system.cpu2.icache.ReadReq_hits 165166 # number of ReadReq hits 356system.cpu2.icache.demand_hits 165166 # number of demand (read+write) hits 357system.cpu2.icache.overall_hits 165166 # number of overall hits 358system.cpu2.icache.ReadReq_misses 366 # number of ReadReq misses 359system.cpu2.icache.demand_misses 366 # number of demand (read+write) misses 360system.cpu2.icache.overall_misses 366 # number of overall misses 361system.cpu2.icache.ReadReq_miss_latency 5648500 # number of ReadReq miss cycles 362system.cpu2.icache.demand_miss_latency 5648500 # number of demand (read+write) miss cycles 363system.cpu2.icache.overall_miss_latency 5648500 # number of overall miss cycles 364system.cpu2.icache.ReadReq_accesses 165532 # number of ReadReq accesses(hits+misses) 365system.cpu2.icache.demand_accesses 165532 # number of demand (read+write) accesses 366system.cpu2.icache.overall_accesses 165532 # number of overall (read+write) accesses 367system.cpu2.icache.ReadReq_miss_rate 0.002211 # miss rate for ReadReq accesses 368system.cpu2.icache.demand_miss_rate 0.002211 # miss rate for demand accesses 369system.cpu2.icache.overall_miss_rate 0.002211 # miss rate for overall accesses 370system.cpu2.icache.ReadReq_avg_miss_latency 15433.060109 # average ReadReq miss latency 371system.cpu2.icache.demand_avg_miss_latency 15433.060109 # average overall miss latency 372system.cpu2.icache.overall_avg_miss_latency 15433.060109 # average overall miss latency 373system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 374system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 375system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 376system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 377system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 378system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 379system.cpu2.icache.fast_writes 0 # number of fast writes performed 380system.cpu2.icache.cache_copies 0 # number of cache copies performed 381system.cpu2.icache.writebacks 0 # number of writebacks 382system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 383system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits 384system.cpu2.icache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses 385system.cpu2.icache.demand_mshr_misses 366 # number of demand (read+write) MSHR misses 386system.cpu2.icache.overall_mshr_misses 366 # number of overall MSHR misses 387system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 388system.cpu2.icache.ReadReq_mshr_miss_latency 4550500 # number of ReadReq MSHR miss cycles 389system.cpu2.icache.demand_mshr_miss_latency 4550500 # number of demand (read+write) MSHR miss cycles 390system.cpu2.icache.overall_mshr_miss_latency 4550500 # number of overall MSHR miss cycles 391system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 392system.cpu2.icache.ReadReq_mshr_miss_rate 0.002211 # mshr miss rate for ReadReq accesses 393system.cpu2.icache.demand_mshr_miss_rate 0.002211 # mshr miss rate for demand accesses 394system.cpu2.icache.overall_mshr_miss_rate 0.002211 # mshr miss rate for overall accesses 395system.cpu2.icache.ReadReq_avg_mshr_miss_latency 12433.060109 # average ReadReq mshr miss latency 396system.cpu2.icache.demand_avg_mshr_miss_latency 12433.060109 # average overall mshr miss latency 397system.cpu2.icache.overall_avg_mshr_miss_latency 12433.060109 # average overall mshr miss latency 398system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 399system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated 400system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 401system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 402system.cpu2.dcache.replacements 2 # number of replacements 403system.cpu2.dcache.tagsinuse 23.305393 # Cycle average of tags in use 404system.cpu2.dcache.total_refs 34578 # Total number of references to valid blocks. 405system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. 406system.cpu2.dcache.avg_refs 1115.419355 # Average number of references to valid blocks. 407system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 408system.cpu2.dcache.occ_blocks::0 24.943438 # Average occupied blocks per context 409system.cpu2.dcache.occ_blocks::1 -1.638045 # Average occupied blocks per context 410system.cpu2.dcache.occ_percent::0 0.048718 # Average percentage of cache occupancy 411system.cpu2.dcache.occ_percent::1 -0.003199 # Average percentage of cache occupancy 412system.cpu2.dcache.ReadReq_hits 41688 # number of ReadReq hits 413system.cpu2.dcache.WriteReq_hits 15916 # number of WriteReq hits 414system.cpu2.dcache.SwapReq_hits 11 # number of SwapReq hits 415system.cpu2.dcache.demand_hits 57604 # number of demand (read+write) hits 416system.cpu2.dcache.overall_hits 57604 # number of overall hits 417system.cpu2.dcache.ReadReq_misses 156 # number of ReadReq misses 418system.cpu2.dcache.WriteReq_misses 109 # number of WriteReq misses 419system.cpu2.dcache.SwapReq_misses 51 # number of SwapReq misses 420system.cpu2.dcache.demand_misses 265 # number of demand (read+write) misses 421system.cpu2.dcache.overall_misses 265 # number of overall misses 422system.cpu2.dcache.ReadReq_miss_latency 2527000 # number of ReadReq miss cycles 423system.cpu2.dcache.WriteReq_miss_latency 2084000 # number of WriteReq miss cycles 424system.cpu2.dcache.SwapReq_miss_latency 305000 # number of SwapReq miss cycles 425system.cpu2.dcache.demand_miss_latency 4611000 # number of demand (read+write) miss cycles 426system.cpu2.dcache.overall_miss_latency 4611000 # number of overall miss cycles 427system.cpu2.dcache.ReadReq_accesses 41844 # number of ReadReq accesses(hits+misses) 428system.cpu2.dcache.WriteReq_accesses 16025 # number of WriteReq accesses(hits+misses) 429system.cpu2.dcache.SwapReq_accesses 62 # number of SwapReq accesses(hits+misses) 430system.cpu2.dcache.demand_accesses 57869 # number of demand (read+write) accesses 431system.cpu2.dcache.overall_accesses 57869 # number of overall (read+write) accesses 432system.cpu2.dcache.ReadReq_miss_rate 0.003728 # miss rate for ReadReq accesses 433system.cpu2.dcache.WriteReq_miss_rate 0.006802 # miss rate for WriteReq accesses 434system.cpu2.dcache.SwapReq_miss_rate 0.822581 # miss rate for SwapReq accesses 435system.cpu2.dcache.demand_miss_rate 0.004579 # miss rate for demand accesses 436system.cpu2.dcache.overall_miss_rate 0.004579 # miss rate for overall accesses 437system.cpu2.dcache.ReadReq_avg_miss_latency 16198.717949 # average ReadReq miss latency 438system.cpu2.dcache.WriteReq_avg_miss_latency 19119.266055 # average WriteReq miss latency 439system.cpu2.dcache.SwapReq_avg_miss_latency 5980.392157 # average SwapReq miss latency 440system.cpu2.dcache.demand_avg_miss_latency 17400 # average overall miss latency 441system.cpu2.dcache.overall_avg_miss_latency 17400 # average overall miss latency 442system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 443system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 444system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 445system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 446system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 447system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 448system.cpu2.dcache.fast_writes 0 # number of fast writes performed 449system.cpu2.dcache.cache_copies 0 # number of cache copies performed 450system.cpu2.dcache.writebacks 1 # number of writebacks 451system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 452system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits 453system.cpu2.dcache.ReadReq_mshr_misses 156 # number of ReadReq MSHR misses 454system.cpu2.dcache.WriteReq_mshr_misses 109 # number of WriteReq MSHR misses 455system.cpu2.dcache.SwapReq_mshr_misses 51 # number of SwapReq MSHR misses 456system.cpu2.dcache.demand_mshr_misses 265 # number of demand (read+write) MSHR misses 457system.cpu2.dcache.overall_mshr_misses 265 # number of overall MSHR misses 458system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 459system.cpu2.dcache.ReadReq_mshr_miss_latency 2059000 # number of ReadReq MSHR miss cycles 460system.cpu2.dcache.WriteReq_mshr_miss_latency 1757000 # number of WriteReq MSHR miss cycles 461system.cpu2.dcache.SwapReq_mshr_miss_latency 152000 # number of SwapReq MSHR miss cycles 462system.cpu2.dcache.demand_mshr_miss_latency 3816000 # number of demand (read+write) MSHR miss cycles 463system.cpu2.dcache.overall_mshr_miss_latency 3816000 # number of overall MSHR miss cycles 464system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 465system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003728 # mshr miss rate for ReadReq accesses 466system.cpu2.dcache.WriteReq_mshr_miss_rate 0.006802 # mshr miss rate for WriteReq accesses 467system.cpu2.dcache.SwapReq_mshr_miss_rate 0.822581 # mshr miss rate for SwapReq accesses 468system.cpu2.dcache.demand_mshr_miss_rate 0.004579 # mshr miss rate for demand accesses 469system.cpu2.dcache.overall_mshr_miss_rate 0.004579 # mshr miss rate for overall accesses 470system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 13198.717949 # average ReadReq mshr miss latency 471system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16119.266055 # average WriteReq mshr miss latency 472system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 2980.392157 # average SwapReq mshr miss latency 473system.cpu2.dcache.demand_avg_mshr_miss_latency 14400 # average overall mshr miss latency 474system.cpu2.dcache.overall_avg_mshr_miss_latency 14400 # average overall mshr miss latency 475system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 476system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 477system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 478system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 479system.cpu3.numCycles 524596 # number of cpu cycles simulated 480system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 481system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 482system.cpu3.num_insts 166130 # Number of instructions executed 483system.cpu3.num_int_alu_accesses 112098 # Number of integer alu accesses 484system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 485system.cpu3.num_func_calls 637 # number of times a function call or return occured 486system.cpu3.num_conditional_control_insts 31024 # number of instructions that are conditional controls 487system.cpu3.num_int_insts 112098 # number of integer instructions 488system.cpu3.num_fp_insts 0 # number of float instructions 489system.cpu3.num_int_register_reads 286475 # number of times the integer registers were read 490system.cpu3.num_int_register_writes 109360 # number of times the integer registers were written 491system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 492system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 493system.cpu3.num_mem_refs 57243 # number of memory refs 494system.cpu3.num_load_insts 41720 # Number of load instructions 495system.cpu3.num_store_insts 15523 # Number of store instructions 496system.cpu3.num_idle_cycles 69090.001737 # Number of idle cycles 497system.cpu3.num_busy_cycles 455505.998263 # Number of busy cycles 498system.cpu3.not_idle_fraction 0.868299 # Percentage of non-idle cycles 499system.cpu3.idle_fraction 0.131701 # Percentage of idle cycles 500system.cpu3.icache.replacements 281 # number of replacements 501system.cpu3.icache.tagsinuse 67.737646 # Cycle average of tags in use 502system.cpu3.icache.total_refs 165796 # Total number of references to valid blocks. 503system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. 504system.cpu3.icache.avg_refs 451.760218 # Average number of references to valid blocks. 505system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 506system.cpu3.icache.occ_blocks::0 67.737646 # Average occupied blocks per context 507system.cpu3.icache.occ_percent::0 0.132300 # Average percentage of cache occupancy 508system.cpu3.icache.ReadReq_hits 165796 # number of ReadReq hits 509system.cpu3.icache.demand_hits 165796 # number of demand (read+write) hits 510system.cpu3.icache.overall_hits 165796 # number of overall hits 511system.cpu3.icache.ReadReq_misses 367 # number of ReadReq misses 512system.cpu3.icache.demand_misses 367 # number of demand (read+write) misses 513system.cpu3.icache.overall_misses 367 # number of overall misses 514system.cpu3.icache.ReadReq_miss_latency 5531500 # number of ReadReq miss cycles 515system.cpu3.icache.demand_miss_latency 5531500 # number of demand (read+write) miss cycles 516system.cpu3.icache.overall_miss_latency 5531500 # number of overall miss cycles 517system.cpu3.icache.ReadReq_accesses 166163 # number of ReadReq accesses(hits+misses) 518system.cpu3.icache.demand_accesses 166163 # number of demand (read+write) accesses 519system.cpu3.icache.overall_accesses 166163 # number of overall (read+write) accesses 520system.cpu3.icache.ReadReq_miss_rate 0.002209 # miss rate for ReadReq accesses 521system.cpu3.icache.demand_miss_rate 0.002209 # miss rate for demand accesses 522system.cpu3.icache.overall_miss_rate 0.002209 # miss rate for overall accesses 523system.cpu3.icache.ReadReq_avg_miss_latency 15072.207084 # average ReadReq miss latency 524system.cpu3.icache.demand_avg_miss_latency 15072.207084 # average overall miss latency 525system.cpu3.icache.overall_avg_miss_latency 15072.207084 # average overall miss latency 526system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 527system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 528system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 529system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 530system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 531system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 532system.cpu3.icache.fast_writes 0 # number of fast writes performed 533system.cpu3.icache.cache_copies 0 # number of cache copies performed 534system.cpu3.icache.writebacks 0 # number of writebacks 535system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 536system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits 537system.cpu3.icache.ReadReq_mshr_misses 367 # number of ReadReq MSHR misses 538system.cpu3.icache.demand_mshr_misses 367 # number of demand (read+write) MSHR misses 539system.cpu3.icache.overall_mshr_misses 367 # number of overall MSHR misses 540system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 541system.cpu3.icache.ReadReq_mshr_miss_latency 4430500 # number of ReadReq MSHR miss cycles 542system.cpu3.icache.demand_mshr_miss_latency 4430500 # number of demand (read+write) MSHR miss cycles 543system.cpu3.icache.overall_mshr_miss_latency 4430500 # number of overall MSHR miss cycles 544system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 545system.cpu3.icache.ReadReq_mshr_miss_rate 0.002209 # mshr miss rate for ReadReq accesses 546system.cpu3.icache.demand_mshr_miss_rate 0.002209 # mshr miss rate for demand accesses 547system.cpu3.icache.overall_mshr_miss_rate 0.002209 # mshr miss rate for overall accesses 548system.cpu3.icache.ReadReq_avg_mshr_miss_latency 12072.207084 # average ReadReq mshr miss latency 549system.cpu3.icache.demand_avg_mshr_miss_latency 12072.207084 # average overall mshr miss latency 550system.cpu3.icache.overall_avg_mshr_miss_latency 12072.207084 # average overall mshr miss latency 551system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 552system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated 553system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 554system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 555system.cpu3.dcache.replacements 2 # number of replacements 556system.cpu3.dcache.tagsinuse 22.083417 # Cycle average of tags in use 557system.cpu3.dcache.total_refs 33474 # Total number of references to valid blocks. 558system.cpu3.dcache.sampled_refs 32 # Sample count of references to valid blocks. 559system.cpu3.dcache.avg_refs 1046.062500 # Average number of references to valid blocks. 560system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 561system.cpu3.dcache.occ_blocks::0 25.684916 # Average occupied blocks per context 562system.cpu3.dcache.occ_blocks::1 -3.601499 # Average occupied blocks per context 563system.cpu3.dcache.occ_percent::0 0.050166 # Average percentage of cache occupancy 564system.cpu3.dcache.occ_percent::1 -0.007034 # Average percentage of cache occupancy 565system.cpu3.dcache.ReadReq_hits 41555 # number of ReadReq hits 566system.cpu3.dcache.WriteReq_hits 15348 # number of WriteReq hits 567system.cpu3.dcache.SwapReq_hits 11 # number of SwapReq hits 568system.cpu3.dcache.demand_hits 56903 # number of demand (read+write) hits 569system.cpu3.dcache.overall_hits 56903 # number of overall hits 570system.cpu3.dcache.ReadReq_misses 157 # number of ReadReq misses 571system.cpu3.dcache.WriteReq_misses 108 # number of WriteReq misses 572system.cpu3.dcache.SwapReq_misses 54 # number of SwapReq misses 573system.cpu3.dcache.demand_misses 265 # number of demand (read+write) misses 574system.cpu3.dcache.overall_misses 265 # number of overall misses 575system.cpu3.dcache.ReadReq_miss_latency 2569000 # number of ReadReq miss cycles 576system.cpu3.dcache.WriteReq_miss_latency 2080000 # number of WriteReq miss cycles 577system.cpu3.dcache.SwapReq_miss_latency 326000 # number of SwapReq miss cycles 578system.cpu3.dcache.demand_miss_latency 4649000 # number of demand (read+write) miss cycles 579system.cpu3.dcache.overall_miss_latency 4649000 # number of overall miss cycles 580system.cpu3.dcache.ReadReq_accesses 41712 # number of ReadReq accesses(hits+misses) 581system.cpu3.dcache.WriteReq_accesses 15456 # number of WriteReq accesses(hits+misses) 582system.cpu3.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses) 583system.cpu3.dcache.demand_accesses 57168 # number of demand (read+write) accesses 584system.cpu3.dcache.overall_accesses 57168 # number of overall (read+write) accesses 585system.cpu3.dcache.ReadReq_miss_rate 0.003764 # miss rate for ReadReq accesses 586system.cpu3.dcache.WriteReq_miss_rate 0.006988 # miss rate for WriteReq accesses 587system.cpu3.dcache.SwapReq_miss_rate 0.830769 # miss rate for SwapReq accesses 588system.cpu3.dcache.demand_miss_rate 0.004635 # miss rate for demand accesses 589system.cpu3.dcache.overall_miss_rate 0.004635 # miss rate for overall accesses 590system.cpu3.dcache.ReadReq_avg_miss_latency 16363.057325 # average ReadReq miss latency 591system.cpu3.dcache.WriteReq_avg_miss_latency 19259.259259 # average WriteReq miss latency 592system.cpu3.dcache.SwapReq_avg_miss_latency 6037.037037 # average SwapReq miss latency 593system.cpu3.dcache.demand_avg_miss_latency 17543.396226 # average overall miss latency 594system.cpu3.dcache.overall_avg_miss_latency 17543.396226 # average overall miss latency 595system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 596system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 597system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 598system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 599system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 600system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 601system.cpu3.dcache.fast_writes 0 # number of fast writes performed 602system.cpu3.dcache.cache_copies 0 # number of cache copies performed 603system.cpu3.dcache.writebacks 1 # number of writebacks 604system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 605system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits 606system.cpu3.dcache.ReadReq_mshr_misses 157 # number of ReadReq MSHR misses 607system.cpu3.dcache.WriteReq_mshr_misses 108 # number of WriteReq MSHR misses 608system.cpu3.dcache.SwapReq_mshr_misses 54 # number of SwapReq MSHR misses 609system.cpu3.dcache.demand_mshr_misses 265 # number of demand (read+write) MSHR misses 610system.cpu3.dcache.overall_mshr_misses 265 # number of overall MSHR misses 611system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 612system.cpu3.dcache.ReadReq_mshr_miss_latency 2098000 # number of ReadReq MSHR miss cycles 613system.cpu3.dcache.WriteReq_mshr_miss_latency 1756000 # number of WriteReq MSHR miss cycles 614system.cpu3.dcache.SwapReq_mshr_miss_latency 164000 # number of SwapReq MSHR miss cycles 615system.cpu3.dcache.demand_mshr_miss_latency 3854000 # number of demand (read+write) MSHR miss cycles 616system.cpu3.dcache.overall_mshr_miss_latency 3854000 # number of overall MSHR miss cycles 617system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 618system.cpu3.dcache.ReadReq_mshr_miss_rate 0.003764 # mshr miss rate for ReadReq accesses 619system.cpu3.dcache.WriteReq_mshr_miss_rate 0.006988 # mshr miss rate for WriteReq accesses 620system.cpu3.dcache.SwapReq_mshr_miss_rate 0.830769 # mshr miss rate for SwapReq accesses 621system.cpu3.dcache.demand_mshr_miss_rate 0.004635 # mshr miss rate for demand accesses 622system.cpu3.dcache.overall_mshr_miss_rate 0.004635 # mshr miss rate for overall accesses 623system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13363.057325 # average ReadReq mshr miss latency 624system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 16259.259259 # average WriteReq mshr miss latency 625system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 3037.037037 # average SwapReq mshr miss latency 626system.cpu3.dcache.demand_avg_mshr_miss_latency 14543.396226 # average overall mshr miss latency 627system.cpu3.dcache.overall_avg_mshr_miss_latency 14543.396226 # average overall mshr miss latency 628system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 629system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 630system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 631system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 632system.l2c.replacements 0 # number of replacements 633system.l2c.tagsinuse 353.886259 # Cycle average of tags in use 634system.l2c.total_refs 1223 # Total number of references to valid blocks. 635system.l2c.sampled_refs 434 # Sample count of references to valid blocks. 636system.l2c.avg_refs 2.817972 # Average number of references to valid blocks. 637system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 638system.l2c.occ_blocks::0 286.079543 # Average occupied blocks per context 639system.l2c.occ_blocks::1 57.730360 # Average occupied blocks per context 640system.l2c.occ_blocks::2 2.746586 # Average occupied blocks per context 641system.l2c.occ_blocks::3 1.731874 # Average occupied blocks per context 642system.l2c.occ_blocks::4 5.597896 # Average occupied blocks per context 643system.l2c.occ_percent::0 0.004365 # Average percentage of cache occupancy 644system.l2c.occ_percent::1 0.000881 # Average percentage of cache occupancy 645system.l2c.occ_percent::2 0.000042 # Average percentage of cache occupancy 646system.l2c.occ_percent::3 0.000026 # Average percentage of cache occupancy 647system.l2c.occ_percent::4 0.000085 # Average percentage of cache occupancy 648system.l2c.ReadReq_hits::0 187 # number of ReadReq hits 649system.l2c.ReadReq_hits::1 305 # number of ReadReq hits 650system.l2c.ReadReq_hits::2 365 # number of ReadReq hits 651system.l2c.ReadReq_hits::3 369 # number of ReadReq hits 652system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits 653system.l2c.Writeback_hits::0 9 # number of Writeback hits 654system.l2c.Writeback_hits::total 9 # number of Writeback hits 655system.l2c.UpgradeReq_hits::0 2 # number of UpgradeReq hits 656system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 657system.l2c.demand_hits::0 187 # number of demand (read+write) hits 658system.l2c.demand_hits::1 305 # number of demand (read+write) hits 659system.l2c.demand_hits::2 365 # number of demand (read+write) hits 660system.l2c.demand_hits::3 369 # number of demand (read+write) hits 661system.l2c.demand_hits::total 1226 # number of demand (read+write) hits 662system.l2c.overall_hits::0 187 # number of overall hits 663system.l2c.overall_hits::1 305 # number of overall hits 664system.l2c.overall_hits::2 365 # number of overall hits 665system.l2c.overall_hits::3 369 # number of overall hits 666system.l2c.overall_hits::total 1226 # number of overall hits 667system.l2c.ReadReq_misses::0 351 # number of ReadReq misses 668system.l2c.ReadReq_misses::1 74 # number of ReadReq misses 669system.l2c.ReadReq_misses::2 14 # number of ReadReq misses 670system.l2c.ReadReq_misses::3 11 # number of ReadReq misses 671system.l2c.ReadReq_misses::total 450 # number of ReadReq misses 672system.l2c.UpgradeReq_misses::0 28 # number of UpgradeReq misses 673system.l2c.UpgradeReq_misses::1 12 # number of UpgradeReq misses 674system.l2c.UpgradeReq_misses::2 16 # number of UpgradeReq misses 675system.l2c.UpgradeReq_misses::3 16 # number of UpgradeReq misses 676system.l2c.UpgradeReq_misses::total 72 # number of UpgradeReq misses 677system.l2c.ReadExReq_misses::0 99 # number of ReadExReq misses 678system.l2c.ReadExReq_misses::1 15 # number of ReadExReq misses 679system.l2c.ReadExReq_misses::2 14 # number of ReadExReq misses 680system.l2c.ReadExReq_misses::3 14 # number of ReadExReq misses 681system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 682system.l2c.demand_misses::0 450 # number of demand (read+write) misses 683system.l2c.demand_misses::1 89 # number of demand (read+write) misses 684system.l2c.demand_misses::2 28 # number of demand (read+write) misses 685system.l2c.demand_misses::3 25 # number of demand (read+write) misses 686system.l2c.demand_misses::total 592 # number of demand (read+write) misses 687system.l2c.overall_misses::0 450 # number of overall misses 688system.l2c.overall_misses::1 89 # number of overall misses 689system.l2c.overall_misses::2 28 # number of overall misses 690system.l2c.overall_misses::3 25 # number of overall misses 691system.l2c.overall_misses::total 592 # number of overall misses 692system.l2c.ReadReq_miss_latency 23330000 # number of ReadReq miss cycles 693system.l2c.UpgradeReq_miss_latency 156000 # number of UpgradeReq miss cycles 694system.l2c.ReadExReq_miss_latency 7385000 # number of ReadExReq miss cycles 695system.l2c.demand_miss_latency 30715000 # number of demand (read+write) miss cycles 696system.l2c.overall_miss_latency 30715000 # number of overall miss cycles 697system.l2c.ReadReq_accesses::0 538 # number of ReadReq accesses(hits+misses) 698system.l2c.ReadReq_accesses::1 379 # number of ReadReq accesses(hits+misses) 699system.l2c.ReadReq_accesses::2 379 # number of ReadReq accesses(hits+misses) 700system.l2c.ReadReq_accesses::3 380 # number of ReadReq accesses(hits+misses) 701system.l2c.ReadReq_accesses::total 1676 # number of ReadReq accesses(hits+misses) 702system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) 703system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) 704system.l2c.UpgradeReq_accesses::0 30 # number of UpgradeReq accesses(hits+misses) 705system.l2c.UpgradeReq_accesses::1 12 # number of UpgradeReq accesses(hits+misses) 706system.l2c.UpgradeReq_accesses::2 16 # number of UpgradeReq accesses(hits+misses) 707system.l2c.UpgradeReq_accesses::3 16 # number of UpgradeReq accesses(hits+misses) 708system.l2c.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses) 709system.l2c.ReadExReq_accesses::0 99 # number of ReadExReq accesses(hits+misses) 710system.l2c.ReadExReq_accesses::1 15 # number of ReadExReq accesses(hits+misses) 711system.l2c.ReadExReq_accesses::2 14 # number of ReadExReq accesses(hits+misses) 712system.l2c.ReadExReq_accesses::3 14 # number of ReadExReq accesses(hits+misses) 713system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) 714system.l2c.demand_accesses::0 637 # number of demand (read+write) accesses 715system.l2c.demand_accesses::1 394 # number of demand (read+write) accesses 716system.l2c.demand_accesses::2 393 # number of demand (read+write) accesses 717system.l2c.demand_accesses::3 394 # number of demand (read+write) accesses 718system.l2c.demand_accesses::total 1818 # number of demand (read+write) accesses 719system.l2c.overall_accesses::0 637 # number of overall (read+write) accesses 720system.l2c.overall_accesses::1 394 # number of overall (read+write) accesses 721system.l2c.overall_accesses::2 393 # number of overall (read+write) accesses 722system.l2c.overall_accesses::3 394 # number of overall (read+write) accesses 723system.l2c.overall_accesses::total 1818 # number of overall (read+write) accesses 724system.l2c.ReadReq_miss_rate::0 0.652416 # miss rate for ReadReq accesses 725system.l2c.ReadReq_miss_rate::1 0.195251 # miss rate for ReadReq accesses 726system.l2c.ReadReq_miss_rate::2 0.036939 # miss rate for ReadReq accesses 727system.l2c.ReadReq_miss_rate::3 0.028947 # miss rate for ReadReq accesses 728system.l2c.ReadReq_miss_rate::total 0.913554 # miss rate for ReadReq accesses 729system.l2c.UpgradeReq_miss_rate::0 0.933333 # miss rate for UpgradeReq accesses 730system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses 731system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses 732system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses 733system.l2c.UpgradeReq_miss_rate::total 3.933333 # miss rate for UpgradeReq accesses 734system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses 735system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses 736system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses 737system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses 738system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses 739system.l2c.demand_miss_rate::0 0.706436 # miss rate for demand accesses 740system.l2c.demand_miss_rate::1 0.225888 # miss rate for demand accesses 741system.l2c.demand_miss_rate::2 0.071247 # miss rate for demand accesses 742system.l2c.demand_miss_rate::3 0.063452 # miss rate for demand accesses 743system.l2c.demand_miss_rate::total 1.067023 # miss rate for demand accesses 744system.l2c.overall_miss_rate::0 0.706436 # miss rate for overall accesses 745system.l2c.overall_miss_rate::1 0.225888 # miss rate for overall accesses 746system.l2c.overall_miss_rate::2 0.071247 # miss rate for overall accesses 747system.l2c.overall_miss_rate::3 0.063452 # miss rate for overall accesses 748system.l2c.overall_miss_rate::total 1.067023 # miss rate for overall accesses 749system.l2c.ReadReq_avg_miss_latency::0 66467.236467 # average ReadReq miss latency 750system.l2c.ReadReq_avg_miss_latency::1 315270.270270 # average ReadReq miss latency 751system.l2c.ReadReq_avg_miss_latency::2 1666428.571429 # average ReadReq miss latency 752system.l2c.ReadReq_avg_miss_latency::3 2120909.090909 # average ReadReq miss latency 753system.l2c.ReadReq_avg_miss_latency::total 4169075.169075 # average ReadReq miss latency 754system.l2c.UpgradeReq_avg_miss_latency::0 5571.428571 # average UpgradeReq miss latency 755system.l2c.UpgradeReq_avg_miss_latency::1 13000 # average UpgradeReq miss latency 756system.l2c.UpgradeReq_avg_miss_latency::2 9750 # average UpgradeReq miss latency 757system.l2c.UpgradeReq_avg_miss_latency::3 9750 # average UpgradeReq miss latency 758system.l2c.UpgradeReq_avg_miss_latency::total 38071.428571 # average UpgradeReq miss latency 759system.l2c.ReadExReq_avg_miss_latency::0 74595.959596 # average ReadExReq miss latency 760system.l2c.ReadExReq_avg_miss_latency::1 492333.333333 # average ReadExReq miss latency 761system.l2c.ReadExReq_avg_miss_latency::2 527500 # average ReadExReq miss latency 762system.l2c.ReadExReq_avg_miss_latency::3 527500 # average ReadExReq miss latency 763system.l2c.ReadExReq_avg_miss_latency::total 1621929.292929 # average ReadExReq miss latency 764system.l2c.demand_avg_miss_latency::0 68255.555556 # average overall miss latency 765system.l2c.demand_avg_miss_latency::1 345112.359551 # average overall miss latency 766system.l2c.demand_avg_miss_latency::2 1096964.285714 # average overall miss latency 767system.l2c.demand_avg_miss_latency::3 1228600 # average overall miss latency 768system.l2c.demand_avg_miss_latency::total 2738932.200820 # average overall miss latency 769system.l2c.overall_avg_miss_latency::0 68255.555556 # average overall miss latency 770system.l2c.overall_avg_miss_latency::1 345112.359551 # average overall miss latency 771system.l2c.overall_avg_miss_latency::2 1096964.285714 # average overall miss latency 772system.l2c.overall_avg_miss_latency::3 1228600 # average overall miss latency 773system.l2c.overall_avg_miss_latency::total 2738932.200820 # average overall miss latency 774system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 775system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 776system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 777system.l2c.blocked::no_targets 0 # number of cycles access was blocked 778system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 779system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 780system.l2c.fast_writes 0 # number of fast writes performed 781system.l2c.cache_copies 0 # number of cache copies performed 782system.l2c.writebacks 0 # number of writebacks 783system.l2c.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits 784system.l2c.demand_mshr_hits 20 # number of demand (read+write) MSHR hits 785system.l2c.overall_mshr_hits 20 # number of overall MSHR hits 786system.l2c.ReadReq_mshr_misses 430 # number of ReadReq MSHR misses 787system.l2c.UpgradeReq_mshr_misses 72 # number of UpgradeReq MSHR misses 788system.l2c.ReadExReq_mshr_misses 142 # number of ReadExReq MSHR misses 789system.l2c.demand_mshr_misses 572 # number of demand (read+write) MSHR misses 790system.l2c.overall_mshr_misses 572 # number of overall MSHR misses 791system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 792system.l2c.ReadReq_mshr_miss_latency 17203000 # number of ReadReq MSHR miss cycles 793system.l2c.UpgradeReq_mshr_miss_latency 2880000 # number of UpgradeReq MSHR miss cycles 794system.l2c.ReadExReq_mshr_miss_latency 5681000 # number of ReadExReq MSHR miss cycles 795system.l2c.demand_mshr_miss_latency 22884000 # number of demand (read+write) MSHR miss cycles 796system.l2c.overall_mshr_miss_latency 22884000 # number of overall MSHR miss cycles 797system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 798system.l2c.ReadReq_mshr_miss_rate::0 0.799257 # mshr miss rate for ReadReq accesses 799system.l2c.ReadReq_mshr_miss_rate::1 1.134565 # mshr miss rate for ReadReq accesses 800system.l2c.ReadReq_mshr_miss_rate::2 1.134565 # mshr miss rate for ReadReq accesses 801system.l2c.ReadReq_mshr_miss_rate::3 1.131579 # mshr miss rate for ReadReq accesses 802system.l2c.ReadReq_mshr_miss_rate::total 4.199965 # mshr miss rate for ReadReq accesses 803system.l2c.UpgradeReq_mshr_miss_rate::0 2.400000 # mshr miss rate for UpgradeReq accesses 804system.l2c.UpgradeReq_mshr_miss_rate::1 6 # mshr miss rate for UpgradeReq accesses 805system.l2c.UpgradeReq_mshr_miss_rate::2 4.500000 # mshr miss rate for UpgradeReq accesses 806system.l2c.UpgradeReq_mshr_miss_rate::3 4.500000 # mshr miss rate for UpgradeReq accesses 807system.l2c.UpgradeReq_mshr_miss_rate::total 17.400000 # mshr miss rate for UpgradeReq accesses 808system.l2c.ReadExReq_mshr_miss_rate::0 1.434343 # mshr miss rate for ReadExReq accesses 809system.l2c.ReadExReq_mshr_miss_rate::1 9.466667 # mshr miss rate for ReadExReq accesses 810system.l2c.ReadExReq_mshr_miss_rate::2 10.142857 # mshr miss rate for ReadExReq accesses 811system.l2c.ReadExReq_mshr_miss_rate::3 10.142857 # mshr miss rate for ReadExReq accesses 812system.l2c.ReadExReq_mshr_miss_rate::total 31.186724 # mshr miss rate for ReadExReq accesses 813system.l2c.demand_mshr_miss_rate::0 0.897959 # mshr miss rate for demand accesses 814system.l2c.demand_mshr_miss_rate::1 1.451777 # mshr miss rate for demand accesses 815system.l2c.demand_mshr_miss_rate::2 1.455471 # mshr miss rate for demand accesses 816system.l2c.demand_mshr_miss_rate::3 1.451777 # mshr miss rate for demand accesses 817system.l2c.demand_mshr_miss_rate::total 5.256983 # mshr miss rate for demand accesses 818system.l2c.overall_mshr_miss_rate::0 0.897959 # mshr miss rate for overall accesses 819system.l2c.overall_mshr_miss_rate::1 1.451777 # mshr miss rate for overall accesses 820system.l2c.overall_mshr_miss_rate::2 1.455471 # mshr miss rate for overall accesses 821system.l2c.overall_mshr_miss_rate::3 1.451777 # mshr miss rate for overall accesses 822system.l2c.overall_mshr_miss_rate::total 5.256983 # mshr miss rate for overall accesses 823system.l2c.ReadReq_avg_mshr_miss_latency 40006.976744 # average ReadReq mshr miss latency 824system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency 825system.l2c.ReadExReq_avg_mshr_miss_latency 40007.042254 # average ReadExReq mshr miss latency 826system.l2c.demand_avg_mshr_miss_latency 40006.993007 # average overall mshr miss latency 827system.l2c.overall_avg_mshr_miss_latency 40006.993007 # average overall mshr miss latency 828system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 829system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 830system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 831system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 832 833---------- End Simulation Statistics ---------- 834