stats.txt revision 11570:4aac82f10951
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000264 # Number of seconds simulated 4sim_ticks 264174500 # Number of ticks simulated 5final_tick 264174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 538178 # Simulator instruction rate (inst/s) 8host_op_rate 538161 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 214299964 # Simulator tick rate (ticks/s) 10host_mem_usage 259104 # Number of bytes of host memory used 11host_seconds 1.23 # Real time elapsed on the host 12sim_insts 663394 # Number of instructions simulated 13sim_ops 663394 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory 25system.physmem.bytes_read::total 36608 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 31system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory 39system.physmem.num_reads::total 572 # Number of read requests responded to by this memory 40system.physmem.bw_read::cpu0.inst 69045271 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu0.data 39973578 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.inst 1695849 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu1.data 3633962 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.inst 14051318 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu2.data 5572075 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.inst 969056 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu3.data 3633962 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::total 138575071 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu0.inst 69045271 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu1.inst 1695849 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu2.inst 14051318 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu3.inst 969056 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::total 85761495 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_total::cpu0.inst 69045271 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu0.data 39973578 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.inst 1695849 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu1.data 3633962 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.inst 14051318 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu2.data 5572075 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.inst 969056 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu3.data 3633962 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::total 138575071 # Total bandwidth to/from this memory (bytes/s) 63system.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 64system.cpu_clk_domain.clock 500 # Clock period in ticks 65system.cpu0.workload.num_syscalls 89 # Number of system calls 66system.cpu0.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states 67system.cpu0.numCycles 528349 # number of cpu cycles simulated 68system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 69system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 70system.cpu0.committedInsts 158268 # Number of instructions committed 71system.cpu0.committedOps 158268 # Number of ops (including micro ops) committed 72system.cpu0.num_int_alu_accesses 109004 # Number of integer alu accesses 73system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 74system.cpu0.num_func_calls 390 # number of times a function call or return occured 75system.cpu0.num_conditional_control_insts 25981 # number of instructions that are conditional controls 76system.cpu0.num_int_insts 109004 # number of integer instructions 77system.cpu0.num_fp_insts 0 # number of float instructions 78system.cpu0.num_int_register_reads 315170 # number of times the integer registers were read 79system.cpu0.num_int_register_writes 110610 # number of times the integer registers were written 80system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 81system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 82system.cpu0.num_mem_refs 73868 # number of memory refs 83system.cpu0.num_load_insts 48905 # Number of load instructions 84system.cpu0.num_store_insts 24963 # Number of store instructions 85system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles 86system.cpu0.num_busy_cycles 528348.998000 # Number of busy cycles 87system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles 88system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles 89system.cpu0.Branches 26846 # Number of branches fetched 90system.cpu0.op_class::No_OpClass 23573 14.89% 14.89% # Class of executed instruction 91system.cpu0.op_class::IntAlu 60805 38.40% 53.29% # Class of executed instruction 92system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction 93system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction 94system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction 95system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction 96system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction 97system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction 98system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction 99system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction 100system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction 101system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction 102system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction 103system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction 104system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction 105system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction 106system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction 107system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction 108system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction 109system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction 110system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction 111system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction 112system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction 113system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction 114system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction 115system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction 116system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction 117system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction 118system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction 119system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction 120system.cpu0.op_class::MemRead 48989 30.94% 84.23% # Class of executed instruction 121system.cpu0.op_class::MemWrite 24963 15.77% 100.00% # Class of executed instruction 122system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 123system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 124system.cpu0.op_class::total 158330 # Class of executed instruction 125system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 126system.cpu0.dcache.tags.replacements 2 # number of replacements 127system.cpu0.dcache.tags.tagsinuse 144.970648 # Cycle average of tags in use 128system.cpu0.dcache.tags.total_refs 73336 # Total number of references to valid blocks. 129system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 130system.cpu0.dcache.tags.avg_refs 439.137725 # Average number of references to valid blocks. 131system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 132system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.970648 # Average occupied blocks per requestor 133system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283146 # Average percentage of cache occupancy 134system.cpu0.dcache.tags.occ_percent::total 0.283146 # Average percentage of cache occupancy 135system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 136system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 137system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id 138system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 139system.cpu0.dcache.tags.tag_accesses 295705 # Number of tag accesses 140system.cpu0.dcache.tags.data_accesses 295705 # Number of data accesses 141system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 142system.cpu0.dcache.ReadReq_hits::cpu0.data 48725 # number of ReadReq hits 143system.cpu0.dcache.ReadReq_hits::total 48725 # number of ReadReq hits 144system.cpu0.dcache.WriteReq_hits::cpu0.data 24729 # number of WriteReq hits 145system.cpu0.dcache.WriteReq_hits::total 24729 # number of WriteReq hits 146system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 147system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits 148system.cpu0.dcache.demand_hits::cpu0.data 73454 # number of demand (read+write) hits 149system.cpu0.dcache.demand_hits::total 73454 # number of demand (read+write) hits 150system.cpu0.dcache.overall_hits::cpu0.data 73454 # number of overall hits 151system.cpu0.dcache.overall_hits::total 73454 # number of overall hits 152system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses 153system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses 154system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 155system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 156system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 157system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 158system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses 159system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses 160system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses 161system.cpu0.dcache.overall_misses::total 353 # number of overall misses 162system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4908500 # number of ReadReq miss cycles 163system.cpu0.dcache.ReadReq_miss_latency::total 4908500 # number of ReadReq miss cycles 164system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7106500 # number of WriteReq miss cycles 165system.cpu0.dcache.WriteReq_miss_latency::total 7106500 # number of WriteReq miss cycles 166system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 400000 # number of SwapReq miss cycles 167system.cpu0.dcache.SwapReq_miss_latency::total 400000 # number of SwapReq miss cycles 168system.cpu0.dcache.demand_miss_latency::cpu0.data 12015000 # number of demand (read+write) miss cycles 169system.cpu0.dcache.demand_miss_latency::total 12015000 # number of demand (read+write) miss cycles 170system.cpu0.dcache.overall_miss_latency::cpu0.data 12015000 # number of overall miss cycles 171system.cpu0.dcache.overall_miss_latency::total 12015000 # number of overall miss cycles 172system.cpu0.dcache.ReadReq_accesses::cpu0.data 48895 # number of ReadReq accesses(hits+misses) 173system.cpu0.dcache.ReadReq_accesses::total 48895 # number of ReadReq accesses(hits+misses) 174system.cpu0.dcache.WriteReq_accesses::cpu0.data 24912 # number of WriteReq accesses(hits+misses) 175system.cpu0.dcache.WriteReq_accesses::total 24912 # number of WriteReq accesses(hits+misses) 176system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 177system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 178system.cpu0.dcache.demand_accesses::cpu0.data 73807 # number of demand (read+write) accesses 179system.cpu0.dcache.demand_accesses::total 73807 # number of demand (read+write) accesses 180system.cpu0.dcache.overall_accesses::cpu0.data 73807 # number of overall (read+write) accesses 181system.cpu0.dcache.overall_accesses::total 73807 # number of overall (read+write) accesses 182system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003477 # miss rate for ReadReq accesses 183system.cpu0.dcache.ReadReq_miss_rate::total 0.003477 # miss rate for ReadReq accesses 184system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007346 # miss rate for WriteReq accesses 185system.cpu0.dcache.WriteReq_miss_rate::total 0.007346 # miss rate for WriteReq accesses 186system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 187system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses 188system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004783 # miss rate for demand accesses 189system.cpu0.dcache.demand_miss_rate::total 0.004783 # miss rate for demand accesses 190system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004783 # miss rate for overall accesses 191system.cpu0.dcache.overall_miss_rate::total 0.004783 # miss rate for overall accesses 192system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28873.529412 # average ReadReq miss latency 193system.cpu0.dcache.ReadReq_avg_miss_latency::total 28873.529412 # average ReadReq miss latency 194system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38833.333333 # average WriteReq miss latency 195system.cpu0.dcache.WriteReq_avg_miss_latency::total 38833.333333 # average WriteReq miss latency 196system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15384.615385 # average SwapReq miss latency 197system.cpu0.dcache.SwapReq_avg_miss_latency::total 15384.615385 # average SwapReq miss latency 198system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34036.827195 # average overall miss latency 199system.cpu0.dcache.demand_avg_miss_latency::total 34036.827195 # average overall miss latency 200system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34036.827195 # average overall miss latency 201system.cpu0.dcache.overall_avg_miss_latency::total 34036.827195 # average overall miss latency 202system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 203system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 204system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 205system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 206system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 207system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 208system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 209system.cpu0.dcache.writebacks::total 1 # number of writebacks 210system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses 211system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses 212system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 213system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 214system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 215system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 216system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses 217system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses 218system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses 219system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses 220system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4738500 # number of ReadReq MSHR miss cycles 221system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4738500 # number of ReadReq MSHR miss cycles 222system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6923500 # number of WriteReq MSHR miss cycles 223system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6923500 # number of WriteReq MSHR miss cycles 224system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374000 # number of SwapReq MSHR miss cycles 225system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374000 # number of SwapReq MSHR miss cycles 226system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11662000 # number of demand (read+write) MSHR miss cycles 227system.cpu0.dcache.demand_mshr_miss_latency::total 11662000 # number of demand (read+write) MSHR miss cycles 228system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11662000 # number of overall MSHR miss cycles 229system.cpu0.dcache.overall_mshr_miss_latency::total 11662000 # number of overall MSHR miss cycles 230system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003477 # mshr miss rate for ReadReq accesses 231system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003477 # mshr miss rate for ReadReq accesses 232system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007346 # mshr miss rate for WriteReq accesses 233system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007346 # mshr miss rate for WriteReq accesses 234system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 235system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses 236system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004783 # mshr miss rate for demand accesses 237system.cpu0.dcache.demand_mshr_miss_rate::total 0.004783 # mshr miss rate for demand accesses 238system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004783 # mshr miss rate for overall accesses 239system.cpu0.dcache.overall_mshr_miss_rate::total 0.004783 # mshr miss rate for overall accesses 240system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27873.529412 # average ReadReq mshr miss latency 241system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27873.529412 # average ReadReq mshr miss latency 242system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37833.333333 # average WriteReq mshr miss latency 243system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37833.333333 # average WriteReq mshr miss latency 244system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14384.615385 # average SwapReq mshr miss latency 245system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14384.615385 # average SwapReq mshr miss latency 246system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency 247system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency 248system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency 249system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency 250system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 251system.cpu0.icache.tags.replacements 215 # number of replacements 252system.cpu0.icache.tags.tagsinuse 211.220090 # Cycle average of tags in use 253system.cpu0.icache.tags.total_refs 157864 # Total number of references to valid blocks. 254system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 255system.cpu0.icache.tags.avg_refs 338.038544 # Average number of references to valid blocks. 256system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 257system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.220090 # Average occupied blocks per requestor 258system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412539 # Average percentage of cache occupancy 259system.cpu0.icache.tags.occ_percent::total 0.412539 # Average percentage of cache occupancy 260system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 261system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 262system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 263system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 264system.cpu0.icache.tags.tag_accesses 158798 # Number of tag accesses 265system.cpu0.icache.tags.data_accesses 158798 # Number of data accesses 266system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 267system.cpu0.icache.ReadReq_hits::cpu0.inst 157864 # number of ReadReq hits 268system.cpu0.icache.ReadReq_hits::total 157864 # number of ReadReq hits 269system.cpu0.icache.demand_hits::cpu0.inst 157864 # number of demand (read+write) hits 270system.cpu0.icache.demand_hits::total 157864 # number of demand (read+write) hits 271system.cpu0.icache.overall_hits::cpu0.inst 157864 # number of overall hits 272system.cpu0.icache.overall_hits::total 157864 # number of overall hits 273system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 274system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 275system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 276system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 277system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 278system.cpu0.icache.overall_misses::total 467 # number of overall misses 279system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20426500 # number of ReadReq miss cycles 280system.cpu0.icache.ReadReq_miss_latency::total 20426500 # number of ReadReq miss cycles 281system.cpu0.icache.demand_miss_latency::cpu0.inst 20426500 # number of demand (read+write) miss cycles 282system.cpu0.icache.demand_miss_latency::total 20426500 # number of demand (read+write) miss cycles 283system.cpu0.icache.overall_miss_latency::cpu0.inst 20426500 # number of overall miss cycles 284system.cpu0.icache.overall_miss_latency::total 20426500 # number of overall miss cycles 285system.cpu0.icache.ReadReq_accesses::cpu0.inst 158331 # number of ReadReq accesses(hits+misses) 286system.cpu0.icache.ReadReq_accesses::total 158331 # number of ReadReq accesses(hits+misses) 287system.cpu0.icache.demand_accesses::cpu0.inst 158331 # number of demand (read+write) accesses 288system.cpu0.icache.demand_accesses::total 158331 # number of demand (read+write) accesses 289system.cpu0.icache.overall_accesses::cpu0.inst 158331 # number of overall (read+write) accesses 290system.cpu0.icache.overall_accesses::total 158331 # number of overall (read+write) accesses 291system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses 292system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses 293system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses 294system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses 295system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses 296system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses 297system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43739.828694 # average ReadReq miss latency 298system.cpu0.icache.ReadReq_avg_miss_latency::total 43739.828694 # average ReadReq miss latency 299system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43739.828694 # average overall miss latency 300system.cpu0.icache.demand_avg_miss_latency::total 43739.828694 # average overall miss latency 301system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43739.828694 # average overall miss latency 302system.cpu0.icache.overall_avg_miss_latency::total 43739.828694 # average overall miss latency 303system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 304system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 305system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 306system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 307system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 308system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 309system.cpu0.icache.writebacks::writebacks 215 # number of writebacks 310system.cpu0.icache.writebacks::total 215 # number of writebacks 311system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 312system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 313system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 314system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 315system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 316system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses 317system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19959500 # number of ReadReq MSHR miss cycles 318system.cpu0.icache.ReadReq_mshr_miss_latency::total 19959500 # number of ReadReq MSHR miss cycles 319system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19959500 # number of demand (read+write) MSHR miss cycles 320system.cpu0.icache.demand_mshr_miss_latency::total 19959500 # number of demand (read+write) MSHR miss cycles 321system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19959500 # number of overall MSHR miss cycles 322system.cpu0.icache.overall_mshr_miss_latency::total 19959500 # number of overall MSHR miss cycles 323system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses 324system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses 325system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses 326system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses 327system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses 328system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses 329system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average ReadReq mshr miss latency 330system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42739.828694 # average ReadReq mshr miss latency 331system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average overall mshr miss latency 332system.cpu0.icache.demand_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency 333system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average overall mshr miss latency 334system.cpu0.icache.overall_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency 335system.cpu1.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states 336system.cpu1.numCycles 528348 # number of cpu cycles simulated 337system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 338system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 339system.cpu1.committedInsts 170000 # Number of instructions committed 340system.cpu1.committedOps 170000 # Number of ops (including micro ops) committed 341system.cpu1.num_int_alu_accesses 111041 # Number of integer alu accesses 342system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 343system.cpu1.num_func_calls 637 # number of times a function call or return occured 344system.cpu1.num_conditional_control_insts 33487 # number of instructions that are conditional controls 345system.cpu1.num_int_insts 111041 # number of integer instructions 346system.cpu1.num_fp_insts 0 # number of float instructions 347system.cpu1.num_int_register_reads 272446 # number of times the integer registers were read 348system.cpu1.num_int_register_writes 102959 # number of times the integer registers were written 349system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 350system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 351system.cpu1.num_mem_refs 53722 # number of memory refs 352system.cpu1.num_load_insts 41185 # Number of load instructions 353system.cpu1.num_store_insts 12537 # Number of store instructions 354system.cpu1.num_idle_cycles 74693.860345 # Number of idle cycles 355system.cpu1.num_busy_cycles 453654.139655 # Number of busy cycles 356system.cpu1.not_idle_fraction 0.858628 # Percentage of non-idle cycles 357system.cpu1.idle_fraction 0.141372 # Percentage of idle cycles 358system.cpu1.Branches 35142 # Number of branches fetched 359system.cpu1.op_class::No_OpClass 25921 15.24% 15.24% # Class of executed instruction 360system.cpu1.op_class::IntAlu 74786 43.98% 59.23% # Class of executed instruction 361system.cpu1.op_class::IntMult 0 0.00% 59.23% # Class of executed instruction 362system.cpu1.op_class::IntDiv 0 0.00% 59.23% # Class of executed instruction 363system.cpu1.op_class::FloatAdd 0 0.00% 59.23% # Class of executed instruction 364system.cpu1.op_class::FloatCmp 0 0.00% 59.23% # Class of executed instruction 365system.cpu1.op_class::FloatCvt 0 0.00% 59.23% # Class of executed instruction 366system.cpu1.op_class::FloatMult 0 0.00% 59.23% # Class of executed instruction 367system.cpu1.op_class::FloatDiv 0 0.00% 59.23% # Class of executed instruction 368system.cpu1.op_class::FloatSqrt 0 0.00% 59.23% # Class of executed instruction 369system.cpu1.op_class::SimdAdd 0 0.00% 59.23% # Class of executed instruction 370system.cpu1.op_class::SimdAddAcc 0 0.00% 59.23% # Class of executed instruction 371system.cpu1.op_class::SimdAlu 0 0.00% 59.23% # Class of executed instruction 372system.cpu1.op_class::SimdCmp 0 0.00% 59.23% # Class of executed instruction 373system.cpu1.op_class::SimdCvt 0 0.00% 59.23% # Class of executed instruction 374system.cpu1.op_class::SimdMisc 0 0.00% 59.23% # Class of executed instruction 375system.cpu1.op_class::SimdMult 0 0.00% 59.23% # Class of executed instruction 376system.cpu1.op_class::SimdMultAcc 0 0.00% 59.23% # Class of executed instruction 377system.cpu1.op_class::SimdShift 0 0.00% 59.23% # Class of executed instruction 378system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.23% # Class of executed instruction 379system.cpu1.op_class::SimdSqrt 0 0.00% 59.23% # Class of executed instruction 380system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.23% # Class of executed instruction 381system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.23% # Class of executed instruction 382system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.23% # Class of executed instruction 383system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.23% # Class of executed instruction 384system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.23% # Class of executed instruction 385system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.23% # Class of executed instruction 386system.cpu1.op_class::SimdFloatMult 0 0.00% 59.23% # Class of executed instruction 387system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.23% # Class of executed instruction 388system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.23% # Class of executed instruction 389system.cpu1.op_class::MemRead 56788 33.40% 92.63% # Class of executed instruction 390system.cpu1.op_class::MemWrite 12537 7.37% 100.00% # Class of executed instruction 391system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 392system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 393system.cpu1.op_class::total 170032 # Class of executed instruction 394system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 395system.cpu1.dcache.tags.replacements 0 # number of replacements 396system.cpu1.dcache.tags.tagsinuse 26.444551 # Cycle average of tags in use 397system.cpu1.dcache.tags.total_refs 27473 # Total number of references to valid blocks. 398system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 399system.cpu1.dcache.tags.avg_refs 915.766667 # Average number of references to valid blocks. 400system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 401system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.444551 # Average occupied blocks per requestor 402system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051650 # Average percentage of cache occupancy 403system.cpu1.dcache.tags.occ_percent::total 0.051650 # Average percentage of cache occupancy 404system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 405system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 406system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 407system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 408system.cpu1.dcache.tags.tag_accesses 215113 # Number of tag accesses 409system.cpu1.dcache.tags.data_accesses 215113 # Number of data accesses 410system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 411system.cpu1.dcache.ReadReq_hits::cpu1.data 41008 # number of ReadReq hits 412system.cpu1.dcache.ReadReq_hits::total 41008 # number of ReadReq hits 413system.cpu1.dcache.WriteReq_hits::cpu1.data 12359 # number of WriteReq hits 414system.cpu1.dcache.WriteReq_hits::total 12359 # number of WriteReq hits 415system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits 416system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits 417system.cpu1.dcache.demand_hits::cpu1.data 53367 # number of demand (read+write) hits 418system.cpu1.dcache.demand_hits::total 53367 # number of demand (read+write) hits 419system.cpu1.dcache.overall_hits::cpu1.data 53367 # number of overall hits 420system.cpu1.dcache.overall_hits::total 53367 # number of overall hits 421system.cpu1.dcache.ReadReq_misses::cpu1.data 169 # number of ReadReq misses 422system.cpu1.dcache.ReadReq_misses::total 169 # number of ReadReq misses 423system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses 424system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses 425system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses 426system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses 427system.cpu1.dcache.demand_misses::cpu1.data 274 # number of demand (read+write) misses 428system.cpu1.dcache.demand_misses::total 274 # number of demand (read+write) misses 429system.cpu1.dcache.overall_misses::cpu1.data 274 # number of overall misses 430system.cpu1.dcache.overall_misses::total 274 # number of overall misses 431system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1910000 # number of ReadReq miss cycles 432system.cpu1.dcache.ReadReq_miss_latency::total 1910000 # number of ReadReq miss cycles 433system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1724000 # number of WriteReq miss cycles 434system.cpu1.dcache.WriteReq_miss_latency::total 1724000 # number of WriteReq miss cycles 435system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 260500 # number of SwapReq miss cycles 436system.cpu1.dcache.SwapReq_miss_latency::total 260500 # number of SwapReq miss cycles 437system.cpu1.dcache.demand_miss_latency::cpu1.data 3634000 # number of demand (read+write) miss cycles 438system.cpu1.dcache.demand_miss_latency::total 3634000 # number of demand (read+write) miss cycles 439system.cpu1.dcache.overall_miss_latency::cpu1.data 3634000 # number of overall miss cycles 440system.cpu1.dcache.overall_miss_latency::total 3634000 # number of overall miss cycles 441system.cpu1.dcache.ReadReq_accesses::cpu1.data 41177 # number of ReadReq accesses(hits+misses) 442system.cpu1.dcache.ReadReq_accesses::total 41177 # number of ReadReq accesses(hits+misses) 443system.cpu1.dcache.WriteReq_accesses::cpu1.data 12464 # number of WriteReq accesses(hits+misses) 444system.cpu1.dcache.WriteReq_accesses::total 12464 # number of WriteReq accesses(hits+misses) 445system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 446system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 447system.cpu1.dcache.demand_accesses::cpu1.data 53641 # number of demand (read+write) accesses 448system.cpu1.dcache.demand_accesses::total 53641 # number of demand (read+write) accesses 449system.cpu1.dcache.overall_accesses::cpu1.data 53641 # number of overall (read+write) accesses 450system.cpu1.dcache.overall_accesses::total 53641 # number of overall (read+write) accesses 451system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004104 # miss rate for ReadReq accesses 452system.cpu1.dcache.ReadReq_miss_rate::total 0.004104 # miss rate for ReadReq accesses 453system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008424 # miss rate for WriteReq accesses 454system.cpu1.dcache.WriteReq_miss_rate::total 0.008424 # miss rate for WriteReq accesses 455system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.816901 # miss rate for SwapReq accesses 456system.cpu1.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses 457system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005108 # miss rate for demand accesses 458system.cpu1.dcache.demand_miss_rate::total 0.005108 # miss rate for demand accesses 459system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005108 # miss rate for overall accesses 460system.cpu1.dcache.overall_miss_rate::total 0.005108 # miss rate for overall accesses 461system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11301.775148 # average ReadReq miss latency 462system.cpu1.dcache.ReadReq_avg_miss_latency::total 11301.775148 # average ReadReq miss latency 463system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16419.047619 # average WriteReq miss latency 464system.cpu1.dcache.WriteReq_avg_miss_latency::total 16419.047619 # average WriteReq miss latency 465system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4491.379310 # average SwapReq miss latency 466system.cpu1.dcache.SwapReq_avg_miss_latency::total 4491.379310 # average SwapReq miss latency 467system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13262.773723 # average overall miss latency 468system.cpu1.dcache.demand_avg_miss_latency::total 13262.773723 # average overall miss latency 469system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13262.773723 # average overall miss latency 470system.cpu1.dcache.overall_avg_miss_latency::total 13262.773723 # average overall miss latency 471system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 472system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 473system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 474system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 475system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 476system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 477system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 169 # number of ReadReq MSHR misses 478system.cpu1.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses 479system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses 480system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 481system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses 482system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses 483system.cpu1.dcache.demand_mshr_misses::cpu1.data 274 # number of demand (read+write) MSHR misses 484system.cpu1.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses 485system.cpu1.dcache.overall_mshr_misses::cpu1.data 274 # number of overall MSHR misses 486system.cpu1.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses 487system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1741000 # number of ReadReq MSHR miss cycles 488system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1741000 # number of ReadReq MSHR miss cycles 489system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1619000 # number of WriteReq MSHR miss cycles 490system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1619000 # number of WriteReq MSHR miss cycles 491system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 202500 # number of SwapReq MSHR miss cycles 492system.cpu1.dcache.SwapReq_mshr_miss_latency::total 202500 # number of SwapReq MSHR miss cycles 493system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3360000 # number of demand (read+write) MSHR miss cycles 494system.cpu1.dcache.demand_mshr_miss_latency::total 3360000 # number of demand (read+write) MSHR miss cycles 495system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3360000 # number of overall MSHR miss cycles 496system.cpu1.dcache.overall_mshr_miss_latency::total 3360000 # number of overall MSHR miss cycles 497system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004104 # mshr miss rate for ReadReq accesses 498system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004104 # mshr miss rate for ReadReq accesses 499system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008424 # mshr miss rate for WriteReq accesses 500system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008424 # mshr miss rate for WriteReq accesses 501system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.816901 # mshr miss rate for SwapReq accesses 502system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses 503system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005108 # mshr miss rate for demand accesses 504system.cpu1.dcache.demand_mshr_miss_rate::total 0.005108 # mshr miss rate for demand accesses 505system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005108 # mshr miss rate for overall accesses 506system.cpu1.dcache.overall_mshr_miss_rate::total 0.005108 # mshr miss rate for overall accesses 507system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10301.775148 # average ReadReq mshr miss latency 508system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10301.775148 # average ReadReq mshr miss latency 509system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15419.047619 # average WriteReq mshr miss latency 510system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15419.047619 # average WriteReq mshr miss latency 511system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3491.379310 # average SwapReq mshr miss latency 512system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3491.379310 # average SwapReq mshr miss latency 513system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency 514system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency 515system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency 516system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency 517system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 518system.cpu1.icache.tags.replacements 280 # number of replacements 519system.cpu1.icache.tags.tagsinuse 66.843295 # Cycle average of tags in use 520system.cpu1.icache.tags.total_refs 169667 # Total number of references to valid blocks. 521system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 522system.cpu1.icache.tags.avg_refs 463.571038 # Average number of references to valid blocks. 523system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 524system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.843295 # Average occupied blocks per requestor 525system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130553 # Average percentage of cache occupancy 526system.cpu1.icache.tags.occ_percent::total 0.130553 # Average percentage of cache occupancy 527system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 528system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 529system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 530system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 531system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 532system.cpu1.icache.tags.tag_accesses 170399 # Number of tag accesses 533system.cpu1.icache.tags.data_accesses 170399 # Number of data accesses 534system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 535system.cpu1.icache.ReadReq_hits::cpu1.inst 169667 # number of ReadReq hits 536system.cpu1.icache.ReadReq_hits::total 169667 # number of ReadReq hits 537system.cpu1.icache.demand_hits::cpu1.inst 169667 # number of demand (read+write) hits 538system.cpu1.icache.demand_hits::total 169667 # number of demand (read+write) hits 539system.cpu1.icache.overall_hits::cpu1.inst 169667 # number of overall hits 540system.cpu1.icache.overall_hits::total 169667 # number of overall hits 541system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 542system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 543system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 544system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 545system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 546system.cpu1.icache.overall_misses::total 366 # number of overall misses 547system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5695000 # number of ReadReq miss cycles 548system.cpu1.icache.ReadReq_miss_latency::total 5695000 # number of ReadReq miss cycles 549system.cpu1.icache.demand_miss_latency::cpu1.inst 5695000 # number of demand (read+write) miss cycles 550system.cpu1.icache.demand_miss_latency::total 5695000 # number of demand (read+write) miss cycles 551system.cpu1.icache.overall_miss_latency::cpu1.inst 5695000 # number of overall miss cycles 552system.cpu1.icache.overall_miss_latency::total 5695000 # number of overall miss cycles 553system.cpu1.icache.ReadReq_accesses::cpu1.inst 170033 # number of ReadReq accesses(hits+misses) 554system.cpu1.icache.ReadReq_accesses::total 170033 # number of ReadReq accesses(hits+misses) 555system.cpu1.icache.demand_accesses::cpu1.inst 170033 # number of demand (read+write) accesses 556system.cpu1.icache.demand_accesses::total 170033 # number of demand (read+write) accesses 557system.cpu1.icache.overall_accesses::cpu1.inst 170033 # number of overall (read+write) accesses 558system.cpu1.icache.overall_accesses::total 170033 # number of overall (read+write) accesses 559system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002153 # miss rate for ReadReq accesses 560system.cpu1.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses 561system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002153 # miss rate for demand accesses 562system.cpu1.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses 563system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002153 # miss rate for overall accesses 564system.cpu1.icache.overall_miss_rate::total 0.002153 # miss rate for overall accesses 565system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15560.109290 # average ReadReq miss latency 566system.cpu1.icache.ReadReq_avg_miss_latency::total 15560.109290 # average ReadReq miss latency 567system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15560.109290 # average overall miss latency 568system.cpu1.icache.demand_avg_miss_latency::total 15560.109290 # average overall miss latency 569system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15560.109290 # average overall miss latency 570system.cpu1.icache.overall_avg_miss_latency::total 15560.109290 # average overall miss latency 571system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 572system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 573system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 574system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 575system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 576system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 577system.cpu1.icache.writebacks::writebacks 280 # number of writebacks 578system.cpu1.icache.writebacks::total 280 # number of writebacks 579system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 580system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 581system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 582system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 583system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 584system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 585system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5329000 # number of ReadReq MSHR miss cycles 586system.cpu1.icache.ReadReq_mshr_miss_latency::total 5329000 # number of ReadReq MSHR miss cycles 587system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5329000 # number of demand (read+write) MSHR miss cycles 588system.cpu1.icache.demand_mshr_miss_latency::total 5329000 # number of demand (read+write) MSHR miss cycles 589system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5329000 # number of overall MSHR miss cycles 590system.cpu1.icache.overall_mshr_miss_latency::total 5329000 # number of overall MSHR miss cycles 591system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002153 # mshr miss rate for ReadReq accesses 592system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses 593system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002153 # mshr miss rate for demand accesses 594system.cpu1.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses 595system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002153 # mshr miss rate for overall accesses 596system.cpu1.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses 597system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average ReadReq mshr miss latency 598system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14560.109290 # average ReadReq mshr miss latency 599system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average overall mshr miss latency 600system.cpu1.icache.demand_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency 601system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average overall mshr miss latency 602system.cpu1.icache.overall_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency 603system.cpu2.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states 604system.cpu2.numCycles 528349 # number of cpu cycles simulated 605system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 606system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 607system.cpu2.committedInsts 165687 # Number of instructions committed 608system.cpu2.committedOps 165687 # Number of ops (including micro ops) committed 609system.cpu2.num_int_alu_accesses 110528 # Number of integer alu accesses 610system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 611system.cpu2.num_func_calls 637 # number of times a function call or return occured 612system.cpu2.num_conditional_control_insts 31586 # number of instructions that are conditional controls 613system.cpu2.num_int_insts 110528 # number of integer instructions 614system.cpu2.num_fp_insts 0 # number of float instructions 615system.cpu2.num_int_register_reads 278004 # number of times the integer registers were read 616system.cpu2.num_int_register_writes 105995 # number of times the integer registers were written 617system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 618system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 619system.cpu2.num_mem_refs 55111 # number of memory refs 620system.cpu2.num_load_insts 40928 # Number of load instructions 621system.cpu2.num_store_insts 14183 # Number of store instructions 622system.cpu2.num_idle_cycles 74966.001716 # Number of idle cycles 623system.cpu2.num_busy_cycles 453382.998284 # Number of busy cycles 624system.cpu2.not_idle_fraction 0.858113 # Percentage of non-idle cycles 625system.cpu2.idle_fraction 0.141887 # Percentage of idle cycles 626system.cpu2.Branches 33243 # Number of branches fetched 627system.cpu2.op_class::No_OpClass 24020 14.49% 14.49% # Class of executed instruction 628system.cpu2.op_class::IntAlu 74533 44.98% 59.47% # Class of executed instruction 629system.cpu2.op_class::IntMult 0 0.00% 59.47% # Class of executed instruction 630system.cpu2.op_class::IntDiv 0 0.00% 59.47% # Class of executed instruction 631system.cpu2.op_class::FloatAdd 0 0.00% 59.47% # Class of executed instruction 632system.cpu2.op_class::FloatCmp 0 0.00% 59.47% # Class of executed instruction 633system.cpu2.op_class::FloatCvt 0 0.00% 59.47% # Class of executed instruction 634system.cpu2.op_class::FloatMult 0 0.00% 59.47% # Class of executed instruction 635system.cpu2.op_class::FloatDiv 0 0.00% 59.47% # Class of executed instruction 636system.cpu2.op_class::FloatSqrt 0 0.00% 59.47% # Class of executed instruction 637system.cpu2.op_class::SimdAdd 0 0.00% 59.47% # Class of executed instruction 638system.cpu2.op_class::SimdAddAcc 0 0.00% 59.47% # Class of executed instruction 639system.cpu2.op_class::SimdAlu 0 0.00% 59.47% # Class of executed instruction 640system.cpu2.op_class::SimdCmp 0 0.00% 59.47% # Class of executed instruction 641system.cpu2.op_class::SimdCvt 0 0.00% 59.47% # Class of executed instruction 642system.cpu2.op_class::SimdMisc 0 0.00% 59.47% # Class of executed instruction 643system.cpu2.op_class::SimdMult 0 0.00% 59.47% # Class of executed instruction 644system.cpu2.op_class::SimdMultAcc 0 0.00% 59.47% # Class of executed instruction 645system.cpu2.op_class::SimdShift 0 0.00% 59.47% # Class of executed instruction 646system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.47% # Class of executed instruction 647system.cpu2.op_class::SimdSqrt 0 0.00% 59.47% # Class of executed instruction 648system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.47% # Class of executed instruction 649system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.47% # Class of executed instruction 650system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.47% # Class of executed instruction 651system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.47% # Class of executed instruction 652system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.47% # Class of executed instruction 653system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.47% # Class of executed instruction 654system.cpu2.op_class::SimdFloatMult 0 0.00% 59.47% # Class of executed instruction 655system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.47% # Class of executed instruction 656system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.47% # Class of executed instruction 657system.cpu2.op_class::MemRead 52983 31.97% 91.44% # Class of executed instruction 658system.cpu2.op_class::MemWrite 14183 8.56% 100.00% # Class of executed instruction 659system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 660system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 661system.cpu2.op_class::total 165719 # Class of executed instruction 662system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 663system.cpu2.dcache.tags.replacements 0 # number of replacements 664system.cpu2.dcache.tags.tagsinuse 27.447331 # Cycle average of tags in use 665system.cpu2.dcache.tags.total_refs 30642 # Total number of references to valid blocks. 666system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 667system.cpu2.dcache.tags.avg_refs 1056.620690 # Average number of references to valid blocks. 668system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 669system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.447331 # Average occupied blocks per requestor 670system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053608 # Average percentage of cache occupancy 671system.cpu2.dcache.tags.occ_percent::total 0.053608 # Average percentage of cache occupancy 672system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 673system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 674system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 675system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 676system.cpu2.dcache.tags.tag_accesses 220669 # Number of tag accesses 677system.cpu2.dcache.tags.data_accesses 220669 # Number of data accesses 678system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 679system.cpu2.dcache.ReadReq_hits::cpu2.data 40751 # number of ReadReq hits 680system.cpu2.dcache.ReadReq_hits::total 40751 # number of ReadReq hits 681system.cpu2.dcache.WriteReq_hits::cpu2.data 14004 # number of WriteReq hits 682system.cpu2.dcache.WriteReq_hits::total 14004 # number of WriteReq hits 683system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits 684system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits 685system.cpu2.dcache.demand_hits::cpu2.data 54755 # number of demand (read+write) hits 686system.cpu2.dcache.demand_hits::total 54755 # number of demand (read+write) hits 687system.cpu2.dcache.overall_hits::cpu2.data 54755 # number of overall hits 688system.cpu2.dcache.overall_hits::total 54755 # number of overall hits 689system.cpu2.dcache.ReadReq_misses::cpu2.data 169 # number of ReadReq misses 690system.cpu2.dcache.ReadReq_misses::total 169 # number of ReadReq misses 691system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses 692system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses 693system.cpu2.dcache.SwapReq_misses::cpu2.data 60 # number of SwapReq misses 694system.cpu2.dcache.SwapReq_misses::total 60 # number of SwapReq misses 695system.cpu2.dcache.demand_misses::cpu2.data 274 # number of demand (read+write) misses 696system.cpu2.dcache.demand_misses::total 274 # number of demand (read+write) misses 697system.cpu2.dcache.overall_misses::cpu2.data 274 # number of overall misses 698system.cpu2.dcache.overall_misses::total 274 # number of overall misses 699system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2144500 # number of ReadReq miss cycles 700system.cpu2.dcache.ReadReq_miss_latency::total 2144500 # number of ReadReq miss cycles 701system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1802500 # number of WriteReq miss cycles 702system.cpu2.dcache.WriteReq_miss_latency::total 1802500 # number of WriteReq miss cycles 703system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 267500 # number of SwapReq miss cycles 704system.cpu2.dcache.SwapReq_miss_latency::total 267500 # number of SwapReq miss cycles 705system.cpu2.dcache.demand_miss_latency::cpu2.data 3947000 # number of demand (read+write) miss cycles 706system.cpu2.dcache.demand_miss_latency::total 3947000 # number of demand (read+write) miss cycles 707system.cpu2.dcache.overall_miss_latency::cpu2.data 3947000 # number of overall miss cycles 708system.cpu2.dcache.overall_miss_latency::total 3947000 # number of overall miss cycles 709system.cpu2.dcache.ReadReq_accesses::cpu2.data 40920 # number of ReadReq accesses(hits+misses) 710system.cpu2.dcache.ReadReq_accesses::total 40920 # number of ReadReq accesses(hits+misses) 711system.cpu2.dcache.WriteReq_accesses::cpu2.data 14109 # number of WriteReq accesses(hits+misses) 712system.cpu2.dcache.WriteReq_accesses::total 14109 # number of WriteReq accesses(hits+misses) 713system.cpu2.dcache.SwapReq_accesses::cpu2.data 72 # number of SwapReq accesses(hits+misses) 714system.cpu2.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) 715system.cpu2.dcache.demand_accesses::cpu2.data 55029 # number of demand (read+write) accesses 716system.cpu2.dcache.demand_accesses::total 55029 # number of demand (read+write) accesses 717system.cpu2.dcache.overall_accesses::cpu2.data 55029 # number of overall (read+write) accesses 718system.cpu2.dcache.overall_accesses::total 55029 # number of overall (read+write) accesses 719system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004130 # miss rate for ReadReq accesses 720system.cpu2.dcache.ReadReq_miss_rate::total 0.004130 # miss rate for ReadReq accesses 721system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007442 # miss rate for WriteReq accesses 722system.cpu2.dcache.WriteReq_miss_rate::total 0.007442 # miss rate for WriteReq accesses 723system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses 724system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses 725system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004979 # miss rate for demand accesses 726system.cpu2.dcache.demand_miss_rate::total 0.004979 # miss rate for demand accesses 727system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004979 # miss rate for overall accesses 728system.cpu2.dcache.overall_miss_rate::total 0.004979 # miss rate for overall accesses 729system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12689.349112 # average ReadReq miss latency 730system.cpu2.dcache.ReadReq_avg_miss_latency::total 12689.349112 # average ReadReq miss latency 731system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17166.666667 # average WriteReq miss latency 732system.cpu2.dcache.WriteReq_avg_miss_latency::total 17166.666667 # average WriteReq miss latency 733system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4458.333333 # average SwapReq miss latency 734system.cpu2.dcache.SwapReq_avg_miss_latency::total 4458.333333 # average SwapReq miss latency 735system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14405.109489 # average overall miss latency 736system.cpu2.dcache.demand_avg_miss_latency::total 14405.109489 # average overall miss latency 737system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14405.109489 # average overall miss latency 738system.cpu2.dcache.overall_avg_miss_latency::total 14405.109489 # average overall miss latency 739system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 740system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 741system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 742system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 743system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 744system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 745system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 169 # number of ReadReq MSHR misses 746system.cpu2.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses 747system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses 748system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 749system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 60 # number of SwapReq MSHR misses 750system.cpu2.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses 751system.cpu2.dcache.demand_mshr_misses::cpu2.data 274 # number of demand (read+write) MSHR misses 752system.cpu2.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses 753system.cpu2.dcache.overall_mshr_misses::cpu2.data 274 # number of overall MSHR misses 754system.cpu2.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses 755system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1975500 # number of ReadReq MSHR miss cycles 756system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1975500 # number of ReadReq MSHR miss cycles 757system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1697500 # number of WriteReq MSHR miss cycles 758system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1697500 # number of WriteReq MSHR miss cycles 759system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 207500 # number of SwapReq MSHR miss cycles 760system.cpu2.dcache.SwapReq_mshr_miss_latency::total 207500 # number of SwapReq MSHR miss cycles 761system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3673000 # number of demand (read+write) MSHR miss cycles 762system.cpu2.dcache.demand_mshr_miss_latency::total 3673000 # number of demand (read+write) MSHR miss cycles 763system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3673000 # number of overall MSHR miss cycles 764system.cpu2.dcache.overall_mshr_miss_latency::total 3673000 # number of overall MSHR miss cycles 765system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004130 # mshr miss rate for ReadReq accesses 766system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004130 # mshr miss rate for ReadReq accesses 767system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007442 # mshr miss rate for WriteReq accesses 768system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007442 # mshr miss rate for WriteReq accesses 769system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses 770system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses 771system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004979 # mshr miss rate for demand accesses 772system.cpu2.dcache.demand_mshr_miss_rate::total 0.004979 # mshr miss rate for demand accesses 773system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004979 # mshr miss rate for overall accesses 774system.cpu2.dcache.overall_mshr_miss_rate::total 0.004979 # mshr miss rate for overall accesses 775system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11689.349112 # average ReadReq mshr miss latency 776system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11689.349112 # average ReadReq mshr miss latency 777system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16166.666667 # average WriteReq mshr miss latency 778system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16166.666667 # average WriteReq mshr miss latency 779system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3458.333333 # average SwapReq mshr miss latency 780system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3458.333333 # average SwapReq mshr miss latency 781system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13405.109489 # average overall mshr miss latency 782system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency 783system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13405.109489 # average overall mshr miss latency 784system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency 785system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 786system.cpu2.icache.tags.replacements 280 # number of replacements 787system.cpu2.icache.tags.tagsinuse 69.258301 # Cycle average of tags in use 788system.cpu2.icache.tags.total_refs 165354 # Total number of references to valid blocks. 789system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 790system.cpu2.icache.tags.avg_refs 451.786885 # Average number of references to valid blocks. 791system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 792system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.258301 # Average occupied blocks per requestor 793system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135270 # Average percentage of cache occupancy 794system.cpu2.icache.tags.occ_percent::total 0.135270 # Average percentage of cache occupancy 795system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 796system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 797system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 798system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 799system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 800system.cpu2.icache.tags.tag_accesses 166086 # Number of tag accesses 801system.cpu2.icache.tags.data_accesses 166086 # Number of data accesses 802system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 803system.cpu2.icache.ReadReq_hits::cpu2.inst 165354 # number of ReadReq hits 804system.cpu2.icache.ReadReq_hits::total 165354 # number of ReadReq hits 805system.cpu2.icache.demand_hits::cpu2.inst 165354 # number of demand (read+write) hits 806system.cpu2.icache.demand_hits::total 165354 # number of demand (read+write) hits 807system.cpu2.icache.overall_hits::cpu2.inst 165354 # number of overall hits 808system.cpu2.icache.overall_hits::total 165354 # number of overall hits 809system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 810system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 811system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 812system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 813system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 814system.cpu2.icache.overall_misses::total 366 # number of overall misses 815system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8165500 # number of ReadReq miss cycles 816system.cpu2.icache.ReadReq_miss_latency::total 8165500 # number of ReadReq miss cycles 817system.cpu2.icache.demand_miss_latency::cpu2.inst 8165500 # number of demand (read+write) miss cycles 818system.cpu2.icache.demand_miss_latency::total 8165500 # number of demand (read+write) miss cycles 819system.cpu2.icache.overall_miss_latency::cpu2.inst 8165500 # number of overall miss cycles 820system.cpu2.icache.overall_miss_latency::total 8165500 # number of overall miss cycles 821system.cpu2.icache.ReadReq_accesses::cpu2.inst 165720 # number of ReadReq accesses(hits+misses) 822system.cpu2.icache.ReadReq_accesses::total 165720 # number of ReadReq accesses(hits+misses) 823system.cpu2.icache.demand_accesses::cpu2.inst 165720 # number of demand (read+write) accesses 824system.cpu2.icache.demand_accesses::total 165720 # number of demand (read+write) accesses 825system.cpu2.icache.overall_accesses::cpu2.inst 165720 # number of overall (read+write) accesses 826system.cpu2.icache.overall_accesses::total 165720 # number of overall (read+write) accesses 827system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002209 # miss rate for ReadReq accesses 828system.cpu2.icache.ReadReq_miss_rate::total 0.002209 # miss rate for ReadReq accesses 829system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002209 # miss rate for demand accesses 830system.cpu2.icache.demand_miss_rate::total 0.002209 # miss rate for demand accesses 831system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002209 # miss rate for overall accesses 832system.cpu2.icache.overall_miss_rate::total 0.002209 # miss rate for overall accesses 833system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22310.109290 # average ReadReq miss latency 834system.cpu2.icache.ReadReq_avg_miss_latency::total 22310.109290 # average ReadReq miss latency 835system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22310.109290 # average overall miss latency 836system.cpu2.icache.demand_avg_miss_latency::total 22310.109290 # average overall miss latency 837system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22310.109290 # average overall miss latency 838system.cpu2.icache.overall_avg_miss_latency::total 22310.109290 # average overall miss latency 839system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 840system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 841system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 842system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 843system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 844system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 845system.cpu2.icache.writebacks::writebacks 280 # number of writebacks 846system.cpu2.icache.writebacks::total 280 # number of writebacks 847system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 848system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 849system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 850system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 851system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 852system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 853system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7799500 # number of ReadReq MSHR miss cycles 854system.cpu2.icache.ReadReq_mshr_miss_latency::total 7799500 # number of ReadReq MSHR miss cycles 855system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7799500 # number of demand (read+write) MSHR miss cycles 856system.cpu2.icache.demand_mshr_miss_latency::total 7799500 # number of demand (read+write) MSHR miss cycles 857system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7799500 # number of overall MSHR miss cycles 858system.cpu2.icache.overall_mshr_miss_latency::total 7799500 # number of overall MSHR miss cycles 859system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002209 # mshr miss rate for ReadReq accesses 860system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002209 # mshr miss rate for ReadReq accesses 861system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002209 # mshr miss rate for demand accesses 862system.cpu2.icache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses 863system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002209 # mshr miss rate for overall accesses 864system.cpu2.icache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses 865system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average ReadReq mshr miss latency 866system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21310.109290 # average ReadReq mshr miss latency 867system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average overall mshr miss latency 868system.cpu2.icache.demand_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency 869system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average overall mshr miss latency 870system.cpu2.icache.overall_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency 871system.cpu3.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states 872system.cpu3.numCycles 528348 # number of cpu cycles simulated 873system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 874system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 875system.cpu3.committedInsts 169439 # Number of instructions committed 876system.cpu3.committedOps 169439 # Number of ops (including micro ops) committed 877system.cpu3.num_int_alu_accesses 111342 # Number of integer alu accesses 878system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 879system.cpu3.num_func_calls 637 # number of times a function call or return occured 880system.cpu3.num_conditional_control_insts 33059 # number of instructions that are conditional controls 881system.cpu3.num_int_insts 111342 # number of integer instructions 882system.cpu3.num_fp_insts 0 # number of float instructions 883system.cpu3.num_int_register_reads 275359 # number of times the integer registers were read 884system.cpu3.num_int_register_writes 104262 # number of times the integer registers were written 885system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 886system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 887system.cpu3.num_mem_refs 54451 # number of memory refs 888system.cpu3.num_load_insts 41338 # Number of load instructions 889system.cpu3.num_store_insts 13113 # Number of store instructions 890system.cpu3.num_idle_cycles 75238.859311 # Number of idle cycles 891system.cpu3.num_busy_cycles 453109.140689 # Number of busy cycles 892system.cpu3.not_idle_fraction 0.857596 # Percentage of non-idle cycles 893system.cpu3.idle_fraction 0.142404 # Percentage of idle cycles 894system.cpu3.Branches 34709 # Number of branches fetched 895system.cpu3.op_class::No_OpClass 25492 15.04% 15.04% # Class of executed instruction 896system.cpu3.op_class::IntAlu 74930 44.21% 59.26% # Class of executed instruction 897system.cpu3.op_class::IntMult 0 0.00% 59.26% # Class of executed instruction 898system.cpu3.op_class::IntDiv 0 0.00% 59.26% # Class of executed instruction 899system.cpu3.op_class::FloatAdd 0 0.00% 59.26% # Class of executed instruction 900system.cpu3.op_class::FloatCmp 0 0.00% 59.26% # Class of executed instruction 901system.cpu3.op_class::FloatCvt 0 0.00% 59.26% # Class of executed instruction 902system.cpu3.op_class::FloatMult 0 0.00% 59.26% # Class of executed instruction 903system.cpu3.op_class::FloatDiv 0 0.00% 59.26% # Class of executed instruction 904system.cpu3.op_class::FloatSqrt 0 0.00% 59.26% # Class of executed instruction 905system.cpu3.op_class::SimdAdd 0 0.00% 59.26% # Class of executed instruction 906system.cpu3.op_class::SimdAddAcc 0 0.00% 59.26% # Class of executed instruction 907system.cpu3.op_class::SimdAlu 0 0.00% 59.26% # Class of executed instruction 908system.cpu3.op_class::SimdCmp 0 0.00% 59.26% # Class of executed instruction 909system.cpu3.op_class::SimdCvt 0 0.00% 59.26% # Class of executed instruction 910system.cpu3.op_class::SimdMisc 0 0.00% 59.26% # Class of executed instruction 911system.cpu3.op_class::SimdMult 0 0.00% 59.26% # Class of executed instruction 912system.cpu3.op_class::SimdMultAcc 0 0.00% 59.26% # Class of executed instruction 913system.cpu3.op_class::SimdShift 0 0.00% 59.26% # Class of executed instruction 914system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.26% # Class of executed instruction 915system.cpu3.op_class::SimdSqrt 0 0.00% 59.26% # Class of executed instruction 916system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.26% # Class of executed instruction 917system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.26% # Class of executed instruction 918system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.26% # Class of executed instruction 919system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.26% # Class of executed instruction 920system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.26% # Class of executed instruction 921system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.26% # Class of executed instruction 922system.cpu3.op_class::SimdFloatMult 0 0.00% 59.26% # Class of executed instruction 923system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.26% # Class of executed instruction 924system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.26% # Class of executed instruction 925system.cpu3.op_class::MemRead 55936 33.01% 92.26% # Class of executed instruction 926system.cpu3.op_class::MemWrite 13113 7.74% 100.00% # Class of executed instruction 927system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 928system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 929system.cpu3.op_class::total 169471 # Class of executed instruction 930system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 931system.cpu3.dcache.tags.replacements 0 # number of replacements 932system.cpu3.dcache.tags.tagsinuse 25.601960 # Cycle average of tags in use 933system.cpu3.dcache.tags.total_refs 28504 # Total number of references to valid blocks. 934system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 935system.cpu3.dcache.tags.avg_refs 982.896552 # Average number of references to valid blocks. 936system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 937system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.601960 # Average occupied blocks per requestor 938system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050004 # Average percentage of cache occupancy 939system.cpu3.dcache.tags.occ_percent::total 0.050004 # Average percentage of cache occupancy 940system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 941system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 942system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 943system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 944system.cpu3.dcache.tags.tag_accesses 218004 # Number of tag accesses 945system.cpu3.dcache.tags.data_accesses 218004 # Number of data accesses 946system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 947system.cpu3.dcache.ReadReq_hits::cpu3.data 41179 # number of ReadReq hits 948system.cpu3.dcache.ReadReq_hits::total 41179 # number of ReadReq hits 949system.cpu3.dcache.WriteReq_hits::cpu3.data 12939 # number of WriteReq hits 950system.cpu3.dcache.WriteReq_hits::total 12939 # number of WriteReq hits 951system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 952system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 953system.cpu3.dcache.demand_hits::cpu3.data 54118 # number of demand (read+write) hits 954system.cpu3.dcache.demand_hits::total 54118 # number of demand (read+write) hits 955system.cpu3.dcache.overall_hits::cpu3.data 54118 # number of overall hits 956system.cpu3.dcache.overall_hits::total 54118 # number of overall hits 957system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses 958system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses 959system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses 960system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses 961system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses 962system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses 963system.cpu3.dcache.demand_misses::cpu3.data 256 # number of demand (read+write) misses 964system.cpu3.dcache.demand_misses::total 256 # number of demand (read+write) misses 965system.cpu3.dcache.overall_misses::cpu3.data 256 # number of overall misses 966system.cpu3.dcache.overall_misses::total 256 # number of overall misses 967system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1675000 # number of ReadReq miss cycles 968system.cpu3.dcache.ReadReq_miss_latency::total 1675000 # number of ReadReq miss cycles 969system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1736000 # number of WriteReq miss cycles 970system.cpu3.dcache.WriteReq_miss_latency::total 1736000 # number of WriteReq miss cycles 971system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 234000 # number of SwapReq miss cycles 972system.cpu3.dcache.SwapReq_miss_latency::total 234000 # number of SwapReq miss cycles 973system.cpu3.dcache.demand_miss_latency::cpu3.data 3411000 # number of demand (read+write) miss cycles 974system.cpu3.dcache.demand_miss_latency::total 3411000 # number of demand (read+write) miss cycles 975system.cpu3.dcache.overall_miss_latency::cpu3.data 3411000 # number of overall miss cycles 976system.cpu3.dcache.overall_miss_latency::total 3411000 # number of overall miss cycles 977system.cpu3.dcache.ReadReq_accesses::cpu3.data 41330 # number of ReadReq accesses(hits+misses) 978system.cpu3.dcache.ReadReq_accesses::total 41330 # number of ReadReq accesses(hits+misses) 979system.cpu3.dcache.WriteReq_accesses::cpu3.data 13044 # number of WriteReq accesses(hits+misses) 980system.cpu3.dcache.WriteReq_accesses::total 13044 # number of WriteReq accesses(hits+misses) 981system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) 982system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) 983system.cpu3.dcache.demand_accesses::cpu3.data 54374 # number of demand (read+write) accesses 984system.cpu3.dcache.demand_accesses::total 54374 # number of demand (read+write) accesses 985system.cpu3.dcache.overall_accesses::cpu3.data 54374 # number of overall (read+write) accesses 986system.cpu3.dcache.overall_accesses::total 54374 # number of overall (read+write) accesses 987system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003654 # miss rate for ReadReq accesses 988system.cpu3.dcache.ReadReq_miss_rate::total 0.003654 # miss rate for ReadReq accesses 989system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008050 # miss rate for WriteReq accesses 990system.cpu3.dcache.WriteReq_miss_rate::total 0.008050 # miss rate for WriteReq accesses 991system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.776119 # miss rate for SwapReq accesses 992system.cpu3.dcache.SwapReq_miss_rate::total 0.776119 # miss rate for SwapReq accesses 993system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004708 # miss rate for demand accesses 994system.cpu3.dcache.demand_miss_rate::total 0.004708 # miss rate for demand accesses 995system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004708 # miss rate for overall accesses 996system.cpu3.dcache.overall_miss_rate::total 0.004708 # miss rate for overall accesses 997system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 11092.715232 # average ReadReq miss latency 998system.cpu3.dcache.ReadReq_avg_miss_latency::total 11092.715232 # average ReadReq miss latency 999system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16533.333333 # average WriteReq miss latency 1000system.cpu3.dcache.WriteReq_avg_miss_latency::total 16533.333333 # average WriteReq miss latency 1001system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4500 # average SwapReq miss latency 1002system.cpu3.dcache.SwapReq_avg_miss_latency::total 4500 # average SwapReq miss latency 1003system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13324.218750 # average overall miss latency 1004system.cpu3.dcache.demand_avg_miss_latency::total 13324.218750 # average overall miss latency 1005system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13324.218750 # average overall miss latency 1006system.cpu3.dcache.overall_avg_miss_latency::total 13324.218750 # average overall miss latency 1007system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1008system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1009system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1010system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 1011system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1012system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1013system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 151 # number of ReadReq MSHR misses 1014system.cpu3.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses 1015system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses 1016system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 1017system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses 1018system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses 1019system.cpu3.dcache.demand_mshr_misses::cpu3.data 256 # number of demand (read+write) MSHR misses 1020system.cpu3.dcache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses 1021system.cpu3.dcache.overall_mshr_misses::cpu3.data 256 # number of overall MSHR misses 1022system.cpu3.dcache.overall_mshr_misses::total 256 # number of overall MSHR misses 1023system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1524000 # number of ReadReq MSHR miss cycles 1024system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1524000 # number of ReadReq MSHR miss cycles 1025system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1631000 # number of WriteReq MSHR miss cycles 1026system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1631000 # number of WriteReq MSHR miss cycles 1027system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 182000 # number of SwapReq MSHR miss cycles 1028system.cpu3.dcache.SwapReq_mshr_miss_latency::total 182000 # number of SwapReq MSHR miss cycles 1029system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3155000 # number of demand (read+write) MSHR miss cycles 1030system.cpu3.dcache.demand_mshr_miss_latency::total 3155000 # number of demand (read+write) MSHR miss cycles 1031system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3155000 # number of overall MSHR miss cycles 1032system.cpu3.dcache.overall_mshr_miss_latency::total 3155000 # number of overall MSHR miss cycles 1033system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003654 # mshr miss rate for ReadReq accesses 1034system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003654 # mshr miss rate for ReadReq accesses 1035system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008050 # mshr miss rate for WriteReq accesses 1036system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008050 # mshr miss rate for WriteReq accesses 1037system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.776119 # mshr miss rate for SwapReq accesses 1038system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.776119 # mshr miss rate for SwapReq accesses 1039system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004708 # mshr miss rate for demand accesses 1040system.cpu3.dcache.demand_mshr_miss_rate::total 0.004708 # mshr miss rate for demand accesses 1041system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004708 # mshr miss rate for overall accesses 1042system.cpu3.dcache.overall_mshr_miss_rate::total 0.004708 # mshr miss rate for overall accesses 1043system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10092.715232 # average ReadReq mshr miss latency 1044system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10092.715232 # average ReadReq mshr miss latency 1045system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15533.333333 # average WriteReq mshr miss latency 1046system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15533.333333 # average WriteReq mshr miss latency 1047system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3500 # average SwapReq mshr miss latency 1048system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3500 # average SwapReq mshr miss latency 1049system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency 1050system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency 1051system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency 1052system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency 1053system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 1054system.cpu3.icache.tags.replacements 281 # number of replacements 1055system.cpu3.icache.tags.tagsinuse 64.834449 # Cycle average of tags in use 1056system.cpu3.icache.tags.total_refs 169105 # Total number of references to valid blocks. 1057system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 1058system.cpu3.icache.tags.avg_refs 460.776567 # Average number of references to valid blocks. 1059system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1060system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.834449 # Average occupied blocks per requestor 1061system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126630 # Average percentage of cache occupancy 1062system.cpu3.icache.tags.occ_percent::total 0.126630 # Average percentage of cache occupancy 1063system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1064system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1065system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 1066system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1067system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 1068system.cpu3.icache.tags.tag_accesses 169839 # Number of tag accesses 1069system.cpu3.icache.tags.data_accesses 169839 # Number of data accesses 1070system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 1071system.cpu3.icache.ReadReq_hits::cpu3.inst 169105 # number of ReadReq hits 1072system.cpu3.icache.ReadReq_hits::total 169105 # number of ReadReq hits 1073system.cpu3.icache.demand_hits::cpu3.inst 169105 # number of demand (read+write) hits 1074system.cpu3.icache.demand_hits::total 169105 # number of demand (read+write) hits 1075system.cpu3.icache.overall_hits::cpu3.inst 169105 # number of overall hits 1076system.cpu3.icache.overall_hits::total 169105 # number of overall hits 1077system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 1078system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 1079system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 1080system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 1081system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 1082system.cpu3.icache.overall_misses::total 367 # number of overall misses 1083system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5481500 # number of ReadReq miss cycles 1084system.cpu3.icache.ReadReq_miss_latency::total 5481500 # number of ReadReq miss cycles 1085system.cpu3.icache.demand_miss_latency::cpu3.inst 5481500 # number of demand (read+write) miss cycles 1086system.cpu3.icache.demand_miss_latency::total 5481500 # number of demand (read+write) miss cycles 1087system.cpu3.icache.overall_miss_latency::cpu3.inst 5481500 # number of overall miss cycles 1088system.cpu3.icache.overall_miss_latency::total 5481500 # number of overall miss cycles 1089system.cpu3.icache.ReadReq_accesses::cpu3.inst 169472 # number of ReadReq accesses(hits+misses) 1090system.cpu3.icache.ReadReq_accesses::total 169472 # number of ReadReq accesses(hits+misses) 1091system.cpu3.icache.demand_accesses::cpu3.inst 169472 # number of demand (read+write) accesses 1092system.cpu3.icache.demand_accesses::total 169472 # number of demand (read+write) accesses 1093system.cpu3.icache.overall_accesses::cpu3.inst 169472 # number of overall (read+write) accesses 1094system.cpu3.icache.overall_accesses::total 169472 # number of overall (read+write) accesses 1095system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002166 # miss rate for ReadReq accesses 1096system.cpu3.icache.ReadReq_miss_rate::total 0.002166 # miss rate for ReadReq accesses 1097system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002166 # miss rate for demand accesses 1098system.cpu3.icache.demand_miss_rate::total 0.002166 # miss rate for demand accesses 1099system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002166 # miss rate for overall accesses 1100system.cpu3.icache.overall_miss_rate::total 0.002166 # miss rate for overall accesses 1101system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14935.967302 # average ReadReq miss latency 1102system.cpu3.icache.ReadReq_avg_miss_latency::total 14935.967302 # average ReadReq miss latency 1103system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14935.967302 # average overall miss latency 1104system.cpu3.icache.demand_avg_miss_latency::total 14935.967302 # average overall miss latency 1105system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14935.967302 # average overall miss latency 1106system.cpu3.icache.overall_avg_miss_latency::total 14935.967302 # average overall miss latency 1107system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1108system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1109system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1110system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1111system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1112system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1113system.cpu3.icache.writebacks::writebacks 281 # number of writebacks 1114system.cpu3.icache.writebacks::total 281 # number of writebacks 1115system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 1116system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 1117system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 1118system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 1119system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 1120system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 1121system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5114500 # number of ReadReq MSHR miss cycles 1122system.cpu3.icache.ReadReq_mshr_miss_latency::total 5114500 # number of ReadReq MSHR miss cycles 1123system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5114500 # number of demand (read+write) MSHR miss cycles 1124system.cpu3.icache.demand_mshr_miss_latency::total 5114500 # number of demand (read+write) MSHR miss cycles 1125system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5114500 # number of overall MSHR miss cycles 1126system.cpu3.icache.overall_mshr_miss_latency::total 5114500 # number of overall MSHR miss cycles 1127system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002166 # mshr miss rate for ReadReq accesses 1128system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses 1129system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002166 # mshr miss rate for demand accesses 1130system.cpu3.icache.demand_mshr_miss_rate::total 0.002166 # mshr miss rate for demand accesses 1131system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002166 # mshr miss rate for overall accesses 1132system.cpu3.icache.overall_mshr_miss_rate::total 0.002166 # mshr miss rate for overall accesses 1133system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average ReadReq mshr miss latency 1134system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13935.967302 # average ReadReq mshr miss latency 1135system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average overall mshr miss latency 1136system.cpu3.icache.demand_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency 1137system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average overall mshr miss latency 1138system.cpu3.icache.overall_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency 1139system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 1140system.l2c.tags.replacements 0 # number of replacements 1141system.l2c.tags.tagsinuse 346.893205 # Cycle average of tags in use 1142system.l2c.tags.total_refs 1714 # Total number of references to valid blocks. 1143system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 1144system.l2c.tags.avg_refs 3.995338 # Average number of references to valid blocks. 1145system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1146system.l2c.tags.occ_blocks::writebacks 0.880236 # Average occupied blocks per requestor 1147system.l2c.tags.occ_blocks::cpu0.inst 230.548613 # Average occupied blocks per requestor 1148system.l2c.tags.occ_blocks::cpu0.data 53.975789 # Average occupied blocks per requestor 1149system.l2c.tags.occ_blocks::cpu1.inst 6.154320 # Average occupied blocks per requestor 1150system.l2c.tags.occ_blocks::cpu1.data 0.833705 # Average occupied blocks per requestor 1151system.l2c.tags.occ_blocks::cpu2.inst 46.678374 # Average occupied blocks per requestor 1152system.l2c.tags.occ_blocks::cpu2.data 6.077199 # Average occupied blocks per requestor 1153system.l2c.tags.occ_blocks::cpu3.inst 0.942850 # Average occupied blocks per requestor 1154system.l2c.tags.occ_blocks::cpu3.data 0.802119 # Average occupied blocks per requestor 1155system.l2c.tags.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy 1156system.l2c.tags.occ_percent::cpu0.inst 0.003518 # Average percentage of cache occupancy 1157system.l2c.tags.occ_percent::cpu0.data 0.000824 # Average percentage of cache occupancy 1158system.l2c.tags.occ_percent::cpu1.inst 0.000094 # Average percentage of cache occupancy 1159system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy 1160system.l2c.tags.occ_percent::cpu2.inst 0.000712 # Average percentage of cache occupancy 1161system.l2c.tags.occ_percent::cpu2.data 0.000093 # Average percentage of cache occupancy 1162system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy 1163system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy 1164system.l2c.tags.occ_percent::total 0.005293 # Average percentage of cache occupancy 1165system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id 1166system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 1167system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id 1168system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id 1169system.l2c.tags.tag_accesses 19677 # Number of tag accesses 1170system.l2c.tags.data_accesses 19677 # Number of data accesses 1171system.l2c.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 1172system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 1173system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 1174system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits 1175system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits 1176system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 1177system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 1178system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits 1179system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits 1180system.l2c.ReadCleanReq_hits::cpu2.inst 301 # number of ReadCleanReq hits 1181system.l2c.ReadCleanReq_hits::cpu3.inst 357 # number of ReadCleanReq hits 1182system.l2c.ReadCleanReq_hits::total 1192 # number of ReadCleanReq hits 1183system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 1184system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits 1185system.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits 1186system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits 1187system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits 1188system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits 1189system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 1190system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits 1191system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits 1192system.l2c.demand_hits::cpu2.inst 301 # number of demand (read+write) hits 1193system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits 1194system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits 1195system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 1196system.l2c.demand_hits::total 1218 # number of demand (read+write) hits 1197system.l2c.overall_hits::cpu0.inst 182 # number of overall hits 1198system.l2c.overall_hits::cpu0.data 5 # number of overall hits 1199system.l2c.overall_hits::cpu1.inst 352 # number of overall hits 1200system.l2c.overall_hits::cpu1.data 9 # number of overall hits 1201system.l2c.overall_hits::cpu2.inst 301 # number of overall hits 1202system.l2c.overall_hits::cpu2.data 3 # number of overall hits 1203system.l2c.overall_hits::cpu3.inst 357 # number of overall hits 1204system.l2c.overall_hits::cpu3.data 9 # number of overall hits 1205system.l2c.overall_hits::total 1218 # number of overall hits 1206system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses 1207system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses 1208system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses 1209system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses 1210system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses 1211system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 1212system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses 1213system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses 1214system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 1215system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 1216system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses 1217system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses 1218system.l2c.ReadCleanReq_misses::cpu2.inst 65 # number of ReadCleanReq misses 1219system.l2c.ReadCleanReq_misses::cpu3.inst 10 # number of ReadCleanReq misses 1220system.l2c.ReadCleanReq_misses::total 374 # number of ReadCleanReq misses 1221system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses 1222system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses 1223system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses 1224system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses 1225system.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses 1226system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses 1227system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 1228system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses 1229system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses 1230system.l2c.demand_misses::cpu2.inst 65 # number of demand (read+write) misses 1231system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses 1232system.l2c.demand_misses::cpu3.inst 10 # number of demand (read+write) misses 1233system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses 1234system.l2c.demand_misses::total 594 # number of demand (read+write) misses 1235system.l2c.overall_misses::cpu0.inst 285 # number of overall misses 1236system.l2c.overall_misses::cpu0.data 165 # number of overall misses 1237system.l2c.overall_misses::cpu1.inst 14 # number of overall misses 1238system.l2c.overall_misses::cpu1.data 16 # number of overall misses 1239system.l2c.overall_misses::cpu2.inst 65 # number of overall misses 1240system.l2c.overall_misses::cpu2.data 23 # number of overall misses 1241system.l2c.overall_misses::cpu3.inst 10 # number of overall misses 1242system.l2c.overall_misses::cpu3.data 16 # number of overall misses 1243system.l2c.overall_misses::total 594 # number of overall misses 1244system.l2c.ReadExReq_miss_latency::cpu0.data 5991000 # number of ReadExReq miss cycles 1245system.l2c.ReadExReq_miss_latency::cpu1.data 856000 # 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number of demand (read+write) MSHR miss cycles 1474system.l2c.demand_mshr_miss_latency::cpu0.data 8334500 # number of demand (read+write) MSHR miss cycles 1475system.l2c.demand_mshr_miss_latency::cpu1.inst 358000 # number of demand (read+write) MSHR miss cycles 1476system.l2c.demand_mshr_miss_latency::cpu1.data 766500 # number of demand (read+write) MSHR miss cycles 1477system.l2c.demand_mshr_miss_latency::cpu2.inst 2929500 # number of demand (read+write) MSHR miss cycles 1478system.l2c.demand_mshr_miss_latency::cpu2.data 1165000 # number of demand (read+write) MSHR miss cycles 1479system.l2c.demand_mshr_miss_latency::cpu3.inst 203000 # number of demand (read+write) MSHR miss cycles 1480system.l2c.demand_mshr_miss_latency::cpu3.data 767000 # number of demand (read+write) MSHR miss cycles 1481system.l2c.demand_mshr_miss_latency::total 28925000 # number of demand (read+write) MSHR miss cycles 1482system.l2c.overall_mshr_miss_latency::cpu0.inst 14401500 # number of overall MSHR miss cycles 1483system.l2c.overall_mshr_miss_latency::cpu0.data 8334500 # number of overall MSHR miss cycles 1484system.l2c.overall_mshr_miss_latency::cpu1.inst 358000 # number of overall MSHR miss cycles 1485system.l2c.overall_mshr_miss_latency::cpu1.data 766500 # number of overall MSHR miss cycles 1486system.l2c.overall_mshr_miss_latency::cpu2.inst 2929500 # number of overall MSHR miss cycles 1487system.l2c.overall_mshr_miss_latency::cpu2.data 1165000 # number of overall MSHR miss cycles 1488system.l2c.overall_mshr_miss_latency::cpu3.inst 203000 # number of overall MSHR miss cycles 1489system.l2c.overall_mshr_miss_latency::cpu3.data 767000 # number of overall MSHR miss cycles 1490system.l2c.overall_mshr_miss_latency::total 28925000 # number of overall MSHR miss cycles 1491system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 1492system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 1493system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 1494system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 1495system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses 1496system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 1497system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 1498system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 1499system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 1500system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1501system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses 1502system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadCleanReq accesses 1503system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for ReadCleanReq accesses 1504system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for ReadCleanReq accesses 1505system.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses 1506system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses 1507system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadSharedReq accesses 1508system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.727273 # mshr miss rate for ReadSharedReq accesses 1509system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadSharedReq accesses 1510system.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # mshr miss rate for ReadSharedReq accesses 1511system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 1512system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses 1513system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for demand accesses 1514system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses 1515system.l2c.demand_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for demand accesses 1516system.l2c.demand_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for demand accesses 1517system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for demand accesses 1518system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses 1519system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses 1520system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 1521system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 1522system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses 1523system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses 1524system.l2c.overall_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for overall accesses 1525system.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses 1526system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for overall accesses 1527system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses 1528system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses 1529system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20035.714286 # average UpgradeReq mshr miss latency 1530system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19937.500000 # average UpgradeReq mshr miss latency 1531system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19794.117647 # average UpgradeReq mshr miss latency 1532system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20687.500000 # average UpgradeReq mshr miss latency 1533system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20097.402597 # average UpgradeReq mshr miss latency 1534system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 50515.151515 # average ReadExReq mshr miss latency 1535system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51142.857143 # average ReadExReq mshr miss latency 1536system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 50733.333333 # average ReadExReq mshr miss latency 1537system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 51178.571429 # average ReadExReq mshr miss latency 1538system.l2c.ReadExReq_avg_mshr_miss_latency::total 50665.492958 # average ReadExReq mshr miss latency 1539system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 50531.578947 # average ReadCleanReq mshr miss latency 1540system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51142.857143 # average ReadCleanReq mshr miss latency 1541system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average ReadCleanReq mshr miss latency 1542system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 50750 # average ReadCleanReq mshr miss latency 1543system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 50542.372881 # average ReadCleanReq mshr miss latency 1544system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 50507.575758 # average ReadSharedReq mshr miss latency 1545system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 50500 # average ReadSharedReq mshr miss latency 1546system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 50500 # average ReadSharedReq mshr miss latency 1547system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 50500 # average ReadSharedReq mshr miss latency 1548system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50506.578947 # average ReadSharedReq mshr miss latency 1549system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50531.578947 # average overall mshr miss latency 1550system.l2c.demand_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency 1551system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51142.857143 # average overall mshr miss latency 1552system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51100 # average overall mshr miss latency 1553system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency 1554system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency 1555system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 50750 # average overall mshr miss latency 1556system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51133.333333 # average overall mshr miss latency 1557system.l2c.demand_avg_mshr_miss_latency::total 50568.181818 # average overall mshr miss latency 1558system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50531.578947 # average overall mshr miss latency 1559system.l2c.overall_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency 1560system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51142.857143 # average overall mshr miss latency 1561system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51100 # average overall mshr miss latency 1562system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency 1563system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency 1564system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50750 # average overall mshr miss latency 1565system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51133.333333 # average overall mshr miss latency 1566system.l2c.overall_avg_mshr_miss_latency::total 50568.181818 # average overall mshr miss latency 1567system.membus.snoop_filter.tot_requests 916 # Total number of requests made to the snoop filter. 1568system.membus.snoop_filter.hit_single_requests 338 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1569system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1570system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1571system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1572system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1573system.membus.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 1574system.membus.trans_dist::ReadResp 430 # Transaction distribution 1575system.membus.trans_dist::UpgradeReq 272 # Transaction distribution 1576system.membus.trans_dist::ReadExReq 208 # Transaction distribution 1577system.membus.trans_dist::ReadExResp 142 # Transaction distribution 1578system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution 1579system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1482 # Packet count per connected master and slave (bytes) 1580system.membus.pkt_count::total 1482 # Packet count per connected master and slave (bytes) 1581system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) 1582system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) 1583system.membus.snoops 261 # Total snoops (count) 1584system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 1585system.membus.snoop_fanout::samples 916 # Request fanout histogram 1586system.membus.snoop_fanout::mean 0 # Request fanout histogram 1587system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1588system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1589system.membus.snoop_fanout::0 916 100.00% 100.00% # Request fanout histogram 1590system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1591system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1592system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1593system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1594system.membus.snoop_fanout::total 916 # Request fanout histogram 1595system.membus.reqLayer0.occupancy 683633 # Layer occupancy (ticks) 1596system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 1597system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) 1598system.membus.respLayer1.utilization 1.1 # Layer utilization (%) 1599system.toL2Bus.snoop_filter.tot_requests 3977 # Total number of requests made to the snoop filter. 1600system.toL2Bus.snoop_filter.hit_single_requests 1110 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1601system.toL2Bus.snoop_filter.hit_multi_requests 1865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1602system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1603system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1604system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1605system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states 1606system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution 1607system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 1608system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution 1609system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 1610system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution 1611system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution 1612system.toL2Bus.trans_dist::ReadExReq 420 # Transaction distribution 1613system.toL2Bus.trans_dist::ReadExResp 420 # Transaction distribution 1614system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution 1615system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution 1616system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) 1617system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes) 1618system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) 1619system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes) 1620system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) 1621system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 377 # Packet count per connected master and slave (bytes) 1622system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes) 1623system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 349 # Packet count per connected master and slave (bytes) 1624system.toL2Bus.pkt_count::total 5868 # Packet count per connected master and slave (bytes) 1625system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) 1626system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 1627system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) 1628system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 1629system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) 1630system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 1631system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 # Cumulative packet size per connected master and slave (bytes) 1632system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 1633system.toL2Bus.pkt_size::total 183616 # Cumulative packet size per connected master and slave (bytes) 1634system.toL2Bus.snoops 1028 # Total snoops (count) 1635system.toL2Bus.snoopTraffic 53312 # Total snoop traffic (bytes) 1636system.toL2Bus.snoop_fanout::samples 2919 # Request fanout histogram 1637system.toL2Bus.snoop_fanout::mean 1.272011 # Request fanout histogram 1638system.toL2Bus.snoop_fanout::stdev 1.157273 # Request fanout histogram 1639system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1640system.toL2Bus.snoop_fanout::0 1002 34.33% 34.33% # Request fanout histogram 1641system.toL2Bus.snoop_fanout::1 784 26.86% 61.19% # Request fanout histogram 1642system.toL2Bus.snoop_fanout::2 470 16.10% 77.29% # Request fanout histogram 1643system.toL2Bus.snoop_fanout::3 663 22.71% 100.00% # Request fanout histogram 1644system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 1645system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 1646system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 1647system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram 1648system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 1649system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1650system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1651system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 1652system.toL2Bus.snoop_fanout::total 2919 # Request fanout histogram 1653system.toL2Bus.reqLayer0.occupancy 3051987 # Layer occupancy (ticks) 1654system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 1655system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) 1656system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) 1657system.toL2Bus.respLayer1.occupancy 501494 # Layer occupancy (ticks) 1658system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 1659system.toL2Bus.respLayer2.occupancy 552489 # Layer occupancy (ticks) 1660system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) 1661system.toL2Bus.respLayer3.occupancy 440975 # Layer occupancy (ticks) 1662system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) 1663system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) 1664system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) 1665system.toL2Bus.respLayer5.occupancy 442472 # Layer occupancy (ticks) 1666system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) 1667system.toL2Bus.respLayer6.occupancy 553492 # Layer occupancy (ticks) 1668system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) 1669system.toL2Bus.respLayer7.occupancy 403476 # Layer occupancy (ticks) 1670system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 1671 1672---------- End Simulation Statistics ---------- 1673