xref: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000260                       # Number of seconds simulated
sim_ticks                                   260037500                       # Number of ticks simulated
final_tick                                  260037500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 961598                       # Simulator instruction rate (inst/s)
host_op_rate                                   961579                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              379344878                       # Simulator tick rate (ticks/s)
host_mem_usage                                 302744                       # Number of bytes of host memory used
host_seconds                                     0.69                       # Real time elapsed on the host
sim_insts                                      659142                       # Number of instructions simulated
sim_ops                                        659142                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst            18240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst              448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data              960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst             3904                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data             1472                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst               64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              960                       # Number of bytes read from this memory
system.physmem.bytes_read::total                36608                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        18240                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst          448                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst         3904                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst           64                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           22656                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               285                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               165                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                 7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                61                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                23                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                 1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   572                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst            70143729                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            40609527                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst             1722828                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             3691775                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst            15013219                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             5660722                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst              246118                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             3691775                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               140779695                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst       70143729                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst        1722828                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst       15013219                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst         246118                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           87125895                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst           70143729                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           40609527                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst            1722828                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            3691775                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst           15013219                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            5660722                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst             246118                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            3691775                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              140779695                       # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          520075                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                     157392                       # Number of instructions committed
system.cpu0.committedOps                       157392                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses               108420                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts        25835                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                      108420                       # number of integer instructions
system.cpu0.num_fp_insts                            0                       # number of float instructions
system.cpu0.num_int_register_reads             313418                       # number of times the integer registers were read
system.cpu0.num_int_register_writes            110026                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu0.num_mem_refs                        73430                       # number of memory refs
system.cpu0.num_load_insts                      48613                       # Number of load instructions
system.cpu0.num_store_insts                     24817                       # Number of store instructions
system.cpu0.num_idle_cycles                  0.002000                       # Number of idle cycles
system.cpu0.num_busy_cycles              520074.998000                       # Number of busy cycles
system.cpu0.not_idle_fraction                1.000000                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.000000                       # Percentage of idle cycles
system.cpu0.Branches                            26700                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                23427     14.88%     14.88% # Class of executed instruction
system.cpu0.op_class::IntAlu                    60513     38.43%     53.31% # Class of executed instruction
system.cpu0.op_class::IntMult                       0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     53.31% # Class of executed instruction
system.cpu0.op_class::MemRead                   48697     30.93%     84.24% # Class of executed instruction
system.cpu0.op_class::MemWrite                  24817     15.76%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                    157454                       # Class of executed instruction
system.cpu0.dcache.tags.replacements                2                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          145.649829                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs              72898                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs              167                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs           436.514970                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   145.649829                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.284472                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.284472                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          165                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.322266                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses           293953                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses          293953                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data        48433                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          48433                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        24583                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         24583                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           16                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data        73016                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total           73016                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data        73016                       # number of overall hits
system.cpu0.dcache.overall_hits::total          73016                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          170                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          170                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          183                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          183                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           26                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           26                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data          353                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total           353                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data          353                       # number of overall misses
system.cpu0.dcache.overall_misses::total          353                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data      4637996                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total      4637996                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      6976000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total      6976000                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       359000                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       359000                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     11613996                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     11613996                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     11613996                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     11613996                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        48603                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        48603                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        24766                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        24766                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data        73369                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total        73369                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data        73369                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total        73369                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003498                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.003498                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007389                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.007389                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.619048                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.619048                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.004811                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.004811                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.004811                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.004811                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27282.329412                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 27282.329412                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38120.218579                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38120.218579                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32900.838527                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 32900.838527                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32900.838527                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 32900.838527                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          170                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          170                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          183                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          183                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           26                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           26                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          353                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          353                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          353                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          353                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4372004                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4372004                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6701500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6701500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       320000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       320000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     11073504                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     11073504                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     11073504                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     11073504                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003498                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003498                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007389                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007389                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.619048                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.619048                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.004811                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.004811                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.004811                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.004811                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25717.670588                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25717.670588                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36620.218579                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36620.218579                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12307.692308                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12307.692308                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31369.699717                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31369.699717                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31369.699717                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31369.699717                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements              215                       # number of replacements
system.cpu0.icache.tags.tagsinuse          212.581030                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs             156988                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs              467                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           336.162741                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   212.581030                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.415197                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.415197                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          252                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.492188                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses           157922                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses          157922                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst       156988                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total         156988                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst       156988                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total          156988                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst       156988                       # number of overall hits
system.cpu0.icache.overall_hits::total         156988                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
system.cpu0.icache.overall_misses::total          467                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     18041500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     18041500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     18041500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     18041500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     18041500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     18041500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst       157455                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total       157455                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst       157455                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total       157455                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst       157455                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total       157455                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002966                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.002966                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002966                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.002966                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002966                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.002966                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38632.762313                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 38632.762313                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38632.762313                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 38632.762313                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38632.762313                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 38632.762313                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          467                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          467                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          467                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          467                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          467                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          467                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     17341000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     17341000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     17341000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     17341000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     17341000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     17341000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.002966                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.002966                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.002966                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.002966                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.002966                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.002966                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37132.762313                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37132.762313                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37132.762313                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 37132.762313                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37132.762313                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 37132.762313                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                          520075                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                     168980                       # Number of instructions committed
system.cpu1.committedOps                       168980                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses               110320                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                        637                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts        33339                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                      110320                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads             270098                       # number of times the integer registers were read
system.cpu1.num_int_register_writes            102062                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_mem_refs                        53149                       # number of memory refs
system.cpu1.num_load_insts                      40825                       # Number of load instructions
system.cpu1.num_store_insts                     12324                       # Number of store instructions
system.cpu1.num_idle_cycles              67727.001740                       # Number of idle cycles
system.cpu1.num_busy_cycles              452347.998260                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.869775                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.130225                       # Percentage of idle cycles
system.cpu1.Branches                            34992                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                25772     15.25%     15.25% # Class of executed instruction
system.cpu1.op_class::IntAlu                    74368     44.00%     59.25% # Class of executed instruction
system.cpu1.op_class::IntMult                       0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     59.25% # Class of executed instruction
system.cpu1.op_class::MemRead                   56548     33.46%     92.71% # Class of executed instruction
system.cpu1.op_class::MemWrite                  12324      7.29%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                    169012                       # Class of executed instruction
system.cpu1.dcache.tags.replacements                0                       # number of replacements
system.cpu1.dcache.tags.tagsinuse           25.995164                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs              26990                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs           899.666667                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data    25.995164                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.050772                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.050772                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses           212815                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses          212815                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data        40655                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          40655                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        12144                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         12144                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           14                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        52799                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           52799                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        52799                       # number of overall hits
system.cpu1.dcache.overall_hits::total          52799                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          162                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          162                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          108                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          108                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           56                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          270                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           270                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          270                       # number of overall misses
system.cpu1.dcache.overall_misses::total          270                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      2619475                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      2619475                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      1982498                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      1982498                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       237000                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       237000                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data      4601973                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total      4601973                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data      4601973                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total      4601973                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        40817                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        40817                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        12252                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        12252                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           70                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        53069                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        53069                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        53069                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        53069                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.003969                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.003969                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.008815                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.008815                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.800000                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.800000                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005088                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.005088                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005088                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.005088                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16169.598765                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16169.598765                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18356.462963                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18356.462963                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  4232.142857                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total  4232.142857                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17044.344444                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17044.344444                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17044.344444                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 17044.344444                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          162                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          162                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          108                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           56                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          270                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          270                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          270                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          270                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2358525                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2358525                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1818502                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1818502                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       153000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       153000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      4177027                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      4177027                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      4177027                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      4177027                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003969                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003969                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.008815                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.008815                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.800000                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.005088                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.005088                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.005088                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.005088                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14558.796296                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14558.796296                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16837.981481                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16837.981481                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  2732.142857                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  2732.142857                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15470.470370                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15470.470370                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15470.470370                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15470.470370                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements              280                       # number of replacements
system.cpu1.icache.tags.tagsinuse           65.697365                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs             168647                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs              366                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs           460.784153                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst    65.697365                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.128315                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.128315                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses           169379                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses          169379                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst       168647                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total         168647                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst       168647                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total          168647                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst       168647                       # number of overall hits
system.cpu1.icache.overall_hits::total         168647                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          366                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          366                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          366                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           366                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          366                       # number of overall misses
system.cpu1.icache.overall_misses::total          366                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      5333988                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total      5333988                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst      5333988                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total      5333988                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst      5333988                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total      5333988                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst       169013                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total       169013                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst       169013                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total       169013                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst       169013                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total       169013                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002166                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.002166                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002166                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.002166                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002166                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.002166                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14573.737705                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14573.737705                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14573.737705                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14573.737705                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14573.737705                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14573.737705                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          366                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          366                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          366                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      4778012                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total      4778012                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      4778012                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total      4778012                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      4778012                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total      4778012                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.002166                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.002166                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.002166                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.002166                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.002166                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.002166                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13054.677596                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13054.677596                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13054.677596                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13054.677596                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13054.677596                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13054.677596                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.numCycles                          520075                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.committedInsts                     164869                       # Number of instructions committed
system.cpu2.committedOps                       164869                       # Number of ops (including micro ops) committed
system.cpu2.num_int_alu_accesses               110069                       # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu2.num_func_calls                        637                       # number of times a function call or return occured
system.cpu2.num_conditional_control_insts        31409                       # number of instructions that are conditional controls
system.cpu2.num_int_insts                      110069                       # number of integer instructions
system.cpu2.num_fp_insts                            0                       # number of float instructions
system.cpu2.num_int_register_reads             276820                       # number of times the integer registers were read
system.cpu2.num_int_register_writes            105549                       # number of times the integer registers were written
system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu2.num_mem_refs                        54829                       # number of memory refs
system.cpu2.num_load_insts                      40701                       # Number of load instructions
system.cpu2.num_store_insts                     14128                       # Number of store instructions
system.cpu2.num_idle_cycles              67985.001739                       # Number of idle cycles
system.cpu2.num_busy_cycles              452089.998261                       # Number of busy cycles
system.cpu2.not_idle_fraction                0.869278                       # Percentage of non-idle cycles
system.cpu2.idle_fraction                    0.130722                       # Percentage of idle cycles
system.cpu2.Branches                            33062                       # Number of branches fetched
system.cpu2.op_class::No_OpClass                23842     14.46%     14.46% # Class of executed instruction
system.cpu2.op_class::IntAlu                    74244     45.02%     59.48% # Class of executed instruction
system.cpu2.op_class::IntMult                       0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::IntDiv                        0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::FloatAdd                      0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::FloatCmp                      0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::FloatCvt                      0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::FloatMult                     0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::FloatDiv                      0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::FloatSqrt                     0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdAdd                       0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdAddAcc                    0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdAlu                       0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdCmp                       0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdCvt                       0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdMisc                      0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdMult                      0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdMultAcc                   0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdShift                     0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdShiftAcc                  0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdSqrt                      0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatAdd                  0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatAlu                  0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatCmp                  0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatCvt                  0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatDiv                  0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatMisc                 0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatMult                 0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::MemRead                   52687     31.95%     91.43% # Class of executed instruction
system.cpu2.op_class::MemWrite                  14128      8.57%    100.00% # Class of executed instruction
system.cpu2.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu2.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu2.op_class::total                    164901                       # Class of executed instruction
system.cpu2.dcache.tags.replacements                0                       # number of replacements
system.cpu2.dcache.tags.tagsinuse           27.767003                       # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs              30481                       # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs          1051.068966                       # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data    27.767003                       # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data     0.054232                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total     0.054232                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses           219531                       # Number of tag accesses
system.cpu2.dcache.tags.data_accesses          219531                       # Number of data accesses
system.cpu2.dcache.ReadReq_hits::cpu2.data        40534                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          40534                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        13949                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         13949                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           13                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        54483                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           54483                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        54483                       # number of overall hits
system.cpu2.dcache.overall_hits::total          54483                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          159                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          159                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          108                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          108                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           56                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          267                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           267                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          267                       # number of overall misses
system.cpu2.dcache.overall_misses::total          267                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      2767480                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      2767480                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2022500                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      2022500                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       237000                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       237000                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data      4789980                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total      4789980                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data      4789980                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total      4789980                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        40693                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        40693                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        14057                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        14057                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           69                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        54750                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        54750                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        54750                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        54750                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.003907                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.003907                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.007683                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.007683                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.811594                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.811594                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.004877                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.004877                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.004877                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.004877                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17405.534591                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 17405.534591                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18726.851852                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 18726.851852                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  4232.142857                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total  4232.142857                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data        17940                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total        17940                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data        17940                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total        17940                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          159                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          159                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          108                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           56                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          267                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          267                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          267                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          267                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2514020                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2514020                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1860500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1860500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       153000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       153000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      4374520                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      4374520                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      4374520                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      4374520                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003907                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003907                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.007683                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.007683                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.811594                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.811594                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.004877                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.004877                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.004877                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.004877                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15811.446541                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15811.446541                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17226.851852                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17226.851852                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  2732.142857                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  2732.142857                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16383.970037                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16383.970037                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16383.970037                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16383.970037                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.icache.tags.replacements              280                       # number of replacements
system.cpu2.icache.tags.tagsinuse           70.145256                       # Cycle average of tags in use
system.cpu2.icache.tags.total_refs             164536                       # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs              366                       # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs           449.551913                       # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst    70.145256                       # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst     0.137002                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total     0.137002                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
system.cpu2.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses           165268                       # Number of tag accesses
system.cpu2.icache.tags.data_accesses          165268                       # Number of data accesses
system.cpu2.icache.ReadReq_hits::cpu2.inst       164536                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total         164536                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst       164536                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total          164536                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst       164536                       # number of overall hits
system.cpu2.icache.overall_hits::total         164536                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          366                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          366                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          366                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           366                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          366                       # number of overall misses
system.cpu2.icache.overall_misses::total          366                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      7445997                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total      7445997                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst      7445997                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total      7445997                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst      7445997                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total      7445997                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst       164902                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total       164902                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst       164902                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total       164902                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst       164902                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total       164902                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002220                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.002220                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002220                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.002220                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002220                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.002220                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20344.254098                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 20344.254098                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20344.254098                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 20344.254098                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20344.254098                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 20344.254098                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          366                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          366                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          366                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      6894003                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total      6894003                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      6894003                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total      6894003                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      6894003                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total      6894003                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.002220                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.002220                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.002220                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.002220                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.002220                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.002220                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18836.073770                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 18836.073770                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18836.073770                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 18836.073770                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18836.073770                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 18836.073770                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.numCycles                          520075                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.committedInsts                     167901                       # Number of instructions committed
system.cpu3.committedOps                       167901                       # Number of ops (including micro ops) committed
system.cpu3.num_int_alu_accesses               110672                       # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu3.num_func_calls                        637                       # number of times a function call or return occured
system.cpu3.num_conditional_control_insts        32621                       # number of instructions that are conditional controls
system.cpu3.num_int_insts                      110672                       # number of integer instructions
system.cpu3.num_fp_insts                            0                       # number of float instructions
system.cpu3.num_int_register_reads             274378                       # number of times the integer registers were read
system.cpu3.num_int_register_writes            104026                       # number of times the integer registers were written
system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu3.num_mem_refs                        54219                       # number of memory refs
system.cpu3.num_load_insts                      41000                       # Number of load instructions
system.cpu3.num_store_insts                     13219                       # Number of store instructions
system.cpu3.num_idle_cycles              68239.001738                       # Number of idle cycles
system.cpu3.num_busy_cycles              451835.998262                       # Number of busy cycles
system.cpu3.not_idle_fraction                0.868790                       # Percentage of non-idle cycles
system.cpu3.idle_fraction                    0.131210                       # Percentage of idle cycles
system.cpu3.Branches                            34277                       # Number of branches fetched
system.cpu3.op_class::No_OpClass                25056     14.92%     14.92% # Class of executed instruction
system.cpu3.op_class::IntAlu                    74547     44.39%     59.31% # Class of executed instruction
system.cpu3.op_class::IntMult                       0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::IntDiv                        0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::FloatAdd                      0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::FloatCmp                      0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::FloatCvt                      0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::FloatMult                     0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::FloatDiv                      0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::FloatSqrt                     0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdAdd                       0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdAddAcc                    0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdAlu                       0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdCmp                       0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdCvt                       0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdMisc                      0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdMult                      0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdMultAcc                   0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdShift                     0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdShiftAcc                  0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdSqrt                      0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdFloatAdd                  0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdFloatAlu                  0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdFloatCmp                  0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdFloatCvt                  0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdFloatDiv                  0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdFloatMisc                 0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdFloatMult                 0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     59.31% # Class of executed instruction
system.cpu3.op_class::MemRead                   55111     32.82%     92.13% # Class of executed instruction
system.cpu3.op_class::MemWrite                  13219      7.87%    100.00% # Class of executed instruction
system.cpu3.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu3.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu3.op_class::total                    167933                       # Class of executed instruction
system.cpu3.dcache.tags.replacements                0                       # number of replacements
system.cpu3.dcache.tags.tagsinuse           26.810589                       # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs              28657                       # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs           988.172414                       # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data    26.810589                       # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data     0.052364                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total     0.052364                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses           217093                       # Number of tag accesses
system.cpu3.dcache.tags.data_accesses          217093                       # Number of data accesses
system.cpu3.dcache.ReadReq_hits::cpu3.data        40832                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          40832                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        13038                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         13038                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           13                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        53870                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           53870                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        53870                       # number of overall hits
system.cpu3.dcache.overall_hits::total          53870                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          160                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          160                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          108                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          108                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           58                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          268                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           268                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          268                       # number of overall misses
system.cpu3.dcache.overall_misses::total          268                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      2513476                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      2513476                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2024000                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      2024000                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       244500                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       244500                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data      4537476                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total      4537476                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data      4537476                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total      4537476                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        40992                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        40992                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        13146                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        13146                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           71                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        54138                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        54138                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        54138                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        54138                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.003903                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.003903                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.008215                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.008215                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.816901                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.816901                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.004950                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.004950                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.004950                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.004950                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15709.225000                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 15709.225000                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18740.740741                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 18740.740741                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  4215.517241                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total  4215.517241                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16930.880597                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 16930.880597                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16930.880597                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 16930.880597                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          160                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          160                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          108                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           58                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          268                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          268                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          268                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          268                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      2256524                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      2256524                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1862000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1862000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       157500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       157500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      4118524                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      4118524                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      4118524                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      4118524                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003903                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003903                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.008215                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.008215                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.816901                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.816901                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.004950                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.004950                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.004950                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.004950                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14103.275000                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 14103.275000                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17240.740741                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17240.740741                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  2715.517241                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  2715.517241                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 15367.626866                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 15367.626866                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 15367.626866                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 15367.626866                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.icache.tags.replacements              281                       # number of replacements
system.cpu3.icache.tags.tagsinuse           67.819588                       # Cycle average of tags in use
system.cpu3.icache.tags.total_refs             167567                       # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs              367                       # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs           456.585831                       # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst    67.819588                       # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst     0.132460                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total     0.132460                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses           168301                       # Number of tag accesses
system.cpu3.icache.tags.data_accesses          168301                       # Number of data accesses
system.cpu3.icache.ReadReq_hits::cpu3.inst       167567                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total         167567                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst       167567                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total          167567                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst       167567                       # number of overall hits
system.cpu3.icache.overall_hits::total         167567                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          367                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          367                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          367                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           367                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          367                       # number of overall misses
system.cpu3.icache.overall_misses::total          367                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      5144490                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total      5144490                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst      5144490                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total      5144490                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst      5144490                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total      5144490                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst       167934                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total       167934                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst       167934                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total       167934                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst       167934                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total       167934                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002185                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.002185                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002185                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.002185                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002185                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.002185                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14017.683924                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 14017.683924                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14017.683924                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 14017.683924                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14017.683924                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 14017.683924                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          367                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          367                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          367                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          367                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          367                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          367                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4586010                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total      4586010                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4586010                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total      4586010                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4586010                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total      4586010                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.002185                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.002185                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.002185                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.002185                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.002185                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.002185                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12495.940054                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12495.940054                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12495.940054                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 12495.940054                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12495.940054                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 12495.940054                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                        0                       # number of replacements
system.l2c.tags.tagsinuse                  349.350598                       # Cycle average of tags in use
system.l2c.tags.total_refs                       1220                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                      429                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.843823                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks       0.890412                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst      231.950361                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data       54.237281                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst        6.226273                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data        0.814088                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst       47.344433                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data        6.154120                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst        0.888026                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data        0.845603                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.000014                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.003539                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.000828                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.000095                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000012                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.000722                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.000094                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.000014                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.000013                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.005331                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024          429                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          374                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.006546                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                    15709                       # Number of tag accesses
system.l2c.tags.data_accesses                   15709                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst                182                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst                352                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data                  9                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst                302                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data                  3                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst                358                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1220                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst                 182                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 352                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                   9                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 302                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                   3                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 358                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1220                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                182                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                352                       # number of overall hits
system.l2c.overall_hits::cpu1.data                  9                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                302                       # number of overall hits
system.l2c.overall_hits::cpu2.data                  3                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                358                       # number of overall hits
system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
system.l2c.overall_hits::total                   1220                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst              285                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data               66                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst               14                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data                2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst               64                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data                8                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst                9                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data                2                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  450                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data            28                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            16                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            16                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            17                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                77                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             14                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             15                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             14                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                142                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst               285                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                14                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                16                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                64                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                23                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                 9                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                16                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   592                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              285                       # number of overall misses
system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               14                       # number of overall misses
system.l2c.overall_misses::cpu1.data               16                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               64                       # number of overall misses
system.l2c.overall_misses::cpu2.data               23                       # number of overall misses
system.l2c.overall_misses::cpu3.inst                9                       # number of overall misses
system.l2c.overall_misses::cpu3.data               16                       # number of overall misses
system.l2c.overall_misses::total                  592                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst     14963000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data      3465000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst       714500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data       104000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst      3356500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data       420000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst       458000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data       103500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       23584500                       # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data      5197500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data       744000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data       791500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       740000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total      7473000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     14963000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data      8662500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst       714500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data       848000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst      3356500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data      1211500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst       458000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data       843500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        31057500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     14963000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data      8662500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst       714500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data       848000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst      3356500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data      1211500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst       458000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data       843500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       31057500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst            467                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data             71                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst            366                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data             11                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst            366                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data             11                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst            367                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data             11                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               1670                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           16                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           16                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           17                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              79                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           14                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           15                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           14                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              142                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             366                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             366                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              26                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             367                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                1812                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            366                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            366                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             26                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            367                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               1812                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.610278                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.929577                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.038251                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.181818                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.174863                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.727273                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst      0.024523                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data      0.181818                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.269461                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.933333                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.974684                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.610278                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.038251                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.640000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.174863                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.884615                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.024523                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.640000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.326711                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.610278                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.038251                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.640000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.174863                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.884615                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.024523                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.640000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.326711                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52501.754386                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data        52500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51035.714286                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data        52000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52445.312500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data        52500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 50888.888889                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data        51750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total        52410                       # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data        52500                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53142.857143                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52766.666667                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52857.142857                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52626.760563                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52501.754386                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data        52500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 51035.714286                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data        53000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 52445.312500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 52673.913043                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 50888.888889                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 52718.750000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52461.993243                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52501.754386                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data        52500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 51035.714286                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data        53000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 52445.312500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 52673.913043                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 50888.888889                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 52718.750000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52461.993243                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                20                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 20                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                20                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst          285                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data           66                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst           61                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data            8                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             430                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data           28                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           16                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           16                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           17                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           77                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           99                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           14                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           15                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           14                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           142                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          285                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          165                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst            7                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           15                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst           61                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           23                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           15                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              572                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          285                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          165                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst            7                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           15                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst           61                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           23                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           15                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             572                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     11542500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data      2673000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst       283500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data        40500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst      2475000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data       324000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst        40500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data        40500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     17419500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data      1134000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       649996                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       648000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       688500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      3120496                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      4009500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       575500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       611500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       571000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      5767500                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     11542500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data      6682500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst       283500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data       616000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst      2475000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data       935500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst        40500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data       611500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     23187000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     11542500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data      6682500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst       283500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data       616000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst      2475000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data       935500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst        40500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data       611500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     23187000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.929577                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.019126                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.090909                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.166667                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.727273                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.090909                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.257485                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.933333                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.974684                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.019126                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.600000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.166667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.884615                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.600000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.315673                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.019126                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.600000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.166667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.884615                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.600000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.315673                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst        40500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data        40500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst        40500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        40500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40573.770492                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        40500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        40500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        40500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40510.465116                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        40500                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40624.750000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        40500                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        40500                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40525.922078                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data        40500                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41107.142857                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40766.666667                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40785.714286                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40616.197183                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst        40500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data        40500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        40500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41066.666667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40573.770492                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40673.913043                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        40500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40766.666667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40536.713287                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst        40500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data        40500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        40500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41066.666667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40573.770492                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40673.913043                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40766.666667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40536.713287                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq                 430                       # Transaction distribution
system.membus.trans_dist::ReadResp                430                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              272                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              77                       # Transaction distribution
system.membus.trans_dist::ReadExReq               208                       # Transaction distribution
system.membus.trans_dist::ReadExResp              142                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1559                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1559                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        36608                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   36608                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              261                       # Total snoops (count)
system.membus.snoop_fanout::samples               914                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     914    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 914                       # Request fanout histogram
system.membus.reqLayer0.occupancy              679142                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
system.membus.respLayer1.occupancy            2961502                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
system.toL2Bus.trans_dist::ReadReq               2217                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp              2217                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq             274                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp            274                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq              429                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp             429                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side          934                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          580                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          732                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          367                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          732                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          365                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          734                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          368                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total                  4812                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        29888                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        10944                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        23424                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        23424                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        23488                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total                 116032                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                            1029                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples             2921                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean                   7                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7                   2921    100.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              7                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total               2921                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy            1466989                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.6                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy            700500                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy            503996                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy            552488                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy            431973                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy            550497                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy            423980                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy            554490                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy            428476                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------