stats.txt revision 11956
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311606Sandreas.sandberg@arm.comsim_seconds 0.000263 # Number of seconds simulated 411606Sandreas.sandberg@arm.comsim_ticks 263409500 # Number of ticks simulated 511606Sandreas.sandberg@arm.comfinal_tick 263409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711754Sandreas.hansson@arm.comhost_inst_rate 870162 # Simulator instruction rate (inst/s) 811754Sandreas.hansson@arm.comhost_op_rate 870149 # Simulator op (including micro ops) rate (op/s) 911754Sandreas.hansson@arm.comhost_tick_rate 345251596 # Simulator tick rate (ticks/s) 1011754Sandreas.hansson@arm.comhost_mem_usage 264052 # Number of bytes of host memory used 1111754Sandreas.hansson@arm.comhost_seconds 0.76 # Real time elapsed on the host 1211606Sandreas.sandberg@arm.comsim_insts 663871 # Number of instructions simulated 1311606Sandreas.sandberg@arm.comsim_ops 663871 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611606Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 1911606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory 2311606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory 2411507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory 2511507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 36608 # Number of bytes read from this memory 2611507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory 2711606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory 2811507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory 2911606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory 3011507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 3111507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 3211507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 3311606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 3411507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory 3511507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory 3611507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory 3711606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory 3811507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory 3911507SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 572 # Number of read requests responded to by this memory 4011606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.inst 69245794 # Total read bandwidth from this memory (bytes/s) 4111606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.data 40089670 # Total read bandwidth from this memory (bytes/s) 4211606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.inst 2429677 # Total read bandwidth from this memory (bytes/s) 4311606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.data 3644515 # Total read bandwidth from this memory (bytes/s) 4411606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu2.inst 14092127 # Total read bandwidth from this memory (bytes/s) 4511606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu2.data 5588257 # Total read bandwidth from this memory (bytes/s) 4611606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu3.inst 242968 # Total read bandwidth from this memory (bytes/s) 4711606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu3.data 3644515 # Total read bandwidth from this memory (bytes/s) 4811606Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 138977524 # Total read bandwidth from this memory (bytes/s) 4911606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu0.inst 69245794 # Instruction read bandwidth from this memory (bytes/s) 5011606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu1.inst 2429677 # Instruction read bandwidth from this memory (bytes/s) 5111606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu2.inst 14092127 # Instruction read bandwidth from this memory (bytes/s) 5211606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu3.inst 242968 # Instruction read bandwidth from this memory (bytes/s) 5311606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::total 86010565 # Instruction read bandwidth from this memory (bytes/s) 5411606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.inst 69245794 # Total bandwidth to/from this memory (bytes/s) 5511606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.data 40089670 # Total bandwidth to/from this memory (bytes/s) 5611606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.inst 2429677 # Total bandwidth to/from this memory (bytes/s) 5711606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.data 3644515 # Total bandwidth to/from this memory (bytes/s) 5811606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu2.inst 14092127 # Total bandwidth to/from this memory (bytes/s) 5911606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu2.data 5588257 # Total bandwidth to/from this memory (bytes/s) 6011606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu3.inst 242968 # Total bandwidth to/from this memory (bytes/s) 6111606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu3.data 3644515 # Total bandwidth to/from this memory (bytes/s) 6211606Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 138977524 # Total bandwidth to/from this memory (bytes/s) 6311606Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 6411507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 6511955Sgabeblack@google.comsystem.cpu0.workload.numSyscalls 89 # Number of system calls 6611606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states 6711606Sandreas.sandberg@arm.comsystem.cpu0.numCycles 526819 # number of cpu cycles simulated 6811507SCurtis.Dunham@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 6911507SCurtis.Dunham@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 7011606Sandreas.sandberg@arm.comsystem.cpu0.committedInsts 158244 # Number of instructions committed 7111606Sandreas.sandberg@arm.comsystem.cpu0.committedOps 158244 # Number of ops (including micro ops) committed 7211606Sandreas.sandberg@arm.comsystem.cpu0.num_int_alu_accesses 108988 # Number of integer alu accesses 7311507SCurtis.Dunham@arm.comsystem.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 7411507SCurtis.Dunham@arm.comsystem.cpu0.num_func_calls 390 # number of times a function call or return occured 7511606Sandreas.sandberg@arm.comsystem.cpu0.num_conditional_control_insts 25977 # number of instructions that are conditional controls 7611606Sandreas.sandberg@arm.comsystem.cpu0.num_int_insts 108988 # number of integer instructions 7711507SCurtis.Dunham@arm.comsystem.cpu0.num_fp_insts 0 # number of float instructions 7811606Sandreas.sandberg@arm.comsystem.cpu0.num_int_register_reads 315122 # number of times the integer registers were read 7911606Sandreas.sandberg@arm.comsystem.cpu0.num_int_register_writes 110594 # number of times the integer registers were written 8011507SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 8111507SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 8211606Sandreas.sandberg@arm.comsystem.cpu0.num_mem_refs 73856 # number of memory refs 8311606Sandreas.sandberg@arm.comsystem.cpu0.num_load_insts 48897 # Number of load instructions 8411606Sandreas.sandberg@arm.comsystem.cpu0.num_store_insts 24959 # Number of store instructions 8511507SCurtis.Dunham@arm.comsystem.cpu0.num_idle_cycles 0.002000 # Number of idle cycles 8611606Sandreas.sandberg@arm.comsystem.cpu0.num_busy_cycles 526818.998000 # Number of busy cycles 8711507SCurtis.Dunham@arm.comsystem.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles 8811507SCurtis.Dunham@arm.comsystem.cpu0.idle_fraction 0.000000 # Percentage of idle cycles 8911606Sandreas.sandberg@arm.comsystem.cpu0.Branches 26842 # Number of branches fetched 9011606Sandreas.sandberg@arm.comsystem.cpu0.op_class::No_OpClass 23569 14.89% 14.89% # Class of executed instruction 9111606Sandreas.sandberg@arm.comsystem.cpu0.op_class::IntAlu 60797 38.40% 53.29% # Class of executed instruction 9211507SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction 9311507SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction 9411507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction 9511507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction 9611507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction 9711507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction 9811687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMultAcc 0 0.00% 53.29% # Class of executed instruction 9911507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction 10011687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMisc 0 0.00% 53.29% # Class of executed instruction 10111507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction 10211507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction 10311507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction 10411507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction 10511507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction 10611507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction 10711507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction 10811507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction 10911507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction 11011507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction 11111507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction 11211507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction 11311507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction 11411507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction 11511507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction 11611507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction 11711507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction 11811507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction 11911507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction 12011507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction 12111507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction 12211606Sandreas.sandberg@arm.comsystem.cpu0.op_class::MemRead 48981 30.94% 84.23% # Class of executed instruction 12311606Sandreas.sandberg@arm.comsystem.cpu0.op_class::MemWrite 24959 15.77% 100.00% # Class of executed instruction 12411687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 12511687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 12611507SCurtis.Dunham@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 12711507SCurtis.Dunham@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 12811606Sandreas.sandberg@arm.comsystem.cpu0.op_class::total 158306 # Class of executed instruction 12911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 13011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 2 # number of replacements 13111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.tagsinuse 144.946606 # Cycle average of tags in use 13211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.total_refs 73324 # Total number of references to valid blocks. 13311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 13411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.avg_refs 439.065868 # Average number of references to valid blocks. 13511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 13611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 144.946606 # Average occupied blocks per requestor 13711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.283099 # Average percentage of cache occupancy 13811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.283099 # Average percentage of cache occupancy 13911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 14011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 14111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id 14211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 14311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.tag_accesses 295657 # Number of tag accesses 14411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.data_accesses 295657 # Number of data accesses 14511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 14611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits 14711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits 14811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 24725 # number of WriteReq hits 14911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_hits::total 24725 # number of WriteReq hits 15011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 15111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits 15211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 73442 # number of demand (read+write) hits 15311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_hits::total 73442 # number of demand (read+write) hits 15411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 73442 # number of overall hits 15511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_hits::total 73442 # number of overall hits 15611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses 15711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses 15811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 15911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 16011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 16111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 16211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses 16311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses 16411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses 16511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::total 353 # number of overall misses 16611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4701000 # number of ReadReq miss cycles 16711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 4701000 # number of ReadReq miss cycles 16811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6585500 # number of WriteReq miss cycles 16911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 6585500 # number of WriteReq miss cycles 17011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_miss_latency::cpu0.data 400000 # number of SwapReq miss cycles 17111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_miss_latency::total 400000 # number of SwapReq miss cycles 17211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 11286500 # number of demand (read+write) miss cycles 17311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_latency::total 11286500 # number of demand (read+write) miss cycles 17411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 11286500 # number of overall miss cycles 17511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_latency::total 11286500 # number of overall miss cycles 17611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 48887 # number of ReadReq accesses(hits+misses) 17711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 48887 # number of ReadReq accesses(hits+misses) 17811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 24908 # number of WriteReq accesses(hits+misses) 17911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses) 18011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 18111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 18211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 73795 # number of demand (read+write) accesses 18311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_accesses::total 73795 # number of demand (read+write) accesses 18411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 73795 # number of overall (read+write) accesses 18511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_accesses::total 73795 # number of overall (read+write) accesses 18611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003477 # miss rate for ReadReq accesses 18711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.003477 # miss rate for ReadReq accesses 18811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses 18911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses 19011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 19111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses 19211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.004784 # miss rate for demand accesses 19311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.004784 # miss rate for demand accesses 19411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.004784 # miss rate for overall accesses 19511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.004784 # miss rate for overall accesses 19611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27652.941176 # average ReadReq miss latency 19711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 27652.941176 # average ReadReq miss latency 19811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35986.338798 # average WriteReq miss latency 19911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 35986.338798 # average WriteReq miss latency 20011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15384.615385 # average SwapReq miss latency 20111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_avg_miss_latency::total 15384.615385 # average SwapReq miss latency 20211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency 20311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 31973.087819 # average overall miss latency 20411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency 20511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 31973.087819 # average overall miss latency 20611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 20711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 20811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 20911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 21011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 21111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 21211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 21311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::total 1 # number of writebacks 21411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses 21511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses 21611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 21711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 21811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 21911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 22011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses 22111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses 22211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses 22311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses 22411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4531000 # number of ReadReq MSHR miss cycles 22511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 4531000 # number of ReadReq MSHR miss cycles 22611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6402500 # number of WriteReq MSHR miss cycles 22711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 6402500 # number of WriteReq MSHR miss cycles 22811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374000 # number of SwapReq MSHR miss cycles 22911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_miss_latency::total 374000 # number of SwapReq MSHR miss cycles 23011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10933500 # number of demand (read+write) MSHR miss cycles 23111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 10933500 # number of demand (read+write) MSHR miss cycles 23211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10933500 # number of overall MSHR miss cycles 23311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 10933500 # number of overall MSHR miss cycles 23411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003477 # mshr miss rate for ReadReq accesses 23511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003477 # mshr miss rate for ReadReq accesses 23611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses 23711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses 23811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 23911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses 24011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for demand accesses 24111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.004784 # mshr miss rate for demand accesses 24211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for overall accesses 24311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.004784 # mshr miss rate for overall accesses 24411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26652.941176 # average ReadReq mshr miss latency 24511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26652.941176 # average ReadReq mshr miss latency 24611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34986.338798 # average WriteReq mshr miss latency 24711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34986.338798 # average WriteReq mshr miss latency 24811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14384.615385 # average SwapReq mshr miss latency 24911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14384.615385 # average SwapReq mshr miss latency 25011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency 25111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency 25211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency 25311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency 25411606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 25511507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 215 # number of replacements 25611606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.tagsinuse 211.173601 # Cycle average of tags in use 25711606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.total_refs 157840 # Total number of references to valid blocks. 25811507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 25911606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.avg_refs 337.987152 # Average number of references to valid blocks. 26011507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 26111606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 211.173601 # Average occupied blocks per requestor 26211606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.412448 # Average percentage of cache occupancy 26311606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.412448 # Average percentage of cache occupancy 26411507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 26511507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 26611507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 26711507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 26811606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.tag_accesses 158774 # Number of tag accesses 26911606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.data_accesses 158774 # Number of data accesses 27011606Sandreas.sandberg@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 27111606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 157840 # number of ReadReq hits 27211606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_hits::total 157840 # number of ReadReq hits 27311606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 157840 # number of demand (read+write) hits 27411606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_hits::total 157840 # number of demand (read+write) hits 27511606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 157840 # number of overall hits 27611606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_hits::total 157840 # number of overall hits 27711507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 27811507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 27911507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 28011507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 28111507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 28211507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 467 # number of overall misses 28311606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20426000 # number of ReadReq miss cycles 28411606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 20426000 # number of ReadReq miss cycles 28511606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 20426000 # number of demand (read+write) miss cycles 28611606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_miss_latency::total 20426000 # number of demand (read+write) miss cycles 28711606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 20426000 # number of overall miss cycles 28811606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_miss_latency::total 20426000 # number of overall miss cycles 28911606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 158307 # number of ReadReq accesses(hits+misses) 29011606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_accesses::total 158307 # number of ReadReq accesses(hits+misses) 29111606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 158307 # number of demand (read+write) accesses 29211606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_accesses::total 158307 # number of demand (read+write) accesses 29311606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 158307 # number of overall (read+write) accesses 29411606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_accesses::total 158307 # number of overall (read+write) accesses 29511507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses 29611507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses 29711507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses 29811507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses 29911507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses 30011507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses 30111606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43738.758030 # average ReadReq miss latency 30211606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 43738.758030 # average ReadReq miss latency 30311606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency 30411606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 43738.758030 # average overall miss latency 30511606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency 30611606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 43738.758030 # average overall miss latency 30711507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 30811507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 30911507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 31011507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 31111507SCurtis.Dunham@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 31211507SCurtis.Dunham@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 31311507SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::writebacks 215 # number of writebacks 31411507SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::total 215 # number of writebacks 31511507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 31611507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 31711507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 31811507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 31911507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 32011507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses 32111606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19959000 # number of ReadReq MSHR miss cycles 32211606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 19959000 # number of ReadReq MSHR miss cycles 32311606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19959000 # number of demand (read+write) MSHR miss cycles 32411606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 19959000 # number of demand (read+write) MSHR miss cycles 32511606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19959000 # number of overall MSHR miss cycles 32611606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 19959000 # number of overall MSHR miss cycles 32711507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses 32811507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses 32911507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses 33011507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses 33111507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses 33211507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses 33311606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average ReadReq mshr miss latency 33411606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42738.758030 # average ReadReq mshr miss latency 33511606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency 33611606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency 33711606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency 33811606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency 33911606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states 34011606Sandreas.sandberg@arm.comsystem.cpu1.numCycles 526818 # number of cpu cycles simulated 34111507SCurtis.Dunham@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 34211507SCurtis.Dunham@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 34311606Sandreas.sandberg@arm.comsystem.cpu1.committedInsts 169340 # Number of instructions committed 34411606Sandreas.sandberg@arm.comsystem.cpu1.committedOps 169340 # Number of ops (including micro ops) committed 34511606Sandreas.sandberg@arm.comsystem.cpu1.num_int_alu_accesses 111465 # Number of integer alu accesses 34611507SCurtis.Dunham@arm.comsystem.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 34711507SCurtis.Dunham@arm.comsystem.cpu1.num_func_calls 637 # number of times a function call or return occured 34811606Sandreas.sandberg@arm.comsystem.cpu1.num_conditional_control_insts 32946 # number of instructions that are conditional controls 34911606Sandreas.sandberg@arm.comsystem.cpu1.num_int_insts 111465 # number of integer instructions 35011507SCurtis.Dunham@arm.comsystem.cpu1.num_fp_insts 0 # number of float instructions 35111606Sandreas.sandberg@arm.comsystem.cpu1.num_int_register_reads 276307 # number of times the integer registers were read 35211606Sandreas.sandberg@arm.comsystem.cpu1.num_int_register_writes 104671 # number of times the integer registers were written 35311507SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 35411507SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 35511606Sandreas.sandberg@arm.comsystem.cpu1.num_mem_refs 54688 # number of memory refs 35611606Sandreas.sandberg@arm.comsystem.cpu1.num_load_insts 41399 # Number of load instructions 35711606Sandreas.sandberg@arm.comsystem.cpu1.num_store_insts 13289 # Number of store instructions 35811606Sandreas.sandberg@arm.comsystem.cpu1.num_idle_cycles 74658.860000 # Number of idle cycles 35911606Sandreas.sandberg@arm.comsystem.cpu1.num_busy_cycles 452159.140000 # Number of busy cycles 36011606Sandreas.sandberg@arm.comsystem.cpu1.not_idle_fraction 0.858283 # Percentage of non-idle cycles 36111606Sandreas.sandberg@arm.comsystem.cpu1.idle_fraction 0.141717 # Percentage of idle cycles 36211606Sandreas.sandberg@arm.comsystem.cpu1.Branches 34599 # Number of branches fetched 36311606Sandreas.sandberg@arm.comsystem.cpu1.op_class::No_OpClass 25380 14.98% 14.98% # Class of executed instruction 36411606Sandreas.sandberg@arm.comsystem.cpu1.op_class::IntAlu 74993 44.28% 59.26% # Class of executed instruction 36511606Sandreas.sandberg@arm.comsystem.cpu1.op_class::IntMult 0 0.00% 59.26% # Class of executed instruction 36611606Sandreas.sandberg@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 59.26% # Class of executed instruction 36711606Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 59.26% # Class of executed instruction 36811606Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 59.26% # Class of executed instruction 36911606Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 59.26% # Class of executed instruction 37011606Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 59.26% # Class of executed instruction 37111687Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMultAcc 0 0.00% 59.26% # Class of executed instruction 37211606Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 59.26% # Class of executed instruction 37311687Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMisc 0 0.00% 59.26% # Class of executed instruction 37411606Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 59.26% # Class of executed instruction 37511606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 59.26% # Class of executed instruction 37611606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 59.26% # Class of executed instruction 37711606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 59.26% # Class of executed instruction 37811606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 59.26% # Class of executed instruction 37911606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 59.26% # Class of executed instruction 38011606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 59.26% # Class of executed instruction 38111606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 59.26% # Class of executed instruction 38211606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 59.26% # Class of executed instruction 38311606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 59.26% # Class of executed instruction 38411606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 59.26% # Class of executed instruction 38511606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 59.26% # Class of executed instruction 38611606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 59.26% # Class of executed instruction 38711606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 59.26% # Class of executed instruction 38811606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 59.26% # Class of executed instruction 38911606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 59.26% # Class of executed instruction 39011606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 59.26% # Class of executed instruction 39111606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatMisc 0 0.00% 59.26% # Class of executed instruction 39211606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 59.26% # Class of executed instruction 39311606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.26% # Class of executed instruction 39411606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.26% # Class of executed instruction 39511606Sandreas.sandberg@arm.comsystem.cpu1.op_class::MemRead 55710 32.89% 92.15% # Class of executed instruction 39611606Sandreas.sandberg@arm.comsystem.cpu1.op_class::MemWrite 13289 7.85% 100.00% # Class of executed instruction 39711687Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 39811687Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 39911507SCurtis.Dunham@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 40011507SCurtis.Dunham@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 40111606Sandreas.sandberg@arm.comsystem.cpu1.op_class::total 169372 # Class of executed instruction 40211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 40311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.replacements 0 # number of replacements 40411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.tagsinuse 26.434544 # Cycle average of tags in use 40511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.total_refs 28854 # Total number of references to valid blocks. 40611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 40711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.avg_refs 994.965517 # Average number of references to valid blocks. 40811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 40911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 26.434544 # Average occupied blocks per requestor 41011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.051630 # Average percentage of cache occupancy 41111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.051630 # Average percentage of cache occupancy 41211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 41311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 41411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 41511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 41611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.tag_accesses 218970 # Number of tag accesses 41711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.data_accesses 218970 # Number of data accesses 41811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 41911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 41227 # number of ReadReq hits 42011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_hits::total 41227 # number of ReadReq hits 42111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 13113 # number of WriteReq hits 42211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_hits::total 13113 # number of WriteReq hits 42311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits 42411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits 42511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 54340 # number of demand (read+write) hits 42611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_hits::total 54340 # number of demand (read+write) hits 42711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 54340 # number of overall hits 42811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_hits::total 54340 # number of overall hits 42911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 164 # number of ReadReq misses 43011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_misses::total 164 # number of ReadReq misses 43111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses 43211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses 43311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses 43411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses 43511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 269 # number of demand (read+write) misses 43611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_misses::total 269 # number of demand (read+write) misses 43711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 269 # number of overall misses 43811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_misses::total 269 # number of overall misses 43911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1132500 # number of ReadReq miss cycles 44011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 1132500 # number of ReadReq miss cycles 44111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1426000 # number of WriteReq miss cycles 44211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 1426000 # number of WriteReq miss cycles 44311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_miss_latency::cpu1.data 250000 # number of SwapReq miss cycles 44411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_miss_latency::total 250000 # number of SwapReq miss cycles 44511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 2558500 # number of demand (read+write) miss cycles 44611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_latency::total 2558500 # number of demand (read+write) miss cycles 44711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 2558500 # number of overall miss cycles 44811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_latency::total 2558500 # number of overall miss cycles 44911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 41391 # number of ReadReq accesses(hits+misses) 45011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 41391 # number of ReadReq accesses(hits+misses) 45111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 13218 # number of WriteReq accesses(hits+misses) 45211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 13218 # number of WriteReq accesses(hits+misses) 45311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) 45411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) 45511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 54609 # number of demand (read+write) accesses 45611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_accesses::total 54609 # number of demand (read+write) accesses 45711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 54609 # number of overall (read+write) accesses 45811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_accesses::total 54609 # number of overall (read+write) accesses 45911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003962 # miss rate for ReadReq accesses 46011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.003962 # miss rate for ReadReq accesses 46111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007944 # miss rate for WriteReq accesses 46211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.007944 # miss rate for WriteReq accesses 46311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses 46411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses 46511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.004926 # miss rate for demand accesses 46611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.004926 # miss rate for demand accesses 46711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.004926 # miss rate for overall accesses 46811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.004926 # miss rate for overall accesses 46911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 6905.487805 # average ReadReq miss latency 47011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 6905.487805 # average ReadReq miss latency 47111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 13580.952381 # average WriteReq miss latency 47211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 13580.952381 # average WriteReq miss latency 47311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4464.285714 # average SwapReq miss latency 47411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_avg_miss_latency::total 4464.285714 # average SwapReq miss latency 47511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency 47611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 9511.152416 # average overall miss latency 47711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency 47811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 9511.152416 # average overall miss latency 47911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 48011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 48111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 48211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 48311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 48411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 48511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses 48611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses 48711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses 48811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 48911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses 49011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 49111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 269 # number of demand (read+write) MSHR misses 49211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses 49311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 269 # number of overall MSHR misses 49411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses 49511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 968500 # number of ReadReq MSHR miss cycles 49611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 968500 # number of ReadReq MSHR miss cycles 49711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1321000 # number of WriteReq MSHR miss cycles 49811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 1321000 # number of WriteReq MSHR miss cycles 49911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 194000 # number of SwapReq MSHR miss cycles 50011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_mshr_miss_latency::total 194000 # number of SwapReq MSHR miss cycles 50111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2289500 # number of demand (read+write) MSHR miss cycles 50211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 2289500 # number of demand (read+write) MSHR miss cycles 50311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2289500 # number of overall MSHR miss cycles 50411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 2289500 # number of overall MSHR miss cycles 50511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003962 # mshr miss rate for ReadReq accesses 50611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003962 # mshr miss rate for ReadReq accesses 50711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007944 # mshr miss rate for WriteReq accesses 50811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007944 # mshr miss rate for WriteReq accesses 50911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses 51011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses 51111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for demand accesses 51211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.004926 # mshr miss rate for demand accesses 51311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for overall accesses 51411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.004926 # mshr miss rate for overall accesses 51511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 5905.487805 # average ReadReq mshr miss latency 51611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 5905.487805 # average ReadReq mshr miss latency 51711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12580.952381 # average WriteReq mshr miss latency 51811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12580.952381 # average WriteReq mshr miss latency 51911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3464.285714 # average SwapReq mshr miss latency 52011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3464.285714 # average SwapReq mshr miss latency 52111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency 52211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency 52311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency 52411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency 52511606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 52611507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.replacements 280 # number of replacements 52711606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.tagsinuse 66.813763 # Cycle average of tags in use 52811606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.total_refs 169007 # Total number of references to valid blocks. 52911507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 53011606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.avg_refs 461.767760 # Average number of references to valid blocks. 53111507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 53211606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 66.813763 # Average occupied blocks per requestor 53311606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.130496 # Average percentage of cache occupancy 53411606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.130496 # Average percentage of cache occupancy 53511507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 53611606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 53711606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 53811507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 53911507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 54011606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.tag_accesses 169739 # Number of tag accesses 54111606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.data_accesses 169739 # Number of data accesses 54211606Sandreas.sandberg@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 54311606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 169007 # number of ReadReq hits 54411606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_hits::total 169007 # number of ReadReq hits 54511606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 169007 # number of demand (read+write) hits 54611606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_hits::total 169007 # number of demand (read+write) hits 54711606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 169007 # number of overall hits 54811606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_hits::total 169007 # number of overall hits 54911507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 55011507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 55111507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 55211507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 55311507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 55411507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 366 # number of overall misses 55511606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5703000 # number of ReadReq miss cycles 55611606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 5703000 # number of ReadReq miss cycles 55711606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 5703000 # number of demand (read+write) miss cycles 55811606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_latency::total 5703000 # number of demand (read+write) miss cycles 55911606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 5703000 # number of overall miss cycles 56011606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_latency::total 5703000 # number of overall miss cycles 56111606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 169373 # number of ReadReq accesses(hits+misses) 56211606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_accesses::total 169373 # number of ReadReq accesses(hits+misses) 56311606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 169373 # number of demand (read+write) accesses 56411606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_accesses::total 169373 # number of demand (read+write) accesses 56511606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 169373 # number of overall (read+write) accesses 56611606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_accesses::total 169373 # number of overall (read+write) accesses 56711606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002161 # miss rate for ReadReq accesses 56811606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.002161 # miss rate for ReadReq accesses 56911606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.002161 # miss rate for demand accesses 57011606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.002161 # miss rate for demand accesses 57111606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.002161 # miss rate for overall accesses 57211606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.002161 # miss rate for overall accesses 57311606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15581.967213 # average ReadReq miss latency 57411606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 15581.967213 # average ReadReq miss latency 57511606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency 57611606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 15581.967213 # average overall miss latency 57711606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency 57811606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 15581.967213 # average overall miss latency 57911507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 58011507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 58111507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 58211507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 58311507SCurtis.Dunham@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 58411507SCurtis.Dunham@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 58511507SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::writebacks 280 # number of writebacks 58611507SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::total 280 # number of writebacks 58711507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 58811507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 58911507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 59011507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 59111507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 59211507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 59311606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5337000 # number of ReadReq MSHR miss cycles 59411606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 5337000 # number of ReadReq MSHR miss cycles 59511606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5337000 # number of demand (read+write) MSHR miss cycles 59611606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 5337000 # number of demand (read+write) MSHR miss cycles 59711606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5337000 # number of overall MSHR miss cycles 59811606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 5337000 # number of overall MSHR miss cycles 59911606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for ReadReq accesses 60011606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002161 # mshr miss rate for ReadReq accesses 60111606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for demand accesses 60211606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.002161 # mshr miss rate for demand accesses 60311606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for overall accesses 60411606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.002161 # mshr miss rate for overall accesses 60511606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average ReadReq mshr miss latency 60611606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14581.967213 # average ReadReq mshr miss latency 60711606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency 60811606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency 60911606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency 61011606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency 61111606Sandreas.sandberg@arm.comsystem.cpu2.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states 61211606Sandreas.sandberg@arm.comsystem.cpu2.numCycles 526819 # number of cpu cycles simulated 61311507SCurtis.Dunham@arm.comsystem.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 61411507SCurtis.Dunham@arm.comsystem.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 61511606Sandreas.sandberg@arm.comsystem.cpu2.committedInsts 165892 # Number of instructions committed 61611606Sandreas.sandberg@arm.comsystem.cpu2.committedOps 165892 # Number of ops (including micro ops) committed 61711606Sandreas.sandberg@arm.comsystem.cpu2.num_int_alu_accesses 110657 # Number of integer alu accesses 61811507SCurtis.Dunham@arm.comsystem.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 61911507SCurtis.Dunham@arm.comsystem.cpu2.num_func_calls 637 # number of times a function call or return occured 62011606Sandreas.sandberg@arm.comsystem.cpu2.num_conditional_control_insts 31626 # number of instructions that are conditional controls 62111606Sandreas.sandberg@arm.comsystem.cpu2.num_int_insts 110657 # number of integer instructions 62211507SCurtis.Dunham@arm.comsystem.cpu2.num_fp_insts 0 # number of float instructions 62311606Sandreas.sandberg@arm.comsystem.cpu2.num_int_register_reads 278357 # number of times the integer registers were read 62411606Sandreas.sandberg@arm.comsystem.cpu2.num_int_register_writes 106099 # number of times the integer registers were written 62511507SCurtis.Dunham@arm.comsystem.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 62611507SCurtis.Dunham@arm.comsystem.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 62711606Sandreas.sandberg@arm.comsystem.cpu2.num_mem_refs 55200 # number of memory refs 62811606Sandreas.sandberg@arm.comsystem.cpu2.num_load_insts 40995 # Number of load instructions 62911606Sandreas.sandberg@arm.comsystem.cpu2.num_store_insts 14205 # Number of store instructions 63011606Sandreas.sandberg@arm.comsystem.cpu2.num_idle_cycles 74930.001716 # Number of idle cycles 63111606Sandreas.sandberg@arm.comsystem.cpu2.num_busy_cycles 451888.998284 # Number of busy cycles 63211606Sandreas.sandberg@arm.comsystem.cpu2.not_idle_fraction 0.857769 # Percentage of non-idle cycles 63311606Sandreas.sandberg@arm.comsystem.cpu2.idle_fraction 0.142231 # Percentage of idle cycles 63411606Sandreas.sandberg@arm.comsystem.cpu2.Branches 33279 # Number of branches fetched 63511606Sandreas.sandberg@arm.comsystem.cpu2.op_class::No_OpClass 24060 14.50% 14.50% # Class of executed instruction 63611606Sandreas.sandberg@arm.comsystem.cpu2.op_class::IntAlu 74589 44.95% 59.45% # Class of executed instruction 63711606Sandreas.sandberg@arm.comsystem.cpu2.op_class::IntMult 0 0.00% 59.45% # Class of executed instruction 63811606Sandreas.sandberg@arm.comsystem.cpu2.op_class::IntDiv 0 0.00% 59.45% # Class of executed instruction 63911606Sandreas.sandberg@arm.comsystem.cpu2.op_class::FloatAdd 0 0.00% 59.45% # Class of executed instruction 64011606Sandreas.sandberg@arm.comsystem.cpu2.op_class::FloatCmp 0 0.00% 59.45% # Class of executed instruction 64111606Sandreas.sandberg@arm.comsystem.cpu2.op_class::FloatCvt 0 0.00% 59.45% # Class of executed instruction 64211606Sandreas.sandberg@arm.comsystem.cpu2.op_class::FloatMult 0 0.00% 59.45% # Class of executed instruction 64311687Sandreas.hansson@arm.comsystem.cpu2.op_class::FloatMultAcc 0 0.00% 59.45% # Class of executed instruction 64411606Sandreas.sandberg@arm.comsystem.cpu2.op_class::FloatDiv 0 0.00% 59.45% # Class of executed instruction 64511687Sandreas.hansson@arm.comsystem.cpu2.op_class::FloatMisc 0 0.00% 59.45% # Class of executed instruction 64611606Sandreas.sandberg@arm.comsystem.cpu2.op_class::FloatSqrt 0 0.00% 59.45% # Class of executed instruction 64711606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdAdd 0 0.00% 59.45% # Class of executed instruction 64811606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdAddAcc 0 0.00% 59.45% # Class of executed instruction 64911606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdAlu 0 0.00% 59.45% # Class of executed instruction 65011606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdCmp 0 0.00% 59.45% # Class of executed instruction 65111606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdCvt 0 0.00% 59.45% # Class of executed instruction 65211606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdMisc 0 0.00% 59.45% # Class of executed instruction 65311606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdMult 0 0.00% 59.45% # Class of executed instruction 65411606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdMultAcc 0 0.00% 59.45% # Class of executed instruction 65511606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdShift 0 0.00% 59.45% # Class of executed instruction 65611606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdShiftAcc 0 0.00% 59.45% # Class of executed instruction 65711606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdSqrt 0 0.00% 59.45% # Class of executed instruction 65811606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdFloatAdd 0 0.00% 59.45% # Class of executed instruction 65911606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdFloatAlu 0 0.00% 59.45% # Class of executed instruction 66011606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdFloatCmp 0 0.00% 59.45% # Class of executed instruction 66111606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdFloatCvt 0 0.00% 59.45% # Class of executed instruction 66211606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdFloatDiv 0 0.00% 59.45% # Class of executed instruction 66311606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdFloatMisc 0 0.00% 59.45% # Class of executed instruction 66411606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdFloatMult 0 0.00% 59.45% # Class of executed instruction 66511606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.45% # Class of executed instruction 66611606Sandreas.sandberg@arm.comsystem.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.45% # Class of executed instruction 66711606Sandreas.sandberg@arm.comsystem.cpu2.op_class::MemRead 53070 31.98% 91.44% # Class of executed instruction 66811606Sandreas.sandberg@arm.comsystem.cpu2.op_class::MemWrite 14205 8.56% 100.00% # Class of executed instruction 66911687Sandreas.hansson@arm.comsystem.cpu2.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 67011687Sandreas.hansson@arm.comsystem.cpu2.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 67111507SCurtis.Dunham@arm.comsystem.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 67211507SCurtis.Dunham@arm.comsystem.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 67311606Sandreas.sandberg@arm.comsystem.cpu2.op_class::total 165924 # Class of executed instruction 67411606Sandreas.sandberg@arm.comsystem.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 67511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.replacements 0 # number of replacements 67611606Sandreas.sandberg@arm.comsystem.cpu2.dcache.tags.tagsinuse 27.420509 # Cycle average of tags in use 67711606Sandreas.sandberg@arm.comsystem.cpu2.dcache.tags.total_refs 30687 # Total number of references to valid blocks. 67811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 67911606Sandreas.sandberg@arm.comsystem.cpu2.dcache.tags.avg_refs 1058.172414 # Average number of references to valid blocks. 68011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 68111606Sandreas.sandberg@arm.comsystem.cpu2.dcache.tags.occ_blocks::cpu2.data 27.420509 # Average occupied blocks per requestor 68211606Sandreas.sandberg@arm.comsystem.cpu2.dcache.tags.occ_percent::cpu2.data 0.053556 # Average percentage of cache occupancy 68311606Sandreas.sandberg@arm.comsystem.cpu2.dcache.tags.occ_percent::total 0.053556 # Average percentage of cache occupancy 68411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 68511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 68611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 68711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 68811606Sandreas.sandberg@arm.comsystem.cpu2.dcache.tags.tag_accesses 221019 # Number of tag accesses 68911606Sandreas.sandberg@arm.comsystem.cpu2.dcache.tags.data_accesses 221019 # Number of data accesses 69011606Sandreas.sandberg@arm.comsystem.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 69111606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_hits::cpu2.data 40826 # number of ReadReq hits 69211606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_hits::total 40826 # number of ReadReq hits 69311606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_hits::cpu2.data 14029 # number of WriteReq hits 69411606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_hits::total 14029 # number of WriteReq hits 69511606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits 69611606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits 69711606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_hits::cpu2.data 54855 # number of demand (read+write) hits 69811606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_hits::total 54855 # number of demand (read+write) hits 69911606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_hits::cpu2.data 54855 # number of overall hits 70011606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_hits::total 54855 # number of overall hits 70111606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses 70211606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses 70311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses 70411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses 70511606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses 70611606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses 70711606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses 70811606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses 70911606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses 71011606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_misses::total 267 # number of overall misses 71111606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1409000 # number of ReadReq miss cycles 71211606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_miss_latency::total 1409000 # number of ReadReq miss cycles 71311606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1485000 # number of WriteReq miss cycles 71411606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles 71511606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_miss_latency::cpu2.data 251000 # number of SwapReq miss cycles 71611606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_miss_latency::total 251000 # number of SwapReq miss cycles 71711606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_miss_latency::cpu2.data 2894000 # number of demand (read+write) miss cycles 71811606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_miss_latency::total 2894000 # number of demand (read+write) miss cycles 71911606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_miss_latency::cpu2.data 2894000 # number of overall miss cycles 72011606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_miss_latency::total 2894000 # number of overall miss cycles 72111606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_accesses::cpu2.data 40988 # number of ReadReq accesses(hits+misses) 72211606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_accesses::total 40988 # number of ReadReq accesses(hits+misses) 72311606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_accesses::cpu2.data 14134 # number of WriteReq accesses(hits+misses) 72411606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_accesses::total 14134 # number of WriteReq accesses(hits+misses) 72511606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) 72611606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) 72711606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_accesses::cpu2.data 55122 # number of demand (read+write) accesses 72811606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_accesses::total 55122 # number of demand (read+write) accesses 72911606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_accesses::cpu2.data 55122 # number of overall (read+write) accesses 73011606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_accesses::total 55122 # number of overall (read+write) accesses 73111606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003952 # miss rate for ReadReq accesses 73211606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_miss_rate::total 0.003952 # miss rate for ReadReq accesses 73311606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007429 # miss rate for WriteReq accesses 73411606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_miss_rate::total 0.007429 # miss rate for WriteReq accesses 73511606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses 73611606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses 73711606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_miss_rate::cpu2.data 0.004844 # miss rate for demand accesses 73811606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_miss_rate::total 0.004844 # miss rate for demand accesses 73911606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_miss_rate::cpu2.data 0.004844 # miss rate for overall accesses 74011606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_miss_rate::total 0.004844 # miss rate for overall accesses 74111606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8697.530864 # average ReadReq miss latency 74211606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_avg_miss_latency::total 8697.530864 # average ReadReq miss latency 74311606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 14142.857143 # average WriteReq miss latency 74411606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_avg_miss_latency::total 14142.857143 # average WriteReq miss latency 74511606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4482.142857 # average SwapReq miss latency 74611606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_avg_miss_latency::total 4482.142857 # average SwapReq miss latency 74711606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency 74811606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_avg_miss_latency::total 10838.951311 # average overall miss latency 74911606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency 75011606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_avg_miss_latency::total 10838.951311 # average overall miss latency 75111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 75211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 75311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 75411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 75511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 75611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 75711606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses 75811606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses 75911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses 76011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 76111606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses 76211606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 76311606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses 76411606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses 76511606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses 76611606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses 76711606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1247000 # number of ReadReq MSHR miss cycles 76811606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_mshr_miss_latency::total 1247000 # number of ReadReq MSHR miss cycles 76911606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1380000 # number of WriteReq MSHR miss cycles 77011606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_mshr_miss_latency::total 1380000 # number of WriteReq MSHR miss cycles 77111606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 195000 # number of SwapReq MSHR miss cycles 77211606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_mshr_miss_latency::total 195000 # number of SwapReq MSHR miss cycles 77311606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2627000 # number of demand (read+write) MSHR miss cycles 77411606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_mshr_miss_latency::total 2627000 # number of demand (read+write) MSHR miss cycles 77511606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2627000 # number of overall MSHR miss cycles 77611606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_mshr_miss_latency::total 2627000 # number of overall MSHR miss cycles 77711606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003952 # mshr miss rate for ReadReq accesses 77811606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003952 # mshr miss rate for ReadReq accesses 77911606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007429 # mshr miss rate for WriteReq accesses 78011606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007429 # mshr miss rate for WriteReq accesses 78111606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses 78211606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses 78311606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for demand accesses 78411606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_mshr_miss_rate::total 0.004844 # mshr miss rate for demand accesses 78511606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for overall accesses 78611606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_mshr_miss_rate::total 0.004844 # mshr miss rate for overall accesses 78711606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7697.530864 # average ReadReq mshr miss latency 78811606Sandreas.sandberg@arm.comsystem.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7697.530864 # average ReadReq mshr miss latency 78911606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13142.857143 # average WriteReq mshr miss latency 79011606Sandreas.sandberg@arm.comsystem.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13142.857143 # average WriteReq mshr miss latency 79111606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3482.142857 # average SwapReq mshr miss latency 79211606Sandreas.sandberg@arm.comsystem.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3482.142857 # average SwapReq mshr miss latency 79311606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency 79411606Sandreas.sandberg@arm.comsystem.cpu2.dcache.demand_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency 79511606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency 79611606Sandreas.sandberg@arm.comsystem.cpu2.dcache.overall_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency 79711606Sandreas.sandberg@arm.comsystem.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 79811507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.replacements 280 # number of replacements 79911606Sandreas.sandberg@arm.comsystem.cpu2.icache.tags.tagsinuse 69.231273 # Cycle average of tags in use 80011606Sandreas.sandberg@arm.comsystem.cpu2.icache.tags.total_refs 165559 # Total number of references to valid blocks. 80111507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 80211606Sandreas.sandberg@arm.comsystem.cpu2.icache.tags.avg_refs 452.346995 # Average number of references to valid blocks. 80311507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 80411606Sandreas.sandberg@arm.comsystem.cpu2.icache.tags.occ_blocks::cpu2.inst 69.231273 # Average occupied blocks per requestor 80511606Sandreas.sandberg@arm.comsystem.cpu2.icache.tags.occ_percent::cpu2.inst 0.135217 # Average percentage of cache occupancy 80611606Sandreas.sandberg@arm.comsystem.cpu2.icache.tags.occ_percent::total 0.135217 # Average percentage of cache occupancy 80711507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 80811507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 80911507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 81011507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 81111507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 81211606Sandreas.sandberg@arm.comsystem.cpu2.icache.tags.tag_accesses 166291 # Number of tag accesses 81311606Sandreas.sandberg@arm.comsystem.cpu2.icache.tags.data_accesses 166291 # Number of data accesses 81411606Sandreas.sandberg@arm.comsystem.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 81511606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_hits::cpu2.inst 165559 # number of ReadReq hits 81611606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_hits::total 165559 # number of ReadReq hits 81711606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_hits::cpu2.inst 165559 # number of demand (read+write) hits 81811606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_hits::total 165559 # number of demand (read+write) hits 81911606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_hits::cpu2.inst 165559 # number of overall hits 82011606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_hits::total 165559 # number of overall hits 82111507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 82211507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 82311507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 82411507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 82511507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 82611507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_misses::total 366 # number of overall misses 82711606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8164000 # number of ReadReq miss cycles 82811606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_miss_latency::total 8164000 # number of ReadReq miss cycles 82911606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_miss_latency::cpu2.inst 8164000 # number of demand (read+write) miss cycles 83011606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_miss_latency::total 8164000 # number of demand (read+write) miss cycles 83111606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_miss_latency::cpu2.inst 8164000 # number of overall miss cycles 83211606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_miss_latency::total 8164000 # number of overall miss cycles 83311606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_accesses::cpu2.inst 165925 # number of ReadReq accesses(hits+misses) 83411606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_accesses::total 165925 # number of ReadReq accesses(hits+misses) 83511606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_accesses::cpu2.inst 165925 # number of demand (read+write) accesses 83611606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_accesses::total 165925 # number of demand (read+write) accesses 83711606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_accesses::cpu2.inst 165925 # number of overall (read+write) accesses 83811606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_accesses::total 165925 # number of overall (read+write) accesses 83911606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002206 # miss rate for ReadReq accesses 84011606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_miss_rate::total 0.002206 # miss rate for ReadReq accesses 84111606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_miss_rate::cpu2.inst 0.002206 # miss rate for demand accesses 84211606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_miss_rate::total 0.002206 # miss rate for demand accesses 84311606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_miss_rate::cpu2.inst 0.002206 # miss rate for overall accesses 84411606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_miss_rate::total 0.002206 # miss rate for overall accesses 84511606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22306.010929 # average ReadReq miss latency 84611606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_avg_miss_latency::total 22306.010929 # average ReadReq miss latency 84711606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency 84811606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_avg_miss_latency::total 22306.010929 # average overall miss latency 84911606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency 85011606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_avg_miss_latency::total 22306.010929 # average overall miss latency 85111507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 85211507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 85311507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 85411507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 85511507SCurtis.Dunham@arm.comsystem.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 85611507SCurtis.Dunham@arm.comsystem.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 85711507SCurtis.Dunham@arm.comsystem.cpu2.icache.writebacks::writebacks 280 # number of writebacks 85811507SCurtis.Dunham@arm.comsystem.cpu2.icache.writebacks::total 280 # number of writebacks 85911507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 86011507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 86111507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 86211507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 86311507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 86411507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 86511606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7798000 # number of ReadReq MSHR miss cycles 86611606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_mshr_miss_latency::total 7798000 # number of ReadReq MSHR miss cycles 86711606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7798000 # number of demand (read+write) MSHR miss cycles 86811606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_mshr_miss_latency::total 7798000 # number of demand (read+write) MSHR miss cycles 86911606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7798000 # number of overall MSHR miss cycles 87011606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_mshr_miss_latency::total 7798000 # number of overall MSHR miss cycles 87111606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for ReadReq accesses 87211606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002206 # mshr miss rate for ReadReq accesses 87311606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for demand accesses 87411606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_mshr_miss_rate::total 0.002206 # mshr miss rate for demand accesses 87511606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for overall accesses 87611606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_mshr_miss_rate::total 0.002206 # mshr miss rate for overall accesses 87711606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average ReadReq mshr miss latency 87811606Sandreas.sandberg@arm.comsystem.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21306.010929 # average ReadReq mshr miss latency 87911606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency 88011606Sandreas.sandberg@arm.comsystem.cpu2.icache.demand_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency 88111606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency 88211606Sandreas.sandberg@arm.comsystem.cpu2.icache.overall_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency 88311606Sandreas.sandberg@arm.comsystem.cpu3.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states 88411606Sandreas.sandberg@arm.comsystem.cpu3.numCycles 526818 # number of cpu cycles simulated 88511507SCurtis.Dunham@arm.comsystem.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 88611507SCurtis.Dunham@arm.comsystem.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 88711606Sandreas.sandberg@arm.comsystem.cpu3.committedInsts 170395 # Number of instructions committed 88811606Sandreas.sandberg@arm.comsystem.cpu3.committedOps 170395 # Number of ops (including micro ops) committed 88911606Sandreas.sandberg@arm.comsystem.cpu3.num_int_alu_accesses 111057 # Number of integer alu accesses 89011507SCurtis.Dunham@arm.comsystem.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 89111507SCurtis.Dunham@arm.comsystem.cpu3.num_func_calls 637 # number of times a function call or return occured 89211606Sandreas.sandberg@arm.comsystem.cpu3.num_conditional_control_insts 33676 # number of instructions that are conditional controls 89311606Sandreas.sandberg@arm.comsystem.cpu3.num_int_insts 111057 # number of integer instructions 89411507SCurtis.Dunham@arm.comsystem.cpu3.num_fp_insts 0 # number of float instructions 89511606Sandreas.sandberg@arm.comsystem.cpu3.num_int_register_reads 271753 # number of times the integer registers were read 89611606Sandreas.sandberg@arm.comsystem.cpu3.num_int_register_writes 102596 # number of times the integer registers were written 89711507SCurtis.Dunham@arm.comsystem.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 89811507SCurtis.Dunham@arm.comsystem.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 89911606Sandreas.sandberg@arm.comsystem.cpu3.num_mem_refs 53550 # number of memory refs 90011606Sandreas.sandberg@arm.comsystem.cpu3.num_load_insts 41191 # Number of load instructions 90111606Sandreas.sandberg@arm.comsystem.cpu3.num_store_insts 12359 # Number of store instructions 90211606Sandreas.sandberg@arm.comsystem.cpu3.num_idle_cycles 75201.858967 # Number of idle cycles 90311606Sandreas.sandberg@arm.comsystem.cpu3.num_busy_cycles 451616.141033 # Number of busy cycles 90411606Sandreas.sandberg@arm.comsystem.cpu3.not_idle_fraction 0.857253 # Percentage of non-idle cycles 90511606Sandreas.sandberg@arm.comsystem.cpu3.idle_fraction 0.142747 # Percentage of idle cycles 90611606Sandreas.sandberg@arm.comsystem.cpu3.Branches 35332 # Number of branches fetched 90711606Sandreas.sandberg@arm.comsystem.cpu3.op_class::No_OpClass 26110 15.32% 15.32% # Class of executed instruction 90811606Sandreas.sandberg@arm.comsystem.cpu3.op_class::IntAlu 74791 43.88% 59.20% # Class of executed instruction 90911606Sandreas.sandberg@arm.comsystem.cpu3.op_class::IntMult 0 0.00% 59.20% # Class of executed instruction 91011606Sandreas.sandberg@arm.comsystem.cpu3.op_class::IntDiv 0 0.00% 59.20% # Class of executed instruction 91111606Sandreas.sandberg@arm.comsystem.cpu3.op_class::FloatAdd 0 0.00% 59.20% # Class of executed instruction 91211606Sandreas.sandberg@arm.comsystem.cpu3.op_class::FloatCmp 0 0.00% 59.20% # Class of executed instruction 91311606Sandreas.sandberg@arm.comsystem.cpu3.op_class::FloatCvt 0 0.00% 59.20% # Class of executed instruction 91411606Sandreas.sandberg@arm.comsystem.cpu3.op_class::FloatMult 0 0.00% 59.20% # Class of executed instruction 91511687Sandreas.hansson@arm.comsystem.cpu3.op_class::FloatMultAcc 0 0.00% 59.20% # Class of executed instruction 91611606Sandreas.sandberg@arm.comsystem.cpu3.op_class::FloatDiv 0 0.00% 59.20% # Class of executed instruction 91711687Sandreas.hansson@arm.comsystem.cpu3.op_class::FloatMisc 0 0.00% 59.20% # Class of executed instruction 91811606Sandreas.sandberg@arm.comsystem.cpu3.op_class::FloatSqrt 0 0.00% 59.20% # Class of executed instruction 91911606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdAdd 0 0.00% 59.20% # Class of executed instruction 92011606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdAddAcc 0 0.00% 59.20% # Class of executed instruction 92111606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdAlu 0 0.00% 59.20% # Class of executed instruction 92211606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdCmp 0 0.00% 59.20% # Class of executed instruction 92311606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdCvt 0 0.00% 59.20% # Class of executed instruction 92411606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdMisc 0 0.00% 59.20% # Class of executed instruction 92511606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdMult 0 0.00% 59.20% # Class of executed instruction 92611606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdMultAcc 0 0.00% 59.20% # Class of executed instruction 92711606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdShift 0 0.00% 59.20% # Class of executed instruction 92811606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdShiftAcc 0 0.00% 59.20% # Class of executed instruction 92911606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdSqrt 0 0.00% 59.20% # Class of executed instruction 93011606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdFloatAdd 0 0.00% 59.20% # Class of executed instruction 93111606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdFloatAlu 0 0.00% 59.20% # Class of executed instruction 93211606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdFloatCmp 0 0.00% 59.20% # Class of executed instruction 93311606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdFloatCvt 0 0.00% 59.20% # Class of executed instruction 93411606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdFloatDiv 0 0.00% 59.20% # Class of executed instruction 93511606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdFloatMisc 0 0.00% 59.20% # Class of executed instruction 93611606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdFloatMult 0 0.00% 59.20% # Class of executed instruction 93711606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.20% # Class of executed instruction 93811606Sandreas.sandberg@arm.comsystem.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.20% # Class of executed instruction 93911606Sandreas.sandberg@arm.comsystem.cpu3.op_class::MemRead 57167 33.54% 92.75% # Class of executed instruction 94011606Sandreas.sandberg@arm.comsystem.cpu3.op_class::MemWrite 12359 7.25% 100.00% # Class of executed instruction 94111687Sandreas.hansson@arm.comsystem.cpu3.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 94211687Sandreas.hansson@arm.comsystem.cpu3.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 94311507SCurtis.Dunham@arm.comsystem.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 94411507SCurtis.Dunham@arm.comsystem.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94511606Sandreas.sandberg@arm.comsystem.cpu3.op_class::total 170427 # Class of executed instruction 94611606Sandreas.sandberg@arm.comsystem.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 94711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.replacements 0 # number of replacements 94811606Sandreas.sandberg@arm.comsystem.cpu3.dcache.tags.tagsinuse 25.613981 # Cycle average of tags in use 94911606Sandreas.sandberg@arm.comsystem.cpu3.dcache.tags.total_refs 27108 # Total number of references to valid blocks. 95011606Sandreas.sandberg@arm.comsystem.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 95111606Sandreas.sandberg@arm.comsystem.cpu3.dcache.tags.avg_refs 903.600000 # Average number of references to valid blocks. 95211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 95311606Sandreas.sandberg@arm.comsystem.cpu3.dcache.tags.occ_blocks::cpu3.data 25.613981 # Average occupied blocks per requestor 95411606Sandreas.sandberg@arm.comsystem.cpu3.dcache.tags.occ_percent::cpu3.data 0.050027 # Average percentage of cache occupancy 95511606Sandreas.sandberg@arm.comsystem.cpu3.dcache.tags.occ_percent::total 0.050027 # Average percentage of cache occupancy 95611606Sandreas.sandberg@arm.comsystem.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 95711606Sandreas.sandberg@arm.comsystem.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 95811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 95911606Sandreas.sandberg@arm.comsystem.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 96011606Sandreas.sandberg@arm.comsystem.cpu3.dcache.tags.tag_accesses 214417 # Number of tag accesses 96111606Sandreas.sandberg@arm.comsystem.cpu3.dcache.tags.data_accesses 214417 # Number of data accesses 96211606Sandreas.sandberg@arm.comsystem.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 96311606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_hits::cpu3.data 41020 # number of ReadReq hits 96411606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_hits::total 41020 # number of ReadReq hits 96511606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_hits::cpu3.data 12180 # number of WriteReq hits 96611606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_hits::total 12180 # number of WriteReq hits 96711606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits 96811606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits 96911606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_hits::cpu3.data 53200 # number of demand (read+write) hits 97011606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_hits::total 53200 # number of demand (read+write) hits 97111606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_hits::cpu3.data 53200 # number of overall hits 97211606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_hits::total 53200 # number of overall hits 97311606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses 97411606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses 97511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses 97611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses 97711606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses 97811606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses 97911606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses 98011606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses 98111606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses 98211606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_misses::total 268 # number of overall misses 98311606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1141000 # number of ReadReq miss cycles 98411606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_miss_latency::total 1141000 # number of ReadReq miss cycles 98511606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1445000 # number of WriteReq miss cycles 98611606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_miss_latency::total 1445000 # number of WriteReq miss cycles 98711606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_miss_latency::cpu3.data 263000 # number of SwapReq miss cycles 98811606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_miss_latency::total 263000 # number of SwapReq miss cycles 98911606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_miss_latency::cpu3.data 2586000 # number of demand (read+write) miss cycles 99011606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_miss_latency::total 2586000 # number of demand (read+write) miss cycles 99111606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_miss_latency::cpu3.data 2586000 # number of overall miss cycles 99211606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_miss_latency::total 2586000 # number of overall miss cycles 99311606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_accesses::cpu3.data 41183 # number of ReadReq accesses(hits+misses) 99411606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_accesses::total 41183 # number of ReadReq accesses(hits+misses) 99511606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_accesses::cpu3.data 12285 # number of WriteReq accesses(hits+misses) 99611606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_accesses::total 12285 # number of WriteReq accesses(hits+misses) 99711606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) 99811606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) 99911606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_accesses::cpu3.data 53468 # number of demand (read+write) accesses 100011606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_accesses::total 53468 # number of demand (read+write) accesses 100111606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_accesses::cpu3.data 53468 # number of overall (read+write) accesses 100211606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_accesses::total 53468 # number of overall (read+write) accesses 100311606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003958 # miss rate for ReadReq accesses 100411606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_miss_rate::total 0.003958 # miss rate for ReadReq accesses 100511606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008547 # miss rate for WriteReq accesses 100611606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_miss_rate::total 0.008547 # miss rate for WriteReq accesses 100711606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses 100811606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses 100911606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_miss_rate::cpu3.data 0.005012 # miss rate for demand accesses 101011606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_miss_rate::total 0.005012 # miss rate for demand accesses 101111606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_miss_rate::cpu3.data 0.005012 # miss rate for overall accesses 101211606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_miss_rate::total 0.005012 # miss rate for overall accesses 101311606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7000 # average ReadReq miss latency 101411606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_avg_miss_latency::total 7000 # average ReadReq miss latency 101511606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 13761.904762 # average WriteReq miss latency 101611606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_avg_miss_latency::total 13761.904762 # average WriteReq miss latency 101711606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4534.482759 # average SwapReq miss latency 101811606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_avg_miss_latency::total 4534.482759 # average SwapReq miss latency 101911606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency 102011606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_avg_miss_latency::total 9649.253731 # average overall miss latency 102111606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency 102211606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_avg_miss_latency::total 9649.253731 # average overall miss latency 102311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 102411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 102511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 102611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 102711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 102811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 102911606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses 103011606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses 103111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses 103211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 103311606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses 103411606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses 103511606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses 103611606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses 103711606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses 103811606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses 103911606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 978000 # number of ReadReq MSHR miss cycles 104011606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_mshr_miss_latency::total 978000 # number of ReadReq MSHR miss cycles 104111606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1340000 # number of WriteReq MSHR miss cycles 104211606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_mshr_miss_latency::total 1340000 # number of WriteReq MSHR miss cycles 104311606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 205000 # number of SwapReq MSHR miss cycles 104411606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_mshr_miss_latency::total 205000 # number of SwapReq MSHR miss cycles 104511606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2318000 # number of demand (read+write) MSHR miss cycles 104611606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_mshr_miss_latency::total 2318000 # number of demand (read+write) MSHR miss cycles 104711606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2318000 # number of overall MSHR miss cycles 104811606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_mshr_miss_latency::total 2318000 # number of overall MSHR miss cycles 104911606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003958 # mshr miss rate for ReadReq accesses 105011606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003958 # mshr miss rate for ReadReq accesses 105111606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008547 # mshr miss rate for WriteReq accesses 105211606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008547 # mshr miss rate for WriteReq accesses 105311606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses 105411606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses 105511606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005012 # mshr miss rate for demand accesses 105611606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_mshr_miss_rate::total 0.005012 # mshr miss rate for demand accesses 105711606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005012 # mshr miss rate for overall accesses 105811606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_mshr_miss_rate::total 0.005012 # mshr miss rate for overall accesses 105911606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6000 # average ReadReq mshr miss latency 106011606Sandreas.sandberg@arm.comsystem.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6000 # average ReadReq mshr miss latency 106111606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12761.904762 # average WriteReq mshr miss latency 106211606Sandreas.sandberg@arm.comsystem.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12761.904762 # average WriteReq mshr miss latency 106311606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3534.482759 # average SwapReq mshr miss latency 106411606Sandreas.sandberg@arm.comsystem.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3534.482759 # average SwapReq mshr miss latency 106511606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8649.253731 # average overall mshr miss latency 106611606Sandreas.sandberg@arm.comsystem.cpu3.dcache.demand_avg_mshr_miss_latency::total 8649.253731 # average overall mshr miss latency 106711606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8649.253731 # average overall mshr miss latency 106811606Sandreas.sandberg@arm.comsystem.cpu3.dcache.overall_avg_mshr_miss_latency::total 8649.253731 # average overall mshr miss latency 106911606Sandreas.sandberg@arm.comsystem.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 107011507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.replacements 281 # number of replacements 107111606Sandreas.sandberg@arm.comsystem.cpu3.icache.tags.tagsinuse 64.803703 # Cycle average of tags in use 107211606Sandreas.sandberg@arm.comsystem.cpu3.icache.tags.total_refs 170061 # Total number of references to valid blocks. 107311507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 107411606Sandreas.sandberg@arm.comsystem.cpu3.icache.tags.avg_refs 463.381471 # Average number of references to valid blocks. 107511507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 107611606Sandreas.sandberg@arm.comsystem.cpu3.icache.tags.occ_blocks::cpu3.inst 64.803703 # Average occupied blocks per requestor 107711606Sandreas.sandberg@arm.comsystem.cpu3.icache.tags.occ_percent::cpu3.inst 0.126570 # Average percentage of cache occupancy 107811606Sandreas.sandberg@arm.comsystem.cpu3.icache.tags.occ_percent::total 0.126570 # Average percentage of cache occupancy 107911507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 108011606Sandreas.sandberg@arm.comsystem.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 108111606Sandreas.sandberg@arm.comsystem.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 108211507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 108311507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 108411606Sandreas.sandberg@arm.comsystem.cpu3.icache.tags.tag_accesses 170795 # Number of tag accesses 108511606Sandreas.sandberg@arm.comsystem.cpu3.icache.tags.data_accesses 170795 # Number of data accesses 108611606Sandreas.sandberg@arm.comsystem.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 108711606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_hits::cpu3.inst 170061 # number of ReadReq hits 108811606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_hits::total 170061 # number of ReadReq hits 108911606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_hits::cpu3.inst 170061 # number of demand (read+write) hits 109011606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_hits::total 170061 # number of demand (read+write) hits 109111606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_hits::cpu3.inst 170061 # number of overall hits 109211606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_hits::total 170061 # number of overall hits 109311507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 109411507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 109511507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 109611507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 109711507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 109811507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_misses::total 367 # number of overall misses 109911606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5475500 # number of ReadReq miss cycles 110011606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_miss_latency::total 5475500 # number of ReadReq miss cycles 110111606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_miss_latency::cpu3.inst 5475500 # number of demand (read+write) miss cycles 110211606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_miss_latency::total 5475500 # number of demand (read+write) miss cycles 110311606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_miss_latency::cpu3.inst 5475500 # number of overall miss cycles 110411606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_miss_latency::total 5475500 # number of overall miss cycles 110511606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_accesses::cpu3.inst 170428 # number of ReadReq accesses(hits+misses) 110611606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_accesses::total 170428 # number of ReadReq accesses(hits+misses) 110711606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_accesses::cpu3.inst 170428 # number of demand (read+write) accesses 110811606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_accesses::total 170428 # number of demand (read+write) accesses 110911606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_accesses::cpu3.inst 170428 # number of overall (read+write) accesses 111011606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_accesses::total 170428 # number of overall (read+write) accesses 111111606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002153 # miss rate for ReadReq accesses 111211606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses 111311606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_miss_rate::cpu3.inst 0.002153 # miss rate for demand accesses 111411606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses 111511606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_miss_rate::cpu3.inst 0.002153 # miss rate for overall accesses 111611606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_miss_rate::total 0.002153 # miss rate for overall accesses 111711606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14919.618529 # average ReadReq miss latency 111811606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_avg_miss_latency::total 14919.618529 # average ReadReq miss latency 111911606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14919.618529 # average overall miss latency 112011606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_avg_miss_latency::total 14919.618529 # average overall miss latency 112111606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14919.618529 # average overall miss latency 112211606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_avg_miss_latency::total 14919.618529 # average overall miss latency 112311507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 112411507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 112511507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 112611507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 112711507SCurtis.Dunham@arm.comsystem.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 112811507SCurtis.Dunham@arm.comsystem.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 112911507SCurtis.Dunham@arm.comsystem.cpu3.icache.writebacks::writebacks 281 # number of writebacks 113011507SCurtis.Dunham@arm.comsystem.cpu3.icache.writebacks::total 281 # number of writebacks 113111507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 113211507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 113311507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 113411507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 113511507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 113611507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 113711606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5108500 # number of ReadReq MSHR miss cycles 113811606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles 113911606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5108500 # number of demand (read+write) MSHR miss cycles 114011606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_mshr_miss_latency::total 5108500 # number of demand (read+write) MSHR miss cycles 114111606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5108500 # number of overall MSHR miss cycles 114211606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_mshr_miss_latency::total 5108500 # number of overall MSHR miss cycles 114311606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for ReadReq accesses 114411606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses 114511606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for demand accesses 114611606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses 114711606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for overall accesses 114811606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses 114911606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average ReadReq mshr miss latency 115011606Sandreas.sandberg@arm.comsystem.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13919.618529 # average ReadReq mshr miss latency 115111606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency 115211606Sandreas.sandberg@arm.comsystem.cpu3.icache.demand_avg_mshr_miss_latency::total 13919.618529 # average overall mshr miss latency 115311606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency 115411606Sandreas.sandberg@arm.comsystem.cpu3.icache.overall_avg_mshr_miss_latency::total 13919.618529 # average overall mshr miss latency 115511606Sandreas.sandberg@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 115611507SCurtis.Dunham@arm.comsystem.l2c.tags.replacements 0 # number of replacements 115711606Sandreas.sandberg@arm.comsystem.l2c.tags.tagsinuse 470.663959 # Cycle average of tags in use 115811606Sandreas.sandberg@arm.comsystem.l2c.tags.total_refs 1794 # Total number of references to valid blocks. 115911606Sandreas.sandberg@arm.comsystem.l2c.tags.sampled_refs 572 # Sample count of references to valid blocks. 116011606Sandreas.sandberg@arm.comsystem.l2c.tags.avg_refs 3.136364 # Average number of references to valid blocks. 116111507SCurtis.Dunham@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 116211606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 230.500098 # Average occupied blocks per requestor 116311606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 147.566608 # Average occupied blocks per requestor 116411606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 6.217156 # Average occupied blocks per requestor 116511606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 10.908895 # Average occupied blocks per requestor 116611606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu2.inst 46.660458 # Average occupied blocks per requestor 116711606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu2.data 17.373358 # Average occupied blocks per requestor 116811606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu3.inst 0.877256 # Average occupied blocks per requestor 116911606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu3.data 10.560130 # Average occupied blocks per requestor 117011606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.003517 # Average percentage of cache occupancy 117111606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.002252 # Average percentage of cache occupancy 117211606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy 117311606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.000166 # Average percentage of cache occupancy 117411507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu2.inst 0.000712 # Average percentage of cache occupancy 117511606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu2.data 0.000265 # Average percentage of cache occupancy 117611606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu3.inst 0.000013 # Average percentage of cache occupancy 117711606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu3.data 0.000161 # Average percentage of cache occupancy 117811606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::total 0.007182 # Average percentage of cache occupancy 117911606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 572 # Occupied blocks per task id 118011606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 118111606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id 118211606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.008728 # Percentage of cache occupancy per task id 118311606Sandreas.sandberg@arm.comsystem.l2c.tags.tag_accesses 19676 # Number of tag accesses 118411606Sandreas.sandberg@arm.comsystem.l2c.tags.data_accesses 19676 # Number of data accesses 118511606Sandreas.sandberg@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 118611507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 118711507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 118811507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits 118911507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits 119011606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 30 # number of UpgradeReq hits 119111606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits 119211606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu2.data 16 # number of UpgradeReq hits 119311606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu3.data 17 # number of UpgradeReq hits 119411606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::total 79 # number of UpgradeReq hits 119511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits 119611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits 119711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu2.inst 301 # number of ReadCleanReq hits 119811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu3.inst 357 # number of ReadCleanReq hits 119911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::total 1192 # number of ReadCleanReq hits 120011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 120111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits 120211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits 120311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits 120411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits 120511507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits 120611507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 120711507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits 120811507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits 120911507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu2.inst 301 # number of demand (read+write) hits 121011507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits 121111507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits 121211507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 121311507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::total 1218 # number of demand (read+write) hits 121411507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.inst 182 # number of overall hits 121511507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.data 5 # number of overall hits 121611507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.inst 352 # number of overall hits 121711507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.data 9 # number of overall hits 121811507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu2.inst 301 # number of overall hits 121911507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu2.data 3 # number of overall hits 122011507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu3.inst 357 # number of overall hits 122111507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu3.data 9 # number of overall hits 122211507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::total 1218 # number of overall hits 122311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 122411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses 122511507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses 122611507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 122711507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 122811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses 122911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses 123011507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu2.inst 65 # number of ReadCleanReq misses 123111507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu3.inst 10 # number of ReadCleanReq misses 123211507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::total 374 # number of ReadCleanReq misses 123311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses 123411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses 123511507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses 123611507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses 123711507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses 123811507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses 123911507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 124011507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses 124111507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses 124211507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu2.inst 65 # number of demand (read+write) misses 124311507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses 124411507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu3.inst 10 # number of demand (read+write) misses 124511507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses 124611507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::total 594 # number of demand (read+write) misses 124711507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.inst 285 # number of overall misses 124811507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.data 165 # number of overall misses 124911507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.inst 14 # number of overall misses 125011507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.data 16 # number of overall misses 125111507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu2.inst 65 # number of overall misses 125211507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu2.data 23 # number of overall misses 125311507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu3.inst 10 # number of overall misses 125411507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu3.data 16 # number of overall misses 125511507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::total 594 # number of overall misses 125611507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 5991000 # number of ReadExReq miss cycles 125711606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 851500 # number of ReadExReq miss cycles 125811507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu2.data 911000 # number of ReadExReq miss cycles 125911606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_latency::cpu3.data 861000 # number of ReadExReq miss cycles 126011507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::total 8614500 # number of ReadExReq miss cycles 126111606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu0.inst 17251000 # number of ReadCleanReq miss cycles 126211606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu1.inst 845000 # number of ReadCleanReq miss cycles 126311606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu2.inst 3885000 # number of ReadCleanReq miss cycles 126411606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu3.inst 552500 # number of ReadCleanReq miss cycles 126511606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_miss_latency::total 22533500 # number of ReadCleanReq miss cycles 126611507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 3993500 # number of ReadSharedReq miss cycles 126711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 120000 # number of ReadSharedReq miss cycles 126811507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu2.data 484000 # number of ReadSharedReq miss cycles 126911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu3.data 120500 # number of ReadSharedReq miss cycles 127011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 4718000 # number of ReadSharedReq miss cycles 127111606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 17251000 # number of demand (read+write) miss cycles 127211507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.data 9984500 # number of demand (read+write) miss cycles 127311606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 845000 # number of demand (read+write) miss cycles 127411606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.data 971500 # number of demand (read+write) miss cycles 127511606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu2.inst 3885000 # number of demand (read+write) miss cycles 127611507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu2.data 1395000 # number of demand (read+write) miss cycles 127711606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu3.inst 552500 # number of demand (read+write) miss cycles 127811606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu3.data 981500 # number of demand (read+write) miss cycles 127911606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::total 35866000 # number of demand (read+write) miss cycles 128011606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 17251000 # number of overall miss cycles 128111507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.data 9984500 # number of overall miss cycles 128211606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 845000 # number of overall miss cycles 128311606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.data 971500 # number of overall miss cycles 128411606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu2.inst 3885000 # number of overall miss cycles 128511507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu2.data 1395000 # number of overall miss cycles 128611606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu3.inst 552500 # number of overall miss cycles 128711606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu3.data 981500 # number of overall miss cycles 128811606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::total 35866000 # number of overall miss cycles 128911507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) 129011507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) 129111507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) 129211507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) 129311507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 129411507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) 129511606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) 129611606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses) 129711507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) 129811507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 129911507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) 130011507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses) 130111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) 130211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) 130311507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) 130411507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu1.inst 366 # number of ReadCleanReq accesses(hits+misses) 130511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu2.inst 366 # number of ReadCleanReq accesses(hits+misses) 130611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu3.inst 367 # number of ReadCleanReq accesses(hits+misses) 130711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::total 1566 # number of ReadCleanReq accesses(hits+misses) 130811507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) 130911507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 11 # number of ReadSharedReq accesses(hits+misses) 131011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu2.data 11 # number of ReadSharedReq accesses(hits+misses) 131111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu3.data 11 # number of ReadSharedReq accesses(hits+misses) 131211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::total 104 # number of ReadSharedReq accesses(hits+misses) 131311507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 131411507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 131511507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses 131611507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses 131711507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses 131811507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses 131911507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses 132011507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses 132111507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses 132211507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 132311507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 132411507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses 132511507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses 132611507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses 132711507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses 132811507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses 132911507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses 133011507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses 133111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 133211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 133311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 133411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 133511507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 133611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadCleanReq accesses 133711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadCleanReq accesses 133811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.177596 # miss rate for ReadCleanReq accesses 133911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.027248 # miss rate for ReadCleanReq accesses 134011507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::total 0.238825 # miss rate for ReadCleanReq accesses 134111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses 134211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadSharedReq accesses 134311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadSharedReq accesses 134411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadSharedReq accesses 134511507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.750000 # miss rate for ReadSharedReq accesses 134611507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses 134711507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 134811507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses 134911507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses 135011507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu2.inst 0.177596 # miss rate for demand accesses 135111507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu2.data 0.884615 # miss rate for demand accesses 135211507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu3.inst 0.027248 # miss rate for demand accesses 135311507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses 135411507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::total 0.327815 # miss rate for demand accesses 135511507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses 135611507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 135711507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.038251 # miss rate for overall accesses 135811507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses 135911507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu2.inst 0.177596 # miss rate for overall accesses 136011507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu2.data 0.884615 # miss rate for overall accesses 136111507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu3.inst 0.027248 # miss rate for overall accesses 136211507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses 136311507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::total 0.327815 # miss rate for overall accesses 136411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 60515.151515 # average ReadExReq miss latency 136511606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 60821.428571 # average ReadExReq miss latency 136611507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu2.data 60733.333333 # average ReadExReq miss latency 136711606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu3.data 61500 # average ReadExReq miss latency 136811507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 60665.492958 # average ReadExReq miss latency 136911606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 60529.824561 # average ReadCleanReq miss latency 137011606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 60357.142857 # average ReadCleanReq miss latency 137111606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 59769.230769 # average ReadCleanReq miss latency 137211606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 55250 # average ReadCleanReq miss latency 137311606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::total 60250 # average ReadCleanReq miss latency 137411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 60507.575758 # average ReadSharedReq miss latency 137511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 60000 # average ReadSharedReq miss latency 137611507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 60500 # average ReadSharedReq miss latency 137711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 60250 # average ReadSharedReq miss latency 137811507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 60487.179487 # average ReadSharedReq miss latency 137911606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 60529.824561 # average overall miss latency 138011507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 60512.121212 # average overall miss latency 138111606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 60357.142857 # average overall miss latency 138211606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 60718.750000 # average overall miss latency 138311606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu2.inst 59769.230769 # average overall miss latency 138411507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu2.data 60652.173913 # average overall miss latency 138511606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu3.inst 55250 # average overall miss latency 138611606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu3.data 61343.750000 # average overall miss latency 138711606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::total 60380.471380 # average overall miss latency 138811606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 60529.824561 # average overall miss latency 138911507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 60512.121212 # average overall miss latency 139011606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 60357.142857 # average overall miss latency 139111606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 60718.750000 # average overall miss latency 139211606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu2.inst 59769.230769 # average overall miss latency 139311507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu2.data 60652.173913 # average overall miss latency 139411606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu3.inst 55250 # average overall miss latency 139511606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu3.data 61343.750000 # average overall miss latency 139611606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::total 60380.471380 # average overall miss latency 139711507SCurtis.Dunham@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 139811507SCurtis.Dunham@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 139911507SCurtis.Dunham@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 140011507SCurtis.Dunham@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 140111507SCurtis.Dunham@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 140211507SCurtis.Dunham@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 140311606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 140411507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_hits::cpu2.inst 7 # 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number of overall MSHR misses 145111507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu2.data 23 # number of overall MSHR misses 145211606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses 145311507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses 145411507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses 145511507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5001000 # number of ReadExReq MSHR miss cycles 145611606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 711500 # number of ReadExReq MSHR miss cycles 145711507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu2.data 761000 # number of ReadExReq MSHR miss cycles 145811606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu3.data 721000 # number of ReadExReq MSHR miss cycles 145911507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 7194500 # number of ReadExReq MSHR miss cycles 146011606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 14401000 # number of ReadCleanReq MSHR miss cycles 146111606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 510000 # number of ReadCleanReq MSHR miss cycles 146211507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2929500 # number of ReadCleanReq MSHR miss cycles 146311606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 50500 # number of ReadCleanReq MSHR miss cycles 146411606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::total 17891000 # number of ReadCleanReq MSHR miss cycles 146511507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 3333500 # number of ReadSharedReq MSHR miss cycles 146611507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 50500 # number of ReadSharedReq MSHR miss cycles 146711507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 404000 # number of ReadSharedReq MSHR miss cycles 146811507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 50500 # number of ReadSharedReq MSHR miss cycles 146911507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 3838500 # number of ReadSharedReq MSHR miss cycles 147011606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 14401000 # number of demand (read+write) MSHR miss cycles 147111507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 8334500 # number of demand (read+write) MSHR miss cycles 147211606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 510000 # number of demand (read+write) MSHR miss cycles 147311606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 762000 # number of demand (read+write) MSHR miss cycles 147411507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu2.inst 2929500 # number of demand (read+write) MSHR miss cycles 147511507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu2.data 1165000 # number of demand (read+write) MSHR miss cycles 147611606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu3.inst 50500 # number of demand (read+write) MSHR miss cycles 147711606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu3.data 771500 # number of demand (read+write) MSHR miss cycles 147811606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::total 28924000 # number of demand (read+write) MSHR miss cycles 147911606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 14401000 # number of overall MSHR miss cycles 148011507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 8334500 # number of overall MSHR miss cycles 148111606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 510000 # number of overall MSHR miss cycles 148211606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 762000 # number of overall MSHR miss cycles 148311507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu2.inst 2929500 # number of overall MSHR miss cycles 148411507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu2.data 1165000 # number of overall MSHR miss cycles 148511606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu3.inst 50500 # number of overall MSHR miss cycles 148611606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu3.data 771500 # number of overall MSHR miss cycles 148711606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::total 28924000 # number of overall MSHR miss cycles 148811507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 148911507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 149011507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 149111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 149211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 149311507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses 149411606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for ReadCleanReq accesses 149511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for ReadCleanReq accesses 149611606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadCleanReq accesses 149711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses 149811507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses 149911507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadSharedReq accesses 150011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.727273 # mshr miss rate for ReadSharedReq accesses 150111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadSharedReq accesses 150211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # mshr miss rate for ReadSharedReq accesses 150311507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 150411507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses 150511606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for demand accesses 150611507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses 150711507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for demand accesses 150811507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for demand accesses 150911606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses 151011507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses 151111507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses 151211507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 151311507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 151411606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for overall accesses 151511507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses 151611507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for overall accesses 151711507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses 151811606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses 151911507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses 152011507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses 152111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 50515.151515 # average ReadExReq mshr miss latency 152211606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50821.428571 # average ReadExReq mshr miss latency 152311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 50733.333333 # average ReadExReq mshr miss latency 152411606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 51500 # average ReadExReq mshr miss latency 152511507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 50665.492958 # average ReadExReq mshr miss latency 152611606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average ReadCleanReq mshr miss latency 152711606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51000 # average ReadCleanReq mshr miss latency 152811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average ReadCleanReq mshr miss latency 152911606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 50500 # average ReadCleanReq mshr miss latency 153011606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::total 50539.548023 # average ReadCleanReq mshr miss latency 153111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 50507.575758 # average ReadSharedReq mshr miss latency 153211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 50500 # average ReadSharedReq mshr miss latency 153311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 50500 # average ReadSharedReq mshr miss latency 153411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 50500 # average ReadSharedReq mshr miss latency 153511507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50506.578947 # average ReadSharedReq mshr miss latency 153611606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average overall mshr miss latency 153711507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency 153811606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency 153911606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency 154011507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency 154111507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency 154211606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency 154311606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency 154411606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency 154511606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average overall mshr miss latency 154611507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency 154711606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency 154811606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency 154911507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency 155011507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency 155111606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency 155211606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency 155311606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency 155411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 839 # Total number of requests made to the snoop filter. 155511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 261 # Number of requests hitting in the snoop filter with a single holder of the requested data. 155611507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 155711507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 155811507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 155911507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 156011606Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 156111507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 430 # Transaction distribution 156211606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeReq 195 # Transaction distribution 156311507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 208 # Transaction distribution 156411507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 142 # Transaction distribution 156511507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 430 # Transaction distribution 156611606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1405 # Packet count per connected master and slave (bytes) 156711606Sandreas.sandberg@arm.comsystem.membus.pkt_count::total 1405 # Packet count per connected master and slave (bytes) 156811507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) 156911507SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) 157011507SCurtis.Dunham@arm.comsystem.membus.snoops 261 # Total snoops (count) 157111570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 157211606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::samples 839 # Request fanout histogram 157311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 157411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 157511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 157611606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::0 839 100.00% 100.00% # Request fanout histogram 157711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 157811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 157911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 158011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 158111606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::total 839 # Request fanout histogram 158211606Sandreas.sandberg@arm.comsystem.membus.reqLayer0.occupancy 587124 # Layer occupancy (ticks) 158311606Sandreas.sandberg@arm.comsystem.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 158411507SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) 158511507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 1.1 # Layer utilization (%) 158611507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_requests 3977 # Total number of requests made to the snoop filter. 158711754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 1080 # Number of requests hitting in the snoop filter with a single holder of the requested data. 158811754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1895 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 158911507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 159011507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 159111507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 159211606Sandreas.sandberg@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 159311507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution 159411507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 159511507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution 159611507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 159711507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution 159811507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution 159911507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExReq 420 # Transaction distribution 160011507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExResp 420 # Transaction distribution 160111507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution 160211507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution 160311507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) 160411507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes) 160511507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) 160611606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) 160711507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) 160811606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) 160911507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes) 161011606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) 161111507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count::total 5868 # Packet count per connected master and slave (bytes) 161211507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) 161311507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 161411507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) 161511507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 161611507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) 161711507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 161811507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 # Cumulative packet size per connected master and slave (bytes) 161911507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 162011507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size::total 183616 # Cumulative packet size per connected master and slave (bytes) 162111507SCurtis.Dunham@arm.comsystem.toL2Bus.snoops 1028 # Total snoops (count) 162211570SCurtis.Dunham@arm.comsystem.toL2Bus.snoopTraffic 53312 # Total snoop traffic (bytes) 162311507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::samples 2919 # Request fanout histogram 162411754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 1.294964 # Request fanout histogram 162511754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 1.172134 # Request fanout histogram 162611507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 162711507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::0 1002 34.33% 34.33% # Request fanout histogram 162811754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 753 25.80% 60.12% # Request fanout histogram 162911754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 465 15.93% 76.05% # Request fanout histogram 163011754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::3 699 23.95% 100.00% # Request fanout histogram 163111507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 163211507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 163311507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 163411507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram 163511507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 163611507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 163711507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 163811507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 163911507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::total 2919 # Request fanout histogram 164011606Sandreas.sandberg@arm.comsystem.toL2Bus.reqLayer0.occupancy 3053983 # Layer occupancy (ticks) 164111507SCurtis.Dunham@arm.comsystem.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 164211507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) 164311507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) 164411606Sandreas.sandberg@arm.comsystem.toL2Bus.respLayer1.occupancy 499498 # Layer occupancy (ticks) 164511507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 164611606Sandreas.sandberg@arm.comsystem.toL2Bus.respLayer2.occupancy 550995 # Layer occupancy (ticks) 164711507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) 164811606Sandreas.sandberg@arm.comsystem.toL2Bus.respLayer3.occupancy 431976 # Layer occupancy (ticks) 164911507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) 165011507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) 165111507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) 165211606Sandreas.sandberg@arm.comsystem.toL2Bus.respLayer5.occupancy 427974 # Layer occupancy (ticks) 165311507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) 165411606Sandreas.sandberg@arm.comsystem.toL2Bus.respLayer6.occupancy 554986 # Layer occupancy (ticks) 165511507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) 165611606Sandreas.sandberg@arm.comsystem.toL2Bus.respLayer7.occupancy 431477 # Layer occupancy (ticks) 165711507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 165811507SCurtis.Dunham@arm.com 165911507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 1660