stats.txt revision 11507
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311507SCurtis.Dunham@arm.comsim_seconds 0.000264 # Number of seconds simulated 411507SCurtis.Dunham@arm.comsim_ticks 264174500 # Number of ticks simulated 511507SCurtis.Dunham@arm.comfinal_tick 264174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711507SCurtis.Dunham@arm.comhost_inst_rate 587931 # Simulator instruction rate (inst/s) 811507SCurtis.Dunham@arm.comhost_op_rate 587915 # Simulator op (including micro ops) rate (op/s) 911507SCurtis.Dunham@arm.comhost_tick_rate 234112560 # Simulator tick rate (ticks/s) 1011507SCurtis.Dunham@arm.comhost_mem_usage 258432 # Number of bytes of host memory used 1111507SCurtis.Dunham@arm.comhost_seconds 1.13 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 663394 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 663394 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory 1911507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory 2411507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 36608 # Number of bytes read from this memory 2511507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory 2611507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory 2711507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory 2811507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory 2911507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 3011507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 3111507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 3211507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory 3311507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory 3411507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory 3511507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory 3611507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory 3711507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory 3811507SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 572 # Number of read requests responded to by this memory 3911507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.inst 69045271 # Total read bandwidth from this memory (bytes/s) 4011507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.data 39973578 # Total read bandwidth from this memory (bytes/s) 4111507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.inst 1695849 # Total read bandwidth from this memory (bytes/s) 4211507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.data 3633962 # Total read bandwidth from this memory (bytes/s) 4311507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu2.inst 14051318 # Total read bandwidth from this memory (bytes/s) 4411507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu2.data 5572075 # Total read bandwidth from this memory (bytes/s) 4511507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu3.inst 969056 # Total read bandwidth from this memory (bytes/s) 4611507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu3.data 3633962 # Total read bandwidth from this memory (bytes/s) 4711507SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 138575071 # Total read bandwidth from this memory (bytes/s) 4811507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu0.inst 69045271 # Instruction read bandwidth from this memory (bytes/s) 4911507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu1.inst 1695849 # Instruction read bandwidth from this memory (bytes/s) 5011507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu2.inst 14051318 # Instruction read bandwidth from this memory (bytes/s) 5111507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu3.inst 969056 # Instruction read bandwidth from this memory (bytes/s) 5211507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 85761495 # Instruction read bandwidth from this memory (bytes/s) 5311507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.inst 69045271 # Total bandwidth to/from this memory (bytes/s) 5411507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.data 39973578 # Total bandwidth to/from this memory (bytes/s) 5511507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.inst 1695849 # Total bandwidth to/from this memory (bytes/s) 5611507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.data 3633962 # Total bandwidth to/from this memory (bytes/s) 5711507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu2.inst 14051318 # Total bandwidth to/from this memory (bytes/s) 5811507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu2.data 5572075 # Total bandwidth to/from this memory (bytes/s) 5911507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu3.inst 969056 # Total bandwidth to/from this memory (bytes/s) 6011507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu3.data 3633962 # Total bandwidth to/from this memory (bytes/s) 6111507SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 138575071 # Total bandwidth to/from this memory (bytes/s) 6211507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 6311507SCurtis.Dunham@arm.comsystem.cpu0.workload.num_syscalls 89 # Number of system calls 6411507SCurtis.Dunham@arm.comsystem.cpu0.numCycles 528349 # number of cpu cycles simulated 6511507SCurtis.Dunham@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 6611507SCurtis.Dunham@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 6711507SCurtis.Dunham@arm.comsystem.cpu0.committedInsts 158268 # Number of instructions committed 6811507SCurtis.Dunham@arm.comsystem.cpu0.committedOps 158268 # Number of ops (including micro ops) committed 6911507SCurtis.Dunham@arm.comsystem.cpu0.num_int_alu_accesses 109004 # Number of integer alu accesses 7011507SCurtis.Dunham@arm.comsystem.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 7111507SCurtis.Dunham@arm.comsystem.cpu0.num_func_calls 390 # number of times a function call or return occured 7211507SCurtis.Dunham@arm.comsystem.cpu0.num_conditional_control_insts 25981 # number of instructions that are conditional controls 7311507SCurtis.Dunham@arm.comsystem.cpu0.num_int_insts 109004 # number of integer instructions 7411507SCurtis.Dunham@arm.comsystem.cpu0.num_fp_insts 0 # number of float instructions 7511507SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_reads 315170 # number of times the integer registers were read 7611507SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_writes 110610 # number of times the integer registers were written 7711507SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 7811507SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 7911507SCurtis.Dunham@arm.comsystem.cpu0.num_mem_refs 73868 # number of memory refs 8011507SCurtis.Dunham@arm.comsystem.cpu0.num_load_insts 48905 # Number of load instructions 8111507SCurtis.Dunham@arm.comsystem.cpu0.num_store_insts 24963 # Number of store instructions 8211507SCurtis.Dunham@arm.comsystem.cpu0.num_idle_cycles 0.002000 # Number of idle cycles 8311507SCurtis.Dunham@arm.comsystem.cpu0.num_busy_cycles 528348.998000 # Number of busy cycles 8411507SCurtis.Dunham@arm.comsystem.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles 8511507SCurtis.Dunham@arm.comsystem.cpu0.idle_fraction 0.000000 # Percentage of idle cycles 8611507SCurtis.Dunham@arm.comsystem.cpu0.Branches 26846 # Number of branches fetched 8711507SCurtis.Dunham@arm.comsystem.cpu0.op_class::No_OpClass 23573 14.89% 14.89% # Class of executed instruction 8811507SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntAlu 60805 38.40% 53.29% # Class of executed instruction 8911507SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction 9011507SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction 9111507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction 9211507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction 9311507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction 9411507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction 9511507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction 9611507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction 9711507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction 9811507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction 9911507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction 10011507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction 10111507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction 10211507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction 10311507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction 10411507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction 10511507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction 10611507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction 10711507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction 10811507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction 10911507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction 11011507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction 11111507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction 11211507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction 11311507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction 11411507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction 11511507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction 11611507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction 11711507SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemRead 48989 30.94% 84.23% # Class of executed instruction 11811507SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemWrite 24963 15.77% 100.00% # Class of executed instruction 11911507SCurtis.Dunham@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 12011507SCurtis.Dunham@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 12111507SCurtis.Dunham@arm.comsystem.cpu0.op_class::total 158330 # Class of executed instruction 12211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 2 # number of replacements 12311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tagsinuse 144.970648 # Cycle average of tags in use 12411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.total_refs 73336 # Total number of references to valid blocks. 12511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 12611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.avg_refs 439.137725 # Average number of references to valid blocks. 12711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 12811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 144.970648 # Average occupied blocks per requestor 12911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.283146 # Average percentage of cache occupancy 13011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.283146 # Average percentage of cache occupancy 13111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 13211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 13311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id 13411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 13511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tag_accesses 295705 # Number of tag accesses 13611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 295705 # Number of data accesses 13711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 48725 # number of ReadReq hits 13811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 48725 # number of ReadReq hits 13911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 24729 # number of WriteReq hits 14011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::total 24729 # number of WriteReq hits 14111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 14211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits 14311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 73454 # number of demand (read+write) hits 14411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::total 73454 # number of demand (read+write) hits 14511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 73454 # number of overall hits 14611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::total 73454 # number of overall hits 14711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses 14811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses 14911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 15011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 15111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 15211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 15311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses 15411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses 15511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses 15611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::total 353 # number of overall misses 15711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4908500 # number of ReadReq miss cycles 15811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 4908500 # number of ReadReq miss cycles 15911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7106500 # number of WriteReq miss cycles 16011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 7106500 # number of WriteReq miss cycles 16111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_miss_latency::cpu0.data 400000 # number of SwapReq miss cycles 16211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_miss_latency::total 400000 # number of SwapReq miss cycles 16311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 12015000 # number of demand (read+write) miss cycles 16411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::total 12015000 # number of demand (read+write) miss cycles 16511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 12015000 # number of overall miss cycles 16611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::total 12015000 # number of overall miss cycles 16711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 48895 # number of ReadReq accesses(hits+misses) 16811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 48895 # number of ReadReq accesses(hits+misses) 16911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 24912 # number of WriteReq accesses(hits+misses) 17011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 24912 # number of WriteReq accesses(hits+misses) 17111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 17211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 17311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 73807 # number of demand (read+write) accesses 17411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::total 73807 # number of demand (read+write) accesses 17511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 73807 # number of overall (read+write) accesses 17611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::total 73807 # number of overall (read+write) accesses 17711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003477 # miss rate for ReadReq accesses 17811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.003477 # miss rate for ReadReq accesses 17911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007346 # miss rate for WriteReq accesses 18011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.007346 # miss rate for WriteReq accesses 18111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 18211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses 18311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.004783 # miss rate for demand accesses 18411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.004783 # miss rate for demand accesses 18511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.004783 # miss rate for overall accesses 18611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.004783 # miss rate for overall accesses 18711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28873.529412 # average ReadReq miss latency 18811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 28873.529412 # average ReadReq miss latency 18911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38833.333333 # average WriteReq miss latency 19011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 38833.333333 # average WriteReq miss latency 19111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15384.615385 # average SwapReq miss latency 19211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_avg_miss_latency::total 15384.615385 # average SwapReq miss latency 19311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34036.827195 # average overall miss latency 19411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 34036.827195 # average overall miss latency 19511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34036.827195 # average overall miss latency 19611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 34036.827195 # average overall miss latency 19711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 19811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 19911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 20011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 20111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 20211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 20311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 20411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::total 1 # number of writebacks 20511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses 20611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses 20711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 20811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 20911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 21011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 21111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses 21211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses 21311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses 21411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses 21511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4738500 # number of ReadReq MSHR miss cycles 21611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 4738500 # number of ReadReq MSHR miss cycles 21711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6923500 # number of WriteReq MSHR miss cycles 21811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 6923500 # number of WriteReq MSHR miss cycles 21911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374000 # number of SwapReq MSHR miss cycles 22011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_miss_latency::total 374000 # number of SwapReq MSHR miss cycles 22111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11662000 # number of demand (read+write) MSHR miss cycles 22211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 11662000 # number of demand (read+write) MSHR miss cycles 22311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11662000 # number of overall MSHR miss cycles 22411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 11662000 # number of overall MSHR miss cycles 22511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003477 # mshr miss rate for ReadReq accesses 22611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003477 # mshr miss rate for ReadReq accesses 22711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007346 # mshr miss rate for WriteReq accesses 22811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007346 # mshr miss rate for WriteReq accesses 22911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 23011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses 23111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004783 # mshr miss rate for demand accesses 23211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.004783 # mshr miss rate for demand accesses 23311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004783 # mshr miss rate for overall accesses 23411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.004783 # mshr miss rate for overall accesses 23511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27873.529412 # average ReadReq mshr miss latency 23611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27873.529412 # average ReadReq mshr miss latency 23711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37833.333333 # average WriteReq mshr miss latency 23811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37833.333333 # average WriteReq mshr miss latency 23911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14384.615385 # average SwapReq mshr miss latency 24011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14384.615385 # average SwapReq mshr miss latency 24111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency 24211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency 24311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency 24411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency 24511507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 215 # number of replacements 24611507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tagsinuse 211.220090 # Cycle average of tags in use 24711507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.total_refs 157864 # Total number of references to valid blocks. 24811507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 24911507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.avg_refs 338.038544 # Average number of references to valid blocks. 25011507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 25111507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 211.220090 # Average occupied blocks per requestor 25211507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.412539 # Average percentage of cache occupancy 25311507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.412539 # Average percentage of cache occupancy 25411507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 25511507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 25611507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 25711507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 25811507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tag_accesses 158798 # Number of tag accesses 25911507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.data_accesses 158798 # Number of data accesses 26011507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 157864 # number of ReadReq hits 26111507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::total 157864 # number of ReadReq hits 26211507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 157864 # number of demand (read+write) hits 26311507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::total 157864 # number of demand (read+write) hits 26411507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 157864 # number of overall hits 26511507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::total 157864 # number of overall hits 26611507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 26711507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 26811507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 26911507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 27011507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 27111507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 467 # number of overall misses 27211507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20426500 # number of ReadReq miss cycles 27311507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 20426500 # number of ReadReq miss cycles 27411507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 20426500 # number of demand (read+write) miss cycles 27511507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::total 20426500 # number of demand (read+write) miss cycles 27611507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 20426500 # number of overall miss cycles 27711507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::total 20426500 # number of overall miss cycles 27811507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 158331 # number of ReadReq accesses(hits+misses) 27911507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 158331 # number of ReadReq accesses(hits+misses) 28011507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 158331 # number of demand (read+write) accesses 28111507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 158331 # number of demand (read+write) accesses 28211507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 158331 # number of overall (read+write) accesses 28311507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 158331 # number of overall (read+write) accesses 28411507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses 28511507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses 28611507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses 28711507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses 28811507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses 28911507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses 29011507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43739.828694 # average ReadReq miss latency 29111507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 43739.828694 # average ReadReq miss latency 29211507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43739.828694 # average overall miss latency 29311507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 43739.828694 # average overall miss latency 29411507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43739.828694 # average overall miss latency 29511507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 43739.828694 # average overall miss latency 29611507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 29711507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 29811507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 29911507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 30011507SCurtis.Dunham@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 30111507SCurtis.Dunham@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 30211507SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::writebacks 215 # number of writebacks 30311507SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::total 215 # number of writebacks 30411507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 30511507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 30611507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 30711507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 30811507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 30911507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses 31011507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19959500 # number of ReadReq MSHR miss cycles 31111507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 19959500 # number of ReadReq MSHR miss cycles 31211507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19959500 # number of demand (read+write) MSHR miss cycles 31311507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 19959500 # number of demand (read+write) MSHR miss cycles 31411507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19959500 # number of overall MSHR miss cycles 31511507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 19959500 # number of overall MSHR miss cycles 31611507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses 31711507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses 31811507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses 31911507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses 32011507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses 32111507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses 32211507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average ReadReq mshr miss latency 32311507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42739.828694 # average ReadReq mshr miss latency 32411507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average overall mshr miss latency 32511507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency 32611507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average overall mshr miss latency 32711507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency 32811507SCurtis.Dunham@arm.comsystem.cpu1.numCycles 528348 # number of cpu cycles simulated 32911507SCurtis.Dunham@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 33011507SCurtis.Dunham@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 33111507SCurtis.Dunham@arm.comsystem.cpu1.committedInsts 170000 # Number of instructions committed 33211507SCurtis.Dunham@arm.comsystem.cpu1.committedOps 170000 # Number of ops (including micro ops) committed 33311507SCurtis.Dunham@arm.comsystem.cpu1.num_int_alu_accesses 111041 # Number of integer alu accesses 33411507SCurtis.Dunham@arm.comsystem.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 33511507SCurtis.Dunham@arm.comsystem.cpu1.num_func_calls 637 # number of times a function call or return occured 33611507SCurtis.Dunham@arm.comsystem.cpu1.num_conditional_control_insts 33487 # number of instructions that are conditional controls 33711507SCurtis.Dunham@arm.comsystem.cpu1.num_int_insts 111041 # number of integer instructions 33811507SCurtis.Dunham@arm.comsystem.cpu1.num_fp_insts 0 # number of float instructions 33911507SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_reads 272446 # number of times the integer registers were read 34011507SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_writes 102959 # number of times the integer registers were written 34111507SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 34211507SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 34311507SCurtis.Dunham@arm.comsystem.cpu1.num_mem_refs 53722 # number of memory refs 34411507SCurtis.Dunham@arm.comsystem.cpu1.num_load_insts 41185 # Number of load instructions 34511507SCurtis.Dunham@arm.comsystem.cpu1.num_store_insts 12537 # Number of store instructions 34611507SCurtis.Dunham@arm.comsystem.cpu1.num_idle_cycles 74693.860345 # Number of idle cycles 34711507SCurtis.Dunham@arm.comsystem.cpu1.num_busy_cycles 453654.139655 # Number of busy cycles 34811507SCurtis.Dunham@arm.comsystem.cpu1.not_idle_fraction 0.858628 # Percentage of non-idle cycles 34911507SCurtis.Dunham@arm.comsystem.cpu1.idle_fraction 0.141372 # Percentage of idle cycles 35011507SCurtis.Dunham@arm.comsystem.cpu1.Branches 35142 # Number of branches fetched 35111507SCurtis.Dunham@arm.comsystem.cpu1.op_class::No_OpClass 25921 15.24% 15.24% # Class of executed instruction 35211507SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntAlu 74786 43.98% 59.23% # Class of executed instruction 35311507SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntMult 0 0.00% 59.23% # Class of executed instruction 35411507SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 59.23% # Class of executed instruction 35511507SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 59.23% # Class of executed instruction 35611507SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 59.23% # Class of executed instruction 35711507SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 59.23% # Class of executed instruction 35811507SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 59.23% # Class of executed instruction 35911507SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 59.23% # Class of executed instruction 36011507SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 59.23% # Class of executed instruction 36111507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 59.23% # Class of executed instruction 36211507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 59.23% # Class of executed instruction 36311507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 59.23% # Class of executed instruction 36411507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 59.23% # Class of executed instruction 36511507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 59.23% # Class of executed instruction 36611507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 59.23% # Class of executed instruction 36711507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 59.23% # Class of executed instruction 36811507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 59.23% # Class of executed instruction 36911507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 59.23% # Class of executed instruction 37011507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 59.23% # Class of executed instruction 37111507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 59.23% # Class of executed instruction 37211507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 59.23% # Class of executed instruction 37311507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 59.23% # Class of executed instruction 37411507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 59.23% # Class of executed instruction 37511507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 59.23% # Class of executed instruction 37611507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 59.23% # Class of executed instruction 37711507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMisc 0 0.00% 59.23% # Class of executed instruction 37811507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 59.23% # Class of executed instruction 37911507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.23% # Class of executed instruction 38011507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.23% # Class of executed instruction 38111507SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemRead 56788 33.40% 92.63% # Class of executed instruction 38211507SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemWrite 12537 7.37% 100.00% # Class of executed instruction 38311507SCurtis.Dunham@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 38411507SCurtis.Dunham@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 38511507SCurtis.Dunham@arm.comsystem.cpu1.op_class::total 170032 # Class of executed instruction 38611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.replacements 0 # number of replacements 38711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tagsinuse 26.444551 # Cycle average of tags in use 38811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.total_refs 27473 # Total number of references to valid blocks. 38911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 39011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.avg_refs 915.766667 # Average number of references to valid blocks. 39111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 26.444551 # Average occupied blocks per requestor 39311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.051650 # Average percentage of cache occupancy 39411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.051650 # Average percentage of cache occupancy 39511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 39611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 39711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 39811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 39911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tag_accesses 215113 # Number of tag accesses 40011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.data_accesses 215113 # Number of data accesses 40111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 41008 # number of ReadReq hits 40211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::total 41008 # number of ReadReq hits 40311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 12359 # number of WriteReq hits 40411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::total 12359 # number of WriteReq hits 40511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits 40611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits 40711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 53367 # number of demand (read+write) hits 40811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::total 53367 # number of demand (read+write) hits 40911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 53367 # number of overall hits 41011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::total 53367 # number of overall hits 41111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 169 # number of ReadReq misses 41211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::total 169 # number of ReadReq misses 41311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses 41411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses 41511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses 41611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses 41711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 274 # number of demand (read+write) misses 41811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::total 274 # number of demand (read+write) misses 41911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 274 # number of overall misses 42011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::total 274 # number of overall misses 42111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1910000 # number of ReadReq miss cycles 42211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 1910000 # number of ReadReq miss cycles 42311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1724000 # number of WriteReq miss cycles 42411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 1724000 # number of WriteReq miss cycles 42511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_miss_latency::cpu1.data 260500 # number of SwapReq miss cycles 42611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_miss_latency::total 260500 # number of SwapReq miss cycles 42711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 3634000 # number of demand (read+write) miss cycles 42811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::total 3634000 # number of demand (read+write) miss cycles 42911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 3634000 # number of overall miss cycles 43011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::total 3634000 # number of overall miss cycles 43111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 41177 # number of ReadReq accesses(hits+misses) 43211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 41177 # number of ReadReq accesses(hits+misses) 43311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 12464 # number of WriteReq accesses(hits+misses) 43411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 12464 # number of WriteReq accesses(hits+misses) 43511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 43611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 43711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 53641 # number of demand (read+write) accesses 43811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::total 53641 # number of demand (read+write) accesses 43911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 53641 # number of overall (read+write) accesses 44011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::total 53641 # number of overall (read+write) accesses 44111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004104 # miss rate for ReadReq accesses 44211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.004104 # miss rate for ReadReq accesses 44311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008424 # miss rate for WriteReq accesses 44411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.008424 # miss rate for WriteReq accesses 44511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.816901 # miss rate for SwapReq accesses 44611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses 44711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.005108 # miss rate for demand accesses 44811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.005108 # miss rate for demand accesses 44911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.005108 # miss rate for overall accesses 45011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.005108 # miss rate for overall accesses 45111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11301.775148 # average ReadReq miss latency 45211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 11301.775148 # average ReadReq miss latency 45311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16419.047619 # average WriteReq miss latency 45411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 16419.047619 # average WriteReq miss latency 45511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4491.379310 # average SwapReq miss latency 45611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_avg_miss_latency::total 4491.379310 # average SwapReq miss latency 45711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13262.773723 # average overall miss latency 45811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 13262.773723 # average overall miss latency 45911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13262.773723 # average overall miss latency 46011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 13262.773723 # average overall miss latency 46111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 46211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 46311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 46411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 46511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 46611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 46711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 169 # number of ReadReq MSHR misses 46811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses 46911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses 47011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 47111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses 47211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses 47311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 274 # number of demand (read+write) MSHR misses 47411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses 47511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 274 # number of overall MSHR misses 47611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses 47711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1741000 # number of ReadReq MSHR miss cycles 47811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 1741000 # number of ReadReq MSHR miss cycles 47911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1619000 # number of WriteReq MSHR miss cycles 48011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 1619000 # number of WriteReq MSHR miss cycles 48111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 202500 # number of SwapReq MSHR miss cycles 48211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_mshr_miss_latency::total 202500 # number of SwapReq MSHR miss cycles 48311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3360000 # number of demand (read+write) MSHR miss cycles 48411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 3360000 # number of demand (read+write) MSHR miss cycles 48511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3360000 # number of overall MSHR miss cycles 48611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 3360000 # number of overall MSHR miss cycles 48711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004104 # mshr miss rate for ReadReq accesses 48811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004104 # mshr miss rate for ReadReq accesses 48911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008424 # mshr miss rate for WriteReq accesses 49011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008424 # mshr miss rate for WriteReq accesses 49111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.816901 # mshr miss rate for SwapReq accesses 49211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses 49311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005108 # mshr miss rate for demand accesses 49411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.005108 # mshr miss rate for demand accesses 49511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005108 # mshr miss rate for overall accesses 49611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.005108 # mshr miss rate for overall accesses 49711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10301.775148 # average ReadReq mshr miss latency 49811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10301.775148 # average ReadReq mshr miss latency 49911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15419.047619 # average WriteReq mshr miss latency 50011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15419.047619 # average WriteReq mshr miss latency 50111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3491.379310 # average SwapReq mshr miss latency 50211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3491.379310 # average SwapReq mshr miss latency 50311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency 50411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency 50511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency 50611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency 50711507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.replacements 280 # number of replacements 50811507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tagsinuse 66.843295 # Cycle average of tags in use 50911507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.total_refs 169667 # Total number of references to valid blocks. 51011507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 51111507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 463.571038 # Average number of references to valid blocks. 51211507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 51311507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 66.843295 # Average occupied blocks per requestor 51411507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.130553 # Average percentage of cache occupancy 51511507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.130553 # Average percentage of cache occupancy 51611507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 51711507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 51811507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 51911507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 52011507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 52111507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 170399 # Number of tag accesses 52211507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 170399 # Number of data accesses 52311507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 169667 # number of ReadReq hits 52411507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::total 169667 # number of ReadReq hits 52511507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 169667 # number of demand (read+write) hits 52611507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 169667 # number of demand (read+write) hits 52711507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 169667 # number of overall hits 52811507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::total 169667 # number of overall hits 52911507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 53011507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 53111507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 53211507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 53311507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 53411507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 366 # number of overall misses 53511507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5695000 # number of ReadReq miss cycles 53611507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 5695000 # number of ReadReq miss cycles 53711507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 5695000 # number of demand (read+write) miss cycles 53811507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::total 5695000 # number of demand (read+write) miss cycles 53911507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 5695000 # number of overall miss cycles 54011507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::total 5695000 # number of overall miss cycles 54111507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 170033 # number of ReadReq accesses(hits+misses) 54211507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::total 170033 # number of ReadReq accesses(hits+misses) 54311507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 170033 # number of demand (read+write) accesses 54411507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 170033 # number of demand (read+write) accesses 54511507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 170033 # number of overall (read+write) accesses 54611507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 170033 # number of overall (read+write) accesses 54711507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002153 # miss rate for ReadReq accesses 54811507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses 54911507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.002153 # miss rate for demand accesses 55011507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses 55111507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.002153 # miss rate for overall accesses 55211507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.002153 # miss rate for overall accesses 55311507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15560.109290 # average ReadReq miss latency 55411507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 15560.109290 # average ReadReq miss latency 55511507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15560.109290 # average overall miss latency 55611507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 15560.109290 # average overall miss latency 55711507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15560.109290 # average overall miss latency 55811507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 15560.109290 # average overall miss latency 55911507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 56011507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 56111507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 56211507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 56311507SCurtis.Dunham@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 56411507SCurtis.Dunham@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 56511507SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::writebacks 280 # number of writebacks 56611507SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::total 280 # number of writebacks 56711507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 56811507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 56911507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 57011507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 57111507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 57211507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 57311507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5329000 # number of ReadReq MSHR miss cycles 57411507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 5329000 # number of ReadReq MSHR miss cycles 57511507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5329000 # number of demand (read+write) MSHR miss cycles 57611507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 5329000 # number of demand (read+write) MSHR miss cycles 57711507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5329000 # number of overall MSHR miss cycles 57811507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 5329000 # number of overall MSHR miss cycles 57911507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002153 # mshr miss rate for ReadReq accesses 58011507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses 58111507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002153 # mshr miss rate for demand accesses 58211507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses 58311507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002153 # mshr miss rate for overall accesses 58411507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses 58511507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average ReadReq mshr miss latency 58611507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14560.109290 # average ReadReq mshr miss latency 58711507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average overall mshr miss latency 58811507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency 58911507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average overall mshr miss latency 59011507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency 59111507SCurtis.Dunham@arm.comsystem.cpu2.numCycles 528349 # number of cpu cycles simulated 59211507SCurtis.Dunham@arm.comsystem.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 59311507SCurtis.Dunham@arm.comsystem.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 59411507SCurtis.Dunham@arm.comsystem.cpu2.committedInsts 165687 # Number of instructions committed 59511507SCurtis.Dunham@arm.comsystem.cpu2.committedOps 165687 # Number of ops (including micro ops) committed 59611507SCurtis.Dunham@arm.comsystem.cpu2.num_int_alu_accesses 110528 # Number of integer alu accesses 59711507SCurtis.Dunham@arm.comsystem.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 59811507SCurtis.Dunham@arm.comsystem.cpu2.num_func_calls 637 # number of times a function call or return occured 59911507SCurtis.Dunham@arm.comsystem.cpu2.num_conditional_control_insts 31586 # number of instructions that are conditional controls 60011507SCurtis.Dunham@arm.comsystem.cpu2.num_int_insts 110528 # number of integer instructions 60111507SCurtis.Dunham@arm.comsystem.cpu2.num_fp_insts 0 # number of float instructions 60211507SCurtis.Dunham@arm.comsystem.cpu2.num_int_register_reads 278004 # number of times the integer registers were read 60311507SCurtis.Dunham@arm.comsystem.cpu2.num_int_register_writes 105995 # number of times the integer registers were written 60411507SCurtis.Dunham@arm.comsystem.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 60511507SCurtis.Dunham@arm.comsystem.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 60611507SCurtis.Dunham@arm.comsystem.cpu2.num_mem_refs 55111 # number of memory refs 60711507SCurtis.Dunham@arm.comsystem.cpu2.num_load_insts 40928 # Number of load instructions 60811507SCurtis.Dunham@arm.comsystem.cpu2.num_store_insts 14183 # Number of store instructions 60911507SCurtis.Dunham@arm.comsystem.cpu2.num_idle_cycles 74966.001716 # Number of idle cycles 61011507SCurtis.Dunham@arm.comsystem.cpu2.num_busy_cycles 453382.998284 # Number of busy cycles 61111507SCurtis.Dunham@arm.comsystem.cpu2.not_idle_fraction 0.858113 # Percentage of non-idle cycles 61211507SCurtis.Dunham@arm.comsystem.cpu2.idle_fraction 0.141887 # Percentage of idle cycles 61311507SCurtis.Dunham@arm.comsystem.cpu2.Branches 33243 # Number of branches fetched 61411507SCurtis.Dunham@arm.comsystem.cpu2.op_class::No_OpClass 24020 14.49% 14.49% # Class of executed instruction 61511507SCurtis.Dunham@arm.comsystem.cpu2.op_class::IntAlu 74533 44.98% 59.47% # Class of executed instruction 61611507SCurtis.Dunham@arm.comsystem.cpu2.op_class::IntMult 0 0.00% 59.47% # Class of executed instruction 61711507SCurtis.Dunham@arm.comsystem.cpu2.op_class::IntDiv 0 0.00% 59.47% # Class of executed instruction 61811507SCurtis.Dunham@arm.comsystem.cpu2.op_class::FloatAdd 0 0.00% 59.47% # Class of executed instruction 61911507SCurtis.Dunham@arm.comsystem.cpu2.op_class::FloatCmp 0 0.00% 59.47% # Class of executed instruction 62011507SCurtis.Dunham@arm.comsystem.cpu2.op_class::FloatCvt 0 0.00% 59.47% # Class of executed instruction 62111507SCurtis.Dunham@arm.comsystem.cpu2.op_class::FloatMult 0 0.00% 59.47% # Class of executed instruction 62211507SCurtis.Dunham@arm.comsystem.cpu2.op_class::FloatDiv 0 0.00% 59.47% # Class of executed instruction 62311507SCurtis.Dunham@arm.comsystem.cpu2.op_class::FloatSqrt 0 0.00% 59.47% # Class of executed instruction 62411507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdAdd 0 0.00% 59.47% # Class of executed instruction 62511507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdAddAcc 0 0.00% 59.47% # Class of executed instruction 62611507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdAlu 0 0.00% 59.47% # Class of executed instruction 62711507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdCmp 0 0.00% 59.47% # Class of executed instruction 62811507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdCvt 0 0.00% 59.47% # Class of executed instruction 62911507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdMisc 0 0.00% 59.47% # Class of executed instruction 63011507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdMult 0 0.00% 59.47% # Class of executed instruction 63111507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdMultAcc 0 0.00% 59.47% # Class of executed instruction 63211507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdShift 0 0.00% 59.47% # Class of executed instruction 63311507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdShiftAcc 0 0.00% 59.47% # Class of executed instruction 63411507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdSqrt 0 0.00% 59.47% # Class of executed instruction 63511507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatAdd 0 0.00% 59.47% # Class of executed instruction 63611507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatAlu 0 0.00% 59.47% # Class of executed instruction 63711507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatCmp 0 0.00% 59.47% # Class of executed instruction 63811507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatCvt 0 0.00% 59.47% # Class of executed instruction 63911507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatDiv 0 0.00% 59.47% # Class of executed instruction 64011507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatMisc 0 0.00% 59.47% # Class of executed instruction 64111507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatMult 0 0.00% 59.47% # Class of executed instruction 64211507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.47% # Class of executed instruction 64311507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.47% # Class of executed instruction 64411507SCurtis.Dunham@arm.comsystem.cpu2.op_class::MemRead 52983 31.97% 91.44% # Class of executed instruction 64511507SCurtis.Dunham@arm.comsystem.cpu2.op_class::MemWrite 14183 8.56% 100.00% # Class of executed instruction 64611507SCurtis.Dunham@arm.comsystem.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 64711507SCurtis.Dunham@arm.comsystem.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 64811507SCurtis.Dunham@arm.comsystem.cpu2.op_class::total 165719 # Class of executed instruction 64911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.replacements 0 # number of replacements 65011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.tagsinuse 27.447331 # Cycle average of tags in use 65111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.total_refs 30642 # Total number of references to valid blocks. 65211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 65311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.avg_refs 1056.620690 # Average number of references to valid blocks. 65411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 65511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_blocks::cpu2.data 27.447331 # Average occupied blocks per requestor 65611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_percent::cpu2.data 0.053608 # Average percentage of cache occupancy 65711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_percent::total 0.053608 # Average percentage of cache occupancy 65811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 65911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 66011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 66111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 66211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.tag_accesses 220669 # Number of tag accesses 66311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.data_accesses 220669 # Number of data accesses 66411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_hits::cpu2.data 40751 # number of ReadReq hits 66511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_hits::total 40751 # number of ReadReq hits 66611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_hits::cpu2.data 14004 # number of WriteReq hits 66711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_hits::total 14004 # number of WriteReq hits 66811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits 66911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits 67011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_hits::cpu2.data 54755 # number of demand (read+write) hits 67111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_hits::total 54755 # number of demand (read+write) hits 67211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_hits::cpu2.data 54755 # number of overall hits 67311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_hits::total 54755 # number of overall hits 67411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_misses::cpu2.data 169 # number of ReadReq misses 67511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_misses::total 169 # number of ReadReq misses 67611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses 67711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses 67811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_misses::cpu2.data 60 # number of SwapReq misses 67911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_misses::total 60 # number of SwapReq misses 68011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_misses::cpu2.data 274 # number of demand (read+write) misses 68111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_misses::total 274 # number of demand (read+write) misses 68211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_misses::cpu2.data 274 # number of overall misses 68311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_misses::total 274 # number of overall misses 68411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2144500 # number of ReadReq miss cycles 68511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_miss_latency::total 2144500 # number of ReadReq miss cycles 68611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1802500 # number of WriteReq miss cycles 68711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_miss_latency::total 1802500 # number of WriteReq miss cycles 68811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_miss_latency::cpu2.data 267500 # number of SwapReq miss cycles 68911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_miss_latency::total 267500 # number of SwapReq miss cycles 69011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_miss_latency::cpu2.data 3947000 # number of demand (read+write) miss cycles 69111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_miss_latency::total 3947000 # number of demand (read+write) miss cycles 69211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_miss_latency::cpu2.data 3947000 # number of overall miss cycles 69311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_miss_latency::total 3947000 # number of overall miss cycles 69411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_accesses::cpu2.data 40920 # number of ReadReq accesses(hits+misses) 69511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_accesses::total 40920 # number of ReadReq accesses(hits+misses) 69611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_accesses::cpu2.data 14109 # number of WriteReq accesses(hits+misses) 69711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_accesses::total 14109 # number of WriteReq accesses(hits+misses) 69811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_accesses::cpu2.data 72 # number of SwapReq accesses(hits+misses) 69911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) 70011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_accesses::cpu2.data 55029 # number of demand (read+write) accesses 70111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_accesses::total 55029 # number of demand (read+write) accesses 70211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_accesses::cpu2.data 55029 # number of overall (read+write) accesses 70311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_accesses::total 55029 # number of overall (read+write) accesses 70411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004130 # miss rate for ReadReq accesses 70511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_miss_rate::total 0.004130 # miss rate for ReadReq accesses 70611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007442 # miss rate for WriteReq accesses 70711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_miss_rate::total 0.007442 # miss rate for WriteReq accesses 70811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses 70911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses 71011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_miss_rate::cpu2.data 0.004979 # miss rate for demand accesses 71111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_miss_rate::total 0.004979 # miss rate for demand accesses 71211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_miss_rate::cpu2.data 0.004979 # miss rate for overall accesses 71311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_miss_rate::total 0.004979 # miss rate for overall accesses 71411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12689.349112 # average ReadReq miss latency 71511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_avg_miss_latency::total 12689.349112 # average ReadReq miss latency 71611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17166.666667 # average WriteReq miss latency 71711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_avg_miss_latency::total 17166.666667 # average WriteReq miss latency 71811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4458.333333 # average SwapReq miss latency 71911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_avg_miss_latency::total 4458.333333 # average SwapReq miss latency 72011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14405.109489 # average overall miss latency 72111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_avg_miss_latency::total 14405.109489 # average overall miss latency 72211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14405.109489 # average overall miss latency 72311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_avg_miss_latency::total 14405.109489 # average overall miss latency 72411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 72511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 72611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 72711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 72811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 72911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 73011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 169 # number of ReadReq MSHR misses 73111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses 73211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses 73311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 73411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 60 # number of SwapReq MSHR misses 73511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses 73611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_mshr_misses::cpu2.data 274 # number of demand (read+write) MSHR misses 73711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses 73811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_mshr_misses::cpu2.data 274 # number of overall MSHR misses 73911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses 74011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1975500 # number of ReadReq MSHR miss cycles 74111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_mshr_miss_latency::total 1975500 # number of ReadReq MSHR miss cycles 74211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1697500 # number of WriteReq MSHR miss cycles 74311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_miss_latency::total 1697500 # number of WriteReq MSHR miss cycles 74411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 207500 # number of SwapReq MSHR miss cycles 74511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_mshr_miss_latency::total 207500 # number of SwapReq MSHR miss cycles 74611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3673000 # number of demand (read+write) MSHR miss cycles 74711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_mshr_miss_latency::total 3673000 # number of demand (read+write) MSHR miss cycles 74811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3673000 # number of overall MSHR miss cycles 74911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_mshr_miss_latency::total 3673000 # number of overall MSHR miss cycles 75011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004130 # mshr miss rate for ReadReq accesses 75111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004130 # mshr miss rate for ReadReq accesses 75211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007442 # mshr miss rate for WriteReq accesses 75311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007442 # mshr miss rate for WriteReq accesses 75411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses 75511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses 75611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004979 # mshr miss rate for demand accesses 75711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_mshr_miss_rate::total 0.004979 # mshr miss rate for demand accesses 75811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004979 # mshr miss rate for overall accesses 75911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_mshr_miss_rate::total 0.004979 # mshr miss rate for overall accesses 76011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11689.349112 # average ReadReq mshr miss latency 76111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11689.349112 # average ReadReq mshr miss latency 76211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16166.666667 # average WriteReq mshr miss latency 76311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16166.666667 # average WriteReq mshr miss latency 76411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3458.333333 # average SwapReq mshr miss latency 76511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3458.333333 # average SwapReq mshr miss latency 76611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13405.109489 # average overall mshr miss latency 76711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency 76811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13405.109489 # average overall mshr miss latency 76911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency 77011507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.replacements 280 # number of replacements 77111507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.tagsinuse 69.258301 # Cycle average of tags in use 77211507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.total_refs 165354 # Total number of references to valid blocks. 77311507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 77411507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.avg_refs 451.786885 # Average number of references to valid blocks. 77511507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 77611507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_blocks::cpu2.inst 69.258301 # Average occupied blocks per requestor 77711507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_percent::cpu2.inst 0.135270 # Average percentage of cache occupancy 77811507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_percent::total 0.135270 # Average percentage of cache occupancy 77911507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 78011507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 78111507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 78211507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 78311507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 78411507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.tag_accesses 166086 # Number of tag accesses 78511507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.data_accesses 166086 # Number of data accesses 78611507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_hits::cpu2.inst 165354 # number of ReadReq hits 78711507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_hits::total 165354 # number of ReadReq hits 78811507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_hits::cpu2.inst 165354 # number of demand (read+write) hits 78911507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_hits::total 165354 # number of demand (read+write) hits 79011507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_hits::cpu2.inst 165354 # number of overall hits 79111507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_hits::total 165354 # number of overall hits 79211507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 79311507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 79411507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 79511507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 79611507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 79711507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_misses::total 366 # number of overall misses 79811507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8165500 # number of ReadReq miss cycles 79911507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_miss_latency::total 8165500 # number of ReadReq miss cycles 80011507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_miss_latency::cpu2.inst 8165500 # number of demand (read+write) miss cycles 80111507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_miss_latency::total 8165500 # number of demand (read+write) miss cycles 80211507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_miss_latency::cpu2.inst 8165500 # number of overall miss cycles 80311507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_miss_latency::total 8165500 # number of overall miss cycles 80411507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_accesses::cpu2.inst 165720 # number of ReadReq accesses(hits+misses) 80511507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_accesses::total 165720 # number of ReadReq accesses(hits+misses) 80611507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_accesses::cpu2.inst 165720 # number of demand (read+write) accesses 80711507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_accesses::total 165720 # number of demand (read+write) accesses 80811507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_accesses::cpu2.inst 165720 # number of overall (read+write) accesses 80911507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_accesses::total 165720 # number of overall (read+write) accesses 81011507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002209 # miss rate for ReadReq accesses 81111507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_miss_rate::total 0.002209 # miss rate for ReadReq accesses 81211507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_miss_rate::cpu2.inst 0.002209 # miss rate for demand accesses 81311507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_miss_rate::total 0.002209 # miss rate for demand accesses 81411507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_miss_rate::cpu2.inst 0.002209 # miss rate for overall accesses 81511507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_miss_rate::total 0.002209 # miss rate for overall accesses 81611507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22310.109290 # average ReadReq miss latency 81711507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_avg_miss_latency::total 22310.109290 # average ReadReq miss latency 81811507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22310.109290 # average overall miss latency 81911507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_avg_miss_latency::total 22310.109290 # average overall miss latency 82011507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22310.109290 # average overall miss latency 82111507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_avg_miss_latency::total 22310.109290 # average overall miss latency 82211507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 82311507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 82411507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 82511507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 82611507SCurtis.Dunham@arm.comsystem.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 82711507SCurtis.Dunham@arm.comsystem.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 82811507SCurtis.Dunham@arm.comsystem.cpu2.icache.writebacks::writebacks 280 # number of writebacks 82911507SCurtis.Dunham@arm.comsystem.cpu2.icache.writebacks::total 280 # number of writebacks 83011507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 83111507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 83211507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 83311507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 83411507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 83511507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 83611507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7799500 # number of ReadReq MSHR miss cycles 83711507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_miss_latency::total 7799500 # number of ReadReq MSHR miss cycles 83811507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7799500 # number of demand (read+write) MSHR miss cycles 83911507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_miss_latency::total 7799500 # number of demand (read+write) MSHR miss cycles 84011507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7799500 # number of overall MSHR miss cycles 84111507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_miss_latency::total 7799500 # number of overall MSHR miss cycles 84211507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002209 # mshr miss rate for ReadReq accesses 84311507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002209 # mshr miss rate for ReadReq accesses 84411507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002209 # mshr miss rate for demand accesses 84511507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses 84611507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002209 # mshr miss rate for overall accesses 84711507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses 84811507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average ReadReq mshr miss latency 84911507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21310.109290 # average ReadReq mshr miss latency 85011507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average overall mshr miss latency 85111507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency 85211507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average overall mshr miss latency 85311507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency 85411507SCurtis.Dunham@arm.comsystem.cpu3.numCycles 528348 # number of cpu cycles simulated 85511507SCurtis.Dunham@arm.comsystem.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 85611507SCurtis.Dunham@arm.comsystem.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 85711507SCurtis.Dunham@arm.comsystem.cpu3.committedInsts 169439 # Number of instructions committed 85811507SCurtis.Dunham@arm.comsystem.cpu3.committedOps 169439 # Number of ops (including micro ops) committed 85911507SCurtis.Dunham@arm.comsystem.cpu3.num_int_alu_accesses 111342 # Number of integer alu accesses 86011507SCurtis.Dunham@arm.comsystem.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 86111507SCurtis.Dunham@arm.comsystem.cpu3.num_func_calls 637 # number of times a function call or return occured 86211507SCurtis.Dunham@arm.comsystem.cpu3.num_conditional_control_insts 33059 # number of instructions that are conditional controls 86311507SCurtis.Dunham@arm.comsystem.cpu3.num_int_insts 111342 # number of integer instructions 86411507SCurtis.Dunham@arm.comsystem.cpu3.num_fp_insts 0 # number of float instructions 86511507SCurtis.Dunham@arm.comsystem.cpu3.num_int_register_reads 275359 # number of times the integer registers were read 86611507SCurtis.Dunham@arm.comsystem.cpu3.num_int_register_writes 104262 # number of times the integer registers were written 86711507SCurtis.Dunham@arm.comsystem.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 86811507SCurtis.Dunham@arm.comsystem.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 86911507SCurtis.Dunham@arm.comsystem.cpu3.num_mem_refs 54451 # number of memory refs 87011507SCurtis.Dunham@arm.comsystem.cpu3.num_load_insts 41338 # Number of load instructions 87111507SCurtis.Dunham@arm.comsystem.cpu3.num_store_insts 13113 # Number of store instructions 87211507SCurtis.Dunham@arm.comsystem.cpu3.num_idle_cycles 75238.859311 # Number of idle cycles 87311507SCurtis.Dunham@arm.comsystem.cpu3.num_busy_cycles 453109.140689 # Number of busy cycles 87411507SCurtis.Dunham@arm.comsystem.cpu3.not_idle_fraction 0.857596 # Percentage of non-idle cycles 87511507SCurtis.Dunham@arm.comsystem.cpu3.idle_fraction 0.142404 # Percentage of idle cycles 87611507SCurtis.Dunham@arm.comsystem.cpu3.Branches 34709 # Number of branches fetched 87711507SCurtis.Dunham@arm.comsystem.cpu3.op_class::No_OpClass 25492 15.04% 15.04% # Class of executed instruction 87811507SCurtis.Dunham@arm.comsystem.cpu3.op_class::IntAlu 74930 44.21% 59.26% # Class of executed instruction 87911507SCurtis.Dunham@arm.comsystem.cpu3.op_class::IntMult 0 0.00% 59.26% # Class of executed instruction 88011507SCurtis.Dunham@arm.comsystem.cpu3.op_class::IntDiv 0 0.00% 59.26% # Class of executed instruction 88111507SCurtis.Dunham@arm.comsystem.cpu3.op_class::FloatAdd 0 0.00% 59.26% # Class of executed instruction 88211507SCurtis.Dunham@arm.comsystem.cpu3.op_class::FloatCmp 0 0.00% 59.26% # Class of executed instruction 88311507SCurtis.Dunham@arm.comsystem.cpu3.op_class::FloatCvt 0 0.00% 59.26% # Class of executed instruction 88411507SCurtis.Dunham@arm.comsystem.cpu3.op_class::FloatMult 0 0.00% 59.26% # Class of executed instruction 88511507SCurtis.Dunham@arm.comsystem.cpu3.op_class::FloatDiv 0 0.00% 59.26% # Class of executed instruction 88611507SCurtis.Dunham@arm.comsystem.cpu3.op_class::FloatSqrt 0 0.00% 59.26% # Class of executed instruction 88711507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdAdd 0 0.00% 59.26% # Class of executed instruction 88811507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdAddAcc 0 0.00% 59.26% # Class of executed instruction 88911507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdAlu 0 0.00% 59.26% # Class of executed instruction 89011507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdCmp 0 0.00% 59.26% # Class of executed instruction 89111507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdCvt 0 0.00% 59.26% # Class of executed instruction 89211507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdMisc 0 0.00% 59.26% # Class of executed instruction 89311507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdMult 0 0.00% 59.26% # Class of executed instruction 89411507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdMultAcc 0 0.00% 59.26% # Class of executed instruction 89511507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdShift 0 0.00% 59.26% # Class of executed instruction 89611507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdShiftAcc 0 0.00% 59.26% # Class of executed instruction 89711507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdSqrt 0 0.00% 59.26% # Class of executed instruction 89811507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatAdd 0 0.00% 59.26% # Class of executed instruction 89911507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatAlu 0 0.00% 59.26% # Class of executed instruction 90011507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatCmp 0 0.00% 59.26% # Class of executed instruction 90111507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatCvt 0 0.00% 59.26% # Class of executed instruction 90211507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatDiv 0 0.00% 59.26% # Class of executed instruction 90311507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatMisc 0 0.00% 59.26% # Class of executed instruction 90411507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatMult 0 0.00% 59.26% # Class of executed instruction 90511507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.26% # Class of executed instruction 90611507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.26% # Class of executed instruction 90711507SCurtis.Dunham@arm.comsystem.cpu3.op_class::MemRead 55936 33.01% 92.26% # Class of executed instruction 90811507SCurtis.Dunham@arm.comsystem.cpu3.op_class::MemWrite 13113 7.74% 100.00% # Class of executed instruction 90911507SCurtis.Dunham@arm.comsystem.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 91011507SCurtis.Dunham@arm.comsystem.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 91111507SCurtis.Dunham@arm.comsystem.cpu3.op_class::total 169471 # Class of executed instruction 91211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.replacements 0 # number of replacements 91311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.tagsinuse 25.601960 # Cycle average of tags in use 91411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.total_refs 28504 # Total number of references to valid blocks. 91511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 91611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.avg_refs 982.896552 # Average number of references to valid blocks. 91711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 91811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.occ_blocks::cpu3.data 25.601960 # Average occupied blocks per requestor 91911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.occ_percent::cpu3.data 0.050004 # Average percentage of cache occupancy 92011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.occ_percent::total 0.050004 # Average percentage of cache occupancy 92111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 92211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 92311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 92411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 92511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.tag_accesses 218004 # Number of tag accesses 92611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.data_accesses 218004 # Number of data accesses 92711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_hits::cpu3.data 41179 # number of ReadReq hits 92811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_hits::total 41179 # number of ReadReq hits 92911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_hits::cpu3.data 12939 # number of WriteReq hits 93011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_hits::total 12939 # number of WriteReq hits 93111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 93211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 93311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_hits::cpu3.data 54118 # number of demand (read+write) hits 93411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_hits::total 54118 # number of demand (read+write) hits 93511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_hits::cpu3.data 54118 # number of overall hits 93611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_hits::total 54118 # number of overall hits 93711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses 93811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses 93911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses 94011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses 94111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses 94211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses 94311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_misses::cpu3.data 256 # number of demand (read+write) misses 94411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_misses::total 256 # number of demand (read+write) misses 94511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_misses::cpu3.data 256 # number of overall misses 94611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_misses::total 256 # number of overall misses 94711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1675000 # number of ReadReq miss cycles 94811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_miss_latency::total 1675000 # number of ReadReq miss cycles 94911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1736000 # number of WriteReq miss cycles 95011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_miss_latency::total 1736000 # number of WriteReq miss cycles 95111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_miss_latency::cpu3.data 234000 # number of SwapReq miss cycles 95211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_miss_latency::total 234000 # number of SwapReq miss cycles 95311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_miss_latency::cpu3.data 3411000 # number of demand (read+write) miss cycles 95411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_miss_latency::total 3411000 # number of demand (read+write) miss cycles 95511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_miss_latency::cpu3.data 3411000 # number of overall miss cycles 95611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_miss_latency::total 3411000 # number of overall miss cycles 95711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_accesses::cpu3.data 41330 # number of ReadReq accesses(hits+misses) 95811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_accesses::total 41330 # number of ReadReq accesses(hits+misses) 95911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_accesses::cpu3.data 13044 # number of WriteReq accesses(hits+misses) 96011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_accesses::total 13044 # number of WriteReq accesses(hits+misses) 96111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) 96211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) 96311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_accesses::cpu3.data 54374 # number of demand (read+write) accesses 96411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_accesses::total 54374 # number of demand (read+write) accesses 96511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_accesses::cpu3.data 54374 # number of overall (read+write) accesses 96611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_accesses::total 54374 # number of overall (read+write) accesses 96711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003654 # miss rate for ReadReq accesses 96811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_miss_rate::total 0.003654 # miss rate for ReadReq accesses 96911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008050 # miss rate for WriteReq accesses 97011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_miss_rate::total 0.008050 # miss rate for WriteReq accesses 97111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.776119 # miss rate for SwapReq accesses 97211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_miss_rate::total 0.776119 # miss rate for SwapReq accesses 97311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_miss_rate::cpu3.data 0.004708 # miss rate for demand accesses 97411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_miss_rate::total 0.004708 # miss rate for demand accesses 97511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_miss_rate::cpu3.data 0.004708 # miss rate for overall accesses 97611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_miss_rate::total 0.004708 # miss rate for overall accesses 97711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 11092.715232 # average ReadReq miss latency 97811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_avg_miss_latency::total 11092.715232 # average ReadReq miss latency 97911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16533.333333 # average WriteReq miss latency 98011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_avg_miss_latency::total 16533.333333 # average WriteReq miss latency 98111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4500 # average SwapReq miss latency 98211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_avg_miss_latency::total 4500 # average SwapReq miss latency 98311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13324.218750 # average overall miss latency 98411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_avg_miss_latency::total 13324.218750 # average overall miss latency 98511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13324.218750 # average overall miss latency 98611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_avg_miss_latency::total 13324.218750 # average overall miss latency 98711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 98811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 98911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 99011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 99111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 99211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 99311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 151 # number of ReadReq MSHR misses 99411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses 99511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses 99611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 99711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses 99811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses 99911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_mshr_misses::cpu3.data 256 # number of demand (read+write) MSHR misses 100011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses 100111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_mshr_misses::cpu3.data 256 # number of overall MSHR misses 100211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_mshr_misses::total 256 # number of overall MSHR misses 100311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1524000 # number of ReadReq MSHR miss cycles 100411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_mshr_miss_latency::total 1524000 # number of ReadReq MSHR miss cycles 100511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1631000 # number of WriteReq MSHR miss cycles 100611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_miss_latency::total 1631000 # number of WriteReq MSHR miss cycles 100711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 182000 # number of SwapReq MSHR miss cycles 100811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_mshr_miss_latency::total 182000 # number of SwapReq MSHR miss cycles 100911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3155000 # number of demand (read+write) MSHR miss cycles 101011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_mshr_miss_latency::total 3155000 # number of demand (read+write) MSHR miss cycles 101111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3155000 # number of overall MSHR miss cycles 101211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_mshr_miss_latency::total 3155000 # number of overall MSHR miss cycles 101311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003654 # mshr miss rate for ReadReq accesses 101411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003654 # mshr miss rate for ReadReq accesses 101511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008050 # mshr miss rate for WriteReq accesses 101611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008050 # mshr miss rate for WriteReq accesses 101711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.776119 # mshr miss rate for SwapReq accesses 101811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.776119 # mshr miss rate for SwapReq accesses 101911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004708 # mshr miss rate for demand accesses 102011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_mshr_miss_rate::total 0.004708 # mshr miss rate for demand accesses 102111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004708 # mshr miss rate for overall accesses 102211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_mshr_miss_rate::total 0.004708 # mshr miss rate for overall accesses 102311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10092.715232 # average ReadReq mshr miss latency 102411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10092.715232 # average ReadReq mshr miss latency 102511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15533.333333 # average WriteReq mshr miss latency 102611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15533.333333 # average WriteReq mshr miss latency 102711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3500 # average SwapReq mshr miss latency 102811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3500 # average SwapReq mshr miss latency 102911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency 103011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency 103111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency 103211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency 103311507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.replacements 281 # number of replacements 103411507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.tagsinuse 64.834449 # Cycle average of tags in use 103511507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.total_refs 169105 # Total number of references to valid blocks. 103611507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 103711507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.avg_refs 460.776567 # Average number of references to valid blocks. 103811507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 103911507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_blocks::cpu3.inst 64.834449 # Average occupied blocks per requestor 104011507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_percent::cpu3.inst 0.126630 # Average percentage of cache occupancy 104111507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_percent::total 0.126630 # Average percentage of cache occupancy 104211507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 104311507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 104411507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 104511507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 104611507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 104711507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.tag_accesses 169839 # Number of tag accesses 104811507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.data_accesses 169839 # Number of data accesses 104911507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_hits::cpu3.inst 169105 # number of ReadReq hits 105011507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_hits::total 169105 # number of ReadReq hits 105111507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_hits::cpu3.inst 169105 # number of demand (read+write) hits 105211507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_hits::total 169105 # number of demand (read+write) hits 105311507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_hits::cpu3.inst 169105 # number of overall hits 105411507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_hits::total 169105 # number of overall hits 105511507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 105611507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 105711507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 105811507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 105911507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 106011507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_misses::total 367 # number of overall misses 106111507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5481500 # number of ReadReq miss cycles 106211507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_miss_latency::total 5481500 # number of ReadReq miss cycles 106311507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_miss_latency::cpu3.inst 5481500 # number of demand (read+write) miss cycles 106411507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_miss_latency::total 5481500 # number of demand (read+write) miss cycles 106511507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_miss_latency::cpu3.inst 5481500 # number of overall miss cycles 106611507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_miss_latency::total 5481500 # number of overall miss cycles 106711507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_accesses::cpu3.inst 169472 # number of ReadReq accesses(hits+misses) 106811507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_accesses::total 169472 # number of ReadReq accesses(hits+misses) 106911507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_accesses::cpu3.inst 169472 # number of demand (read+write) accesses 107011507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_accesses::total 169472 # number of demand (read+write) accesses 107111507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_accesses::cpu3.inst 169472 # number of overall (read+write) accesses 107211507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_accesses::total 169472 # number of overall (read+write) accesses 107311507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002166 # miss rate for ReadReq accesses 107411507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_miss_rate::total 0.002166 # miss rate for ReadReq accesses 107511507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_miss_rate::cpu3.inst 0.002166 # miss rate for demand accesses 107611507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_miss_rate::total 0.002166 # miss rate for demand accesses 107711507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_miss_rate::cpu3.inst 0.002166 # miss rate for overall accesses 107811507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_miss_rate::total 0.002166 # miss rate for overall accesses 107911507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14935.967302 # average ReadReq miss latency 108011507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_avg_miss_latency::total 14935.967302 # average ReadReq miss latency 108111507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14935.967302 # average overall miss latency 108211507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_avg_miss_latency::total 14935.967302 # average overall miss latency 108311507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14935.967302 # average overall miss latency 108411507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_avg_miss_latency::total 14935.967302 # average overall miss latency 108511507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 108611507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 108711507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 108811507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 108911507SCurtis.Dunham@arm.comsystem.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 109011507SCurtis.Dunham@arm.comsystem.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 109111507SCurtis.Dunham@arm.comsystem.cpu3.icache.writebacks::writebacks 281 # number of writebacks 109211507SCurtis.Dunham@arm.comsystem.cpu3.icache.writebacks::total 281 # number of writebacks 109311507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 109411507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 109511507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 109611507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 109711507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 109811507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 109911507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5114500 # number of ReadReq MSHR miss cycles 110011507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_miss_latency::total 5114500 # number of ReadReq MSHR miss cycles 110111507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5114500 # number of demand (read+write) MSHR miss cycles 110211507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_miss_latency::total 5114500 # number of demand (read+write) MSHR miss cycles 110311507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5114500 # number of overall MSHR miss cycles 110411507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_miss_latency::total 5114500 # number of overall MSHR miss cycles 110511507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002166 # mshr miss rate for ReadReq accesses 110611507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses 110711507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002166 # mshr miss rate for demand accesses 110811507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_miss_rate::total 0.002166 # mshr miss rate for demand accesses 110911507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002166 # mshr miss rate for overall accesses 111011507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_miss_rate::total 0.002166 # mshr miss rate for overall accesses 111111507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average ReadReq mshr miss latency 111211507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13935.967302 # average ReadReq mshr miss latency 111311507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average overall mshr miss latency 111411507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency 111511507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average overall mshr miss latency 111611507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency 111711507SCurtis.Dunham@arm.comsystem.l2c.tags.replacements 0 # number of replacements 111811507SCurtis.Dunham@arm.comsystem.l2c.tags.tagsinuse 346.893205 # Cycle average of tags in use 111911507SCurtis.Dunham@arm.comsystem.l2c.tags.total_refs 1714 # Total number of references to valid blocks. 112011507SCurtis.Dunham@arm.comsystem.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 112111507SCurtis.Dunham@arm.comsystem.l2c.tags.avg_refs 3.995338 # Average number of references to valid blocks. 112211507SCurtis.Dunham@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 112311507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::writebacks 0.880236 # Average occupied blocks per requestor 112411507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 230.548613 # Average occupied blocks per requestor 112511507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 53.975789 # Average occupied blocks per requestor 112611507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 6.154320 # Average occupied blocks per requestor 112711507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 0.833705 # Average occupied blocks per requestor 112811507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu2.inst 46.678374 # Average occupied blocks per requestor 112911507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu2.data 6.077199 # Average occupied blocks per requestor 113011507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu3.inst 0.942850 # Average occupied blocks per requestor 113111507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu3.data 0.802119 # Average occupied blocks per requestor 113211507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy 113311507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.003518 # Average percentage of cache occupancy 113411507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.000824 # Average percentage of cache occupancy 113511507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.000094 # Average percentage of cache occupancy 113611507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy 113711507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu2.inst 0.000712 # Average percentage of cache occupancy 113811507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu2.data 0.000093 # Average percentage of cache occupancy 113911507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy 114011507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy 114111507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::total 0.005293 # Average percentage of cache occupancy 114211507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id 114311507SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 114411507SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id 114511507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id 114611507SCurtis.Dunham@arm.comsystem.l2c.tags.tag_accesses 19677 # Number of tag accesses 114711507SCurtis.Dunham@arm.comsystem.l2c.tags.data_accesses 19677 # Number of data accesses 114811507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 114911507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 115011507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits 115111507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits 115211507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 115311507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 115411507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits 115511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits 115611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu2.inst 301 # number of ReadCleanReq hits 115711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu3.inst 357 # number of ReadCleanReq hits 115811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::total 1192 # number of ReadCleanReq hits 115911507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 116011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits 116111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits 116211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits 116311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits 116411507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits 116511507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 116611507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits 116711507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits 116811507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu2.inst 301 # number of demand (read+write) hits 116911507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits 117011507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits 117111507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 117211507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::total 1218 # number of demand (read+write) hits 117311507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.inst 182 # number of overall hits 117411507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.data 5 # number of overall hits 117511507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.inst 352 # number of overall hits 117611507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.data 9 # number of overall hits 117711507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu2.inst 301 # number of overall hits 117811507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu2.data 3 # number of overall hits 117911507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu3.inst 357 # number of overall hits 118011507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu3.data 9 # number of overall hits 118111507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::total 1218 # number of overall hits 118211507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses 118311507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses 118411507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses 118511507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses 118611507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses 118711507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 118811507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses 118911507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses 119011507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 119111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 119211507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses 119311507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses 119411507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu2.inst 65 # number of ReadCleanReq misses 119511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu3.inst 10 # number of ReadCleanReq misses 119611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::total 374 # number of ReadCleanReq misses 119711507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses 119811507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses 119911507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses 120011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses 120111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses 120211507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses 120311507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 120411507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses 120511507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses 120611507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu2.inst 65 # number of demand (read+write) misses 120711507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses 120811507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu3.inst 10 # number of demand (read+write) misses 120911507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses 121011507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::total 594 # number of demand (read+write) misses 121111507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.inst 285 # number of overall misses 121211507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.data 165 # number of overall misses 121311507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.inst 14 # number of overall misses 121411507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.data 16 # number of overall misses 121511507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu2.inst 65 # number of overall misses 121611507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu2.data 23 # number of overall misses 121711507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu3.inst 10 # number of overall misses 121811507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu3.data 16 # number of overall misses 121911507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::total 594 # number of overall misses 122011507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 5991000 # number of ReadExReq miss cycles 122111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 856000 # number of ReadExReq miss cycles 122211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu2.data 911000 # number of ReadExReq miss cycles 122311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu3.data 856500 # number of ReadExReq miss cycles 122411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::total 8614500 # number of ReadExReq miss cycles 122511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu0.inst 17251500 # number of ReadCleanReq miss cycles 122611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu1.inst 835000 # number of ReadCleanReq miss cycles 122711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu2.inst 3885500 # number of ReadCleanReq miss cycles 122811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu3.inst 563500 # number of ReadCleanReq miss cycles 122911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_latency::total 22535500 # number of ReadCleanReq miss cycles 123011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 3993500 # number of ReadSharedReq miss cycles 123111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 120500 # number of ReadSharedReq miss cycles 123211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu2.data 484000 # number of ReadSharedReq miss cycles 123311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu3.data 120000 # number of ReadSharedReq miss cycles 123411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 4718000 # number of ReadSharedReq miss cycles 123511507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 17251500 # number of demand (read+write) miss cycles 123611507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.data 9984500 # number of demand (read+write) miss cycles 123711507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 835000 # number of demand (read+write) miss cycles 123811507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.data 976500 # number of demand (read+write) miss cycles 123911507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu2.inst 3885500 # number of demand (read+write) miss cycles 124011507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu2.data 1395000 # number of demand (read+write) miss cycles 124111507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu3.inst 563500 # number of demand (read+write) miss cycles 124211507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu3.data 976500 # number of demand (read+write) miss cycles 124311507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::total 35868000 # number of demand (read+write) miss cycles 124411507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 17251500 # number of overall miss cycles 124511507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.data 9984500 # number of overall miss cycles 124611507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 835000 # number of overall miss cycles 124711507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.data 976500 # number of overall miss cycles 124811507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu2.inst 3885500 # number of overall miss cycles 124911507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu2.data 1395000 # number of overall miss cycles 125011507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu3.inst 563500 # number of overall miss cycles 125111507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu3.data 976500 # number of overall miss cycles 125211507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::total 35868000 # number of overall miss cycles 125311507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) 125411507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) 125511507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) 125611507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) 125711507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 125811507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) 125911507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) 126011507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) 126111507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) 126211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 126311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) 126411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses) 126511507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) 126611507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) 126711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) 126811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu1.inst 366 # number of ReadCleanReq accesses(hits+misses) 126911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu2.inst 366 # number of ReadCleanReq accesses(hits+misses) 127011507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu3.inst 367 # number of ReadCleanReq accesses(hits+misses) 127111507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::total 1566 # number of ReadCleanReq accesses(hits+misses) 127211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) 127311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 11 # number of ReadSharedReq accesses(hits+misses) 127411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu2.data 11 # number of ReadSharedReq accesses(hits+misses) 127511507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu3.data 11 # number of ReadSharedReq accesses(hits+misses) 127611507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::total 104 # number of ReadSharedReq accesses(hits+misses) 127711507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 127811507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 127911507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses 128011507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses 128111507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses 128211507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses 128311507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses 128411507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses 128511507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses 128611507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 128711507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 128811507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses 128911507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses 129011507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses 129111507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses 129211507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses 129311507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses 129411507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses 129511507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses 129611507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 129711507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 129811507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 129911507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses 130011507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 130111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 130211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 130311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 130411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 130511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadCleanReq accesses 130611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadCleanReq accesses 130711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.177596 # miss rate for ReadCleanReq accesses 130811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.027248 # miss rate for ReadCleanReq accesses 130911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::total 0.238825 # miss rate for ReadCleanReq accesses 131011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses 131111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadSharedReq accesses 131211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadSharedReq accesses 131311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadSharedReq accesses 131411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.750000 # miss rate for ReadSharedReq accesses 131511507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses 131611507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 131711507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses 131811507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses 131911507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu2.inst 0.177596 # miss rate for demand accesses 132011507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu2.data 0.884615 # miss rate for demand accesses 132111507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu3.inst 0.027248 # miss rate for demand accesses 132211507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses 132311507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::total 0.327815 # miss rate for demand accesses 132411507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses 132511507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 132611507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.038251 # miss rate for overall accesses 132711507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses 132811507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu2.inst 0.177596 # miss rate for overall accesses 132911507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu2.data 0.884615 # miss rate for overall accesses 133011507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu3.inst 0.027248 # miss rate for overall accesses 133111507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses 133211507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::total 0.327815 # miss rate for overall accesses 133311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 60515.151515 # average ReadExReq miss latency 133411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 61142.857143 # average ReadExReq miss latency 133511507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu2.data 60733.333333 # average ReadExReq miss latency 133611507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu3.data 61178.571429 # average ReadExReq miss latency 133711507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 60665.492958 # average ReadExReq miss latency 133811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 60531.578947 # average ReadCleanReq miss latency 133911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 59642.857143 # average ReadCleanReq miss latency 134011507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 59776.923077 # average ReadCleanReq miss latency 134111507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 56350 # average ReadCleanReq miss latency 134211507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::total 60255.347594 # average ReadCleanReq miss latency 134311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 60507.575758 # average ReadSharedReq miss latency 134411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 60250 # average ReadSharedReq miss latency 134511507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 60500 # average ReadSharedReq miss latency 134611507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 60000 # average ReadSharedReq miss latency 134711507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 60487.179487 # average ReadSharedReq miss latency 134811507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 60531.578947 # average overall miss latency 134911507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 60512.121212 # average overall miss latency 135011507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 59642.857143 # average overall miss latency 135111507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 61031.250000 # average overall miss latency 135211507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu2.inst 59776.923077 # average overall miss latency 135311507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu2.data 60652.173913 # average overall miss latency 135411507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu3.inst 56350 # average overall miss latency 135511507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu3.data 61031.250000 # average overall miss latency 135611507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::total 60383.838384 # average overall miss latency 135711507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 60531.578947 # average overall miss latency 135811507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 60512.121212 # average overall miss latency 135911507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 59642.857143 # average overall miss latency 136011507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 61031.250000 # average overall miss latency 136111507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu2.inst 59776.923077 # average overall miss latency 136211507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu2.data 60652.173913 # average overall miss latency 136311507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu3.inst 56350 # average overall miss latency 136411507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu3.data 61031.250000 # average overall miss latency 136511507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::total 60383.838384 # average overall miss latency 136611507SCurtis.Dunham@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 136711507SCurtis.Dunham@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 136811507SCurtis.Dunham@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 136911507SCurtis.Dunham@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 137011507SCurtis.Dunham@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 137111507SCurtis.Dunham@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 137211507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_hits::cpu1.inst 7 # number of ReadCleanReq MSHR hits 137311507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_hits::cpu2.inst 7 # number of ReadCleanReq MSHR hits 137411507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_hits::cpu3.inst 6 # number of ReadCleanReq MSHR hits 137511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_hits::total 20 # number of ReadCleanReq MSHR hits 137611507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits 137711507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu3.data 1 # number of ReadSharedReq MSHR hits 137811507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits 137911507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits 138011507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 138111507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu2.inst 7 # number of demand (read+write) MSHR hits 138211507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu3.inst 6 # number of demand (read+write) MSHR hits 138311507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits 138411507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits 138511507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits 138611507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 138711507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu2.inst 7 # number of overall MSHR hits 138811507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu3.inst 6 # number of overall MSHR hits 138911507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits 139011507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::total 22 # number of overall MSHR hits 139111507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses 139211507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses 139311507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses 139411507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu3.data 16 # number of UpgradeReq MSHR misses 139511507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses 139611507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses 139711507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses 139811507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu2.data 15 # number of ReadExReq MSHR misses 139911507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses 140011507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses 140111507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_misses::cpu0.inst 285 # number of ReadCleanReq MSHR misses 140211507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_misses::cpu1.inst 7 # number of ReadCleanReq MSHR misses 140311507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_misses::cpu2.inst 58 # number of ReadCleanReq MSHR misses 140411507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_misses::cpu3.inst 4 # number of ReadCleanReq MSHR misses 140511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_misses::total 354 # number of ReadCleanReq MSHR misses 140611507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 66 # number of ReadSharedReq MSHR misses 140711507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 1 # number of ReadSharedReq MSHR misses 140811507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu2.data 8 # number of ReadSharedReq MSHR misses 140911507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu3.data 1 # number of ReadSharedReq MSHR misses 141011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 76 # number of ReadSharedReq MSHR misses 141111507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses 141211507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses 141311507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 7 # number of demand (read+write) MSHR misses 141411507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 15 # number of demand (read+write) MSHR misses 141511507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu2.inst 58 # number of demand (read+write) MSHR misses 141611507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu2.data 23 # number of demand (read+write) MSHR misses 141711507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses 141811507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses 141911507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses 142011507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses 142111507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses 142211507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 7 # number of overall MSHR misses 142311507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 15 # number of overall MSHR misses 142411507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu2.inst 58 # number of overall MSHR misses 142511507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu2.data 23 # number of overall MSHR misses 142611507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses 142711507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses 142811507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses 142911507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 561000 # number of UpgradeReq MSHR miss cycles 143011507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 319000 # number of UpgradeReq MSHR miss cycles 143111507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 336500 # number of UpgradeReq MSHR miss cycles 143211507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 331000 # number of UpgradeReq MSHR miss cycles 143311507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 1547500 # number of UpgradeReq MSHR miss cycles 143411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5001000 # number of ReadExReq MSHR miss cycles 143511507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 716000 # number of ReadExReq MSHR miss cycles 143611507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu2.data 761000 # number of ReadExReq MSHR miss cycles 143711507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu3.data 716500 # number of ReadExReq MSHR miss cycles 143811507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 7194500 # number of ReadExReq MSHR miss cycles 143911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 14401500 # number of ReadCleanReq MSHR miss cycles 144011507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 358000 # number of ReadCleanReq MSHR miss cycles 144111507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2929500 # number of ReadCleanReq MSHR miss cycles 144211507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 203000 # number of ReadCleanReq MSHR miss cycles 144311507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::total 17892000 # number of ReadCleanReq MSHR miss cycles 144411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 3333500 # number of ReadSharedReq MSHR miss cycles 144511507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 50500 # number of ReadSharedReq MSHR miss cycles 144611507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 404000 # number of ReadSharedReq MSHR miss cycles 144711507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 50500 # number of ReadSharedReq MSHR miss cycles 144811507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 3838500 # number of ReadSharedReq MSHR miss cycles 144911507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 14401500 # number of demand (read+write) MSHR miss cycles 145011507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 8334500 # number of demand (read+write) MSHR miss cycles 145111507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 358000 # number of demand (read+write) MSHR miss cycles 145211507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 766500 # number of demand (read+write) MSHR miss cycles 145311507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu2.inst 2929500 # number of demand (read+write) MSHR miss cycles 145411507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu2.data 1165000 # number of demand (read+write) MSHR miss cycles 145511507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu3.inst 203000 # number of demand (read+write) MSHR miss cycles 145611507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu3.data 767000 # number of demand (read+write) MSHR miss cycles 145711507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::total 28925000 # number of demand (read+write) MSHR miss cycles 145811507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 14401500 # number of overall MSHR miss cycles 145911507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 8334500 # number of overall MSHR miss cycles 146011507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 358000 # number of overall MSHR miss cycles 146111507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 766500 # number of overall MSHR miss cycles 146211507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu2.inst 2929500 # number of overall MSHR miss cycles 146311507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu2.data 1165000 # number of overall MSHR miss cycles 146411507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu3.inst 203000 # number of overall MSHR miss cycles 146511507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu3.data 767000 # number of overall MSHR miss cycles 146611507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::total 28925000 # number of overall MSHR miss cycles 146711507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 146811507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 146911507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 147011507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 147111507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses 147211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 147311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 147411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 147511507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 147611507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 147711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses 147811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadCleanReq accesses 147911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for ReadCleanReq accesses 148011507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for ReadCleanReq accesses 148111507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses 148211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses 148311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadSharedReq accesses 148411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.727273 # mshr miss rate for ReadSharedReq accesses 148511507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadSharedReq accesses 148611507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # mshr miss rate for ReadSharedReq accesses 148711507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 148811507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses 148911507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for demand accesses 149011507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses 149111507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for demand accesses 149211507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for demand accesses 149311507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for demand accesses 149411507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses 149511507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses 149611507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 149711507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 149811507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses 149911507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses 150011507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for overall accesses 150111507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses 150211507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for overall accesses 150311507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses 150411507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses 150511507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20035.714286 # average UpgradeReq mshr miss latency 150611507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19937.500000 # average UpgradeReq mshr miss latency 150711507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19794.117647 # average UpgradeReq mshr miss latency 150811507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20687.500000 # average UpgradeReq mshr miss latency 150911507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 20097.402597 # average UpgradeReq mshr miss latency 151011507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 50515.151515 # average ReadExReq mshr miss latency 151111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51142.857143 # average ReadExReq mshr miss latency 151211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 50733.333333 # average ReadExReq mshr miss latency 151311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 51178.571429 # average ReadExReq mshr miss latency 151411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 50665.492958 # average ReadExReq mshr miss latency 151511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 50531.578947 # average ReadCleanReq mshr miss latency 151611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51142.857143 # average ReadCleanReq mshr miss latency 151711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average ReadCleanReq mshr miss latency 151811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 50750 # average ReadCleanReq mshr miss latency 151911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::total 50542.372881 # average ReadCleanReq mshr miss latency 152011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 50507.575758 # average ReadSharedReq mshr miss latency 152111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 50500 # average ReadSharedReq mshr miss latency 152211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 50500 # average ReadSharedReq mshr miss latency 152311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 50500 # average ReadSharedReq mshr miss latency 152411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50506.578947 # average ReadSharedReq mshr miss latency 152511507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50531.578947 # average overall mshr miss latency 152611507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency 152711507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51142.857143 # average overall mshr miss latency 152811507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 51100 # average overall mshr miss latency 152911507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency 153011507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency 153111507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu3.inst 50750 # average overall mshr miss latency 153211507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu3.data 51133.333333 # average overall mshr miss latency 153311507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 50568.181818 # average overall mshr miss latency 153411507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50531.578947 # average overall mshr miss latency 153511507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency 153611507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51142.857143 # average overall mshr miss latency 153711507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 51100 # average overall mshr miss latency 153811507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency 153911507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency 154011507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50750 # average overall mshr miss latency 154111507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu3.data 51133.333333 # average overall mshr miss latency 154211507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 50568.181818 # average overall mshr miss latency 154311507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_requests 916 # Total number of requests made to the snoop filter. 154411507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_requests 338 # Number of requests hitting in the snoop filter with a single holder of the requested data. 154511507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 154611507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 154711507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 154811507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 154911507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 430 # Transaction distribution 155011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 272 # Transaction distribution 155111507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 208 # Transaction distribution 155211507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 142 # Transaction distribution 155311507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 430 # Transaction distribution 155411507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1482 # Packet count per connected master and slave (bytes) 155511507SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 1482 # Packet count per connected master and slave (bytes) 155611507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) 155711507SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) 155811507SCurtis.Dunham@arm.comsystem.membus.snoops 261 # Total snoops (count) 155911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 916 # Request fanout histogram 156011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 156111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 156211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 156311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 916 100.00% 100.00% # Request fanout histogram 156411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 156511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 156611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 156711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 156811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 916 # Request fanout histogram 156911507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 683633 # Layer occupancy (ticks) 157011507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 157111507SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) 157211507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 1.1 # Layer utilization (%) 157311507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_requests 3977 # Total number of requests made to the snoop filter. 157411507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 1110 # Number of requests hitting in the snoop filter with a single holder of the requested data. 157511507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 157611507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 157711507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 157811507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 157911507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution 158011507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 158111507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution 158211507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 158311507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution 158411507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution 158511507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExReq 420 # Transaction distribution 158611507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExResp 420 # Transaction distribution 158711507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution 158811507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution 158911507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) 159011507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes) 159111507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) 159211507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes) 159311507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) 159411507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 377 # Packet count per connected master and slave (bytes) 159511507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes) 159611507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 349 # Packet count per connected master and slave (bytes) 159711507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count::total 5868 # Packet count per connected master and slave (bytes) 159811507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) 159911507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 160011507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) 160111507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 160211507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) 160311507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 160411507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 # Cumulative packet size per connected master and slave (bytes) 160511507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 160611507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size::total 183616 # Cumulative packet size per connected master and slave (bytes) 160711507SCurtis.Dunham@arm.comsystem.toL2Bus.snoops 1028 # Total snoops (count) 160811507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::samples 2919 # Request fanout histogram 160911507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::mean 1.272011 # Request fanout histogram 161011507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::stdev 1.157273 # Request fanout histogram 161111507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 161211507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::0 1002 34.33% 34.33% # Request fanout histogram 161311507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::1 784 26.86% 61.19% # Request fanout histogram 161411507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::2 470 16.10% 77.29% # Request fanout histogram 161511507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::3 663 22.71% 100.00% # Request fanout histogram 161611507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 161711507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 161811507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 161911507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram 162011507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 162111507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 162211507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 162311507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 162411507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::total 2919 # Request fanout histogram 162511507SCurtis.Dunham@arm.comsystem.toL2Bus.reqLayer0.occupancy 3051987 # Layer occupancy (ticks) 162611507SCurtis.Dunham@arm.comsystem.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 162711507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) 162811507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) 162911507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer1.occupancy 501494 # Layer occupancy (ticks) 163011507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 163111507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer2.occupancy 552489 # Layer occupancy (ticks) 163211507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) 163311507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer3.occupancy 440975 # Layer occupancy (ticks) 163411507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) 163511507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) 163611507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) 163711507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer5.occupancy 442472 # Layer occupancy (ticks) 163811507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) 163911507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer6.occupancy 553492 # Layer occupancy (ticks) 164011507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) 164111507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer7.occupancy 403476 # Layer occupancy (ticks) 164211507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 164311507SCurtis.Dunham@arm.com 164411507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 1645