stats.txt revision 9150:a2370fa5c793
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87707000 # Number of ticks simulated 5final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1518076 # Simulator instruction rate (inst/s) 8host_op_rate 1518015 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 196560583 # Simulator tick rate (ticks/s) 10host_mem_usage 1157868 # Number of bytes of host memory used 11host_seconds 0.45 # Real time elapsed on the host 12sim_insts 677327 # Number of instructions simulated 13sim_ops 677327 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 22system.physmem.bytes_read::total 35776 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 36system.physmem.num_reads::total 559 # Number of read requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) 60system.cpu0.workload.num_syscalls 89 # Number of system calls 61system.cpu0.numCycles 175415 # number of cpu cycles simulated 62system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 63system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 64system.cpu0.committedInsts 175326 # Number of instructions committed 65system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed 66system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses 67system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 68system.cpu0.num_func_calls 390 # number of times a function call or return occured 69system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls 70system.cpu0.num_int_insts 120376 # number of integer instructions 71system.cpu0.num_fp_insts 0 # number of float instructions 72system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read 73system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written 74system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 75system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 76system.cpu0.num_mem_refs 82397 # number of memory refs 77system.cpu0.num_load_insts 54591 # Number of load instructions 78system.cpu0.num_store_insts 27806 # Number of store instructions 79system.cpu0.num_idle_cycles 0 # Number of idle cycles 80system.cpu0.num_busy_cycles 175415 # Number of busy cycles 81system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 82system.cpu0.idle_fraction 0 # Percentage of idle cycles 83system.cpu0.icache.replacements 215 # number of replacements 84system.cpu0.icache.tagsinuse 222.772698 # Cycle average of tags in use 85system.cpu0.icache.total_refs 174921 # Total number of references to valid blocks. 86system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. 87system.cpu0.icache.avg_refs 374.563169 # Average number of references to valid blocks. 88system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 89system.cpu0.icache.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor 90system.cpu0.icache.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy 91system.cpu0.icache.occ_percent::total 0.435103 # Average percentage of cache occupancy 92system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits 93system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits 94system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits 95system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits 96system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits 97system.cpu0.icache.overall_hits::total 174921 # number of overall hits 98system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 99system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 100system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 101system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 102system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 103system.cpu0.icache.overall_misses::total 467 # number of overall misses 104system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) 105system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) 106system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses 107system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses 108system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses 109system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses 110system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses 111system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses 112system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses 113system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses 114system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses 115system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses 116system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 117system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 118system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 119system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 120system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 121system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 122system.cpu0.icache.fast_writes 0 # number of fast writes performed 123system.cpu0.icache.cache_copies 0 # number of cache copies performed 124system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 125system.cpu0.dcache.replacements 2 # number of replacements 126system.cpu0.dcache.tagsinuse 150.745494 # Cycle average of tags in use 127system.cpu0.dcache.total_refs 81883 # Total number of references to valid blocks. 128system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. 129system.cpu0.dcache.avg_refs 490.317365 # Average number of references to valid blocks. 130system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 131system.cpu0.dcache.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor 132system.cpu0.dcache.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy 133system.cpu0.dcache.occ_percent::total 0.294425 # Average percentage of cache occupancy 134system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits 135system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits 136system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits 137system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits 138system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits 139system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits 140system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits 141system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits 142system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits 143system.cpu0.dcache.overall_hits::total 82008 # number of overall hits 144system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses 145system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses 146system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses 147system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses 148system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses 149system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses 150system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses 151system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses 152system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses 153system.cpu0.dcache.overall_misses::total 328 # number of overall misses 154system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses) 155system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses) 156system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) 157system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) 158system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 159system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 160system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses 161system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses 162system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses 163system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses 164system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses 165system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses 166system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses 167system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses 168system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses 169system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses 170system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses 171system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses 172system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses 173system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses 174system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 175system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 176system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 177system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 178system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 179system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 180system.cpu0.dcache.fast_writes 0 # number of fast writes performed 181system.cpu0.dcache.cache_copies 0 # number of cache copies performed 182system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 183system.cpu0.dcache.writebacks::total 1 # number of writebacks 184system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 185system.cpu1.numCycles 173295 # number of cpu cycles simulated 186system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 187system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 188system.cpu1.committedInsts 167398 # Number of instructions committed 189system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed 190system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses 191system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 192system.cpu1.num_func_calls 633 # number of times a function call or return occured 193system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls 194system.cpu1.num_int_insts 109926 # number of integer instructions 195system.cpu1.num_fp_insts 0 # number of float instructions 196system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read 197system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written 198system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 199system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 200system.cpu1.num_mem_refs 53394 # number of memory refs 201system.cpu1.num_load_insts 40652 # Number of load instructions 202system.cpu1.num_store_insts 12742 # Number of store instructions 203system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles 204system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles 205system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles 206system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles 207system.cpu1.icache.replacements 278 # number of replacements 208system.cpu1.icache.tagsinuse 76.751702 # Cycle average of tags in use 209system.cpu1.icache.total_refs 167072 # Total number of references to valid blocks. 210system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks. 211system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks. 212system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 213system.cpu1.icache.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor 214system.cpu1.icache.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy 215system.cpu1.icache.occ_percent::total 0.149906 # Average percentage of cache occupancy 216system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits 217system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits 218system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits 219system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits 220system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits 221system.cpu1.icache.overall_hits::total 167072 # number of overall hits 222system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses 223system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses 224system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses 225system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses 226system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses 227system.cpu1.icache.overall_misses::total 358 # number of overall misses 228system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses) 229system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses) 230system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses 231system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses 232system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses 233system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses 234system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses 235system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses 236system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses 237system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses 238system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses 239system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses 240system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 241system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 242system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 243system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 244system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 245system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 246system.cpu1.icache.fast_writes 0 # number of fast writes performed 247system.cpu1.icache.cache_copies 0 # number of cache copies performed 248system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 249system.cpu1.dcache.replacements 0 # number of replacements 250system.cpu1.dcache.tagsinuse 30.316999 # Cycle average of tags in use 251system.cpu1.dcache.total_refs 26731 # Total number of references to valid blocks. 252system.cpu1.dcache.sampled_refs 26 # Sample count of references to valid blocks. 253system.cpu1.dcache.avg_refs 1028.115385 # Average number of references to valid blocks. 254system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 255system.cpu1.dcache.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor 256system.cpu1.dcache.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy 257system.cpu1.dcache.occ_percent::total 0.059213 # Average percentage of cache occupancy 258system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits 259system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits 260system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits 261system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits 262system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 263system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits 264system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits 265system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits 266system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits 267system.cpu1.dcache.overall_hits::total 53033 # number of overall hits 268system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses 269system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses 270system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses 271system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses 272system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses 273system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses 274system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses 275system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses 276system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses 277system.cpu1.dcache.overall_misses::total 280 # number of overall misses 278system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses) 279system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses) 280system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses) 281system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses) 282system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 283system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 284system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses 285system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses 286system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses 287system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses 288system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses 289system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses 290system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses 291system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses 292system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses 293system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses 294system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses 295system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses 296system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses 297system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses 298system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 299system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 300system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 301system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 302system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 303system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 304system.cpu1.dcache.fast_writes 0 # number of fast writes performed 305system.cpu1.dcache.cache_copies 0 # number of cache copies performed 306system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 307system.cpu2.numCycles 173295 # number of cpu cycles simulated 308system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 309system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 310system.cpu2.committedInsts 167334 # Number of instructions committed 311system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed 312system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses 313system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 314system.cpu2.num_func_calls 633 # number of times a function call or return occured 315system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls 316system.cpu2.num_int_insts 113333 # number of integer instructions 317system.cpu2.num_fp_insts 0 # number of float instructions 318system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read 319system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written 320system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 321system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 322system.cpu2.num_mem_refs 58537 # number of memory refs 323system.cpu2.num_load_insts 42362 # Number of load instructions 324system.cpu2.num_store_insts 16175 # Number of store instructions 325system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles 326system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles 327system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles 328system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles 329system.cpu2.icache.replacements 278 # number of replacements 330system.cpu2.icache.tagsinuse 74.781015 # Cycle average of tags in use 331system.cpu2.icache.total_refs 167008 # Total number of references to valid blocks. 332system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks. 333system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks. 334system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 335system.cpu2.icache.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor 336system.cpu2.icache.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy 337system.cpu2.icache.occ_percent::total 0.146057 # Average percentage of cache occupancy 338system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits 339system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits 340system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits 341system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits 342system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits 343system.cpu2.icache.overall_hits::total 167008 # number of overall hits 344system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses 345system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses 346system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses 347system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses 348system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses 349system.cpu2.icache.overall_misses::total 358 # number of overall misses 350system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses) 351system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses) 352system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses 353system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses 354system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses 355system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses 356system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses 357system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses 358system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses 359system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses 360system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses 361system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses 362system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 363system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 364system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 365system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 366system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 367system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 368system.cpu2.icache.fast_writes 0 # number of fast writes performed 369system.cpu2.icache.cache_copies 0 # number of cache copies performed 370system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 371system.cpu2.dcache.replacements 0 # number of replacements 372system.cpu2.dcache.tagsinuse 29.605505 # Cycle average of tags in use 373system.cpu2.dcache.total_refs 33613 # Total number of references to valid blocks. 374system.cpu2.dcache.sampled_refs 26 # Sample count of references to valid blocks. 375system.cpu2.dcache.avg_refs 1292.807692 # Average number of references to valid blocks. 376system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 377system.cpu2.dcache.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor 378system.cpu2.dcache.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy 379system.cpu2.dcache.occ_percent::total 0.057823 # Average percentage of cache occupancy 380system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits 381system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits 382system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits 383system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits 384system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits 385system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits 386system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits 387system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits 388system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits 389system.cpu2.dcache.overall_hits::total 58192 # number of overall hits 390system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses 391system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses 392system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses 393system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses 394system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses 395system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses 396system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses 397system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses 398system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses 399system.cpu2.dcache.overall_misses::total 269 # number of overall misses 400system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses) 401system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses) 402system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses) 403system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses) 404system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) 405system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 406system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses 407system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses 408system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses 409system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses 410system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses 411system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses 412system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses 413system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses 414system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses 415system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses 416system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses 417system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses 418system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses 419system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses 420system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 421system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 422system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 423system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 424system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 425system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 426system.cpu2.dcache.fast_writes 0 # number of fast writes performed 427system.cpu2.dcache.cache_copies 0 # number of cache copies performed 428system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 429system.cpu3.numCycles 173294 # number of cpu cycles simulated 430system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 431system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 432system.cpu3.committedInsts 167269 # Number of instructions committed 433system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed 434system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses 435system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 436system.cpu3.num_func_calls 633 # number of times a function call or return occured 437system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls 438system.cpu3.num_int_insts 111554 # number of integer instructions 439system.cpu3.num_fp_insts 0 # number of float instructions 440system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read 441system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written 442system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 443system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 444system.cpu3.num_mem_refs 55900 # number of memory refs 445system.cpu3.num_load_insts 41466 # Number of load instructions 446system.cpu3.num_store_insts 14434 # Number of store instructions 447system.cpu3.num_idle_cycles 8001.119846 # Number of idle cycles 448system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles 449system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles 450system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles 451system.cpu3.icache.replacements 279 # number of replacements 452system.cpu3.icache.tagsinuse 72.874497 # Cycle average of tags in use 453system.cpu3.icache.total_refs 166942 # Total number of references to valid blocks. 454system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks. 455system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks. 456system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 457system.cpu3.icache.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor 458system.cpu3.icache.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy 459system.cpu3.icache.occ_percent::total 0.142333 # Average percentage of cache occupancy 460system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits 461system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits 462system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits 463system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits 464system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits 465system.cpu3.icache.overall_hits::total 166942 # number of overall hits 466system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses 467system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses 468system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses 469system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses 470system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses 471system.cpu3.icache.overall_misses::total 359 # number of overall misses 472system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses) 473system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses) 474system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses 475system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses 476system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses 477system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses 478system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses 479system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses 480system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses 481system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses 482system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses 483system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses 484system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 485system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 486system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 487system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 488system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 489system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 490system.cpu3.icache.fast_writes 0 # number of fast writes performed 491system.cpu3.icache.cache_copies 0 # number of cache copies performed 492system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 493system.cpu3.dcache.replacements 0 # number of replacements 494system.cpu3.dcache.tagsinuse 28.795404 # Cycle average of tags in use 495system.cpu3.dcache.total_refs 30236 # Total number of references to valid blocks. 496system.cpu3.dcache.sampled_refs 27 # Sample count of references to valid blocks. 497system.cpu3.dcache.avg_refs 1119.851852 # Average number of references to valid blocks. 498system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 499system.cpu3.dcache.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor 500system.cpu3.dcache.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy 501system.cpu3.dcache.occ_percent::total 0.056241 # Average percentage of cache occupancy 502system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits 503system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits 504system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits 505system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits 506system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 507system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 508system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits 509system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits 510system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits 511system.cpu3.dcache.overall_hits::total 55561 # number of overall hits 512system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses 513system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses 514system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses 515system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses 516system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses 517system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses 518system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses 519system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses 520system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses 521system.cpu3.dcache.overall_misses::total 259 # number of overall misses 522system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses) 523system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses) 524system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses) 525system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses) 526system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) 527system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 528system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses 529system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses 530system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses 531system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses 532system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses 533system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses 534system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses 535system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses 536system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses 537system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses 538system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses 539system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses 540system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses 541system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses 542system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 543system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 544system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 545system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 546system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 547system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 548system.cpu3.dcache.fast_writes 0 # number of fast writes performed 549system.cpu3.dcache.cache_copies 0 # number of cache copies performed 550system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 551system.l2c.replacements 0 # number of replacements 552system.l2c.tagsinuse 366.582542 # Cycle average of tags in use 553system.l2c.total_refs 1220 # Total number of references to valid blocks. 554system.l2c.sampled_refs 421 # Sample count of references to valid blocks. 555system.l2c.avg_refs 2.897862 # Average number of references to valid blocks. 556system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 557system.l2c.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor 558system.l2c.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor 559system.l2c.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor 560system.l2c.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor 561system.l2c.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor 562system.l2c.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor 563system.l2c.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor 564system.l2c.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor 565system.l2c.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor 566system.l2c.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy 567system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy 568system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy 569system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy 570system.l2c.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy 571system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy 572system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy 573system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy 574system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy 575system.l2c.occ_percent::total 0.005594 # Average percentage of cache occupancy 576system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits 577system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 578system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits 579system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits 580system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits 581system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits 582system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits 583system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits 584system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits 585system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 586system.l2c.Writeback_hits::total 1 # number of Writeback hits 587system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 588system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 589system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits 590system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 591system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits 592system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits 593system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits 594system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 595system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits 596system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 597system.l2c.demand_hits::total 1220 # number of demand (read+write) hits 598system.l2c.overall_hits::cpu0.inst 185 # number of overall hits 599system.l2c.overall_hits::cpu0.data 5 # number of overall hits 600system.l2c.overall_hits::cpu1.inst 296 # number of overall hits 601system.l2c.overall_hits::cpu1.data 3 # number of overall hits 602system.l2c.overall_hits::cpu2.inst 356 # number of overall hits 603system.l2c.overall_hits::cpu2.data 9 # number of overall hits 604system.l2c.overall_hits::cpu3.inst 357 # number of overall hits 605system.l2c.overall_hits::cpu3.data 9 # number of overall hits 606system.l2c.overall_hits::total 1220 # number of overall hits 607system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses 608system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 609system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses 610system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses 611system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses 612system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses 613system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses 614system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 615system.l2c.ReadReq_misses::total 423 # number of ReadReq misses 616system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses 617system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses 618system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses 619system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses 620system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses 621system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 622system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 623system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 624system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 625system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses 626system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses 627system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 628system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses 629system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses 630system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses 631system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses 632system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses 633system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 634system.l2c.demand_misses::total 559 # number of demand (read+write) misses 635system.l2c.overall_misses::cpu0.inst 282 # number of overall misses 636system.l2c.overall_misses::cpu0.data 165 # number of overall misses 637system.l2c.overall_misses::cpu1.inst 62 # number of overall misses 638system.l2c.overall_misses::cpu1.data 20 # number of overall misses 639system.l2c.overall_misses::cpu2.inst 2 # number of overall misses 640system.l2c.overall_misses::cpu2.data 13 # number of overall misses 641system.l2c.overall_misses::cpu3.inst 2 # number of overall misses 642system.l2c.overall_misses::cpu3.data 13 # number of overall misses 643system.l2c.overall_misses::total 559 # number of overall misses 644system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 645system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 646system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) 647system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) 648system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) 649system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) 650system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) 651system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) 652system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) 653system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 654system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 655system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) 656system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) 657system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) 658system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) 659system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) 660system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 661system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 662system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 663system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 664system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) 665system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 666system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 667system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses 668system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses 669system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses 670system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses 671system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses 672system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses 673system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses 674system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 675system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 676system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses 677system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses 678system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses 679system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses 680system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses 681system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses 682system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses 683system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses 684system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 685system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses 686system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses 687system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses 688system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses 689system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses 690system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses 691system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses 692system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses 693system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 694system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 695system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 696system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses 697system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 698system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 699system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 700system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 701system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 702system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 703system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 704system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses 705system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses 706system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses 707system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses 708system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses 709system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses 710system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses 711system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 712system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 713system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses 714system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses 715system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses 716system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses 717system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses 718system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses 719system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses 720system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 721system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 722system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 723system.l2c.blocked::no_targets 0 # number of cycles access was blocked 724system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 725system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 726system.l2c.fast_writes 0 # number of fast writes performed 727system.l2c.cache_copies 0 # number of cache copies performed 728system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 729 730---------- End Simulation Statistics ---------- 731