stats.txt revision 9568:cd1351d4d850
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000106 # Number of seconds simulated 4sim_ticks 105801500 # Number of ticks simulated 5final_tick 105801500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 173787 # Simulator instruction rate (inst/s) 8host_op_rate 173787 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 17750545 # Simulator tick rate (ticks/s) 10host_mem_usage 247480 # Number of bytes of host memory used 11host_seconds 5.96 # Real time elapsed on the host 12sim_insts 1035849 # Number of instructions simulated 13sim_ops 1035849 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 22system.physmem.bytes_read::total 42240 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 22848 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 28544 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 357 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 36system.physmem.num_reads::total 660 # Number of read requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 215951570 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 101624268 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 48392509 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 12098127 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 3629438 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 7863783 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 1814719 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 7863783 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 399238196 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 215951570 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 48392509 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 3629438 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 1814719 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 269788236 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 215951570 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 101624268 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 48392509 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 12098127 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 3629438 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 7863783 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 1814719 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 7863783 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 399238196 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.readReqs 661 # Total number of read requests seen 61system.physmem.writeReqs 0 # Total number of write requests seen 62system.physmem.cpureqs 732 # Reqs generatd by CPU via cache - shady 63system.physmem.bytesRead 42240 # Total number of bytes read from memory 64system.physmem.bytesWritten 0 # Total number of bytes written to memory 65system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize() 66system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 67system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 68system.physmem.neitherReadNorWrite 71 # Reqs where no action is needed 69system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::2 74 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::3 69 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::4 58 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis 77system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis 78system.physmem.perBankRdReqs::9 14 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::11 13 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::12 37 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::13 60 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::14 74 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::15 23 # Track reads on a per bank basis 85system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 93system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 94system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 101system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 102system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 103system.physmem.totGap 105773500 # Total gap between requests 104system.physmem.readPktSize::0 0 # Categorize read packet sizes 105system.physmem.readPktSize::1 0 # Categorize read packet sizes 106system.physmem.readPktSize::2 0 # Categorize read packet sizes 107system.physmem.readPktSize::3 0 # Categorize read packet sizes 108system.physmem.readPktSize::4 0 # Categorize read packet sizes 109system.physmem.readPktSize::5 0 # Categorize read packet sizes 110system.physmem.readPktSize::6 661 # Categorize read packet sizes 111system.physmem.writePktSize::0 0 # Categorize write packet sizes 112system.physmem.writePktSize::1 0 # Categorize write packet sizes 113system.physmem.writePktSize::2 0 # Categorize write packet sizes 114system.physmem.writePktSize::3 0 # Categorize write packet sizes 115system.physmem.writePktSize::4 0 # Categorize write packet sizes 116system.physmem.writePktSize::5 0 # Categorize write packet sizes 117system.physmem.writePktSize::6 0 # Categorize write packet sizes 118system.physmem.rdQLenPdf::0 377 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::1 205 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 150system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 182system.physmem.totQLat 4076500 # Total cycles spent in queuing delays 183system.physmem.totMemAccLat 20691500 # Sum of mem lat for all requests 184system.physmem.totBusLat 3305000 # Total cycles spent in databus access 185system.physmem.totBankLat 13310000 # Total cycles spent in bank access 186system.physmem.avgQLat 6167.17 # Average queueing delay per request 187system.physmem.avgBankLat 20136.16 # Average bank access latency per request 188system.physmem.avgBusLat 5000.00 # Average bus latency per request 189system.physmem.avgMemAccLat 31303.33 # Average memory access latency 190system.physmem.avgRdBW 399.24 # Average achieved read bandwidth in MB/s 191system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 192system.physmem.avgConsumedRdBW 399.24 # Average consumed read bandwidth in MB/s 193system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 194system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 195system.physmem.busUtil 3.12 # Data bus utilization in percentage 196system.physmem.avgRdQLen 0.20 # Average read queue length over time 197system.physmem.avgWrQLen 0.00 # Average write queue length over time 198system.physmem.readRowHits 465 # Number of row buffer hits during reads 199system.physmem.writeRowHits 0 # Number of row buffer hits during writes 200system.physmem.readRowHitRate 70.35 # Row buffer hit rate for reads 201system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 202system.physmem.avgGap 160020.42 # Average gap between requests 203system.cpu0.branchPred.lookups 82232 # Number of BP lookups 204system.cpu0.branchPred.condPredicted 80005 # Number of conditional branches predicted 205system.cpu0.branchPred.condIncorrect 1236 # Number of conditional branches incorrect 206system.cpu0.branchPred.BTBLookups 79512 # Number of BTB lookups 207system.cpu0.branchPred.BTBHits 77444 # Number of BTB hits 208system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 209system.cpu0.branchPred.BTBHitPct 97.399135 # BTB Hit Percentage 210system.cpu0.branchPred.usedRAS 525 # Number of times the RAS was used to get a target. 211system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. 212system.cpu0.workload.num_syscalls 89 # Number of system calls 213system.cpu0.numCycles 211604 # number of cpu cycles simulated 214system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 215system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 216system.cpu0.fetch.icacheStallCycles 16980 # Number of cycles fetch is stalled on an Icache miss 217system.cpu0.fetch.Insts 488068 # Number of instructions fetch has processed 218system.cpu0.fetch.Branches 82232 # Number of branches that fetch encountered 219system.cpu0.fetch.predictedBranches 77969 # Number of branches that fetch has predicted taken 220system.cpu0.fetch.Cycles 160105 # Number of cycles fetch has run and was not squashing or blocked 221system.cpu0.fetch.SquashCycles 3869 # Number of cycles fetch has spent squashing 222system.cpu0.fetch.BlockedCycles 13032 # Number of cycles fetch has spent blocked 223system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 224system.cpu0.fetch.PendingTrapStallCycles 1378 # Number of stall cycles due to pending traps 225system.cpu0.fetch.CacheLines 5906 # Number of cache lines fetched 226system.cpu0.fetch.IcacheSquashes 485 # Number of outstanding Icache misses that were squashed 227system.cpu0.fetch.rateDist::samples 193984 # Number of instructions fetched each cycle (Total) 228system.cpu0.fetch.rateDist::mean 2.516022 # Number of instructions fetched each cycle (Total) 229system.cpu0.fetch.rateDist::stdev 2.216359 # Number of instructions fetched each cycle (Total) 230system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 231system.cpu0.fetch.rateDist::0 33879 17.46% 17.46% # Number of instructions fetched each cycle (Total) 232system.cpu0.fetch.rateDist::1 79263 40.86% 58.33% # Number of instructions fetched each cycle (Total) 233system.cpu0.fetch.rateDist::2 605 0.31% 58.64% # Number of instructions fetched each cycle (Total) 234system.cpu0.fetch.rateDist::3 997 0.51% 59.15% # Number of instructions fetched each cycle (Total) 235system.cpu0.fetch.rateDist::4 467 0.24% 59.39% # Number of instructions fetched each cycle (Total) 236system.cpu0.fetch.rateDist::5 75310 38.82% 98.21% # Number of instructions fetched each cycle (Total) 237system.cpu0.fetch.rateDist::6 571 0.29% 98.51% # Number of instructions fetched each cycle (Total) 238system.cpu0.fetch.rateDist::7 376 0.19% 98.70% # Number of instructions fetched each cycle (Total) 239system.cpu0.fetch.rateDist::8 2516 1.30% 100.00% # Number of instructions fetched each cycle (Total) 240system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 241system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 242system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 243system.cpu0.fetch.rateDist::total 193984 # Number of instructions fetched each cycle (Total) 244system.cpu0.fetch.branchRate 0.388613 # Number of branch fetches per cycle 245system.cpu0.fetch.rate 2.306516 # Number of inst fetches per cycle 246system.cpu0.decode.IdleCycles 17628 # Number of cycles decode is idle 247system.cpu0.decode.BlockedCycles 14487 # Number of cycles decode is blocked 248system.cpu0.decode.RunCycles 159104 # Number of cycles decode is running 249system.cpu0.decode.UnblockCycles 281 # Number of cycles decode is unblocking 250system.cpu0.decode.SquashCycles 2484 # Number of cycles decode is squashing 251system.cpu0.decode.DecodedInsts 484973 # Number of instructions handled by decode 252system.cpu0.rename.SquashCycles 2484 # Number of cycles rename is squashing 253system.cpu0.rename.IdleCycles 18279 # Number of cycles rename is idle 254system.cpu0.rename.BlockCycles 710 # Number of cycles rename is blocking 255system.cpu0.rename.serializeStallCycles 13181 # count of cycles rename stalled for serializing inst 256system.cpu0.rename.RunCycles 158767 # Number of cycles rename is running 257system.cpu0.rename.UnblockCycles 563 # Number of cycles rename is unblocking 258system.cpu0.rename.RenamedInsts 482144 # Number of instructions processed by rename 259system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 260system.cpu0.rename.LSQFullEvents 156 # Number of times rename has blocked due to LSQ full 261system.cpu0.rename.RenamedOperands 329947 # Number of destination operands rename has renamed 262system.cpu0.rename.RenameLookups 961518 # Number of register rename lookups that rename has made 263system.cpu0.rename.int_rename_lookups 961518 # Number of integer rename lookups 264system.cpu0.rename.CommittedMaps 316491 # Number of HB maps that are committed 265system.cpu0.rename.UndoneMaps 13456 # Number of HB maps that are undone due to squashing 266system.cpu0.rename.serializingInsts 888 # count of serializing insts renamed 267system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed 268system.cpu0.rename.skidInsts 3585 # count of insts added to the skid buffer 269system.cpu0.memDep0.insertedLoads 154112 # Number of loads inserted to the mem dependence unit. 270system.cpu0.memDep0.insertedStores 77863 # Number of stores inserted to the mem dependence unit. 271system.cpu0.memDep0.conflictingLoads 75108 # Number of conflicting loads. 272system.cpu0.memDep0.conflictingStores 74923 # Number of conflicting stores. 273system.cpu0.iq.iqInstsAdded 403093 # Number of instructions added to the IQ (excludes non-spec) 274system.cpu0.iq.iqNonSpecInstsAdded 921 # Number of non-speculative instructions added to the IQ 275system.cpu0.iq.iqInstsIssued 400275 # Number of instructions issued 276system.cpu0.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued 277system.cpu0.iq.iqSquashedInstsExamined 11012 # Number of squashed instructions iterated over during squash; mainly for profiling 278system.cpu0.iq.iqSquashedOperandsExamined 9891 # Number of squashed operands that are examined and possibly removed from graph 279system.cpu0.iq.iqSquashedNonSpecRemoved 362 # Number of squashed non-spec instructions that were removed 280system.cpu0.iq.issued_per_cycle::samples 193984 # Number of insts issued each cycle 281system.cpu0.iq.issued_per_cycle::mean 2.063443 # Number of insts issued each cycle 282system.cpu0.iq.issued_per_cycle::stdev 1.093968 # Number of insts issued each cycle 283system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 284system.cpu0.iq.issued_per_cycle::0 33040 17.03% 17.03% # Number of insts issued each cycle 285system.cpu0.iq.issued_per_cycle::1 4899 2.53% 19.56% # Number of insts issued each cycle 286system.cpu0.iq.issued_per_cycle::2 76941 39.66% 59.22% # Number of insts issued each cycle 287system.cpu0.iq.issued_per_cycle::3 76443 39.41% 98.63% # Number of insts issued each cycle 288system.cpu0.iq.issued_per_cycle::4 1604 0.83% 99.46% # Number of insts issued each cycle 289system.cpu0.iq.issued_per_cycle::5 703 0.36% 99.82% # Number of insts issued each cycle 290system.cpu0.iq.issued_per_cycle::6 261 0.13% 99.95% # Number of insts issued each cycle 291system.cpu0.iq.issued_per_cycle::7 76 0.04% 99.99% # Number of insts issued each cycle 292system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle 293system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 294system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 295system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 296system.cpu0.iq.issued_per_cycle::total 193984 # Number of insts issued each cycle 297system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 298system.cpu0.iq.fu_full::IntAlu 51 22.67% 22.67% # attempts to use FU when none available 299system.cpu0.iq.fu_full::IntMult 0 0.00% 22.67% # attempts to use FU when none available 300system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.67% # attempts to use FU when none available 301system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.67% # attempts to use FU when none available 302system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.67% # attempts to use FU when none available 303system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.67% # attempts to use FU when none available 304system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.67% # attempts to use FU when none available 305system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.67% # attempts to use FU when none available 306system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.67% # attempts to use FU when none available 307system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.67% # attempts to use FU when none available 308system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.67% # attempts to use FU when none available 309system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.67% # attempts to use FU when none available 310system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.67% # attempts to use FU when none available 311system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.67% # attempts to use FU when none available 312system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.67% # attempts to use FU when none available 313system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.67% # attempts to use FU when none available 314system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.67% # attempts to use FU when none available 315system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.67% # attempts to use FU when none available 316system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.67% # attempts to use FU when none available 317system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.67% # attempts to use FU when none available 318system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.67% # attempts to use FU when none available 319system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.67% # attempts to use FU when none available 320system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.67% # attempts to use FU when none available 321system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.67% # attempts to use FU when none available 322system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.67% # attempts to use FU when none available 323system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.67% # attempts to use FU when none available 324system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.67% # attempts to use FU when none available 325system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available 326system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.67% # attempts to use FU when none available 327system.cpu0.iq.fu_full::MemRead 62 27.56% 50.22% # attempts to use FU when none available 328system.cpu0.iq.fu_full::MemWrite 112 49.78% 100.00% # attempts to use FU when none available 329system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 330system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 331system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 332system.cpu0.iq.FU_type_0::IntAlu 169361 42.31% 42.31% # Type of FU issued 333system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.31% # Type of FU issued 334system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.31% # Type of FU issued 335system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.31% # Type of FU issued 336system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.31% # Type of FU issued 337system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.31% # Type of FU issued 338system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.31% # Type of FU issued 339system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.31% # Type of FU issued 340system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.31% # Type of FU issued 341system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.31% # Type of FU issued 342system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.31% # Type of FU issued 343system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.31% # Type of FU issued 344system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.31% # Type of FU issued 345system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.31% # Type of FU issued 346system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.31% # Type of FU issued 347system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.31% # Type of FU issued 348system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.31% # Type of FU issued 349system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.31% # Type of FU issued 350system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.31% # Type of FU issued 351system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.31% # Type of FU issued 352system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.31% # Type of FU issued 353system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.31% # Type of FU issued 354system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.31% # Type of FU issued 355system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.31% # Type of FU issued 356system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.31% # Type of FU issued 357system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.31% # Type of FU issued 358system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.31% # Type of FU issued 359system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.31% # Type of FU issued 360system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.31% # Type of FU issued 361system.cpu0.iq.FU_type_0::MemRead 153636 38.38% 80.69% # Type of FU issued 362system.cpu0.iq.FU_type_0::MemWrite 77278 19.31% 100.00% # Type of FU issued 363system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 364system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 365system.cpu0.iq.FU_type_0::total 400275 # Type of FU issued 366system.cpu0.iq.rate 1.891623 # Inst issue rate 367system.cpu0.iq.fu_busy_cnt 225 # FU busy when requested 368system.cpu0.iq.fu_busy_rate 0.000562 # FU busy rate (busy events/executed inst) 369system.cpu0.iq.int_inst_queue_reads 994851 # Number of integer instruction queue reads 370system.cpu0.iq.int_inst_queue_writes 415081 # Number of integer instruction queue writes 371system.cpu0.iq.int_inst_queue_wakeup_accesses 398443 # Number of integer instruction queue wakeup accesses 372system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 373system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 374system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 375system.cpu0.iq.int_alu_accesses 400500 # Number of integer alu accesses 376system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses 377system.cpu0.iew.lsq.thread0.forwLoads 74634 # Number of loads that had data forwarded from stores 378system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 379system.cpu0.iew.lsq.thread0.squashedLoads 2277 # Number of loads squashed 380system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 381system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations 382system.cpu0.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed 383system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 384system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 385system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 386system.cpu0.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked 387system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 388system.cpu0.iew.iewSquashCycles 2484 # Number of cycles IEW is squashing 389system.cpu0.iew.iewBlockCycles 441 # Number of cycles IEW is blocking 390system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking 391system.cpu0.iew.iewDispatchedInsts 479665 # Number of instructions dispatched to IQ 392system.cpu0.iew.iewDispSquashedInsts 304 # Number of squashed instructions skipped by dispatch 393system.cpu0.iew.iewDispLoadInsts 154112 # Number of dispatched load instructions 394system.cpu0.iew.iewDispStoreInsts 77863 # Number of dispatched store instructions 395system.cpu0.iew.iewDispNonSpecInsts 809 # Number of dispatched non-speculative instructions 396system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall 397system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 398system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations 399system.cpu0.iew.predictedTakenIncorrect 346 # Number of branches that were predicted taken incorrectly 400system.cpu0.iew.predictedNotTakenIncorrect 1112 # Number of branches that were predicted not taken incorrectly 401system.cpu0.iew.branchMispredicts 1458 # Number of branch mispredicts detected at execute 402system.cpu0.iew.iewExecutedInsts 399178 # Number of executed instructions 403system.cpu0.iew.iewExecLoadInsts 153293 # Number of load instructions executed 404system.cpu0.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute 405system.cpu0.iew.exec_swp 0 # number of swp insts executed 406system.cpu0.iew.exec_nop 75651 # number of nop insts executed 407system.cpu0.iew.exec_refs 230462 # number of memory reference insts executed 408system.cpu0.iew.exec_branches 79264 # Number of branches executed 409system.cpu0.iew.exec_stores 77169 # Number of stores executed 410system.cpu0.iew.exec_rate 1.886439 # Inst execution rate 411system.cpu0.iew.wb_sent 398782 # cumulative count of insts sent to commit 412system.cpu0.iew.wb_count 398443 # cumulative count of insts written-back 413system.cpu0.iew.wb_producers 236156 # num instructions producing a value 414system.cpu0.iew.wb_consumers 238721 # num instructions consuming a value 415system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 416system.cpu0.iew.wb_rate 1.882965 # insts written-back per cycle 417system.cpu0.iew.wb_fanout 0.989255 # average fanout of values written-back 418system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 419system.cpu0.commit.commitSquashedInsts 12542 # The number of squashed insts skipped by commit 420system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 421system.cpu0.commit.branchMispredicts 1236 # The number of times a branch was mispredicted 422system.cpu0.commit.committed_per_cycle::samples 191500 # Number of insts commited each cycle 423system.cpu0.commit.committed_per_cycle::mean 2.439102 # Number of insts commited each cycle 424system.cpu0.commit.committed_per_cycle::stdev 2.136121 # Number of insts commited each cycle 425system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 426system.cpu0.commit.committed_per_cycle::0 33551 17.52% 17.52% # Number of insts commited each cycle 427system.cpu0.commit.committed_per_cycle::1 78896 41.20% 58.72% # Number of insts commited each cycle 428system.cpu0.commit.committed_per_cycle::2 2340 1.22% 59.94% # Number of insts commited each cycle 429system.cpu0.commit.committed_per_cycle::3 696 0.36% 60.30% # Number of insts commited each cycle 430system.cpu0.commit.committed_per_cycle::4 545 0.28% 60.59% # Number of insts commited each cycle 431system.cpu0.commit.committed_per_cycle::5 74448 38.88% 99.47% # Number of insts commited each cycle 432system.cpu0.commit.committed_per_cycle::6 466 0.24% 99.71% # Number of insts commited each cycle 433system.cpu0.commit.committed_per_cycle::7 256 0.13% 99.84% # Number of insts commited each cycle 434system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle 435system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 436system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 437system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 438system.cpu0.commit.committed_per_cycle::total 191500 # Number of insts commited each cycle 439system.cpu0.commit.committedInsts 467088 # Number of instructions committed 440system.cpu0.commit.committedOps 467088 # Number of ops (including micro ops) committed 441system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 442system.cpu0.commit.refs 228259 # Number of memory references committed 443system.cpu0.commit.loads 151835 # Number of loads committed 444system.cpu0.commit.membars 84 # Number of memory barriers committed 445system.cpu0.commit.branches 78311 # Number of branches committed 446system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. 447system.cpu0.commit.int_insts 314822 # Number of committed integer instructions. 448system.cpu0.commit.function_calls 223 # Number of function calls committed. 449system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached 450system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 451system.cpu0.rob.rob_reads 669667 # The number of ROB reads 452system.cpu0.rob.rob_writes 961765 # The number of ROB writes 453system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself 454system.cpu0.idleCycles 17620 # Total number of cycles that the CPU has spent unscheduled due to idling 455system.cpu0.committedInsts 391961 # Number of Instructions Simulated 456system.cpu0.committedOps 391961 # Number of Ops (including micro ops) Simulated 457system.cpu0.committedInsts_total 391961 # Number of Instructions Simulated 458system.cpu0.cpi 0.539860 # CPI: Cycles Per Instruction 459system.cpu0.cpi_total 0.539860 # CPI: Total CPI of All Threads 460system.cpu0.ipc 1.852333 # IPC: Instructions Per Cycle 461system.cpu0.ipc_total 1.852333 # IPC: Total IPC of All Threads 462system.cpu0.int_regfile_reads 714059 # number of integer regfile reads 463system.cpu0.int_regfile_writes 321926 # number of integer regfile writes 464system.cpu0.fp_regfile_reads 192 # number of floating regfile reads 465system.cpu0.misc_regfile_reads 232286 # number of misc regfile reads 466system.cpu0.misc_regfile_writes 564 # number of misc regfile writes 467system.cpu0.icache.replacements 298 # number of replacements 468system.cpu0.icache.tagsinuse 245.557795 # Cycle average of tags in use 469system.cpu0.icache.total_refs 5162 # Total number of references to valid blocks. 470system.cpu0.icache.sampled_refs 589 # Sample count of references to valid blocks. 471system.cpu0.icache.avg_refs 8.764007 # Average number of references to valid blocks. 472system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 473system.cpu0.icache.occ_blocks::cpu0.inst 245.557795 # Average occupied blocks per requestor 474system.cpu0.icache.occ_percent::cpu0.inst 0.479605 # Average percentage of cache occupancy 475system.cpu0.icache.occ_percent::total 0.479605 # Average percentage of cache occupancy 476system.cpu0.icache.ReadReq_hits::cpu0.inst 5162 # number of ReadReq hits 477system.cpu0.icache.ReadReq_hits::total 5162 # number of ReadReq hits 478system.cpu0.icache.demand_hits::cpu0.inst 5162 # number of demand (read+write) hits 479system.cpu0.icache.demand_hits::total 5162 # number of demand (read+write) hits 480system.cpu0.icache.overall_hits::cpu0.inst 5162 # number of overall hits 481system.cpu0.icache.overall_hits::total 5162 # number of overall hits 482system.cpu0.icache.ReadReq_misses::cpu0.inst 744 # number of ReadReq misses 483system.cpu0.icache.ReadReq_misses::total 744 # number of ReadReq misses 484system.cpu0.icache.demand_misses::cpu0.inst 744 # number of demand (read+write) misses 485system.cpu0.icache.demand_misses::total 744 # number of demand (read+write) misses 486system.cpu0.icache.overall_misses::cpu0.inst 744 # number of overall misses 487system.cpu0.icache.overall_misses::total 744 # number of overall misses 488system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 26547500 # number of ReadReq miss cycles 489system.cpu0.icache.ReadReq_miss_latency::total 26547500 # number of ReadReq miss cycles 490system.cpu0.icache.demand_miss_latency::cpu0.inst 26547500 # number of demand (read+write) miss cycles 491system.cpu0.icache.demand_miss_latency::total 26547500 # number of demand (read+write) miss cycles 492system.cpu0.icache.overall_miss_latency::cpu0.inst 26547500 # number of overall miss cycles 493system.cpu0.icache.overall_miss_latency::total 26547500 # number of overall miss cycles 494system.cpu0.icache.ReadReq_accesses::cpu0.inst 5906 # number of ReadReq accesses(hits+misses) 495system.cpu0.icache.ReadReq_accesses::total 5906 # number of ReadReq accesses(hits+misses) 496system.cpu0.icache.demand_accesses::cpu0.inst 5906 # number of demand (read+write) accesses 497system.cpu0.icache.demand_accesses::total 5906 # number of demand (read+write) accesses 498system.cpu0.icache.overall_accesses::cpu0.inst 5906 # number of overall (read+write) accesses 499system.cpu0.icache.overall_accesses::total 5906 # number of overall (read+write) accesses 500system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125974 # miss rate for ReadReq accesses 501system.cpu0.icache.ReadReq_miss_rate::total 0.125974 # miss rate for ReadReq accesses 502system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125974 # miss rate for demand accesses 503system.cpu0.icache.demand_miss_rate::total 0.125974 # miss rate for demand accesses 504system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125974 # miss rate for overall accesses 505system.cpu0.icache.overall_miss_rate::total 0.125974 # miss rate for overall accesses 506system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35682.123656 # average ReadReq miss latency 507system.cpu0.icache.ReadReq_avg_miss_latency::total 35682.123656 # average ReadReq miss latency 508system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency 509system.cpu0.icache.demand_avg_miss_latency::total 35682.123656 # average overall miss latency 510system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency 511system.cpu0.icache.overall_avg_miss_latency::total 35682.123656 # average overall miss latency 512system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 513system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 514system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 515system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 516system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 517system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 518system.cpu0.icache.fast_writes 0 # number of fast writes performed 519system.cpu0.icache.cache_copies 0 # number of cache copies performed 520system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 154 # number of ReadReq MSHR hits 521system.cpu0.icache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits 522system.cpu0.icache.demand_mshr_hits::cpu0.inst 154 # number of demand (read+write) MSHR hits 523system.cpu0.icache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits 524system.cpu0.icache.overall_mshr_hits::cpu0.inst 154 # number of overall MSHR hits 525system.cpu0.icache.overall_mshr_hits::total 154 # number of overall MSHR hits 526system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 590 # number of ReadReq MSHR misses 527system.cpu0.icache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses 528system.cpu0.icache.demand_mshr_misses::cpu0.inst 590 # number of demand (read+write) MSHR misses 529system.cpu0.icache.demand_mshr_misses::total 590 # number of demand (read+write) MSHR misses 530system.cpu0.icache.overall_mshr_misses::cpu0.inst 590 # number of overall MSHR misses 531system.cpu0.icache.overall_mshr_misses::total 590 # number of overall MSHR misses 532system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21154500 # number of ReadReq MSHR miss cycles 533system.cpu0.icache.ReadReq_mshr_miss_latency::total 21154500 # number of ReadReq MSHR miss cycles 534system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21154500 # number of demand (read+write) MSHR miss cycles 535system.cpu0.icache.demand_mshr_miss_latency::total 21154500 # number of demand (read+write) MSHR miss cycles 536system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21154500 # number of overall MSHR miss cycles 537system.cpu0.icache.overall_mshr_miss_latency::total 21154500 # number of overall MSHR miss cycles 538system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for ReadReq accesses 539system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.099898 # mshr miss rate for ReadReq accesses 540system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for demand accesses 541system.cpu0.icache.demand_mshr_miss_rate::total 0.099898 # mshr miss rate for demand accesses 542system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for overall accesses 543system.cpu0.icache.overall_mshr_miss_rate::total 0.099898 # mshr miss rate for overall accesses 544system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average ReadReq mshr miss latency 545system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 35855.084746 # average ReadReq mshr miss latency 546system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average overall mshr miss latency 547system.cpu0.icache.demand_avg_mshr_miss_latency::total 35855.084746 # average overall mshr miss latency 548system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average overall mshr miss latency 549system.cpu0.icache.overall_avg_mshr_miss_latency::total 35855.084746 # average overall mshr miss latency 550system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 551system.cpu0.dcache.replacements 2 # number of replacements 552system.cpu0.dcache.tagsinuse 143.429999 # Cycle average of tags in use 553system.cpu0.dcache.total_refs 153854 # Total number of references to valid blocks. 554system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. 555system.cpu0.dcache.avg_refs 905.023529 # Average number of references to valid blocks. 556system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 557system.cpu0.dcache.occ_blocks::cpu0.data 143.429999 # Average occupied blocks per requestor 558system.cpu0.dcache.occ_percent::cpu0.data 0.280137 # Average percentage of cache occupancy 559system.cpu0.dcache.occ_percent::total 0.280137 # Average percentage of cache occupancy 560system.cpu0.dcache.ReadReq_hits::cpu0.data 78105 # number of ReadReq hits 561system.cpu0.dcache.ReadReq_hits::total 78105 # number of ReadReq hits 562system.cpu0.dcache.WriteReq_hits::cpu0.data 75839 # number of WriteReq hits 563system.cpu0.dcache.WriteReq_hits::total 75839 # number of WriteReq hits 564system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits 565system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits 566system.cpu0.dcache.demand_hits::cpu0.data 153944 # number of demand (read+write) hits 567system.cpu0.dcache.demand_hits::total 153944 # number of demand (read+write) hits 568system.cpu0.dcache.overall_hits::cpu0.data 153944 # number of overall hits 569system.cpu0.dcache.overall_hits::total 153944 # number of overall hits 570system.cpu0.dcache.ReadReq_misses::cpu0.data 475 # number of ReadReq misses 571system.cpu0.dcache.ReadReq_misses::total 475 # number of ReadReq misses 572system.cpu0.dcache.WriteReq_misses::cpu0.data 543 # number of WriteReq misses 573system.cpu0.dcache.WriteReq_misses::total 543 # number of WriteReq misses 574system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses 575system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses 576system.cpu0.dcache.demand_misses::cpu0.data 1018 # number of demand (read+write) misses 577system.cpu0.dcache.demand_misses::total 1018 # number of demand (read+write) misses 578system.cpu0.dcache.overall_misses::cpu0.data 1018 # number of overall misses 579system.cpu0.dcache.overall_misses::total 1018 # number of overall misses 580system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11909000 # number of ReadReq miss cycles 581system.cpu0.dcache.ReadReq_miss_latency::total 11909000 # number of ReadReq miss cycles 582system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24675495 # number of WriteReq miss cycles 583system.cpu0.dcache.WriteReq_miss_latency::total 24675495 # number of WriteReq miss cycles 584system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 605500 # number of SwapReq miss cycles 585system.cpu0.dcache.SwapReq_miss_latency::total 605500 # number of SwapReq miss cycles 586system.cpu0.dcache.demand_miss_latency::cpu0.data 36584495 # number of demand (read+write) miss cycles 587system.cpu0.dcache.demand_miss_latency::total 36584495 # number of demand (read+write) miss cycles 588system.cpu0.dcache.overall_miss_latency::cpu0.data 36584495 # number of overall miss cycles 589system.cpu0.dcache.overall_miss_latency::total 36584495 # number of overall miss cycles 590system.cpu0.dcache.ReadReq_accesses::cpu0.data 78580 # number of ReadReq accesses(hits+misses) 591system.cpu0.dcache.ReadReq_accesses::total 78580 # number of ReadReq accesses(hits+misses) 592system.cpu0.dcache.WriteReq_accesses::cpu0.data 76382 # number of WriteReq accesses(hits+misses) 593system.cpu0.dcache.WriteReq_accesses::total 76382 # number of WriteReq accesses(hits+misses) 594system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 595system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 596system.cpu0.dcache.demand_accesses::cpu0.data 154962 # number of demand (read+write) accesses 597system.cpu0.dcache.demand_accesses::total 154962 # number of demand (read+write) accesses 598system.cpu0.dcache.overall_accesses::cpu0.data 154962 # number of overall (read+write) accesses 599system.cpu0.dcache.overall_accesses::total 154962 # number of overall (read+write) accesses 600system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006045 # miss rate for ReadReq accesses 601system.cpu0.dcache.ReadReq_miss_rate::total 0.006045 # miss rate for ReadReq accesses 602system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007109 # miss rate for WriteReq accesses 603system.cpu0.dcache.WriteReq_miss_rate::total 0.007109 # miss rate for WriteReq accesses 604system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses 605system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses 606system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006569 # miss rate for demand accesses 607system.cpu0.dcache.demand_miss_rate::total 0.006569 # miss rate for demand accesses 608system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006569 # miss rate for overall accesses 609system.cpu0.dcache.overall_miss_rate::total 0.006569 # miss rate for overall accesses 610system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25071.578947 # average ReadReq miss latency 611system.cpu0.dcache.ReadReq_avg_miss_latency::total 25071.578947 # average ReadReq miss latency 612system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45442.900552 # average WriteReq miss latency 613system.cpu0.dcache.WriteReq_avg_miss_latency::total 45442.900552 # average WriteReq miss latency 614system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28833.333333 # average SwapReq miss latency 615system.cpu0.dcache.SwapReq_avg_miss_latency::total 28833.333333 # average SwapReq miss latency 616system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency 617system.cpu0.dcache.demand_avg_miss_latency::total 35937.617878 # average overall miss latency 618system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency 619system.cpu0.dcache.overall_avg_miss_latency::total 35937.617878 # average overall miss latency 620system.cpu0.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked 621system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 622system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked 623system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 624system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.142857 # average number of cycles each access was blocked 625system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 626system.cpu0.dcache.fast_writes 0 # number of fast writes performed 627system.cpu0.dcache.cache_copies 0 # number of cache copies performed 628system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 629system.cpu0.dcache.writebacks::total 1 # number of writebacks 630system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits 631system.cpu0.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits 632system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits 633system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits 634system.cpu0.dcache.demand_mshr_hits::cpu0.data 660 # number of demand (read+write) MSHR hits 635system.cpu0.dcache.demand_mshr_hits::total 660 # number of demand (read+write) MSHR hits 636system.cpu0.dcache.overall_mshr_hits::cpu0.data 660 # number of overall MSHR hits 637system.cpu0.dcache.overall_mshr_hits::total 660 # number of overall MSHR hits 638system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses 639system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses 640system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 170 # number of WriteReq MSHR misses 641system.cpu0.dcache.WriteReq_mshr_misses::total 170 # number of WriteReq MSHR misses 642system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses 643system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses 644system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses 645system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses 646system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses 647system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses 648system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5409500 # number of ReadReq MSHR miss cycles 649system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5409500 # number of ReadReq MSHR miss cycles 650system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5718500 # number of WriteReq MSHR miss cycles 651system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5718500 # number of WriteReq MSHR miss cycles 652system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 563500 # number of SwapReq MSHR miss cycles 653system.cpu0.dcache.SwapReq_mshr_miss_latency::total 563500 # number of SwapReq MSHR miss cycles 654system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11128000 # number of demand (read+write) MSHR miss cycles 655system.cpu0.dcache.demand_mshr_miss_latency::total 11128000 # number of demand (read+write) MSHR miss cycles 656system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11128000 # number of overall MSHR miss cycles 657system.cpu0.dcache.overall_mshr_miss_latency::total 11128000 # number of overall MSHR miss cycles 658system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for ReadReq accesses 659system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002392 # mshr miss rate for ReadReq accesses 660system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002226 # mshr miss rate for WriteReq accesses 661system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002226 # mshr miss rate for WriteReq accesses 662system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses 663system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses 664system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for demand accesses 665system.cpu0.dcache.demand_mshr_miss_rate::total 0.002310 # mshr miss rate for demand accesses 666system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for overall accesses 667system.cpu0.dcache.overall_mshr_miss_rate::total 0.002310 # mshr miss rate for overall accesses 668system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28773.936170 # average ReadReq mshr miss latency 669system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28773.936170 # average ReadReq mshr miss latency 670system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33638.235294 # average WriteReq mshr miss latency 671system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33638.235294 # average WriteReq mshr miss latency 672system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26833.333333 # average SwapReq mshr miss latency 673system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26833.333333 # average SwapReq mshr miss latency 674system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency 675system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency 676system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency 677system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency 678system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 679system.cpu1.branchPred.lookups 58098 # Number of BP lookups 680system.cpu1.branchPred.condPredicted 55415 # Number of conditional branches predicted 681system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect 682system.cpu1.branchPred.BTBLookups 51986 # Number of BTB lookups 683system.cpu1.branchPred.BTBHits 51313 # Number of BTB hits 684system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 685system.cpu1.branchPred.BTBHitPct 98.705421 # BTB Hit Percentage 686system.cpu1.branchPred.usedRAS 648 # Number of times the RAS was used to get a target. 687system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 688system.cpu1.numCycles 174790 # number of cpu cycles simulated 689system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 690system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 691system.cpu1.fetch.icacheStallCycles 24349 # Number of cycles fetch is stalled on an Icache miss 692system.cpu1.fetch.Insts 331605 # Number of instructions fetch has processed 693system.cpu1.fetch.Branches 58098 # Number of branches that fetch encountered 694system.cpu1.fetch.predictedBranches 51961 # Number of branches that fetch has predicted taken 695system.cpu1.fetch.Cycles 112635 # Number of cycles fetch has run and was not squashing or blocked 696system.cpu1.fetch.SquashCycles 3690 # Number of cycles fetch has spent squashing 697system.cpu1.fetch.BlockedCycles 23829 # Number of cycles fetch has spent blocked 698system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 699system.cpu1.fetch.NoActiveThreadStallCycles 6397 # Number of stall cycles due to no active thread to fetch from 700system.cpu1.fetch.PendingTrapStallCycles 795 # Number of stall cycles due to pending traps 701system.cpu1.fetch.CacheLines 15584 # Number of cache lines fetched 702system.cpu1.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed 703system.cpu1.fetch.rateDist::samples 170350 # Number of instructions fetched each cycle (Total) 704system.cpu1.fetch.rateDist::mean 1.946610 # Number of instructions fetched each cycle (Total) 705system.cpu1.fetch.rateDist::stdev 2.217345 # Number of instructions fetched each cycle (Total) 706system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 707system.cpu1.fetch.rateDist::0 57715 33.88% 33.88% # Number of instructions fetched each cycle (Total) 708system.cpu1.fetch.rateDist::1 56197 32.99% 66.87% # Number of instructions fetched each cycle (Total) 709system.cpu1.fetch.rateDist::2 4087 2.40% 69.27% # Number of instructions fetched each cycle (Total) 710system.cpu1.fetch.rateDist::3 3199 1.88% 71.15% # Number of instructions fetched each cycle (Total) 711system.cpu1.fetch.rateDist::4 641 0.38% 71.52% # Number of instructions fetched each cycle (Total) 712system.cpu1.fetch.rateDist::5 43239 25.38% 96.91% # Number of instructions fetched each cycle (Total) 713system.cpu1.fetch.rateDist::6 1271 0.75% 97.65% # Number of instructions fetched each cycle (Total) 714system.cpu1.fetch.rateDist::7 756 0.44% 98.10% # Number of instructions fetched each cycle (Total) 715system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total) 716system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 717system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 718system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 719system.cpu1.fetch.rateDist::total 170350 # Number of instructions fetched each cycle (Total) 720system.cpu1.fetch.branchRate 0.332387 # Number of branch fetches per cycle 721system.cpu1.fetch.rate 1.897162 # Number of inst fetches per cycle 722system.cpu1.decode.IdleCycles 27574 # Number of cycles decode is idle 723system.cpu1.decode.BlockedCycles 22245 # Number of cycles decode is blocked 724system.cpu1.decode.RunCycles 108585 # Number of cycles decode is running 725system.cpu1.decode.UnblockCycles 3208 # Number of cycles decode is unblocking 726system.cpu1.decode.SquashCycles 2341 # Number of cycles decode is squashing 727system.cpu1.decode.DecodedInsts 328108 # Number of instructions handled by decode 728system.cpu1.rename.SquashCycles 2341 # Number of cycles rename is squashing 729system.cpu1.rename.IdleCycles 28283 # Number of cycles rename is idle 730system.cpu1.rename.BlockCycles 9804 # Number of cycles rename is blocking 731system.cpu1.rename.serializeStallCycles 11660 # count of cycles rename stalled for serializing inst 732system.cpu1.rename.RunCycles 105676 # Number of cycles rename is running 733system.cpu1.rename.UnblockCycles 6189 # Number of cycles rename is unblocking 734system.cpu1.rename.RenamedInsts 325946 # Number of instructions processed by rename 735system.cpu1.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full 736system.cpu1.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full 737system.cpu1.rename.RenamedOperands 230320 # Number of destination operands rename has renamed 738system.cpu1.rename.RenameLookups 636644 # Number of register rename lookups that rename has made 739system.cpu1.rename.int_rename_lookups 636644 # Number of integer rename lookups 740system.cpu1.rename.CommittedMaps 217343 # Number of HB maps that are committed 741system.cpu1.rename.UndoneMaps 12977 # Number of HB maps that are undone due to squashing 742system.cpu1.rename.serializingInsts 1083 # count of serializing insts renamed 743system.cpu1.rename.tempSerializingInsts 1203 # count of temporary serializing insts renamed 744system.cpu1.rename.skidInsts 8803 # count of insts added to the skid buffer 745system.cpu1.memDep0.insertedLoads 95013 # Number of loads inserted to the mem dependence unit. 746system.cpu1.memDep0.insertedStores 46485 # Number of stores inserted to the mem dependence unit. 747system.cpu1.memDep0.conflictingLoads 44692 # Number of conflicting loads. 748system.cpu1.memDep0.conflictingStores 41453 # Number of conflicting stores. 749system.cpu1.iq.iqInstsAdded 273191 # Number of instructions added to the IQ (excludes non-spec) 750system.cpu1.iq.iqNonSpecInstsAdded 4270 # Number of non-speculative instructions added to the IQ 751system.cpu1.iq.iqInstsIssued 273407 # Number of instructions issued 752system.cpu1.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued 753system.cpu1.iq.iqSquashedInstsExamined 10726 # Number of squashed instructions iterated over during squash; mainly for profiling 754system.cpu1.iq.iqSquashedOperandsExamined 10333 # Number of squashed operands that are examined and possibly removed from graph 755system.cpu1.iq.iqSquashedNonSpecRemoved 504 # Number of squashed non-spec instructions that were removed 756system.cpu1.iq.issued_per_cycle::samples 170350 # Number of insts issued each cycle 757system.cpu1.iq.issued_per_cycle::mean 1.604972 # Number of insts issued each cycle 758system.cpu1.iq.issued_per_cycle::stdev 1.301874 # Number of insts issued each cycle 759system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 760system.cpu1.iq.issued_per_cycle::0 54964 32.27% 32.27% # Number of insts issued each cycle 761system.cpu1.iq.issued_per_cycle::1 16569 9.73% 41.99% # Number of insts issued each cycle 762system.cpu1.iq.issued_per_cycle::2 46599 27.35% 69.35% # Number of insts issued each cycle 763system.cpu1.iq.issued_per_cycle::3 47325 27.78% 97.13% # Number of insts issued each cycle 764system.cpu1.iq.issued_per_cycle::4 3328 1.95% 99.08% # Number of insts issued each cycle 765system.cpu1.iq.issued_per_cycle::5 1208 0.71% 99.79% # Number of insts issued each cycle 766system.cpu1.iq.issued_per_cycle::6 245 0.14% 99.93% # Number of insts issued each cycle 767system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle 768system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle 769system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 770system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 771system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 772system.cpu1.iq.issued_per_cycle::total 170350 # Number of insts issued each cycle 773system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 774system.cpu1.iq.fu_full::IntAlu 17 5.69% 5.69% # attempts to use FU when none available 775system.cpu1.iq.fu_full::IntMult 0 0.00% 5.69% # attempts to use FU when none available 776system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.69% # attempts to use FU when none available 777system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.69% # attempts to use FU when none available 778system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.69% # attempts to use FU when none available 779system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.69% # attempts to use FU when none available 780system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.69% # attempts to use FU when none available 781system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.69% # attempts to use FU when none available 782system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.69% # attempts to use FU when none available 783system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.69% # attempts to use FU when none available 784system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.69% # attempts to use FU when none available 785system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.69% # attempts to use FU when none available 786system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.69% # attempts to use FU when none available 787system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.69% # attempts to use FU when none available 788system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.69% # attempts to use FU when none available 789system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.69% # attempts to use FU when none available 790system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.69% # attempts to use FU when none available 791system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.69% # attempts to use FU when none available 792system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.69% # attempts to use FU when none available 793system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.69% # attempts to use FU when none available 794system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.69% # attempts to use FU when none available 795system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.69% # attempts to use FU when none available 796system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.69% # attempts to use FU when none available 797system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.69% # attempts to use FU when none available 798system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.69% # attempts to use FU when none available 799system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.69% # attempts to use FU when none available 800system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.69% # attempts to use FU when none available 801system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.69% # attempts to use FU when none available 802system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.69% # attempts to use FU when none available 803system.cpu1.iq.fu_full::MemRead 72 24.08% 29.77% # attempts to use FU when none available 804system.cpu1.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available 805system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 806system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 807system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 808system.cpu1.iq.FU_type_0::IntAlu 130168 47.61% 47.61% # Type of FU issued 809system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.61% # Type of FU issued 810system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.61% # Type of FU issued 811system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.61% # Type of FU issued 812system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.61% # Type of FU issued 813system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.61% # Type of FU issued 814system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.61% # Type of FU issued 815system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.61% # Type of FU issued 816system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.61% # Type of FU issued 817system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.61% # Type of FU issued 818system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.61% # Type of FU issued 819system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.61% # Type of FU issued 820system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.61% # Type of FU issued 821system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.61% # Type of FU issued 822system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.61% # Type of FU issued 823system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.61% # Type of FU issued 824system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.61% # Type of FU issued 825system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.61% # Type of FU issued 826system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.61% # Type of FU issued 827system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.61% # Type of FU issued 828system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.61% # Type of FU issued 829system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.61% # Type of FU issued 830system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.61% # Type of FU issued 831system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.61% # Type of FU issued 832system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.61% # Type of FU issued 833system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.61% # Type of FU issued 834system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.61% # Type of FU issued 835system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.61% # Type of FU issued 836system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.61% # Type of FU issued 837system.cpu1.iq.FU_type_0::MemRead 97443 35.64% 83.25% # Type of FU issued 838system.cpu1.iq.FU_type_0::MemWrite 45796 16.75% 100.00% # Type of FU issued 839system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 840system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 841system.cpu1.iq.FU_type_0::total 273407 # Type of FU issued 842system.cpu1.iq.rate 1.564203 # Inst issue rate 843system.cpu1.iq.fu_busy_cnt 299 # FU busy when requested 844system.cpu1.iq.fu_busy_rate 0.001094 # FU busy rate (busy events/executed inst) 845system.cpu1.iq.int_inst_queue_reads 717543 # Number of integer instruction queue reads 846system.cpu1.iq.int_inst_queue_writes 288232 # Number of integer instruction queue writes 847system.cpu1.iq.int_inst_queue_wakeup_accesses 271609 # Number of integer instruction queue wakeup accesses 848system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 849system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 850system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 851system.cpu1.iq.int_alu_accesses 273706 # Number of integer alu accesses 852system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 853system.cpu1.iew.lsq.thread0.forwLoads 41212 # Number of loads that had data forwarded from stores 854system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 855system.cpu1.iew.lsq.thread0.squashedLoads 2369 # Number of loads squashed 856system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 857system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations 858system.cpu1.iew.lsq.thread0.squashedStores 1440 # Number of stores squashed 859system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 860system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 861system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 862system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 863system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 864system.cpu1.iew.iewSquashCycles 2341 # Number of cycles IEW is squashing 865system.cpu1.iew.iewBlockCycles 1392 # Number of cycles IEW is blocking 866system.cpu1.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking 867system.cpu1.iew.iewDispatchedInsts 323061 # Number of instructions dispatched to IQ 868system.cpu1.iew.iewDispSquashedInsts 370 # Number of squashed instructions skipped by dispatch 869system.cpu1.iew.iewDispLoadInsts 95013 # Number of dispatched load instructions 870system.cpu1.iew.iewDispStoreInsts 46485 # Number of dispatched store instructions 871system.cpu1.iew.iewDispNonSpecInsts 1042 # Number of dispatched non-speculative instructions 872system.cpu1.iew.iewIQFullEvents 67 # Number of times the IQ has become full, causing a stall 873system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 874system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations 875system.cpu1.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly 876system.cpu1.iew.predictedNotTakenIncorrect 928 # Number of branches that were predicted not taken incorrectly 877system.cpu1.iew.branchMispredicts 1384 # Number of branch mispredicts detected at execute 878system.cpu1.iew.iewExecutedInsts 272209 # Number of executed instructions 879system.cpu1.iew.iewExecLoadInsts 94088 # Number of load instructions executed 880system.cpu1.iew.iewExecSquashedInsts 1198 # Number of squashed instructions skipped in execute 881system.cpu1.iew.exec_swp 0 # number of swp insts executed 882system.cpu1.iew.exec_nop 45600 # number of nop insts executed 883system.cpu1.iew.exec_refs 139806 # number of memory reference insts executed 884system.cpu1.iew.exec_branches 54914 # Number of branches executed 885system.cpu1.iew.exec_stores 45718 # Number of stores executed 886system.cpu1.iew.exec_rate 1.557349 # Inst execution rate 887system.cpu1.iew.wb_sent 271881 # cumulative count of insts sent to commit 888system.cpu1.iew.wb_count 271609 # cumulative count of insts written-back 889system.cpu1.iew.wb_producers 156621 # num instructions producing a value 890system.cpu1.iew.wb_consumers 161297 # num instructions consuming a value 891system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 892system.cpu1.iew.wb_rate 1.553916 # insts written-back per cycle 893system.cpu1.iew.wb_fanout 0.971010 # average fanout of values written-back 894system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 895system.cpu1.commit.commitSquashedInsts 12317 # The number of squashed insts skipped by commit 896system.cpu1.commit.commitNonSpecStalls 3766 # The number of times commit has been forced to stall to communicate backwards 897system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted 898system.cpu1.commit.committed_per_cycle::samples 161612 # Number of insts commited each cycle 899system.cpu1.commit.committed_per_cycle::mean 1.922772 # Number of insts commited each cycle 900system.cpu1.commit.committed_per_cycle::stdev 2.097017 # Number of insts commited each cycle 901system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 902system.cpu1.commit.committed_per_cycle::0 52280 32.35% 32.35% # Number of insts commited each cycle 903system.cpu1.commit.committed_per_cycle::1 52948 32.76% 65.11% # Number of insts commited each cycle 904system.cpu1.commit.committed_per_cycle::2 6058 3.75% 68.86% # Number of insts commited each cycle 905system.cpu1.commit.committed_per_cycle::3 4700 2.91% 71.77% # Number of insts commited each cycle 906system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.74% # Number of insts commited each cycle 907system.cpu1.commit.committed_per_cycle::5 41692 25.80% 98.54% # Number of insts commited each cycle 908system.cpu1.commit.committed_per_cycle::6 528 0.33% 98.86% # Number of insts commited each cycle 909system.cpu1.commit.committed_per_cycle::7 1013 0.63% 99.49% # Number of insts commited each cycle 910system.cpu1.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle 911system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 912system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 913system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 914system.cpu1.commit.committed_per_cycle::total 161612 # Number of insts commited each cycle 915system.cpu1.commit.committedInsts 310743 # Number of instructions committed 916system.cpu1.commit.committedOps 310743 # Number of ops (including micro ops) committed 917system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 918system.cpu1.commit.refs 137689 # Number of memory references committed 919system.cpu1.commit.loads 92644 # Number of loads committed 920system.cpu1.commit.membars 3055 # Number of memory barriers committed 921system.cpu1.commit.branches 54067 # Number of branches committed 922system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. 923system.cpu1.commit.int_insts 213879 # Number of committed integer instructions. 924system.cpu1.commit.function_calls 322 # Number of function calls committed. 925system.cpu1.commit.bw_lim_events 822 # number cycles where commit BW limit reached 926system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 927system.cpu1.rob.rob_reads 483263 # The number of ROB reads 928system.cpu1.rob.rob_writes 648465 # The number of ROB writes 929system.cpu1.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself 930system.cpu1.idleCycles 4440 # Total number of cycles that the CPU has spent unscheduled due to idling 931system.cpu1.quiesceCycles 36812 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 932system.cpu1.committedInsts 262828 # Number of Instructions Simulated 933system.cpu1.committedOps 262828 # Number of Ops (including micro ops) Simulated 934system.cpu1.committedInsts_total 262828 # Number of Instructions Simulated 935system.cpu1.cpi 0.665036 # CPI: Cycles Per Instruction 936system.cpu1.cpi_total 0.665036 # CPI: Total CPI of All Threads 937system.cpu1.ipc 1.503679 # IPC: Instructions Per Cycle 938system.cpu1.ipc_total 1.503679 # IPC: Total IPC of All Threads 939system.cpu1.int_regfile_reads 478110 # number of integer regfile reads 940system.cpu1.int_regfile_writes 222397 # number of integer regfile writes 941system.cpu1.fp_regfile_writes 64 # number of floating regfile writes 942system.cpu1.misc_regfile_reads 141404 # number of misc regfile reads 943system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 944system.cpu1.icache.replacements 317 # number of replacements 945system.cpu1.icache.tagsinuse 85.239071 # Cycle average of tags in use 946system.cpu1.icache.total_refs 15102 # Total number of references to valid blocks. 947system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. 948system.cpu1.icache.avg_refs 35.534118 # Average number of references to valid blocks. 949system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 950system.cpu1.icache.occ_blocks::cpu1.inst 85.239071 # Average occupied blocks per requestor 951system.cpu1.icache.occ_percent::cpu1.inst 0.166483 # Average percentage of cache occupancy 952system.cpu1.icache.occ_percent::total 0.166483 # Average percentage of cache occupancy 953system.cpu1.icache.ReadReq_hits::cpu1.inst 15102 # number of ReadReq hits 954system.cpu1.icache.ReadReq_hits::total 15102 # number of ReadReq hits 955system.cpu1.icache.demand_hits::cpu1.inst 15102 # number of demand (read+write) hits 956system.cpu1.icache.demand_hits::total 15102 # number of demand (read+write) hits 957system.cpu1.icache.overall_hits::cpu1.inst 15102 # number of overall hits 958system.cpu1.icache.overall_hits::total 15102 # number of overall hits 959system.cpu1.icache.ReadReq_misses::cpu1.inst 482 # number of ReadReq misses 960system.cpu1.icache.ReadReq_misses::total 482 # number of ReadReq misses 961system.cpu1.icache.demand_misses::cpu1.inst 482 # number of demand (read+write) misses 962system.cpu1.icache.demand_misses::total 482 # number of demand (read+write) misses 963system.cpu1.icache.overall_misses::cpu1.inst 482 # number of overall misses 964system.cpu1.icache.overall_misses::total 482 # number of overall misses 965system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10460500 # number of ReadReq miss cycles 966system.cpu1.icache.ReadReq_miss_latency::total 10460500 # number of ReadReq miss cycles 967system.cpu1.icache.demand_miss_latency::cpu1.inst 10460500 # number of demand (read+write) miss cycles 968system.cpu1.icache.demand_miss_latency::total 10460500 # number of demand (read+write) miss cycles 969system.cpu1.icache.overall_miss_latency::cpu1.inst 10460500 # number of overall miss cycles 970system.cpu1.icache.overall_miss_latency::total 10460500 # number of overall miss cycles 971system.cpu1.icache.ReadReq_accesses::cpu1.inst 15584 # number of ReadReq accesses(hits+misses) 972system.cpu1.icache.ReadReq_accesses::total 15584 # number of ReadReq accesses(hits+misses) 973system.cpu1.icache.demand_accesses::cpu1.inst 15584 # number of demand (read+write) accesses 974system.cpu1.icache.demand_accesses::total 15584 # number of demand (read+write) accesses 975system.cpu1.icache.overall_accesses::cpu1.inst 15584 # number of overall (read+write) accesses 976system.cpu1.icache.overall_accesses::total 15584 # number of overall (read+write) accesses 977system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030929 # miss rate for ReadReq accesses 978system.cpu1.icache.ReadReq_miss_rate::total 0.030929 # miss rate for ReadReq accesses 979system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030929 # miss rate for demand accesses 980system.cpu1.icache.demand_miss_rate::total 0.030929 # miss rate for demand accesses 981system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030929 # miss rate for overall accesses 982system.cpu1.icache.overall_miss_rate::total 0.030929 # miss rate for overall accesses 983system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21702.282158 # average ReadReq miss latency 984system.cpu1.icache.ReadReq_avg_miss_latency::total 21702.282158 # average ReadReq miss latency 985system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency 986system.cpu1.icache.demand_avg_miss_latency::total 21702.282158 # average overall miss latency 987system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency 988system.cpu1.icache.overall_avg_miss_latency::total 21702.282158 # average overall miss latency 989system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked 990system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 991system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked 992system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 993system.cpu1.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked 994system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 995system.cpu1.icache.fast_writes 0 # number of fast writes performed 996system.cpu1.icache.cache_copies 0 # number of cache copies performed 997system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 57 # number of ReadReq MSHR hits 998system.cpu1.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits 999system.cpu1.icache.demand_mshr_hits::cpu1.inst 57 # number of demand (read+write) MSHR hits 1000system.cpu1.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits 1001system.cpu1.icache.overall_mshr_hits::cpu1.inst 57 # number of overall MSHR hits 1002system.cpu1.icache.overall_mshr_hits::total 57 # number of overall MSHR hits 1003system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses 1004system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses 1005system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses 1006system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses 1007system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses 1008system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses 1009system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8302000 # number of ReadReq MSHR miss cycles 1010system.cpu1.icache.ReadReq_mshr_miss_latency::total 8302000 # number of ReadReq MSHR miss cycles 1011system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8302000 # number of demand (read+write) MSHR miss cycles 1012system.cpu1.icache.demand_mshr_miss_latency::total 8302000 # number of demand (read+write) MSHR miss cycles 1013system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8302000 # number of overall MSHR miss cycles 1014system.cpu1.icache.overall_mshr_miss_latency::total 8302000 # number of overall MSHR miss cycles 1015system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027272 # mshr miss rate for ReadReq accesses 1016system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027272 # mshr miss rate for ReadReq accesses 1017system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027272 # mshr miss rate for demand accesses 1018system.cpu1.icache.demand_mshr_miss_rate::total 0.027272 # mshr miss rate for demand accesses 1019system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027272 # mshr miss rate for overall accesses 1020system.cpu1.icache.overall_mshr_miss_rate::total 0.027272 # mshr miss rate for overall accesses 1021system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19534.117647 # average ReadReq mshr miss latency 1022system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19534.117647 # average ReadReq mshr miss latency 1023system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19534.117647 # average overall mshr miss latency 1024system.cpu1.icache.demand_avg_mshr_miss_latency::total 19534.117647 # average overall mshr miss latency 1025system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19534.117647 # average overall mshr miss latency 1026system.cpu1.icache.overall_avg_mshr_miss_latency::total 19534.117647 # average overall mshr miss latency 1027system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1028system.cpu1.dcache.replacements 0 # number of replacements 1029system.cpu1.dcache.tagsinuse 27.071497 # Cycle average of tags in use 1030system.cpu1.dcache.total_refs 51063 # Total number of references to valid blocks. 1031system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. 1032system.cpu1.dcache.avg_refs 1823.678571 # Average number of references to valid blocks. 1033system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1034system.cpu1.dcache.occ_blocks::cpu1.data 27.071497 # Average occupied blocks per requestor 1035system.cpu1.dcache.occ_percent::cpu1.data 0.052874 # Average percentage of cache occupancy 1036system.cpu1.dcache.occ_percent::total 0.052874 # Average percentage of cache occupancy 1037system.cpu1.dcache.ReadReq_hits::cpu1.data 52421 # number of ReadReq hits 1038system.cpu1.dcache.ReadReq_hits::total 52421 # number of ReadReq hits 1039system.cpu1.dcache.WriteReq_hits::cpu1.data 44839 # number of WriteReq hits 1040system.cpu1.dcache.WriteReq_hits::total 44839 # number of WriteReq hits 1041system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits 1042system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits 1043system.cpu1.dcache.demand_hits::cpu1.data 97260 # number of demand (read+write) hits 1044system.cpu1.dcache.demand_hits::total 97260 # number of demand (read+write) hits 1045system.cpu1.dcache.overall_hits::cpu1.data 97260 # number of overall hits 1046system.cpu1.dcache.overall_hits::total 97260 # number of overall hits 1047system.cpu1.dcache.ReadReq_misses::cpu1.data 438 # number of ReadReq misses 1048system.cpu1.dcache.ReadReq_misses::total 438 # number of ReadReq misses 1049system.cpu1.dcache.WriteReq_misses::cpu1.data 141 # number of WriteReq misses 1050system.cpu1.dcache.WriteReq_misses::total 141 # number of WriteReq misses 1051system.cpu1.dcache.SwapReq_misses::cpu1.data 54 # number of SwapReq misses 1052system.cpu1.dcache.SwapReq_misses::total 54 # number of SwapReq misses 1053system.cpu1.dcache.demand_misses::cpu1.data 579 # number of demand (read+write) misses 1054system.cpu1.dcache.demand_misses::total 579 # number of demand (read+write) misses 1055system.cpu1.dcache.overall_misses::cpu1.data 579 # number of overall misses 1056system.cpu1.dcache.overall_misses::total 579 # number of overall misses 1057system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8533500 # number of ReadReq miss cycles 1058system.cpu1.dcache.ReadReq_miss_latency::total 8533500 # number of ReadReq miss cycles 1059system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3160000 # number of WriteReq miss cycles 1060system.cpu1.dcache.WriteReq_miss_latency::total 3160000 # number of WriteReq miss cycles 1061system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 510000 # number of SwapReq miss cycles 1062system.cpu1.dcache.SwapReq_miss_latency::total 510000 # number of SwapReq miss cycles 1063system.cpu1.dcache.demand_miss_latency::cpu1.data 11693500 # number of demand (read+write) miss cycles 1064system.cpu1.dcache.demand_miss_latency::total 11693500 # number of demand (read+write) miss cycles 1065system.cpu1.dcache.overall_miss_latency::cpu1.data 11693500 # number of overall miss cycles 1066system.cpu1.dcache.overall_miss_latency::total 11693500 # number of overall miss cycles 1067system.cpu1.dcache.ReadReq_accesses::cpu1.data 52859 # number of ReadReq accesses(hits+misses) 1068system.cpu1.dcache.ReadReq_accesses::total 52859 # number of ReadReq accesses(hits+misses) 1069system.cpu1.dcache.WriteReq_accesses::cpu1.data 44980 # number of WriteReq accesses(hits+misses) 1070system.cpu1.dcache.WriteReq_accesses::total 44980 # number of WriteReq accesses(hits+misses) 1071system.cpu1.dcache.SwapReq_accesses::cpu1.data 65 # number of SwapReq accesses(hits+misses) 1072system.cpu1.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) 1073system.cpu1.dcache.demand_accesses::cpu1.data 97839 # number of demand (read+write) accesses 1074system.cpu1.dcache.demand_accesses::total 97839 # number of demand (read+write) accesses 1075system.cpu1.dcache.overall_accesses::cpu1.data 97839 # number of overall (read+write) accesses 1076system.cpu1.dcache.overall_accesses::total 97839 # number of overall (read+write) accesses 1077system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008286 # miss rate for ReadReq accesses 1078system.cpu1.dcache.ReadReq_miss_rate::total 0.008286 # miss rate for ReadReq accesses 1079system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003135 # miss rate for WriteReq accesses 1080system.cpu1.dcache.WriteReq_miss_rate::total 0.003135 # miss rate for WriteReq accesses 1081system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.830769 # miss rate for SwapReq accesses 1082system.cpu1.dcache.SwapReq_miss_rate::total 0.830769 # miss rate for SwapReq accesses 1083system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005918 # miss rate for demand accesses 1084system.cpu1.dcache.demand_miss_rate::total 0.005918 # miss rate for demand accesses 1085system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005918 # miss rate for overall accesses 1086system.cpu1.dcache.overall_miss_rate::total 0.005918 # miss rate for overall accesses 1087system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19482.876712 # average ReadReq miss latency 1088system.cpu1.dcache.ReadReq_avg_miss_latency::total 19482.876712 # average ReadReq miss latency 1089system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22411.347518 # average WriteReq miss latency 1090system.cpu1.dcache.WriteReq_avg_miss_latency::total 22411.347518 # average WriteReq miss latency 1091system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9444.444444 # average SwapReq miss latency 1092system.cpu1.dcache.SwapReq_avg_miss_latency::total 9444.444444 # average SwapReq miss latency 1093system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20196.027634 # average overall miss latency 1094system.cpu1.dcache.demand_avg_miss_latency::total 20196.027634 # average overall miss latency 1095system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20196.027634 # average overall miss latency 1096system.cpu1.dcache.overall_avg_miss_latency::total 20196.027634 # average overall miss latency 1097system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1098system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1099system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1100system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1101system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1102system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1103system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1104system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1105system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 286 # number of ReadReq MSHR hits 1106system.cpu1.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits 1107system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits 1108system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits 1109system.cpu1.dcache.demand_mshr_hits::cpu1.data 320 # number of demand (read+write) MSHR hits 1110system.cpu1.dcache.demand_mshr_hits::total 320 # number of demand (read+write) MSHR hits 1111system.cpu1.dcache.overall_mshr_hits::cpu1.data 320 # number of overall MSHR hits 1112system.cpu1.dcache.overall_mshr_hits::total 320 # number of overall MSHR hits 1113system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 152 # number of ReadReq MSHR misses 1114system.cpu1.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses 1115system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses 1116system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses 1117system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 54 # number of SwapReq MSHR misses 1118system.cpu1.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses 1119system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses 1120system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses 1121system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses 1122system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses 1123system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1798500 # number of ReadReq MSHR miss cycles 1124system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1798500 # number of ReadReq MSHR miss cycles 1125system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1487000 # number of WriteReq MSHR miss cycles 1126system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1487000 # number of WriteReq MSHR miss cycles 1127system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 402000 # number of SwapReq MSHR miss cycles 1128system.cpu1.dcache.SwapReq_mshr_miss_latency::total 402000 # number of SwapReq MSHR miss cycles 1129system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3285500 # number of demand (read+write) MSHR miss cycles 1130system.cpu1.dcache.demand_mshr_miss_latency::total 3285500 # number of demand (read+write) MSHR miss cycles 1131system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3285500 # number of overall MSHR miss cycles 1132system.cpu1.dcache.overall_mshr_miss_latency::total 3285500 # number of overall MSHR miss cycles 1133system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002876 # mshr miss rate for ReadReq accesses 1134system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002876 # mshr miss rate for ReadReq accesses 1135system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002379 # mshr miss rate for WriteReq accesses 1136system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002379 # mshr miss rate for WriteReq accesses 1137system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.830769 # mshr miss rate for SwapReq accesses 1138system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.830769 # mshr miss rate for SwapReq accesses 1139system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002647 # mshr miss rate for demand accesses 1140system.cpu1.dcache.demand_mshr_miss_rate::total 0.002647 # mshr miss rate for demand accesses 1141system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002647 # mshr miss rate for overall accesses 1142system.cpu1.dcache.overall_mshr_miss_rate::total 0.002647 # mshr miss rate for overall accesses 1143system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11832.236842 # average ReadReq mshr miss latency 1144system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11832.236842 # average ReadReq mshr miss latency 1145system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13897.196262 # average WriteReq mshr miss latency 1146system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13897.196262 # average WriteReq mshr miss latency 1147system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7444.444444 # average SwapReq mshr miss latency 1148system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7444.444444 # average SwapReq mshr miss latency 1149system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency 1150system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency 1151system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency 1152system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency 1153system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1154system.cpu2.branchPred.lookups 45099 # Number of BP lookups 1155system.cpu2.branchPred.condPredicted 42400 # Number of conditional branches predicted 1156system.cpu2.branchPred.condIncorrect 1262 # Number of conditional branches incorrect 1157system.cpu2.branchPred.BTBLookups 39025 # Number of BTB lookups 1158system.cpu2.branchPred.BTBHits 38304 # Number of BTB hits 1159system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1160system.cpu2.branchPred.BTBHitPct 98.152466 # BTB Hit Percentage 1161system.cpu2.branchPred.usedRAS 646 # Number of times the RAS was used to get a target. 1162system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 1163system.cpu2.numCycles 174459 # number of cpu cycles simulated 1164system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1165system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 1166system.cpu2.fetch.icacheStallCycles 32669 # Number of cycles fetch is stalled on an Icache miss 1167system.cpu2.fetch.Insts 244823 # Number of instructions fetch has processed 1168system.cpu2.fetch.Branches 45099 # Number of branches that fetch encountered 1169system.cpu2.fetch.predictedBranches 38950 # Number of branches that fetch has predicted taken 1170system.cpu2.fetch.Cycles 90929 # Number of cycles fetch has run and was not squashing or blocked 1171system.cpu2.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing 1172system.cpu2.fetch.BlockedCycles 39674 # Number of cycles fetch has spent blocked 1173system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1174system.cpu2.fetch.NoActiveThreadStallCycles 6379 # Number of stall cycles due to no active thread to fetch from 1175system.cpu2.fetch.PendingTrapStallCycles 712 # Number of stall cycles due to pending traps 1176system.cpu2.fetch.CacheLines 24269 # Number of cache lines fetched 1177system.cpu2.fetch.IcacheSquashes 265 # Number of outstanding Icache misses that were squashed 1178system.cpu2.fetch.rateDist::samples 172730 # Number of instructions fetched each cycle (Total) 1179system.cpu2.fetch.rateDist::mean 1.417374 # Number of instructions fetched each cycle (Total) 1180system.cpu2.fetch.rateDist::stdev 2.028063 # Number of instructions fetched each cycle (Total) 1181system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1182system.cpu2.fetch.rateDist::0 81801 47.36% 47.36% # Number of instructions fetched each cycle (Total) 1183system.cpu2.fetch.rateDist::1 47495 27.50% 74.85% # Number of instructions fetched each cycle (Total) 1184system.cpu2.fetch.rateDist::2 8404 4.87% 79.72% # Number of instructions fetched each cycle (Total) 1185system.cpu2.fetch.rateDist::3 3201 1.85% 81.57% # Number of instructions fetched each cycle (Total) 1186system.cpu2.fetch.rateDist::4 675 0.39% 81.96% # Number of instructions fetched each cycle (Total) 1187system.cpu2.fetch.rateDist::5 25947 15.02% 96.99% # Number of instructions fetched each cycle (Total) 1188system.cpu2.fetch.rateDist::6 1207 0.70% 97.68% # Number of instructions fetched each cycle (Total) 1189system.cpu2.fetch.rateDist::7 760 0.44% 98.12% # Number of instructions fetched each cycle (Total) 1190system.cpu2.fetch.rateDist::8 3240 1.88% 100.00% # Number of instructions fetched each cycle (Total) 1191system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1192system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1193system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1194system.cpu2.fetch.rateDist::total 172730 # Number of instructions fetched each cycle (Total) 1195system.cpu2.fetch.branchRate 0.258508 # Number of branch fetches per cycle 1196system.cpu2.fetch.rate 1.403327 # Number of inst fetches per cycle 1197system.cpu2.decode.IdleCycles 39762 # Number of cycles decode is idle 1198system.cpu2.decode.BlockedCycles 34129 # Number of cycles decode is blocked 1199system.cpu2.decode.RunCycles 82888 # Number of cycles decode is running 1200system.cpu2.decode.UnblockCycles 7209 # Number of cycles decode is unblocking 1201system.cpu2.decode.SquashCycles 2363 # Number of cycles decode is squashing 1202system.cpu2.decode.DecodedInsts 241309 # Number of instructions handled by decode 1203system.cpu2.rename.SquashCycles 2363 # Number of cycles rename is squashing 1204system.cpu2.rename.IdleCycles 40462 # Number of cycles rename is idle 1205system.cpu2.rename.BlockCycles 21352 # Number of cycles rename is blocking 1206system.cpu2.rename.serializeStallCycles 11989 # count of cycles rename stalled for serializing inst 1207system.cpu2.rename.RunCycles 75976 # Number of cycles rename is running 1208system.cpu2.rename.UnblockCycles 14209 # Number of cycles rename is unblocking 1209system.cpu2.rename.RenamedInsts 239275 # Number of instructions processed by rename 1210system.cpu2.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 1211system.cpu2.rename.LSQFullEvents 36 # Number of times rename has blocked due to LSQ full 1212system.cpu2.rename.RenamedOperands 165256 # Number of destination operands rename has renamed 1213system.cpu2.rename.RenameLookups 446077 # Number of register rename lookups that rename has made 1214system.cpu2.rename.int_rename_lookups 446077 # Number of integer rename lookups 1215system.cpu2.rename.CommittedMaps 152520 # Number of HB maps that are committed 1216system.cpu2.rename.UndoneMaps 12736 # Number of HB maps that are undone due to squashing 1217system.cpu2.rename.serializingInsts 1091 # count of serializing insts renamed 1218system.cpu2.rename.tempSerializingInsts 1215 # count of temporary serializing insts renamed 1219system.cpu2.rename.skidInsts 16777 # count of insts added to the skid buffer 1220system.cpu2.memDep0.insertedLoads 64738 # Number of loads inserted to the mem dependence unit. 1221system.cpu2.memDep0.insertedStores 29196 # Number of stores inserted to the mem dependence unit. 1222system.cpu2.memDep0.conflictingLoads 31698 # Number of conflicting loads. 1223system.cpu2.memDep0.conflictingStores 24168 # Number of conflicting stores. 1224system.cpu2.iq.iqInstsAdded 195168 # Number of instructions added to the IQ (excludes non-spec) 1225system.cpu2.iq.iqNonSpecInstsAdded 8612 # Number of non-speculative instructions added to the IQ 1226system.cpu2.iq.iqInstsIssued 199473 # Number of instructions issued 1227system.cpu2.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued 1228system.cpu2.iq.iqSquashedInstsExamined 10767 # Number of squashed instructions iterated over during squash; mainly for profiling 1229system.cpu2.iq.iqSquashedOperandsExamined 10430 # Number of squashed operands that are examined and possibly removed from graph 1230system.cpu2.iq.iqSquashedNonSpecRemoved 654 # Number of squashed non-spec instructions that were removed 1231system.cpu2.iq.issued_per_cycle::samples 172730 # Number of insts issued each cycle 1232system.cpu2.iq.issued_per_cycle::mean 1.154825 # Number of insts issued each cycle 1233system.cpu2.iq.issued_per_cycle::stdev 1.283743 # Number of insts issued each cycle 1234system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1235system.cpu2.iq.issued_per_cycle::0 79387 45.96% 45.96% # Number of insts issued each cycle 1236system.cpu2.iq.issued_per_cycle::1 29099 16.85% 62.81% # Number of insts issued each cycle 1237system.cpu2.iq.issued_per_cycle::2 29295 16.96% 79.77% # Number of insts issued each cycle 1238system.cpu2.iq.issued_per_cycle::3 30090 17.42% 97.19% # Number of insts issued each cycle 1239system.cpu2.iq.issued_per_cycle::4 3300 1.91% 99.10% # Number of insts issued each cycle 1240system.cpu2.iq.issued_per_cycle::5 1204 0.70% 99.79% # Number of insts issued each cycle 1241system.cpu2.iq.issued_per_cycle::6 247 0.14% 99.94% # Number of insts issued each cycle 1242system.cpu2.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle 1243system.cpu2.iq.issued_per_cycle::8 56 0.03% 100.00% # Number of insts issued each cycle 1244system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1245system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1246system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1247system.cpu2.iq.issued_per_cycle::total 172730 # Number of insts issued each cycle 1248system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1249system.cpu2.iq.fu_full::IntAlu 16 5.67% 5.67% # attempts to use FU when none available 1250system.cpu2.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available 1251system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available 1252system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available 1253system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available 1254system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available 1255system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available 1256system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available 1257system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available 1258system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available 1259system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available 1260system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available 1261system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available 1262system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available 1263system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available 1264system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available 1265system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available 1266system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available 1267system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available 1268system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available 1269system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available 1270system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available 1271system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available 1272system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available 1273system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available 1274system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available 1275system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available 1276system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available 1277system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available 1278system.cpu2.iq.fu_full::MemRead 56 19.86% 25.53% # attempts to use FU when none available 1279system.cpu2.iq.fu_full::MemWrite 210 74.47% 100.00% # attempts to use FU when none available 1280system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1281system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1282system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1283system.cpu2.iq.FU_type_0::IntAlu 99688 49.98% 49.98% # Type of FU issued 1284system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.98% # Type of FU issued 1285system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.98% # Type of FU issued 1286system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.98% # Type of FU issued 1287system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.98% # Type of FU issued 1288system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.98% # Type of FU issued 1289system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.98% # Type of FU issued 1290system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.98% # Type of FU issued 1291system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.98% # Type of FU issued 1292system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.98% # Type of FU issued 1293system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.98% # Type of FU issued 1294system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.98% # Type of FU issued 1295system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.98% # Type of FU issued 1296system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.98% # Type of FU issued 1297system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.98% # Type of FU issued 1298system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.98% # Type of FU issued 1299system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.98% # Type of FU issued 1300system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.98% # Type of FU issued 1301system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.98% # Type of FU issued 1302system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.98% # Type of FU issued 1303system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.98% # Type of FU issued 1304system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.98% # Type of FU issued 1305system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.98% # Type of FU issued 1306system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.98% # Type of FU issued 1307system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.98% # Type of FU issued 1308system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.98% # Type of FU issued 1309system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.98% # Type of FU issued 1310system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.98% # Type of FU issued 1311system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.98% # Type of FU issued 1312system.cpu2.iq.FU_type_0::MemRead 71251 35.72% 85.70% # Type of FU issued 1313system.cpu2.iq.FU_type_0::MemWrite 28534 14.30% 100.00% # Type of FU issued 1314system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1315system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1316system.cpu2.iq.FU_type_0::total 199473 # Type of FU issued 1317system.cpu2.iq.rate 1.143380 # Inst issue rate 1318system.cpu2.iq.fu_busy_cnt 282 # FU busy when requested 1319system.cpu2.iq.fu_busy_rate 0.001414 # FU busy rate (busy events/executed inst) 1320system.cpu2.iq.int_inst_queue_reads 572030 # Number of integer instruction queue reads 1321system.cpu2.iq.int_inst_queue_writes 214590 # Number of integer instruction queue writes 1322system.cpu2.iq.int_inst_queue_wakeup_accesses 197726 # Number of integer instruction queue wakeup accesses 1323system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1324system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1325system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1326system.cpu2.iq.int_alu_accesses 199755 # Number of integer alu accesses 1327system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1328system.cpu2.iew.lsq.thread0.forwLoads 23953 # Number of loads that had data forwarded from stores 1329system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1330system.cpu2.iew.lsq.thread0.squashedLoads 2414 # Number of loads squashed 1331system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1332system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations 1333system.cpu2.iew.lsq.thread0.squashedStores 1398 # Number of stores squashed 1334system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1335system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1336system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1337system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1338system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1339system.cpu2.iew.iewSquashCycles 2363 # Number of cycles IEW is squashing 1340system.cpu2.iew.iewBlockCycles 870 # Number of cycles IEW is blocking 1341system.cpu2.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking 1342system.cpu2.iew.iewDispatchedInsts 236415 # Number of instructions dispatched to IQ 1343system.cpu2.iew.iewDispSquashedInsts 392 # Number of squashed instructions skipped by dispatch 1344system.cpu2.iew.iewDispLoadInsts 64738 # Number of dispatched load instructions 1345system.cpu2.iew.iewDispStoreInsts 29196 # Number of dispatched store instructions 1346system.cpu2.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions 1347system.cpu2.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall 1348system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1349system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations 1350system.cpu2.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly 1351system.cpu2.iew.predictedNotTakenIncorrect 913 # Number of branches that were predicted not taken incorrectly 1352system.cpu2.iew.branchMispredicts 1372 # Number of branch mispredicts detected at execute 1353system.cpu2.iew.iewExecutedInsts 198312 # Number of executed instructions 1354system.cpu2.iew.iewExecLoadInsts 63718 # Number of load instructions executed 1355system.cpu2.iew.iewExecSquashedInsts 1161 # Number of squashed instructions skipped in execute 1356system.cpu2.iew.exec_swp 0 # number of swp insts executed 1357system.cpu2.iew.exec_nop 32635 # number of nop insts executed 1358system.cpu2.iew.exec_refs 92179 # number of memory reference insts executed 1359system.cpu2.iew.exec_branches 41831 # Number of branches executed 1360system.cpu2.iew.exec_stores 28461 # Number of stores executed 1361system.cpu2.iew.exec_rate 1.136726 # Inst execution rate 1362system.cpu2.iew.wb_sent 197998 # cumulative count of insts sent to commit 1363system.cpu2.iew.wb_count 197726 # cumulative count of insts written-back 1364system.cpu2.iew.wb_producers 108943 # num instructions producing a value 1365system.cpu2.iew.wb_consumers 113613 # num instructions consuming a value 1366system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1367system.cpu2.iew.wb_rate 1.133367 # insts written-back per cycle 1368system.cpu2.iew.wb_fanout 0.958896 # average fanout of values written-back 1369system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1370system.cpu2.commit.commitSquashedInsts 12414 # The number of squashed insts skipped by commit 1371system.cpu2.commit.commitNonSpecStalls 7958 # The number of times commit has been forced to stall to communicate backwards 1372system.cpu2.commit.branchMispredicts 1262 # The number of times a branch was mispredicted 1373system.cpu2.commit.committed_per_cycle::samples 163988 # Number of insts commited each cycle 1374system.cpu2.commit.committed_per_cycle::mean 1.365838 # Number of insts commited each cycle 1375system.cpu2.commit.committed_per_cycle::stdev 1.905647 # Number of insts commited each cycle 1376system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1377system.cpu2.commit.committed_per_cycle::0 80806 49.28% 49.28% # Number of insts commited each cycle 1378system.cpu2.commit.committed_per_cycle::1 39854 24.30% 73.58% # Number of insts commited each cycle 1379system.cpu2.commit.committed_per_cycle::2 6054 3.69% 77.27% # Number of insts commited each cycle 1380system.cpu2.commit.committed_per_cycle::3 8882 5.42% 82.69% # Number of insts commited each cycle 1381system.cpu2.commit.committed_per_cycle::4 1574 0.96% 83.65% # Number of insts commited each cycle 1382system.cpu2.commit.committed_per_cycle::5 24481 14.93% 98.57% # Number of insts commited each cycle 1383system.cpu2.commit.committed_per_cycle::6 507 0.31% 98.88% # Number of insts commited each cycle 1384system.cpu2.commit.committed_per_cycle::7 1010 0.62% 99.50% # Number of insts commited each cycle 1385system.cpu2.commit.committed_per_cycle::8 820 0.50% 100.00% # Number of insts commited each cycle 1386system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1387system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1388system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1389system.cpu2.commit.committed_per_cycle::total 163988 # Number of insts commited each cycle 1390system.cpu2.commit.committedInsts 223981 # Number of instructions committed 1391system.cpu2.commit.committedOps 223981 # Number of ops (including micro ops) committed 1392system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed 1393system.cpu2.commit.refs 90122 # Number of memory references committed 1394system.cpu2.commit.loads 62324 # Number of loads committed 1395system.cpu2.commit.membars 7244 # Number of memory barriers committed 1396system.cpu2.commit.branches 41003 # Number of branches committed 1397system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. 1398system.cpu2.commit.int_insts 153248 # Number of committed integer instructions. 1399system.cpu2.commit.function_calls 322 # Number of function calls committed. 1400system.cpu2.commit.bw_lim_events 820 # number cycles where commit BW limit reached 1401system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits 1402system.cpu2.rob.rob_reads 398976 # The number of ROB reads 1403system.cpu2.rob.rob_writes 475157 # The number of ROB writes 1404system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself 1405system.cpu2.idleCycles 1729 # Total number of cycles that the CPU has spent unscheduled due to idling 1406system.cpu2.quiesceCycles 37143 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1407system.cpu2.committedInsts 184944 # Number of Instructions Simulated 1408system.cpu2.committedOps 184944 # Number of Ops (including micro ops) Simulated 1409system.cpu2.committedInsts_total 184944 # Number of Instructions Simulated 1410system.cpu2.cpi 0.943307 # CPI: Cycles Per Instruction 1411system.cpu2.cpi_total 0.943307 # CPI: Total CPI of All Threads 1412system.cpu2.ipc 1.060100 # IPC: Instructions Per Cycle 1413system.cpu2.ipc_total 1.060100 # IPC: Total IPC of All Threads 1414system.cpu2.int_regfile_reads 335090 # number of integer regfile reads 1415system.cpu2.int_regfile_writes 157371 # number of integer regfile writes 1416system.cpu2.fp_regfile_writes 64 # number of floating regfile writes 1417system.cpu2.misc_regfile_reads 93758 # number of misc regfile reads 1418system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 1419system.cpu2.icache.replacements 319 # number of replacements 1420system.cpu2.icache.tagsinuse 83.416337 # Cycle average of tags in use 1421system.cpu2.icache.total_refs 23791 # Total number of references to valid blocks. 1422system.cpu2.icache.sampled_refs 430 # Sample count of references to valid blocks. 1423system.cpu2.icache.avg_refs 55.327907 # Average number of references to valid blocks. 1424system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1425system.cpu2.icache.occ_blocks::cpu2.inst 83.416337 # Average occupied blocks per requestor 1426system.cpu2.icache.occ_percent::cpu2.inst 0.162923 # Average percentage of cache occupancy 1427system.cpu2.icache.occ_percent::total 0.162923 # Average percentage of cache occupancy 1428system.cpu2.icache.ReadReq_hits::cpu2.inst 23791 # number of ReadReq hits 1429system.cpu2.icache.ReadReq_hits::total 23791 # number of ReadReq hits 1430system.cpu2.icache.demand_hits::cpu2.inst 23791 # number of demand (read+write) hits 1431system.cpu2.icache.demand_hits::total 23791 # number of demand (read+write) hits 1432system.cpu2.icache.overall_hits::cpu2.inst 23791 # number of overall hits 1433system.cpu2.icache.overall_hits::total 23791 # number of overall hits 1434system.cpu2.icache.ReadReq_misses::cpu2.inst 478 # number of ReadReq misses 1435system.cpu2.icache.ReadReq_misses::total 478 # number of ReadReq misses 1436system.cpu2.icache.demand_misses::cpu2.inst 478 # number of demand (read+write) misses 1437system.cpu2.icache.demand_misses::total 478 # number of demand (read+write) misses 1438system.cpu2.icache.overall_misses::cpu2.inst 478 # number of overall misses 1439system.cpu2.icache.overall_misses::total 478 # number of overall misses 1440system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6751000 # number of ReadReq miss cycles 1441system.cpu2.icache.ReadReq_miss_latency::total 6751000 # number of ReadReq miss cycles 1442system.cpu2.icache.demand_miss_latency::cpu2.inst 6751000 # number of demand (read+write) miss cycles 1443system.cpu2.icache.demand_miss_latency::total 6751000 # number of demand (read+write) miss cycles 1444system.cpu2.icache.overall_miss_latency::cpu2.inst 6751000 # number of overall miss cycles 1445system.cpu2.icache.overall_miss_latency::total 6751000 # number of overall miss cycles 1446system.cpu2.icache.ReadReq_accesses::cpu2.inst 24269 # number of ReadReq accesses(hits+misses) 1447system.cpu2.icache.ReadReq_accesses::total 24269 # number of ReadReq accesses(hits+misses) 1448system.cpu2.icache.demand_accesses::cpu2.inst 24269 # number of demand (read+write) accesses 1449system.cpu2.icache.demand_accesses::total 24269 # number of demand (read+write) accesses 1450system.cpu2.icache.overall_accesses::cpu2.inst 24269 # number of overall (read+write) accesses 1451system.cpu2.icache.overall_accesses::total 24269 # number of overall (read+write) accesses 1452system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.019696 # miss rate for ReadReq accesses 1453system.cpu2.icache.ReadReq_miss_rate::total 0.019696 # miss rate for ReadReq accesses 1454system.cpu2.icache.demand_miss_rate::cpu2.inst 0.019696 # miss rate for demand accesses 1455system.cpu2.icache.demand_miss_rate::total 0.019696 # miss rate for demand accesses 1456system.cpu2.icache.overall_miss_rate::cpu2.inst 0.019696 # miss rate for overall accesses 1457system.cpu2.icache.overall_miss_rate::total 0.019696 # miss rate for overall accesses 1458system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14123.430962 # average ReadReq miss latency 1459system.cpu2.icache.ReadReq_avg_miss_latency::total 14123.430962 # average ReadReq miss latency 1460system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14123.430962 # average overall miss latency 1461system.cpu2.icache.demand_avg_miss_latency::total 14123.430962 # average overall miss latency 1462system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14123.430962 # average overall miss latency 1463system.cpu2.icache.overall_avg_miss_latency::total 14123.430962 # average overall miss latency 1464system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1465system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1466system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1467system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1468system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1469system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1470system.cpu2.icache.fast_writes 0 # number of fast writes performed 1471system.cpu2.icache.cache_copies 0 # number of cache copies performed 1472system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 48 # number of ReadReq MSHR hits 1473system.cpu2.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits 1474system.cpu2.icache.demand_mshr_hits::cpu2.inst 48 # number of demand (read+write) MSHR hits 1475system.cpu2.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits 1476system.cpu2.icache.overall_mshr_hits::cpu2.inst 48 # number of overall MSHR hits 1477system.cpu2.icache.overall_mshr_hits::total 48 # number of overall MSHR hits 1478system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 430 # number of ReadReq MSHR misses 1479system.cpu2.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 1480system.cpu2.icache.demand_mshr_misses::cpu2.inst 430 # number of demand (read+write) MSHR misses 1481system.cpu2.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses 1482system.cpu2.icache.overall_mshr_misses::cpu2.inst 430 # number of overall MSHR misses 1483system.cpu2.icache.overall_mshr_misses::total 430 # number of overall MSHR misses 1484system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5435000 # number of ReadReq MSHR miss cycles 1485system.cpu2.icache.ReadReq_mshr_miss_latency::total 5435000 # number of ReadReq MSHR miss cycles 1486system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5435000 # number of demand (read+write) MSHR miss cycles 1487system.cpu2.icache.demand_mshr_miss_latency::total 5435000 # number of demand (read+write) MSHR miss cycles 1488system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5435000 # number of overall MSHR miss cycles 1489system.cpu2.icache.overall_mshr_miss_latency::total 5435000 # number of overall MSHR miss cycles 1490system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for ReadReq accesses 1491system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017718 # mshr miss rate for ReadReq accesses 1492system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for demand accesses 1493system.cpu2.icache.demand_mshr_miss_rate::total 0.017718 # mshr miss rate for demand accesses 1494system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for overall accesses 1495system.cpu2.icache.overall_mshr_miss_rate::total 0.017718 # mshr miss rate for overall accesses 1496system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average ReadReq mshr miss latency 1497system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12639.534884 # average ReadReq mshr miss latency 1498system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average overall mshr miss latency 1499system.cpu2.icache.demand_avg_mshr_miss_latency::total 12639.534884 # average overall mshr miss latency 1500system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average overall mshr miss latency 1501system.cpu2.icache.overall_avg_mshr_miss_latency::total 12639.534884 # average overall mshr miss latency 1502system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1503system.cpu2.dcache.replacements 0 # number of replacements 1504system.cpu2.dcache.tagsinuse 25.649065 # Cycle average of tags in use 1505system.cpu2.dcache.total_refs 33911 # Total number of references to valid blocks. 1506system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. 1507system.cpu2.dcache.avg_refs 1169.344828 # Average number of references to valid blocks. 1508system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1509system.cpu2.dcache.occ_blocks::cpu2.data 25.649065 # Average occupied blocks per requestor 1510system.cpu2.dcache.occ_percent::cpu2.data 0.050096 # Average percentage of cache occupancy 1511system.cpu2.dcache.occ_percent::total 0.050096 # Average percentage of cache occupancy 1512system.cpu2.dcache.ReadReq_hits::cpu2.data 39345 # number of ReadReq hits 1513system.cpu2.dcache.ReadReq_hits::total 39345 # number of ReadReq hits 1514system.cpu2.dcache.WriteReq_hits::cpu2.data 27592 # number of WriteReq hits 1515system.cpu2.dcache.WriteReq_hits::total 27592 # number of WriteReq hits 1516system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits 1517system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits 1518system.cpu2.dcache.demand_hits::cpu2.data 66937 # number of demand (read+write) hits 1519system.cpu2.dcache.demand_hits::total 66937 # number of demand (read+write) hits 1520system.cpu2.dcache.overall_hits::cpu2.data 66937 # number of overall hits 1521system.cpu2.dcache.overall_hits::total 66937 # number of overall hits 1522system.cpu2.dcache.ReadReq_misses::cpu2.data 402 # number of ReadReq misses 1523system.cpu2.dcache.ReadReq_misses::total 402 # number of ReadReq misses 1524system.cpu2.dcache.WriteReq_misses::cpu2.data 138 # number of WriteReq misses 1525system.cpu2.dcache.WriteReq_misses::total 138 # number of WriteReq misses 1526system.cpu2.dcache.SwapReq_misses::cpu2.data 53 # number of SwapReq misses 1527system.cpu2.dcache.SwapReq_misses::total 53 # number of SwapReq misses 1528system.cpu2.dcache.demand_misses::cpu2.data 540 # number of demand (read+write) misses 1529system.cpu2.dcache.demand_misses::total 540 # number of demand (read+write) misses 1530system.cpu2.dcache.overall_misses::cpu2.data 540 # number of overall misses 1531system.cpu2.dcache.overall_misses::total 540 # number of overall misses 1532system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5276000 # number of ReadReq miss cycles 1533system.cpu2.dcache.ReadReq_miss_latency::total 5276000 # number of ReadReq miss cycles 1534system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2759500 # number of WriteReq miss cycles 1535system.cpu2.dcache.WriteReq_miss_latency::total 2759500 # number of WriteReq miss cycles 1536system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 558000 # number of SwapReq miss cycles 1537system.cpu2.dcache.SwapReq_miss_latency::total 558000 # number of SwapReq miss cycles 1538system.cpu2.dcache.demand_miss_latency::cpu2.data 8035500 # number of demand (read+write) miss cycles 1539system.cpu2.dcache.demand_miss_latency::total 8035500 # number of demand (read+write) miss cycles 1540system.cpu2.dcache.overall_miss_latency::cpu2.data 8035500 # number of overall miss cycles 1541system.cpu2.dcache.overall_miss_latency::total 8035500 # number of overall miss cycles 1542system.cpu2.dcache.ReadReq_accesses::cpu2.data 39747 # number of ReadReq accesses(hits+misses) 1543system.cpu2.dcache.ReadReq_accesses::total 39747 # number of ReadReq accesses(hits+misses) 1544system.cpu2.dcache.WriteReq_accesses::cpu2.data 27730 # number of WriteReq accesses(hits+misses) 1545system.cpu2.dcache.WriteReq_accesses::total 27730 # number of WriteReq accesses(hits+misses) 1546system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) 1547system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) 1548system.cpu2.dcache.demand_accesses::cpu2.data 67477 # number of demand (read+write) accesses 1549system.cpu2.dcache.demand_accesses::total 67477 # number of demand (read+write) accesses 1550system.cpu2.dcache.overall_accesses::cpu2.data 67477 # number of overall (read+write) accesses 1551system.cpu2.dcache.overall_accesses::total 67477 # number of overall (read+write) accesses 1552system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010114 # miss rate for ReadReq accesses 1553system.cpu2.dcache.ReadReq_miss_rate::total 0.010114 # miss rate for ReadReq accesses 1554system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004977 # miss rate for WriteReq accesses 1555system.cpu2.dcache.WriteReq_miss_rate::total 0.004977 # miss rate for WriteReq accesses 1556system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.779412 # miss rate for SwapReq accesses 1557system.cpu2.dcache.SwapReq_miss_rate::total 0.779412 # miss rate for SwapReq accesses 1558system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008003 # miss rate for demand accesses 1559system.cpu2.dcache.demand_miss_rate::total 0.008003 # miss rate for demand accesses 1560system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008003 # miss rate for overall accesses 1561system.cpu2.dcache.overall_miss_rate::total 0.008003 # miss rate for overall accesses 1562system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13124.378109 # average ReadReq miss latency 1563system.cpu2.dcache.ReadReq_avg_miss_latency::total 13124.378109 # average ReadReq miss latency 1564system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19996.376812 # average WriteReq miss latency 1565system.cpu2.dcache.WriteReq_avg_miss_latency::total 19996.376812 # average WriteReq miss latency 1566system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10528.301887 # average SwapReq miss latency 1567system.cpu2.dcache.SwapReq_avg_miss_latency::total 10528.301887 # average SwapReq miss latency 1568system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14880.555556 # average overall miss latency 1569system.cpu2.dcache.demand_avg_miss_latency::total 14880.555556 # average overall miss latency 1570system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14880.555556 # average overall miss latency 1571system.cpu2.dcache.overall_avg_miss_latency::total 14880.555556 # average overall miss latency 1572system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1573system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1574system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1575system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1576system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1577system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1578system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1579system.cpu2.dcache.cache_copies 0 # number of cache copies performed 1580system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 241 # number of ReadReq MSHR hits 1581system.cpu2.dcache.ReadReq_mshr_hits::total 241 # number of ReadReq MSHR hits 1582system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits 1583system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits 1584system.cpu2.dcache.demand_mshr_hits::cpu2.data 274 # number of demand (read+write) MSHR hits 1585system.cpu2.dcache.demand_mshr_hits::total 274 # number of demand (read+write) MSHR hits 1586system.cpu2.dcache.overall_mshr_hits::cpu2.data 274 # number of overall MSHR hits 1587system.cpu2.dcache.overall_mshr_hits::total 274 # number of overall MSHR hits 1588system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses 1589system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses 1590system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses 1591system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 1592system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 53 # number of SwapReq MSHR misses 1593system.cpu2.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses 1594system.cpu2.dcache.demand_mshr_misses::cpu2.data 266 # number of demand (read+write) MSHR misses 1595system.cpu2.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses 1596system.cpu2.dcache.overall_mshr_misses::cpu2.data 266 # number of overall MSHR misses 1597system.cpu2.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses 1598system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1358500 # number of ReadReq MSHR miss cycles 1599system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1358500 # number of ReadReq MSHR miss cycles 1600system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1350500 # number of WriteReq MSHR miss cycles 1601system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1350500 # number of WriteReq MSHR miss cycles 1602system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 452000 # number of SwapReq MSHR miss cycles 1603system.cpu2.dcache.SwapReq_mshr_miss_latency::total 452000 # number of SwapReq MSHR miss cycles 1604system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2709000 # number of demand (read+write) MSHR miss cycles 1605system.cpu2.dcache.demand_mshr_miss_latency::total 2709000 # number of demand (read+write) MSHR miss cycles 1606system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2709000 # number of overall MSHR miss cycles 1607system.cpu2.dcache.overall_mshr_miss_latency::total 2709000 # number of overall MSHR miss cycles 1608system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004051 # mshr miss rate for ReadReq accesses 1609system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004051 # mshr miss rate for ReadReq accesses 1610system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003787 # mshr miss rate for WriteReq accesses 1611system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003787 # mshr miss rate for WriteReq accesses 1612system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.779412 # mshr miss rate for SwapReq accesses 1613system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.779412 # mshr miss rate for SwapReq accesses 1614system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for demand accesses 1615system.cpu2.dcache.demand_mshr_miss_rate::total 0.003942 # mshr miss rate for demand accesses 1616system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for overall accesses 1617system.cpu2.dcache.overall_mshr_miss_rate::total 0.003942 # mshr miss rate for overall accesses 1618system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8437.888199 # average ReadReq mshr miss latency 1619system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8437.888199 # average ReadReq mshr miss latency 1620system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 12861.904762 # average WriteReq mshr miss latency 1621system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 12861.904762 # average WriteReq mshr miss latency 1622system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8528.301887 # average SwapReq mshr miss latency 1623system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8528.301887 # average SwapReq mshr miss latency 1624system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency 1625system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency 1626system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency 1627system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency 1628system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1629system.cpu3.branchPred.lookups 47073 # Number of BP lookups 1630system.cpu3.branchPred.condPredicted 44334 # Number of conditional branches predicted 1631system.cpu3.branchPred.condIncorrect 1289 # Number of conditional branches incorrect 1632system.cpu3.branchPred.BTBLookups 40998 # Number of BTB lookups 1633system.cpu3.branchPred.BTBHits 40129 # Number of BTB hits 1634system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1635system.cpu3.branchPred.BTBHitPct 97.880384 # BTB Hit Percentage 1636system.cpu3.branchPred.usedRAS 665 # Number of times the RAS was used to get a target. 1637system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 1638system.cpu3.numCycles 174149 # number of cpu cycles simulated 1639system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1640system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 1641system.cpu3.fetch.icacheStallCycles 31334 # Number of cycles fetch is stalled on an Icache miss 1642system.cpu3.fetch.Insts 257802 # Number of instructions fetch has processed 1643system.cpu3.fetch.Branches 47073 # Number of branches that fetch encountered 1644system.cpu3.fetch.predictedBranches 40794 # Number of branches that fetch has predicted taken 1645system.cpu3.fetch.Cycles 94093 # Number of cycles fetch has run and was not squashing or blocked 1646system.cpu3.fetch.SquashCycles 3784 # Number of cycles fetch has spent squashing 1647system.cpu3.fetch.BlockedCycles 37693 # Number of cycles fetch has spent blocked 1648system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1649system.cpu3.fetch.NoActiveThreadStallCycles 6388 # Number of stall cycles due to no active thread to fetch from 1650system.cpu3.fetch.PendingTrapStallCycles 691 # Number of stall cycles due to pending traps 1651system.cpu3.fetch.CacheLines 23091 # Number of cache lines fetched 1652system.cpu3.fetch.IcacheSquashes 274 # Number of outstanding Icache misses that were squashed 1653system.cpu3.fetch.rateDist::samples 172622 # Number of instructions fetched each cycle (Total) 1654system.cpu3.fetch.rateDist::mean 1.493448 # Number of instructions fetched each cycle (Total) 1655system.cpu3.fetch.rateDist::stdev 2.066617 # Number of instructions fetched each cycle (Total) 1656system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1657system.cpu3.fetch.rateDist::0 78529 45.49% 45.49% # Number of instructions fetched each cycle (Total) 1658system.cpu3.fetch.rateDist::1 48697 28.21% 73.70% # Number of instructions fetched each cycle (Total) 1659system.cpu3.fetch.rateDist::2 7780 4.51% 78.21% # Number of instructions fetched each cycle (Total) 1660system.cpu3.fetch.rateDist::3 3181 1.84% 80.05% # Number of instructions fetched each cycle (Total) 1661system.cpu3.fetch.rateDist::4 739 0.43% 80.48% # Number of instructions fetched each cycle (Total) 1662system.cpu3.fetch.rateDist::5 28510 16.52% 97.00% # Number of instructions fetched each cycle (Total) 1663system.cpu3.fetch.rateDist::6 1109 0.64% 97.64% # Number of instructions fetched each cycle (Total) 1664system.cpu3.fetch.rateDist::7 774 0.45% 98.09% # Number of instructions fetched each cycle (Total) 1665system.cpu3.fetch.rateDist::8 3303 1.91% 100.00% # Number of instructions fetched each cycle (Total) 1666system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1667system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1668system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1669system.cpu3.fetch.rateDist::total 172622 # Number of instructions fetched each cycle (Total) 1670system.cpu3.fetch.branchRate 0.270303 # Number of branch fetches per cycle 1671system.cpu3.fetch.rate 1.480353 # Number of inst fetches per cycle 1672system.cpu3.decode.IdleCycles 38095 # Number of cycles decode is idle 1673system.cpu3.decode.BlockedCycles 32492 # Number of cycles decode is blocked 1674system.cpu3.decode.RunCycles 86590 # Number of cycles decode is running 1675system.cpu3.decode.UnblockCycles 6639 # Number of cycles decode is unblocking 1676system.cpu3.decode.SquashCycles 2418 # Number of cycles decode is squashing 1677system.cpu3.decode.DecodedInsts 254216 # Number of instructions handled by decode 1678system.cpu3.rename.SquashCycles 2418 # Number of cycles rename is squashing 1679system.cpu3.rename.IdleCycles 38798 # Number of cycles rename is idle 1680system.cpu3.rename.BlockCycles 19631 # Number of cycles rename is blocking 1681system.cpu3.rename.serializeStallCycles 12074 # count of cycles rename stalled for serializing inst 1682system.cpu3.rename.RunCycles 80231 # Number of cycles rename is running 1683system.cpu3.rename.UnblockCycles 13082 # Number of cycles rename is unblocking 1684system.cpu3.rename.RenamedInsts 251848 # Number of instructions processed by rename 1685system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 1686system.cpu3.rename.LSQFullEvents 33 # Number of times rename has blocked due to LSQ full 1687system.cpu3.rename.RenamedOperands 174600 # Number of destination operands rename has renamed 1688system.cpu3.rename.RenameLookups 473869 # Number of register rename lookups that rename has made 1689system.cpu3.rename.int_rename_lookups 473869 # Number of integer rename lookups 1690system.cpu3.rename.CommittedMaps 161804 # Number of HB maps that are committed 1691system.cpu3.rename.UndoneMaps 12796 # Number of HB maps that are undone due to squashing 1692system.cpu3.rename.serializingInsts 1100 # count of serializing insts renamed 1693system.cpu3.rename.tempSerializingInsts 1222 # count of temporary serializing insts renamed 1694system.cpu3.rename.skidInsts 15769 # count of insts added to the skid buffer 1695system.cpu3.memDep0.insertedLoads 69165 # Number of loads inserted to the mem dependence unit. 1696system.cpu3.memDep0.insertedStores 31749 # Number of stores inserted to the mem dependence unit. 1697system.cpu3.memDep0.conflictingLoads 33643 # Number of conflicting loads. 1698system.cpu3.memDep0.conflictingStores 26714 # Number of conflicting stores. 1699system.cpu3.iq.iqInstsAdded 206536 # Number of instructions added to the IQ (excludes non-spec) 1700system.cpu3.iq.iqNonSpecInstsAdded 7999 # Number of non-speculative instructions added to the IQ 1701system.cpu3.iq.iqInstsIssued 210100 # Number of instructions issued 1702system.cpu3.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued 1703system.cpu3.iq.iqSquashedInstsExamined 10964 # Number of squashed instructions iterated over during squash; mainly for profiling 1704system.cpu3.iq.iqSquashedOperandsExamined 10853 # Number of squashed operands that are examined and possibly removed from graph 1705system.cpu3.iq.iqSquashedNonSpecRemoved 623 # Number of squashed non-spec instructions that were removed 1706system.cpu3.iq.issued_per_cycle::samples 172622 # Number of insts issued each cycle 1707system.cpu3.iq.issued_per_cycle::mean 1.217110 # Number of insts issued each cycle 1708system.cpu3.iq.issued_per_cycle::stdev 1.294923 # Number of insts issued each cycle 1709system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1710system.cpu3.iq.issued_per_cycle::0 76068 44.07% 44.07% # Number of insts issued each cycle 1711system.cpu3.iq.issued_per_cycle::1 27297 15.81% 59.88% # Number of insts issued each cycle 1712system.cpu3.iq.issued_per_cycle::2 31861 18.46% 78.34% # Number of insts issued each cycle 1713system.cpu3.iq.issued_per_cycle::3 32569 18.87% 97.20% # Number of insts issued each cycle 1714system.cpu3.iq.issued_per_cycle::4 3286 1.90% 99.11% # Number of insts issued each cycle 1715system.cpu3.iq.issued_per_cycle::5 1177 0.68% 99.79% # Number of insts issued each cycle 1716system.cpu3.iq.issued_per_cycle::6 258 0.15% 99.94% # Number of insts issued each cycle 1717system.cpu3.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle 1718system.cpu3.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle 1719system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1720system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1721system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1722system.cpu3.iq.issued_per_cycle::total 172622 # Number of insts issued each cycle 1723system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1724system.cpu3.iq.fu_full::IntAlu 11 3.79% 3.79% # attempts to use FU when none available 1725system.cpu3.iq.fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available 1726system.cpu3.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available 1727system.cpu3.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available 1728system.cpu3.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available 1729system.cpu3.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available 1730system.cpu3.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available 1731system.cpu3.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available 1732system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available 1733system.cpu3.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available 1734system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available 1735system.cpu3.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available 1736system.cpu3.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available 1737system.cpu3.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available 1738system.cpu3.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available 1739system.cpu3.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available 1740system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available 1741system.cpu3.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available 1742system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available 1743system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available 1744system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available 1745system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available 1746system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available 1747system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available 1748system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available 1749system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available 1750system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available 1751system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available 1752system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available 1753system.cpu3.iq.fu_full::MemRead 69 23.79% 27.59% # attempts to use FU when none available 1754system.cpu3.iq.fu_full::MemWrite 210 72.41% 100.00% # attempts to use FU when none available 1755system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1756system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1757system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1758system.cpu3.iq.FU_type_0::IntAlu 104024 49.51% 49.51% # Type of FU issued 1759system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.51% # Type of FU issued 1760system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.51% # Type of FU issued 1761system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.51% # Type of FU issued 1762system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.51% # Type of FU issued 1763system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.51% # Type of FU issued 1764system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.51% # Type of FU issued 1765system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.51% # Type of FU issued 1766system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.51% # Type of FU issued 1767system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.51% # Type of FU issued 1768system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.51% # Type of FU issued 1769system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.51% # Type of FU issued 1770system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.51% # Type of FU issued 1771system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.51% # Type of FU issued 1772system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.51% # Type of FU issued 1773system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.51% # Type of FU issued 1774system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.51% # Type of FU issued 1775system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.51% # Type of FU issued 1776system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.51% # Type of FU issued 1777system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.51% # Type of FU issued 1778system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.51% # Type of FU issued 1779system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.51% # Type of FU issued 1780system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.51% # Type of FU issued 1781system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.51% # Type of FU issued 1782system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.51% # Type of FU issued 1783system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.51% # Type of FU issued 1784system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.51% # Type of FU issued 1785system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.51% # Type of FU issued 1786system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.51% # Type of FU issued 1787system.cpu3.iq.FU_type_0::MemRead 75016 35.70% 85.22% # Type of FU issued 1788system.cpu3.iq.FU_type_0::MemWrite 31060 14.78% 100.00% # Type of FU issued 1789system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1790system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1791system.cpu3.iq.FU_type_0::total 210100 # Type of FU issued 1792system.cpu3.iq.rate 1.206438 # Inst issue rate 1793system.cpu3.iq.fu_busy_cnt 290 # FU busy when requested 1794system.cpu3.iq.fu_busy_rate 0.001380 # FU busy rate (busy events/executed inst) 1795system.cpu3.iq.int_inst_queue_reads 593222 # Number of integer instruction queue reads 1796system.cpu3.iq.int_inst_queue_writes 225545 # Number of integer instruction queue writes 1797system.cpu3.iq.int_inst_queue_wakeup_accesses 208328 # Number of integer instruction queue wakeup accesses 1798system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1799system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1800system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1801system.cpu3.iq.int_alu_accesses 210390 # Number of integer alu accesses 1802system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1803system.cpu3.iew.lsq.thread0.forwLoads 26418 # Number of loads that had data forwarded from stores 1804system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1805system.cpu3.iew.lsq.thread0.squashedLoads 2499 # Number of loads squashed 1806system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1807system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations 1808system.cpu3.iew.lsq.thread0.squashedStores 1475 # Number of stores squashed 1809system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1810system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1811system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1812system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1813system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1814system.cpu3.iew.iewSquashCycles 2418 # Number of cycles IEW is squashing 1815system.cpu3.iew.iewBlockCycles 854 # Number of cycles IEW is blocking 1816system.cpu3.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking 1817system.cpu3.iew.iewDispatchedInsts 249047 # Number of instructions dispatched to IQ 1818system.cpu3.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch 1819system.cpu3.iew.iewDispLoadInsts 69165 # Number of dispatched load instructions 1820system.cpu3.iew.iewDispStoreInsts 31749 # Number of dispatched store instructions 1821system.cpu3.iew.iewDispNonSpecInsts 1065 # Number of dispatched non-speculative instructions 1822system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall 1823system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1824system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations 1825system.cpu3.iew.predictedTakenIncorrect 473 # Number of branches that were predicted taken incorrectly 1826system.cpu3.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly 1827system.cpu3.iew.branchMispredicts 1408 # Number of branch mispredicts detected at execute 1828system.cpu3.iew.iewExecutedInsts 208934 # Number of executed instructions 1829system.cpu3.iew.iewExecLoadInsts 68077 # Number of load instructions executed 1830system.cpu3.iew.iewExecSquashedInsts 1166 # Number of squashed instructions skipped in execute 1831system.cpu3.iew.exec_swp 0 # number of swp insts executed 1832system.cpu3.iew.exec_nop 34512 # number of nop insts executed 1833system.cpu3.iew.exec_refs 99056 # number of memory reference insts executed 1834system.cpu3.iew.exec_branches 43690 # Number of branches executed 1835system.cpu3.iew.exec_stores 30979 # Number of stores executed 1836system.cpu3.iew.exec_rate 1.199743 # Inst execution rate 1837system.cpu3.iew.wb_sent 208597 # cumulative count of insts sent to commit 1838system.cpu3.iew.wb_count 208328 # cumulative count of insts written-back 1839system.cpu3.iew.wb_producers 115832 # num instructions producing a value 1840system.cpu3.iew.wb_consumers 120507 # num instructions consuming a value 1841system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1842system.cpu3.iew.wb_rate 1.196263 # insts written-back per cycle 1843system.cpu3.iew.wb_fanout 0.961206 # average fanout of values written-back 1844system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1845system.cpu3.commit.commitSquashedInsts 12582 # The number of squashed insts skipped by commit 1846system.cpu3.commit.commitNonSpecStalls 7376 # The number of times commit has been forced to stall to communicate backwards 1847system.cpu3.commit.branchMispredicts 1289 # The number of times a branch was mispredicted 1848system.cpu3.commit.committed_per_cycle::samples 163816 # Number of insts commited each cycle 1849system.cpu3.commit.committed_per_cycle::mean 1.443357 # Number of insts commited each cycle 1850system.cpu3.commit.committed_per_cycle::stdev 1.942306 # Number of insts commited each cycle 1851system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1852system.cpu3.commit.committed_per_cycle::0 76810 46.89% 46.89% # Number of insts commited each cycle 1853system.cpu3.commit.committed_per_cycle::1 41800 25.52% 72.40% # Number of insts commited each cycle 1854system.cpu3.commit.committed_per_cycle::2 6086 3.72% 76.12% # Number of insts commited each cycle 1855system.cpu3.commit.committed_per_cycle::3 8257 5.04% 81.16% # Number of insts commited each cycle 1856system.cpu3.commit.committed_per_cycle::4 1545 0.94% 82.10% # Number of insts commited each cycle 1857system.cpu3.commit.committed_per_cycle::5 27022 16.50% 98.60% # Number of insts commited each cycle 1858system.cpu3.commit.committed_per_cycle::6 472 0.29% 98.89% # Number of insts commited each cycle 1859system.cpu3.commit.committed_per_cycle::7 1012 0.62% 99.50% # Number of insts commited each cycle 1860system.cpu3.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle 1861system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1862system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1863system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1864system.cpu3.commit.committed_per_cycle::total 163816 # Number of insts commited each cycle 1865system.cpu3.commit.committedInsts 236445 # Number of instructions committed 1866system.cpu3.commit.committedOps 236445 # Number of ops (including micro ops) committed 1867system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed 1868system.cpu3.commit.refs 96940 # Number of memory references committed 1869system.cpu3.commit.loads 66666 # Number of loads committed 1870system.cpu3.commit.membars 6656 # Number of memory barriers committed 1871system.cpu3.commit.branches 42889 # Number of branches committed 1872system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. 1873system.cpu3.commit.int_insts 161946 # Number of committed integer instructions. 1874system.cpu3.commit.function_calls 322 # Number of function calls committed. 1875system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached 1876system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits 1877system.cpu3.rob.rob_reads 411444 # The number of ROB reads 1878system.cpu3.rob.rob_writes 500477 # The number of ROB writes 1879system.cpu3.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself 1880system.cpu3.idleCycles 1527 # Total number of cycles that the CPU has spent unscheduled due to idling 1881system.cpu3.quiesceCycles 37453 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1882system.cpu3.committedInsts 196116 # Number of Instructions Simulated 1883system.cpu3.committedOps 196116 # Number of Ops (including micro ops) Simulated 1884system.cpu3.committedInsts_total 196116 # Number of Instructions Simulated 1885system.cpu3.cpi 0.887990 # CPI: Cycles Per Instruction 1886system.cpu3.cpi_total 0.887990 # CPI: Total CPI of All Threads 1887system.cpu3.ipc 1.126139 # IPC: Instructions Per Cycle 1888system.cpu3.ipc_total 1.126139 # IPC: Total IPC of All Threads 1889system.cpu3.int_regfile_reads 355696 # number of integer regfile reads 1890system.cpu3.int_regfile_writes 166589 # number of integer regfile writes 1891system.cpu3.fp_regfile_writes 64 # number of floating regfile writes 1892system.cpu3.misc_regfile_reads 100584 # number of misc regfile reads 1893system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 1894system.cpu3.icache.replacements 318 # number of replacements 1895system.cpu3.icache.tagsinuse 80.204482 # Cycle average of tags in use 1896system.cpu3.icache.total_refs 22614 # Total number of references to valid blocks. 1897system.cpu3.icache.sampled_refs 429 # Sample count of references to valid blocks. 1898system.cpu3.icache.avg_refs 52.713287 # Average number of references to valid blocks. 1899system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1900system.cpu3.icache.occ_blocks::cpu3.inst 80.204482 # Average occupied blocks per requestor 1901system.cpu3.icache.occ_percent::cpu3.inst 0.156649 # Average percentage of cache occupancy 1902system.cpu3.icache.occ_percent::total 0.156649 # Average percentage of cache occupancy 1903system.cpu3.icache.ReadReq_hits::cpu3.inst 22614 # number of ReadReq hits 1904system.cpu3.icache.ReadReq_hits::total 22614 # number of ReadReq hits 1905system.cpu3.icache.demand_hits::cpu3.inst 22614 # number of demand (read+write) hits 1906system.cpu3.icache.demand_hits::total 22614 # number of demand (read+write) hits 1907system.cpu3.icache.overall_hits::cpu3.inst 22614 # number of overall hits 1908system.cpu3.icache.overall_hits::total 22614 # number of overall hits 1909system.cpu3.icache.ReadReq_misses::cpu3.inst 477 # number of ReadReq misses 1910system.cpu3.icache.ReadReq_misses::total 477 # number of ReadReq misses 1911system.cpu3.icache.demand_misses::cpu3.inst 477 # number of demand (read+write) misses 1912system.cpu3.icache.demand_misses::total 477 # number of demand (read+write) misses 1913system.cpu3.icache.overall_misses::cpu3.inst 477 # number of overall misses 1914system.cpu3.icache.overall_misses::total 477 # number of overall misses 1915system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6252000 # number of ReadReq miss cycles 1916system.cpu3.icache.ReadReq_miss_latency::total 6252000 # number of ReadReq miss cycles 1917system.cpu3.icache.demand_miss_latency::cpu3.inst 6252000 # number of demand (read+write) miss cycles 1918system.cpu3.icache.demand_miss_latency::total 6252000 # number of demand (read+write) miss cycles 1919system.cpu3.icache.overall_miss_latency::cpu3.inst 6252000 # number of overall miss cycles 1920system.cpu3.icache.overall_miss_latency::total 6252000 # number of overall miss cycles 1921system.cpu3.icache.ReadReq_accesses::cpu3.inst 23091 # number of ReadReq accesses(hits+misses) 1922system.cpu3.icache.ReadReq_accesses::total 23091 # number of ReadReq accesses(hits+misses) 1923system.cpu3.icache.demand_accesses::cpu3.inst 23091 # number of demand (read+write) accesses 1924system.cpu3.icache.demand_accesses::total 23091 # number of demand (read+write) accesses 1925system.cpu3.icache.overall_accesses::cpu3.inst 23091 # number of overall (read+write) accesses 1926system.cpu3.icache.overall_accesses::total 23091 # number of overall (read+write) accesses 1927system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020657 # miss rate for ReadReq accesses 1928system.cpu3.icache.ReadReq_miss_rate::total 0.020657 # miss rate for ReadReq accesses 1929system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020657 # miss rate for demand accesses 1930system.cpu3.icache.demand_miss_rate::total 0.020657 # miss rate for demand accesses 1931system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020657 # miss rate for overall accesses 1932system.cpu3.icache.overall_miss_rate::total 0.020657 # miss rate for overall accesses 1933system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13106.918239 # average ReadReq miss latency 1934system.cpu3.icache.ReadReq_avg_miss_latency::total 13106.918239 # average ReadReq miss latency 1935system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13106.918239 # average overall miss latency 1936system.cpu3.icache.demand_avg_miss_latency::total 13106.918239 # average overall miss latency 1937system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13106.918239 # average overall miss latency 1938system.cpu3.icache.overall_avg_miss_latency::total 13106.918239 # average overall miss latency 1939system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1940system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1941system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1942system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1943system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1944system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1945system.cpu3.icache.fast_writes 0 # number of fast writes performed 1946system.cpu3.icache.cache_copies 0 # number of cache copies performed 1947system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 48 # number of ReadReq MSHR hits 1948system.cpu3.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits 1949system.cpu3.icache.demand_mshr_hits::cpu3.inst 48 # number of demand (read+write) MSHR hits 1950system.cpu3.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits 1951system.cpu3.icache.overall_mshr_hits::cpu3.inst 48 # number of overall MSHR hits 1952system.cpu3.icache.overall_mshr_hits::total 48 # number of overall MSHR hits 1953system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 429 # number of ReadReq MSHR misses 1954system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses 1955system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 # number of demand (read+write) MSHR misses 1956system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses 1957system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses 1958system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses 1959system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4992500 # number of ReadReq MSHR miss cycles 1960system.cpu3.icache.ReadReq_mshr_miss_latency::total 4992500 # number of ReadReq MSHR miss cycles 1961system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4992500 # number of demand (read+write) MSHR miss cycles 1962system.cpu3.icache.demand_mshr_miss_latency::total 4992500 # number of demand (read+write) MSHR miss cycles 1963system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4992500 # number of overall MSHR miss cycles 1964system.cpu3.icache.overall_mshr_miss_latency::total 4992500 # number of overall MSHR miss cycles 1965system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for ReadReq accesses 1966system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.018579 # mshr miss rate for ReadReq accesses 1967system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for demand accesses 1968system.cpu3.icache.demand_mshr_miss_rate::total 0.018579 # mshr miss rate for demand accesses 1969system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for overall accesses 1970system.cpu3.icache.overall_mshr_miss_rate::total 0.018579 # mshr miss rate for overall accesses 1971system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11637.529138 # average ReadReq mshr miss latency 1972system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11637.529138 # average ReadReq mshr miss latency 1973system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11637.529138 # average overall mshr miss latency 1974system.cpu3.icache.demand_avg_mshr_miss_latency::total 11637.529138 # average overall mshr miss latency 1975system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11637.529138 # average overall mshr miss latency 1976system.cpu3.icache.overall_avg_mshr_miss_latency::total 11637.529138 # average overall mshr miss latency 1977system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1978system.cpu3.dcache.replacements 0 # number of replacements 1979system.cpu3.dcache.tagsinuse 24.557568 # Cycle average of tags in use 1980system.cpu3.dcache.total_refs 36284 # Total number of references to valid blocks. 1981system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. 1982system.cpu3.dcache.avg_refs 1295.857143 # Average number of references to valid blocks. 1983system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1984system.cpu3.dcache.occ_blocks::cpu3.data 24.557568 # Average occupied blocks per requestor 1985system.cpu3.dcache.occ_percent::cpu3.data 0.047964 # Average percentage of cache occupancy 1986system.cpu3.dcache.occ_percent::total 0.047964 # Average percentage of cache occupancy 1987system.cpu3.dcache.ReadReq_hits::cpu3.data 41265 # number of ReadReq hits 1988system.cpu3.dcache.ReadReq_hits::total 41265 # number of ReadReq hits 1989system.cpu3.dcache.WriteReq_hits::cpu3.data 30070 # number of WriteReq hits 1990system.cpu3.dcache.WriteReq_hits::total 30070 # number of WriteReq hits 1991system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 1992system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 1993system.cpu3.dcache.demand_hits::cpu3.data 71335 # number of demand (read+write) hits 1994system.cpu3.dcache.demand_hits::total 71335 # number of demand (read+write) hits 1995system.cpu3.dcache.overall_hits::cpu3.data 71335 # number of overall hits 1996system.cpu3.dcache.overall_hits::total 71335 # number of overall hits 1997system.cpu3.dcache.ReadReq_misses::cpu3.data 376 # number of ReadReq misses 1998system.cpu3.dcache.ReadReq_misses::total 376 # number of ReadReq misses 1999system.cpu3.dcache.WriteReq_misses::cpu3.data 130 # number of WriteReq misses 2000system.cpu3.dcache.WriteReq_misses::total 130 # number of WriteReq misses 2001system.cpu3.dcache.SwapReq_misses::cpu3.data 59 # number of SwapReq misses 2002system.cpu3.dcache.SwapReq_misses::total 59 # number of SwapReq misses 2003system.cpu3.dcache.demand_misses::cpu3.data 506 # number of demand (read+write) misses 2004system.cpu3.dcache.demand_misses::total 506 # number of demand (read+write) misses 2005system.cpu3.dcache.overall_misses::cpu3.data 506 # number of overall misses 2006system.cpu3.dcache.overall_misses::total 506 # number of overall misses 2007system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4881500 # number of ReadReq miss cycles 2008system.cpu3.dcache.ReadReq_miss_latency::total 4881500 # number of ReadReq miss cycles 2009system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2539500 # number of WriteReq miss cycles 2010system.cpu3.dcache.WriteReq_miss_latency::total 2539500 # number of WriteReq miss cycles 2011system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 546000 # number of SwapReq miss cycles 2012system.cpu3.dcache.SwapReq_miss_latency::total 546000 # number of SwapReq miss cycles 2013system.cpu3.dcache.demand_miss_latency::cpu3.data 7421000 # number of demand (read+write) miss cycles 2014system.cpu3.dcache.demand_miss_latency::total 7421000 # number of demand (read+write) miss cycles 2015system.cpu3.dcache.overall_miss_latency::cpu3.data 7421000 # number of overall miss cycles 2016system.cpu3.dcache.overall_miss_latency::total 7421000 # number of overall miss cycles 2017system.cpu3.dcache.ReadReq_accesses::cpu3.data 41641 # number of ReadReq accesses(hits+misses) 2018system.cpu3.dcache.ReadReq_accesses::total 41641 # number of ReadReq accesses(hits+misses) 2019system.cpu3.dcache.WriteReq_accesses::cpu3.data 30200 # number of WriteReq accesses(hits+misses) 2020system.cpu3.dcache.WriteReq_accesses::total 30200 # number of WriteReq accesses(hits+misses) 2021system.cpu3.dcache.SwapReq_accesses::cpu3.data 74 # number of SwapReq accesses(hits+misses) 2022system.cpu3.dcache.SwapReq_accesses::total 74 # number of SwapReq accesses(hits+misses) 2023system.cpu3.dcache.demand_accesses::cpu3.data 71841 # number of demand (read+write) accesses 2024system.cpu3.dcache.demand_accesses::total 71841 # number of demand (read+write) accesses 2025system.cpu3.dcache.overall_accesses::cpu3.data 71841 # number of overall (read+write) accesses 2026system.cpu3.dcache.overall_accesses::total 71841 # number of overall (read+write) accesses 2027system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009030 # miss rate for ReadReq accesses 2028system.cpu3.dcache.ReadReq_miss_rate::total 0.009030 # miss rate for ReadReq accesses 2029system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004305 # miss rate for WriteReq accesses 2030system.cpu3.dcache.WriteReq_miss_rate::total 0.004305 # miss rate for WriteReq accesses 2031system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.797297 # miss rate for SwapReq accesses 2032system.cpu3.dcache.SwapReq_miss_rate::total 0.797297 # miss rate for SwapReq accesses 2033system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007043 # miss rate for demand accesses 2034system.cpu3.dcache.demand_miss_rate::total 0.007043 # miss rate for demand accesses 2035system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007043 # miss rate for overall accesses 2036system.cpu3.dcache.overall_miss_rate::total 0.007043 # miss rate for overall accesses 2037system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12982.712766 # average ReadReq miss latency 2038system.cpu3.dcache.ReadReq_avg_miss_latency::total 12982.712766 # average ReadReq miss latency 2039system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19534.615385 # average WriteReq miss latency 2040system.cpu3.dcache.WriteReq_avg_miss_latency::total 19534.615385 # average WriteReq miss latency 2041system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9254.237288 # average SwapReq miss latency 2042system.cpu3.dcache.SwapReq_avg_miss_latency::total 9254.237288 # average SwapReq miss latency 2043system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14666.007905 # average overall miss latency 2044system.cpu3.dcache.demand_avg_miss_latency::total 14666.007905 # average overall miss latency 2045system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14666.007905 # average overall miss latency 2046system.cpu3.dcache.overall_avg_miss_latency::total 14666.007905 # average overall miss latency 2047system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2048system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2049system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2050system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2051system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2052system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2053system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2054system.cpu3.dcache.cache_copies 0 # number of cache copies performed 2055system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 218 # number of ReadReq MSHR hits 2056system.cpu3.dcache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits 2057system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 30 # number of WriteReq MSHR hits 2058system.cpu3.dcache.WriteReq_mshr_hits::total 30 # number of WriteReq MSHR hits 2059system.cpu3.dcache.demand_mshr_hits::cpu3.data 248 # number of demand (read+write) MSHR hits 2060system.cpu3.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits 2061system.cpu3.dcache.overall_mshr_hits::cpu3.data 248 # number of overall MSHR hits 2062system.cpu3.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits 2063system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 158 # number of ReadReq MSHR misses 2064system.cpu3.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses 2065system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 100 # number of WriteReq MSHR misses 2066system.cpu3.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses 2067system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 59 # number of SwapReq MSHR misses 2068system.cpu3.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses 2069system.cpu3.dcache.demand_mshr_misses::cpu3.data 258 # number of demand (read+write) MSHR misses 2070system.cpu3.dcache.demand_mshr_misses::total 258 # number of demand (read+write) MSHR misses 2071system.cpu3.dcache.overall_mshr_misses::cpu3.data 258 # number of overall MSHR misses 2072system.cpu3.dcache.overall_mshr_misses::total 258 # number of overall MSHR misses 2073system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1328000 # number of ReadReq MSHR miss cycles 2074system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1328000 # number of ReadReq MSHR miss cycles 2075system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1243000 # number of WriteReq MSHR miss cycles 2076system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1243000 # number of WriteReq MSHR miss cycles 2077system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 428000 # number of SwapReq MSHR miss cycles 2078system.cpu3.dcache.SwapReq_mshr_miss_latency::total 428000 # number of SwapReq MSHR miss cycles 2079system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2571000 # number of demand (read+write) MSHR miss cycles 2080system.cpu3.dcache.demand_mshr_miss_latency::total 2571000 # number of demand (read+write) MSHR miss cycles 2081system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2571000 # number of overall MSHR miss cycles 2082system.cpu3.dcache.overall_mshr_miss_latency::total 2571000 # number of overall MSHR miss cycles 2083system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003794 # mshr miss rate for ReadReq accesses 2084system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003794 # mshr miss rate for ReadReq accesses 2085system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003311 # mshr miss rate for WriteReq accesses 2086system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003311 # mshr miss rate for WriteReq accesses 2087system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.797297 # mshr miss rate for SwapReq accesses 2088system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.797297 # mshr miss rate for SwapReq accesses 2089system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for demand accesses 2090system.cpu3.dcache.demand_mshr_miss_rate::total 0.003591 # mshr miss rate for demand accesses 2091system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for overall accesses 2092system.cpu3.dcache.overall_mshr_miss_rate::total 0.003591 # mshr miss rate for overall accesses 2093system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8405.063291 # average ReadReq mshr miss latency 2094system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8405.063291 # average ReadReq mshr miss latency 2095system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12430 # average WriteReq mshr miss latency 2096system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12430 # average WriteReq mshr miss latency 2097system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7254.237288 # average SwapReq mshr miss latency 2098system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7254.237288 # average SwapReq mshr miss latency 2099system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9965.116279 # average overall mshr miss latency 2100system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency 2101system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9965.116279 # average overall mshr miss latency 2102system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency 2103system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2104system.l2c.replacements 0 # number of replacements 2105system.l2c.tagsinuse 425.230696 # Cycle average of tags in use 2106system.l2c.total_refs 1445 # Total number of references to valid blocks. 2107system.l2c.sampled_refs 527 # Sample count of references to valid blocks. 2108system.l2c.avg_refs 2.741935 # Average number of references to valid blocks. 2109system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2110system.l2c.occ_blocks::writebacks 0.824596 # Average occupied blocks per requestor 2111system.l2c.occ_blocks::cpu0.inst 289.832859 # Average occupied blocks per requestor 2112system.l2c.occ_blocks::cpu0.data 59.073855 # Average occupied blocks per requestor 2113system.l2c.occ_blocks::cpu1.inst 61.730807 # Average occupied blocks per requestor 2114system.l2c.occ_blocks::cpu1.data 5.603647 # Average occupied blocks per requestor 2115system.l2c.occ_blocks::cpu2.inst 4.388882 # Average occupied blocks per requestor 2116system.l2c.occ_blocks::cpu2.data 0.760374 # Average occupied blocks per requestor 2117system.l2c.occ_blocks::cpu3.inst 2.293580 # Average occupied blocks per requestor 2118system.l2c.occ_blocks::cpu3.data 0.722095 # Average occupied blocks per requestor 2119system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy 2120system.l2c.occ_percent::cpu0.inst 0.004422 # Average percentage of cache occupancy 2121system.l2c.occ_percent::cpu0.data 0.000901 # Average percentage of cache occupancy 2122system.l2c.occ_percent::cpu1.inst 0.000942 # Average percentage of cache occupancy 2123system.l2c.occ_percent::cpu1.data 0.000086 # Average percentage of cache occupancy 2124system.l2c.occ_percent::cpu2.inst 0.000067 # Average percentage of cache occupancy 2125system.l2c.occ_percent::cpu2.data 0.000012 # Average percentage of cache occupancy 2126system.l2c.occ_percent::cpu3.inst 0.000035 # Average percentage of cache occupancy 2127system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy 2128system.l2c.occ_percent::total 0.006489 # Average percentage of cache occupancy 2129system.l2c.ReadReq_hits::cpu0.inst 230 # number of ReadReq hits 2130system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 2131system.l2c.ReadReq_hits::cpu1.inst 342 # number of ReadReq hits 2132system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits 2133system.l2c.ReadReq_hits::cpu2.inst 418 # number of ReadReq hits 2134system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits 2135system.l2c.ReadReq_hits::cpu3.inst 423 # number of ReadReq hits 2136system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits 2137system.l2c.ReadReq_hits::total 1445 # number of ReadReq hits 2138system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 2139system.l2c.Writeback_hits::total 1 # number of Writeback hits 2140system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 2141system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 2142system.l2c.demand_hits::cpu0.inst 230 # number of demand (read+write) hits 2143system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 2144system.l2c.demand_hits::cpu1.inst 342 # number of demand (read+write) hits 2145system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits 2146system.l2c.demand_hits::cpu2.inst 418 # number of demand (read+write) hits 2147system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits 2148system.l2c.demand_hits::cpu3.inst 423 # number of demand (read+write) hits 2149system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 2150system.l2c.demand_hits::total 1445 # number of demand (read+write) hits 2151system.l2c.overall_hits::cpu0.inst 230 # number of overall hits 2152system.l2c.overall_hits::cpu0.data 5 # number of overall hits 2153system.l2c.overall_hits::cpu1.inst 342 # number of overall hits 2154system.l2c.overall_hits::cpu1.data 5 # number of overall hits 2155system.l2c.overall_hits::cpu2.inst 418 # number of overall hits 2156system.l2c.overall_hits::cpu2.data 11 # number of overall hits 2157system.l2c.overall_hits::cpu3.inst 423 # number of overall hits 2158system.l2c.overall_hits::cpu3.data 11 # number of overall hits 2159system.l2c.overall_hits::total 1445 # number of overall hits 2160system.l2c.ReadReq_misses::cpu0.inst 360 # number of ReadReq misses 2161system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses 2162system.l2c.ReadReq_misses::cpu1.inst 83 # number of ReadReq misses 2163system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses 2164system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses 2165system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses 2166system.l2c.ReadReq_misses::cpu3.inst 6 # number of ReadReq misses 2167system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 2168system.l2c.ReadReq_misses::total 544 # number of ReadReq misses 2169system.l2c.UpgradeReq_misses::cpu0.data 18 # number of UpgradeReq misses 2170system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses 2171system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses 2172system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses 2173system.l2c.UpgradeReq_misses::total 71 # number of UpgradeReq misses 2174system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 2175system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 2176system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 2177system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 2178system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses 2179system.l2c.demand_misses::cpu0.inst 360 # number of demand (read+write) misses 2180system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses 2181system.l2c.demand_misses::cpu1.inst 83 # number of demand (read+write) misses 2182system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses 2183system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses 2184system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses 2185system.l2c.demand_misses::cpu3.inst 6 # number of demand (read+write) misses 2186system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 2187system.l2c.demand_misses::total 675 # number of demand (read+write) misses 2188system.l2c.overall_misses::cpu0.inst 360 # number of overall misses 2189system.l2c.overall_misses::cpu0.data 168 # number of overall misses 2190system.l2c.overall_misses::cpu1.inst 83 # number of overall misses 2191system.l2c.overall_misses::cpu1.data 20 # number of overall misses 2192system.l2c.overall_misses::cpu2.inst 12 # number of overall misses 2193system.l2c.overall_misses::cpu2.data 13 # number of overall misses 2194system.l2c.overall_misses::cpu3.inst 6 # number of overall misses 2195system.l2c.overall_misses::cpu3.data 13 # number of overall misses 2196system.l2c.overall_misses::total 675 # number of overall misses 2197system.l2c.ReadReq_miss_latency::cpu0.inst 18237500 # number of ReadReq miss cycles 2198system.l2c.ReadReq_miss_latency::cpu0.data 4615000 # number of ReadReq miss cycles 2199system.l2c.ReadReq_miss_latency::cpu1.inst 4399500 # number of ReadReq miss cycles 2200system.l2c.ReadReq_miss_latency::cpu1.data 666000 # number of ReadReq miss cycles 2201system.l2c.ReadReq_miss_latency::cpu2.inst 728500 # number of ReadReq miss cycles 2202system.l2c.ReadReq_miss_latency::cpu2.data 68500 # number of ReadReq miss cycles 2203system.l2c.ReadReq_miss_latency::cpu3.inst 248500 # number of ReadReq miss cycles 2204system.l2c.ReadReq_miss_latency::cpu3.data 68500 # number of ReadReq miss cycles 2205system.l2c.ReadReq_miss_latency::total 29032000 # number of ReadReq miss cycles 2206system.l2c.ReadExReq_miss_latency::cpu0.data 5403000 # number of ReadExReq miss cycles 2207system.l2c.ReadExReq_miss_latency::cpu1.data 996000 # number of ReadExReq miss cycles 2208system.l2c.ReadExReq_miss_latency::cpu2.data 869000 # number of ReadExReq miss cycles 2209system.l2c.ReadExReq_miss_latency::cpu3.data 756000 # number of ReadExReq miss cycles 2210system.l2c.ReadExReq_miss_latency::total 8024000 # number of ReadExReq miss cycles 2211system.l2c.demand_miss_latency::cpu0.inst 18237500 # number of demand (read+write) miss cycles 2212system.l2c.demand_miss_latency::cpu0.data 10018000 # number of demand (read+write) miss cycles 2213system.l2c.demand_miss_latency::cpu1.inst 4399500 # number of demand (read+write) miss cycles 2214system.l2c.demand_miss_latency::cpu1.data 1662000 # number of demand (read+write) miss cycles 2215system.l2c.demand_miss_latency::cpu2.inst 728500 # number of demand (read+write) miss cycles 2216system.l2c.demand_miss_latency::cpu2.data 937500 # number of demand (read+write) miss cycles 2217system.l2c.demand_miss_latency::cpu3.inst 248500 # number of demand (read+write) miss cycles 2218system.l2c.demand_miss_latency::cpu3.data 824500 # number of demand (read+write) miss cycles 2219system.l2c.demand_miss_latency::total 37056000 # number of demand (read+write) miss cycles 2220system.l2c.overall_miss_latency::cpu0.inst 18237500 # number of overall miss cycles 2221system.l2c.overall_miss_latency::cpu0.data 10018000 # number of overall miss cycles 2222system.l2c.overall_miss_latency::cpu1.inst 4399500 # number of overall miss cycles 2223system.l2c.overall_miss_latency::cpu1.data 1662000 # number of overall miss cycles 2224system.l2c.overall_miss_latency::cpu2.inst 728500 # number of overall miss cycles 2225system.l2c.overall_miss_latency::cpu2.data 937500 # number of overall miss cycles 2226system.l2c.overall_miss_latency::cpu3.inst 248500 # number of overall miss cycles 2227system.l2c.overall_miss_latency::cpu3.data 824500 # number of overall miss cycles 2228system.l2c.overall_miss_latency::total 37056000 # number of overall miss cycles 2229system.l2c.ReadReq_accesses::cpu0.inst 590 # number of ReadReq accesses(hits+misses) 2230system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) 2231system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses) 2232system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) 2233system.l2c.ReadReq_accesses::cpu2.inst 430 # number of ReadReq accesses(hits+misses) 2234system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) 2235system.l2c.ReadReq_accesses::cpu3.inst 429 # number of ReadReq accesses(hits+misses) 2236system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) 2237system.l2c.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses) 2238system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 2239system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 2240system.l2c.UpgradeReq_accesses::cpu0.data 21 # number of UpgradeReq accesses(hits+misses) 2241system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) 2242system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) 2243system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) 2244system.l2c.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses) 2245system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 2246system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 2247system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 2248system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 2249system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) 2250system.l2c.demand_accesses::cpu0.inst 590 # number of demand (read+write) accesses 2251system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses 2252system.l2c.demand_accesses::cpu1.inst 425 # number of demand (read+write) accesses 2253system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses 2254system.l2c.demand_accesses::cpu2.inst 430 # number of demand (read+write) accesses 2255system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses 2256system.l2c.demand_accesses::cpu3.inst 429 # number of demand (read+write) accesses 2257system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses 2258system.l2c.demand_accesses::total 2120 # number of demand (read+write) accesses 2259system.l2c.overall_accesses::cpu0.inst 590 # number of overall (read+write) accesses 2260system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses 2261system.l2c.overall_accesses::cpu1.inst 425 # number of overall (read+write) accesses 2262system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses 2263system.l2c.overall_accesses::cpu2.inst 430 # number of overall (read+write) accesses 2264system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses 2265system.l2c.overall_accesses::cpu3.inst 429 # number of overall (read+write) accesses 2266system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses 2267system.l2c.overall_accesses::total 2120 # number of overall (read+write) accesses 2268system.l2c.ReadReq_miss_rate::cpu0.inst 0.610169 # miss rate for ReadReq accesses 2269system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses 2270system.l2c.ReadReq_miss_rate::cpu1.inst 0.195294 # miss rate for ReadReq accesses 2271system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses 2272system.l2c.ReadReq_miss_rate::cpu2.inst 0.027907 # miss rate for ReadReq accesses 2273system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses 2274system.l2c.ReadReq_miss_rate::cpu3.inst 0.013986 # miss rate for ReadReq accesses 2275system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses 2276system.l2c.ReadReq_miss_rate::total 0.273504 # miss rate for ReadReq accesses 2277system.l2c.UpgradeReq_miss_rate::cpu0.data 0.857143 # miss rate for UpgradeReq accesses 2278system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2279system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 2280system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 2281system.l2c.UpgradeReq_miss_rate::total 0.959459 # miss rate for UpgradeReq accesses 2282system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 2283system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 2284system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 2285system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 2286system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 2287system.l2c.demand_miss_rate::cpu0.inst 0.610169 # miss rate for demand accesses 2288system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses 2289system.l2c.demand_miss_rate::cpu1.inst 0.195294 # miss rate for demand accesses 2290system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses 2291system.l2c.demand_miss_rate::cpu2.inst 0.027907 # miss rate for demand accesses 2292system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses 2293system.l2c.demand_miss_rate::cpu3.inst 0.013986 # miss rate for demand accesses 2294system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses 2295system.l2c.demand_miss_rate::total 0.318396 # miss rate for demand accesses 2296system.l2c.overall_miss_rate::cpu0.inst 0.610169 # miss rate for overall accesses 2297system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses 2298system.l2c.overall_miss_rate::cpu1.inst 0.195294 # miss rate for overall accesses 2299system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses 2300system.l2c.overall_miss_rate::cpu2.inst 0.027907 # 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number of overall MSHR miss cycles 2428system.l2c.overall_mshr_miss_latency::cpu1.data 1417011 # number of overall MSHR miss cycles 2429system.l2c.overall_mshr_miss_latency::cpu2.inst 230755 # number of overall MSHR miss cycles 2430system.l2c.overall_mshr_miss_latency::cpu2.data 776261 # number of overall MSHR miss cycles 2431system.l2c.overall_mshr_miss_latency::cpu3.inst 86253 # number of overall MSHR miss cycles 2432system.l2c.overall_mshr_miss_latency::cpu3.data 663761 # number of overall MSHR miss cycles 2433system.l2c.overall_mshr_miss_latency::total 28135994 # number of overall MSHR miss cycles 2434system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for ReadReq accesses 2435system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses 2436system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for ReadReq accesses 2437system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses 2438system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.013953 # 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mshr miss rate for ReadExReq accesses 2450system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 2451system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 2452system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 2453system.l2c.demand_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for demand accesses 2454system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses 2455system.l2c.demand_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for demand accesses 2456system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses 2457system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for demand accesses 2458system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses 2459system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for demand accesses 2460system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses 2461system.l2c.demand_mshr_miss_rate::total 0.311792 # mshr miss rate for demand accesses 2462system.l2c.overall_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for overall accesses 2463system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses 2464system.l2c.overall_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for overall accesses 2465system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses 2466system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for overall accesses 2467system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses 2468system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for overall accesses 2469system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 2470system.l2c.overall_mshr_miss_rate::total 0.311792 # mshr miss rate for overall accesses 2471system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average ReadReq mshr miss latency 2472system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.162162 # average ReadReq mshr miss latency 2473system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average ReadReq mshr miss latency 2474system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608 # average ReadReq mshr miss latency 2475system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average ReadReq mshr miss latency 2476system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56251 # average ReadReq mshr miss latency 2477system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28751 # average ReadReq mshr miss latency 2478system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56251 # average ReadReq mshr miss latency 2479system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.152830 # average ReadReq mshr miss latency 2480system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency 2481system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.263158 # average UpgradeReq mshr miss latency 2482system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10094.562500 # average UpgradeReq mshr miss latency 2483system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10639.500000 # average UpgradeReq mshr miss latency 2484system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10247.211268 # average UpgradeReq mshr miss latency 2485system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45181.468085 # average ReadExReq mshr miss latency 2486system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64519.615385 # average ReadExReq mshr miss latency 2487system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60000.833333 # average ReadExReq mshr miss latency 2488system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50625.833333 # average ReadExReq mshr miss latency 2489system.l2c.ReadExReq_avg_mshr_miss_latency::total 48956.740458 # average ReadExReq mshr miss latency 2490system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency 2491system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency 2492system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency 2493system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency 2494system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency 2495system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency 2496system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency 2497system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency 2498system.l2c.demand_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency 2499system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency 2500system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency 2501system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency 2502system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency 2503system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency 2504system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency 2505system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency 2506system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency 2507system.l2c.overall_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency 2508system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2509 2510---------- End Simulation Statistics ---------- 2511