stats.txt revision 9150:a2370fa5c793
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000114 # Number of seconds simulated 4sim_ticks 113910500 # Number of ticks simulated 5final_tick 113910500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 141669 # Simulator instruction rate (inst/s) 8host_op_rate 141669 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14682125 # Simulator tick rate (ticks/s) 10host_mem_usage 244464 # Number of bytes of host memory used 11host_seconds 7.76 # Real time elapsed on the host 12sim_insts 1099129 # Number of instructions simulated 13sim_ops 1099129 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 5376 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 22system.physmem.bytes_read::total 42944 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 5376 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 29248 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 84 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 36system.physmem.num_reads::total 671 # Number of read requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 203387747 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 94389894 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 47194947 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 11236892 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 2809223 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 7303980 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 3371068 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 7303980 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 376997731 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 203387747 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 47194947 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 2809223 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 3371068 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 256762985 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 203387747 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 94389894 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 47194947 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 11236892 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 2809223 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 7303980 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 3371068 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 7303980 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 376997731 # Total bandwidth to/from this memory (bytes/s) 60system.cpu0.workload.num_syscalls 89 # Number of system calls 61system.cpu0.numCycles 227822 # number of cpu cycles simulated 62system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 63system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 64system.cpu0.BPredUnit.lookups 88179 # Number of BP lookups 65system.cpu0.BPredUnit.condPredicted 85929 # Number of conditional branches predicted 66system.cpu0.BPredUnit.condIncorrect 1290 # Number of conditional branches incorrect 67system.cpu0.BPredUnit.BTBLookups 85894 # Number of BTB lookups 68system.cpu0.BPredUnit.BTBHits 83486 # Number of BTB hits 69system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 70system.cpu0.BPredUnit.usedRAS 517 # Number of times the RAS was used to get a target. 71system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. 72system.cpu0.fetch.icacheStallCycles 17727 # Number of cycles fetch is stalled on an Icache miss 73system.cpu0.fetch.Insts 523680 # Number of instructions fetch has processed 74system.cpu0.fetch.Branches 88179 # Number of branches that fetch encountered 75system.cpu0.fetch.predictedBranches 84003 # Number of branches that fetch has predicted taken 76system.cpu0.fetch.Cycles 172095 # Number of cycles fetch has run and was not squashing or blocked 77system.cpu0.fetch.SquashCycles 4009 # Number of cycles fetch has spent squashing 78system.cpu0.fetch.BlockedCycles 15408 # Number of cycles fetch has spent blocked 79system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 80system.cpu0.fetch.PendingTrapStallCycles 1281 # Number of stall cycles due to pending traps 81system.cpu0.fetch.CacheLines 6036 # Number of cache lines fetched 82system.cpu0.fetch.IcacheSquashes 519 # Number of outstanding Icache misses that were squashed 83system.cpu0.fetch.rateDist::samples 209087 # Number of instructions fetched each cycle (Total) 84system.cpu0.fetch.rateDist::mean 2.504603 # Number of instructions fetched each cycle (Total) 85system.cpu0.fetch.rateDist::stdev 2.209881 # Number of instructions fetched each cycle (Total) 86system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 87system.cpu0.fetch.rateDist::0 36992 17.69% 17.69% # Number of instructions fetched each cycle (Total) 88system.cpu0.fetch.rateDist::1 85294 40.79% 58.49% # Number of instructions fetched each cycle (Total) 89system.cpu0.fetch.rateDist::2 585 0.28% 58.77% # Number of instructions fetched each cycle (Total) 90system.cpu0.fetch.rateDist::3 1000 0.48% 59.24% # Number of instructions fetched each cycle (Total) 91system.cpu0.fetch.rateDist::4 484 0.23% 59.48% # Number of instructions fetched each cycle (Total) 92system.cpu0.fetch.rateDist::5 81297 38.88% 98.36% # Number of instructions fetched each cycle (Total) 93system.cpu0.fetch.rateDist::6 665 0.32% 98.68% # Number of instructions fetched each cycle (Total) 94system.cpu0.fetch.rateDist::7 355 0.17% 98.84% # Number of instructions fetched each cycle (Total) 95system.cpu0.fetch.rateDist::8 2415 1.16% 100.00% # Number of instructions fetched each cycle (Total) 96system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 97system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 98system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 99system.cpu0.fetch.rateDist::total 209087 # Number of instructions fetched each cycle (Total) 100system.cpu0.fetch.branchRate 0.387052 # Number of branch fetches per cycle 101system.cpu0.fetch.rate 2.298637 # Number of inst fetches per cycle 102system.cpu0.decode.IdleCycles 18268 # Number of cycles decode is idle 103system.cpu0.decode.BlockedCycles 16880 # Number of cycles decode is blocked 104system.cpu0.decode.RunCycles 171017 # Number of cycles decode is running 105system.cpu0.decode.UnblockCycles 351 # Number of cycles decode is unblocking 106system.cpu0.decode.SquashCycles 2571 # Number of cycles decode is squashing 107system.cpu0.decode.DecodedInsts 520658 # Number of instructions handled by decode 108system.cpu0.rename.SquashCycles 2571 # Number of cycles rename is squashing 109system.cpu0.rename.IdleCycles 18993 # Number of cycles rename is idle 110system.cpu0.rename.BlockCycles 2288 # Number of cycles rename is blocking 111system.cpu0.rename.serializeStallCycles 13870 # count of cycles rename stalled for serializing inst 112system.cpu0.rename.RunCycles 170679 # Number of cycles rename is running 113system.cpu0.rename.UnblockCycles 686 # Number of cycles rename is unblocking 114system.cpu0.rename.RenamedInsts 517484 # Number of instructions processed by rename 115system.cpu0.rename.LSQFullEvents 297 # Number of times rename has blocked due to LSQ full 116system.cpu0.rename.RenamedOperands 353459 # Number of destination operands rename has renamed 117system.cpu0.rename.RenameLookups 1032335 # Number of register rename lookups that rename has made 118system.cpu0.rename.int_rename_lookups 1032335 # Number of integer rename lookups 119system.cpu0.rename.CommittedMaps 339779 # Number of HB maps that are committed 120system.cpu0.rename.UndoneMaps 13680 # Number of HB maps that are undone due to squashing 121system.cpu0.rename.serializingInsts 904 # count of serializing insts renamed 122system.cpu0.rename.tempSerializingInsts 933 # count of temporary serializing insts renamed 123system.cpu0.rename.skidInsts 4009 # count of insts added to the skid buffer 124system.cpu0.memDep0.insertedLoads 165974 # Number of loads inserted to the mem dependence unit. 125system.cpu0.memDep0.insertedStores 83785 # Number of stores inserted to the mem dependence unit. 126system.cpu0.memDep0.conflictingLoads 81138 # Number of conflicting loads. 127system.cpu0.memDep0.conflictingStores 80830 # Number of conflicting stores. 128system.cpu0.iq.iqInstsAdded 432592 # Number of instructions added to the IQ (excludes non-spec) 129system.cpu0.iq.iqNonSpecInstsAdded 951 # Number of non-speculative instructions added to the IQ 130system.cpu0.iq.iqInstsIssued 429324 # Number of instructions issued 131system.cpu0.iq.iqSquashedInstsIssued 270 # Number of squashed instructions issued 132system.cpu0.iq.iqSquashedInstsExamined 11361 # Number of squashed instructions iterated over during squash; mainly for profiling 133system.cpu0.iq.iqSquashedOperandsExamined 11323 # Number of squashed operands that are examined and possibly removed from graph 134system.cpu0.iq.iqSquashedNonSpecRemoved 392 # Number of squashed non-spec instructions that were removed 135system.cpu0.iq.issued_per_cycle::samples 209087 # Number of insts issued each cycle 136system.cpu0.iq.issued_per_cycle::mean 2.053327 # Number of insts issued each cycle 137system.cpu0.iq.issued_per_cycle::stdev 1.097112 # Number of insts issued each cycle 138system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 139system.cpu0.iq.issued_per_cycle::0 36280 17.35% 17.35% # Number of insts issued each cycle 140system.cpu0.iq.issued_per_cycle::1 5325 2.55% 19.90% # Number of insts issued each cycle 141system.cpu0.iq.issued_per_cycle::2 82668 39.54% 59.44% # Number of insts issued each cycle 142system.cpu0.iq.issued_per_cycle::3 82134 39.28% 98.72% # Number of insts issued each cycle 143system.cpu0.iq.issued_per_cycle::4 1638 0.78% 99.50% # Number of insts issued each cycle 144system.cpu0.iq.issued_per_cycle::5 661 0.32% 99.82% # Number of insts issued each cycle 145system.cpu0.iq.issued_per_cycle::6 275 0.13% 99.95% # Number of insts issued each cycle 146system.cpu0.iq.issued_per_cycle::7 94 0.04% 99.99% # Number of insts issued each cycle 147system.cpu0.iq.issued_per_cycle::8 12 0.01% 100.00% # Number of insts issued each cycle 148system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 149system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 150system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 151system.cpu0.iq.issued_per_cycle::total 209087 # Number of insts issued each cycle 152system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 153system.cpu0.iq.fu_full::IntAlu 52 18.77% 18.77% # attempts to use FU when none available 154system.cpu0.iq.fu_full::IntMult 0 0.00% 18.77% # attempts to use FU when none available 155system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.77% # attempts to use FU when none available 156system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.77% # attempts to use FU when none available 157system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.77% # attempts to use FU when none available 158system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.77% # attempts to use FU when none available 159system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.77% # attempts to use FU when none available 160system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.77% # attempts to use FU when none available 161system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.77% # attempts to use FU when none available 162system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.77% # attempts to use FU when none available 163system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.77% # attempts to use FU when none available 164system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.77% # attempts to use FU when none available 165system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.77% # attempts to use FU when none available 166system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.77% # attempts to use FU when none available 167system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.77% # attempts to use FU when none available 168system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.77% # attempts to use FU when none available 169system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.77% # attempts to use FU when none available 170system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.77% # attempts to use FU when none available 171system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.77% # attempts to use FU when none available 172system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.77% # attempts to use FU when none available 173system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.77% # attempts to use FU when none available 174system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.77% # attempts to use FU when none available 175system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.77% # attempts to use FU when none available 176system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.77% # attempts to use FU when none available 177system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.77% # attempts to use FU when none available 178system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.77% # attempts to use FU when none available 179system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.77% # attempts to use FU when none available 180system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.77% # attempts to use FU when none available 181system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.77% # attempts to use FU when none available 182system.cpu0.iq.fu_full::MemRead 113 40.79% 59.57% # attempts to use FU when none available 183system.cpu0.iq.fu_full::MemWrite 112 40.43% 100.00% # attempts to use FU when none available 184system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 185system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 186system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 187system.cpu0.iq.FU_type_0::IntAlu 180924 42.14% 42.14% # Type of FU issued 188system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.14% # Type of FU issued 189system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.14% # Type of FU issued 190system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.14% # Type of FU issued 191system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.14% # Type of FU issued 192system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.14% # Type of FU issued 193system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.14% # Type of FU issued 194system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.14% # Type of FU issued 195system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.14% # Type of FU issued 196system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.14% # Type of FU issued 197system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.14% # Type of FU issued 198system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.14% # Type of FU issued 199system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.14% # Type of FU issued 200system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.14% # Type of FU issued 201system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.14% # Type of FU issued 202system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.14% # Type of FU issued 203system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.14% # Type of FU issued 204system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.14% # Type of FU issued 205system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.14% # Type of FU issued 206system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.14% # Type of FU issued 207system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.14% # Type of FU issued 208system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.14% # Type of FU issued 209system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.14% # Type of FU issued 210system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.14% # Type of FU issued 211system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.14% # Type of FU issued 212system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.14% # Type of FU issued 213system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.14% # Type of FU issued 214system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.14% # Type of FU issued 215system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.14% # Type of FU issued 216system.cpu0.iq.FU_type_0::MemRead 165296 38.50% 80.64% # Type of FU issued 217system.cpu0.iq.FU_type_0::MemWrite 83104 19.36% 100.00% # Type of FU issued 218system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 219system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 220system.cpu0.iq.FU_type_0::total 429324 # Type of FU issued 221system.cpu0.iq.rate 1.884471 # Inst issue rate 222system.cpu0.iq.fu_busy_cnt 277 # FU busy when requested 223system.cpu0.iq.fu_busy_rate 0.000645 # FU busy rate (busy events/executed inst) 224system.cpu0.iq.int_inst_queue_reads 1068282 # Number of integer instruction queue reads 225system.cpu0.iq.int_inst_queue_writes 444960 # Number of integer instruction queue writes 226system.cpu0.iq.int_inst_queue_wakeup_accesses 427393 # Number of integer instruction queue wakeup accesses 227system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 228system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 229system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 230system.cpu0.iq.int_alu_accesses 429601 # Number of integer alu accesses 231system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses 232system.cpu0.iew.lsq.thread0.forwLoads 80458 # Number of loads that had data forwarded from stores 233system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 234system.cpu0.iew.lsq.thread0.squashedLoads 2495 # Number of loads squashed 235system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 236system.cpu0.iew.lsq.thread0.memOrderViolation 56 # Number of memory ordering violations 237system.cpu0.iew.lsq.thread0.squashedStores 1539 # Number of stores squashed 238system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 239system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 240system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 241system.cpu0.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked 242system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 243system.cpu0.iew.iewSquashCycles 2571 # Number of cycles IEW is squashing 244system.cpu0.iew.iewBlockCycles 1789 # Number of cycles IEW is blocking 245system.cpu0.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking 246system.cpu0.iew.iewDispatchedInsts 515149 # Number of instructions dispatched to IQ 247system.cpu0.iew.iewDispSquashedInsts 291 # Number of squashed instructions skipped by dispatch 248system.cpu0.iew.iewDispLoadInsts 165974 # Number of dispatched load instructions 249system.cpu0.iew.iewDispStoreInsts 83785 # Number of dispatched store instructions 250system.cpu0.iew.iewDispNonSpecInsts 838 # Number of dispatched non-speculative instructions 251system.cpu0.iew.iewIQFullEvents 95 # Number of times the IQ has become full, causing a stall 252system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 253system.cpu0.iew.memOrderViolationEvents 56 # Number of memory order violations 254system.cpu0.iew.predictedTakenIncorrect 383 # Number of branches that were predicted taken incorrectly 255system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly 256system.cpu0.iew.branchMispredicts 1496 # Number of branch mispredicts detected at execute 257system.cpu0.iew.iewExecutedInsts 428216 # Number of executed instructions 258system.cpu0.iew.iewExecLoadInsts 164977 # Number of load instructions executed 259system.cpu0.iew.iewExecSquashedInsts 1108 # Number of squashed instructions skipped in execute 260system.cpu0.iew.exec_swp 0 # number of swp insts executed 261system.cpu0.iew.exec_nop 81606 # number of nop insts executed 262system.cpu0.iew.exec_refs 247935 # number of memory reference insts executed 263system.cpu0.iew.exec_branches 85106 # Number of branches executed 264system.cpu0.iew.exec_stores 82958 # Number of stores executed 265system.cpu0.iew.exec_rate 1.879608 # Inst execution rate 266system.cpu0.iew.wb_sent 427739 # cumulative count of insts sent to commit 267system.cpu0.iew.wb_count 427393 # cumulative count of insts written-back 268system.cpu0.iew.wb_producers 253334 # num instructions producing a value 269system.cpu0.iew.wb_consumers 255736 # num instructions consuming a value 270system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 271system.cpu0.iew.wb_rate 1.875995 # insts written-back per cycle 272system.cpu0.iew.wb_fanout 0.990608 # average fanout of values written-back 273system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 274system.cpu0.commit.commitCommittedInsts 502020 # The number of committed instructions 275system.cpu0.commit.commitCommittedOps 502020 # The number of committed instructions 276system.cpu0.commit.commitSquashedInsts 13085 # The number of squashed insts skipped by commit 277system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 278system.cpu0.commit.branchMispredicts 1290 # The number of times a branch was mispredicted 279system.cpu0.commit.committed_per_cycle::samples 206533 # Number of insts commited each cycle 280system.cpu0.commit.committed_per_cycle::mean 2.430701 # Number of insts commited each cycle 281system.cpu0.commit.committed_per_cycle::stdev 2.136521 # Number of insts commited each cycle 282system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 283system.cpu0.commit.committed_per_cycle::0 36757 17.80% 17.80% # Number of insts commited each cycle 284system.cpu0.commit.committed_per_cycle::1 84830 41.07% 58.87% # Number of insts commited each cycle 285system.cpu0.commit.committed_per_cycle::2 2489 1.21% 60.08% # Number of insts commited each cycle 286system.cpu0.commit.committed_per_cycle::3 701 0.34% 60.42% # Number of insts commited each cycle 287system.cpu0.commit.committed_per_cycle::4 579 0.28% 60.70% # Number of insts commited each cycle 288system.cpu0.commit.committed_per_cycle::5 80093 38.78% 99.48% # Number of insts commited each cycle 289system.cpu0.commit.committed_per_cycle::6 561 0.27% 99.75% # Number of insts commited each cycle 290system.cpu0.commit.committed_per_cycle::7 222 0.11% 99.85% # Number of insts commited each cycle 291system.cpu0.commit.committed_per_cycle::8 301 0.15% 100.00% # Number of insts commited each cycle 292system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 293system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 294system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 295system.cpu0.commit.committed_per_cycle::total 206533 # Number of insts commited each cycle 296system.cpu0.commit.committedInsts 502020 # Number of instructions committed 297system.cpu0.commit.committedOps 502020 # Number of ops (including micro ops) committed 298system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 299system.cpu0.commit.refs 245725 # Number of memory references committed 300system.cpu0.commit.loads 163479 # Number of loads committed 301system.cpu0.commit.membars 84 # Number of memory barriers committed 302system.cpu0.commit.branches 84133 # Number of branches committed 303system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. 304system.cpu0.commit.int_insts 338110 # Number of committed integer instructions. 305system.cpu0.commit.function_calls 223 # Number of function calls committed. 306system.cpu0.commit.bw_lim_events 301 # number cycles where commit BW limit reached 307system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 308system.cpu0.rob.rob_reads 720176 # The number of ROB reads 309system.cpu0.rob.rob_writes 1032801 # The number of ROB writes 310system.cpu0.timesIdled 336 # Number of times that the entire CPU went into an idle state and unscheduled itself 311system.cpu0.idleCycles 18735 # Total number of cycles that the CPU has spent unscheduled due to idling 312system.cpu0.committedInsts 421071 # Number of Instructions Simulated 313system.cpu0.committedOps 421071 # Number of Ops (including micro ops) Simulated 314system.cpu0.committedInsts_total 421071 # Number of Instructions Simulated 315system.cpu0.cpi 0.541054 # CPI: Cycles Per Instruction 316system.cpu0.cpi_total 0.541054 # CPI: Total CPI of All Threads 317system.cpu0.ipc 1.848246 # IPC: Instructions Per Cycle 318system.cpu0.ipc_total 1.848246 # IPC: Total IPC of All Threads 319system.cpu0.int_regfile_reads 766308 # number of integer regfile reads 320system.cpu0.int_regfile_writes 345106 # number of integer regfile writes 321system.cpu0.fp_regfile_reads 192 # number of floating regfile reads 322system.cpu0.misc_regfile_reads 249733 # number of misc regfile reads 323system.cpu0.misc_regfile_writes 564 # number of misc regfile writes 324system.cpu0.icache.replacements 302 # number of replacements 325system.cpu0.icache.tagsinuse 247.706871 # Cycle average of tags in use 326system.cpu0.icache.total_refs 5276 # Total number of references to valid blocks. 327system.cpu0.icache.sampled_refs 594 # Sample count of references to valid blocks. 328system.cpu0.icache.avg_refs 8.882155 # Average number of references to valid blocks. 329system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 330system.cpu0.icache.occ_blocks::cpu0.inst 247.706871 # Average occupied blocks per requestor 331system.cpu0.icache.occ_percent::cpu0.inst 0.483802 # Average percentage of cache occupancy 332system.cpu0.icache.occ_percent::total 0.483802 # Average percentage of cache occupancy 333system.cpu0.icache.ReadReq_hits::cpu0.inst 5276 # number of ReadReq hits 334system.cpu0.icache.ReadReq_hits::total 5276 # number of ReadReq hits 335system.cpu0.icache.demand_hits::cpu0.inst 5276 # number of demand (read+write) hits 336system.cpu0.icache.demand_hits::total 5276 # number of demand (read+write) hits 337system.cpu0.icache.overall_hits::cpu0.inst 5276 # number of overall hits 338system.cpu0.icache.overall_hits::total 5276 # number of overall hits 339system.cpu0.icache.ReadReq_misses::cpu0.inst 760 # number of ReadReq misses 340system.cpu0.icache.ReadReq_misses::total 760 # number of ReadReq misses 341system.cpu0.icache.demand_misses::cpu0.inst 760 # number of demand (read+write) misses 342system.cpu0.icache.demand_misses::total 760 # number of demand (read+write) misses 343system.cpu0.icache.overall_misses::cpu0.inst 760 # number of overall misses 344system.cpu0.icache.overall_misses::total 760 # number of overall misses 345system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29374500 # number of ReadReq miss cycles 346system.cpu0.icache.ReadReq_miss_latency::total 29374500 # number of ReadReq miss cycles 347system.cpu0.icache.demand_miss_latency::cpu0.inst 29374500 # number of demand (read+write) miss cycles 348system.cpu0.icache.demand_miss_latency::total 29374500 # number of demand (read+write) miss cycles 349system.cpu0.icache.overall_miss_latency::cpu0.inst 29374500 # number of overall miss cycles 350system.cpu0.icache.overall_miss_latency::total 29374500 # number of overall miss cycles 351system.cpu0.icache.ReadReq_accesses::cpu0.inst 6036 # number of ReadReq accesses(hits+misses) 352system.cpu0.icache.ReadReq_accesses::total 6036 # number of ReadReq accesses(hits+misses) 353system.cpu0.icache.demand_accesses::cpu0.inst 6036 # number of demand (read+write) accesses 354system.cpu0.icache.demand_accesses::total 6036 # number of demand (read+write) accesses 355system.cpu0.icache.overall_accesses::cpu0.inst 6036 # number of overall (read+write) accesses 356system.cpu0.icache.overall_accesses::total 6036 # number of overall (read+write) accesses 357system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125911 # miss rate for ReadReq accesses 358system.cpu0.icache.ReadReq_miss_rate::total 0.125911 # miss rate for ReadReq accesses 359system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125911 # miss rate for demand accesses 360system.cpu0.icache.demand_miss_rate::total 0.125911 # miss rate for demand accesses 361system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125911 # miss rate for overall accesses 362system.cpu0.icache.overall_miss_rate::total 0.125911 # miss rate for overall accesses 363system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38650.657895 # average ReadReq miss latency 364system.cpu0.icache.ReadReq_avg_miss_latency::total 38650.657895 # average ReadReq miss latency 365system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38650.657895 # average overall miss latency 366system.cpu0.icache.demand_avg_miss_latency::total 38650.657895 # average overall miss latency 367system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38650.657895 # average overall miss latency 368system.cpu0.icache.overall_avg_miss_latency::total 38650.657895 # average overall miss latency 369system.cpu0.icache.blocked_cycles::no_mshrs 13500 # number of cycles access was blocked 370system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 371system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked 372system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 373system.cpu0.icache.avg_blocked_cycles::no_mshrs 13500 # average number of cycles each access was blocked 374system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 375system.cpu0.icache.fast_writes 0 # number of fast writes performed 376system.cpu0.icache.cache_copies 0 # number of cache copies performed 377system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 165 # number of ReadReq MSHR hits 378system.cpu0.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits 379system.cpu0.icache.demand_mshr_hits::cpu0.inst 165 # number of demand (read+write) MSHR hits 380system.cpu0.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits 381system.cpu0.icache.overall_mshr_hits::cpu0.inst 165 # number of overall MSHR hits 382system.cpu0.icache.overall_mshr_hits::total 165 # number of overall MSHR hits 383system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 595 # number of ReadReq MSHR misses 384system.cpu0.icache.ReadReq_mshr_misses::total 595 # number of ReadReq MSHR misses 385system.cpu0.icache.demand_mshr_misses::cpu0.inst 595 # number of demand (read+write) MSHR misses 386system.cpu0.icache.demand_mshr_misses::total 595 # number of demand (read+write) MSHR misses 387system.cpu0.icache.overall_mshr_misses::cpu0.inst 595 # number of overall MSHR misses 388system.cpu0.icache.overall_mshr_misses::total 595 # number of overall MSHR misses 389system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22317000 # number of ReadReq MSHR miss cycles 390system.cpu0.icache.ReadReq_mshr_miss_latency::total 22317000 # number of ReadReq MSHR miss cycles 391system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22317000 # number of demand (read+write) MSHR miss cycles 392system.cpu0.icache.demand_mshr_miss_latency::total 22317000 # number of demand (read+write) MSHR miss cycles 393system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22317000 # number of overall MSHR miss cycles 394system.cpu0.icache.overall_mshr_miss_latency::total 22317000 # number of overall MSHR miss cycles 395system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.098575 # mshr miss rate for ReadReq accesses 396system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.098575 # mshr miss rate for ReadReq accesses 397system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.098575 # mshr miss rate for demand accesses 398system.cpu0.icache.demand_mshr_miss_rate::total 0.098575 # mshr miss rate for demand accesses 399system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.098575 # mshr miss rate for overall accesses 400system.cpu0.icache.overall_mshr_miss_rate::total 0.098575 # mshr miss rate for overall accesses 401system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37507.563025 # average ReadReq mshr miss latency 402system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37507.563025 # average ReadReq mshr miss latency 403system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37507.563025 # average overall mshr miss latency 404system.cpu0.icache.demand_avg_mshr_miss_latency::total 37507.563025 # average overall mshr miss latency 405system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37507.563025 # average overall mshr miss latency 406system.cpu0.icache.overall_avg_mshr_miss_latency::total 37507.563025 # average overall mshr miss latency 407system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 408system.cpu0.dcache.replacements 2 # number of replacements 409system.cpu0.dcache.tagsinuse 144.389455 # Cycle average of tags in use 410system.cpu0.dcache.total_refs 165484 # Total number of references to valid blocks. 411system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. 412system.cpu0.dcache.avg_refs 973.435294 # Average number of references to valid blocks. 413system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 414system.cpu0.dcache.occ_blocks::cpu0.data 144.389455 # Average occupied blocks per requestor 415system.cpu0.dcache.occ_percent::cpu0.data 0.282011 # Average percentage of cache occupancy 416system.cpu0.dcache.occ_percent::total 0.282011 # Average percentage of cache occupancy 417system.cpu0.dcache.ReadReq_hits::cpu0.data 83924 # number of ReadReq hits 418system.cpu0.dcache.ReadReq_hits::total 83924 # number of ReadReq hits 419system.cpu0.dcache.WriteReq_hits::cpu0.data 81641 # number of WriteReq hits 420system.cpu0.dcache.WriteReq_hits::total 81641 # number of WriteReq hits 421system.cpu0.dcache.SwapReq_hits::cpu0.data 17 # number of SwapReq hits 422system.cpu0.dcache.SwapReq_hits::total 17 # number of SwapReq hits 423system.cpu0.dcache.demand_hits::cpu0.data 165565 # number of demand (read+write) hits 424system.cpu0.dcache.demand_hits::total 165565 # number of demand (read+write) hits 425system.cpu0.dcache.overall_hits::cpu0.data 165565 # number of overall hits 426system.cpu0.dcache.overall_hits::total 165565 # number of overall hits 427system.cpu0.dcache.ReadReq_misses::cpu0.data 532 # number of ReadReq misses 428system.cpu0.dcache.ReadReq_misses::total 532 # number of ReadReq misses 429system.cpu0.dcache.WriteReq_misses::cpu0.data 563 # number of WriteReq misses 430system.cpu0.dcache.WriteReq_misses::total 563 # number of WriteReq misses 431system.cpu0.dcache.SwapReq_misses::cpu0.data 25 # number of SwapReq misses 432system.cpu0.dcache.SwapReq_misses::total 25 # number of SwapReq misses 433system.cpu0.dcache.demand_misses::cpu0.data 1095 # number of demand (read+write) misses 434system.cpu0.dcache.demand_misses::total 1095 # number of demand (read+write) misses 435system.cpu0.dcache.overall_misses::cpu0.data 1095 # number of overall misses 436system.cpu0.dcache.overall_misses::total 1095 # number of overall misses 437system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16935000 # number of ReadReq miss cycles 438system.cpu0.dcache.ReadReq_miss_latency::total 16935000 # number of ReadReq miss cycles 439system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 28694494 # number of WriteReq miss cycles 440system.cpu0.dcache.WriteReq_miss_latency::total 28694494 # number of WriteReq miss cycles 441system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 516500 # number of SwapReq miss cycles 442system.cpu0.dcache.SwapReq_miss_latency::total 516500 # number of SwapReq miss cycles 443system.cpu0.dcache.demand_miss_latency::cpu0.data 45629494 # number of demand (read+write) miss cycles 444system.cpu0.dcache.demand_miss_latency::total 45629494 # number of demand (read+write) miss cycles 445system.cpu0.dcache.overall_miss_latency::cpu0.data 45629494 # number of overall miss cycles 446system.cpu0.dcache.overall_miss_latency::total 45629494 # number of overall miss cycles 447system.cpu0.dcache.ReadReq_accesses::cpu0.data 84456 # number of ReadReq accesses(hits+misses) 448system.cpu0.dcache.ReadReq_accesses::total 84456 # number of ReadReq accesses(hits+misses) 449system.cpu0.dcache.WriteReq_accesses::cpu0.data 82204 # number of WriteReq accesses(hits+misses) 450system.cpu0.dcache.WriteReq_accesses::total 82204 # number of WriteReq accesses(hits+misses) 451system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 452system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 453system.cpu0.dcache.demand_accesses::cpu0.data 166660 # number of demand (read+write) accesses 454system.cpu0.dcache.demand_accesses::total 166660 # number of demand (read+write) accesses 455system.cpu0.dcache.overall_accesses::cpu0.data 166660 # number of overall (read+write) accesses 456system.cpu0.dcache.overall_accesses::total 166660 # number of overall (read+write) accesses 457system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006299 # miss rate for ReadReq accesses 458system.cpu0.dcache.ReadReq_miss_rate::total 0.006299 # miss rate for ReadReq accesses 459system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006849 # miss rate for WriteReq accesses 460system.cpu0.dcache.WriteReq_miss_rate::total 0.006849 # miss rate for WriteReq accesses 461system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.595238 # miss rate for SwapReq accesses 462system.cpu0.dcache.SwapReq_miss_rate::total 0.595238 # miss rate for SwapReq accesses 463system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006570 # miss rate for demand accesses 464system.cpu0.dcache.demand_miss_rate::total 0.006570 # miss rate for demand accesses 465system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006570 # miss rate for overall accesses 466system.cpu0.dcache.overall_miss_rate::total 0.006570 # miss rate for overall accesses 467system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31832.706767 # average ReadReq miss latency 468system.cpu0.dcache.ReadReq_avg_miss_latency::total 31832.706767 # average ReadReq miss latency 469system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50967.129663 # average WriteReq miss latency 470system.cpu0.dcache.WriteReq_avg_miss_latency::total 50967.129663 # average WriteReq miss latency 471system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20660 # average SwapReq miss latency 472system.cpu0.dcache.SwapReq_avg_miss_latency::total 20660 # average SwapReq miss latency 473system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41670.770776 # average overall miss latency 474system.cpu0.dcache.demand_avg_miss_latency::total 41670.770776 # average overall miss latency 475system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41670.770776 # average overall miss latency 476system.cpu0.dcache.overall_avg_miss_latency::total 41670.770776 # average overall miss latency 477system.cpu0.dcache.blocked_cycles::no_mshrs 112000 # number of cycles access was blocked 478system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 479system.cpu0.dcache.blocked::no_mshrs 18 # number of cycles access was blocked 480system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 481system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6222.222222 # average number of cycles each access was blocked 482system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 483system.cpu0.dcache.fast_writes 0 # number of fast writes performed 484system.cpu0.dcache.cache_copies 0 # number of cache copies performed 485system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 486system.cpu0.dcache.writebacks::total 1 # number of writebacks 487system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 351 # number of ReadReq MSHR hits 488system.cpu0.dcache.ReadReq_mshr_hits::total 351 # number of ReadReq MSHR hits 489system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 394 # number of WriteReq MSHR hits 490system.cpu0.dcache.WriteReq_mshr_hits::total 394 # number of WriteReq MSHR hits 491system.cpu0.dcache.demand_mshr_hits::cpu0.data 745 # number of demand (read+write) MSHR hits 492system.cpu0.dcache.demand_mshr_hits::total 745 # number of demand (read+write) MSHR hits 493system.cpu0.dcache.overall_mshr_hits::cpu0.data 745 # number of overall MSHR hits 494system.cpu0.dcache.overall_mshr_hits::total 745 # number of overall MSHR hits 495system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 181 # number of ReadReq MSHR misses 496system.cpu0.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses 497system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 169 # number of WriteReq MSHR misses 498system.cpu0.dcache.WriteReq_mshr_misses::total 169 # number of WriteReq MSHR misses 499system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 25 # number of SwapReq MSHR misses 500system.cpu0.dcache.SwapReq_mshr_misses::total 25 # number of SwapReq MSHR misses 501system.cpu0.dcache.demand_mshr_misses::cpu0.data 350 # number of demand (read+write) MSHR misses 502system.cpu0.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 503system.cpu0.dcache.overall_mshr_misses::cpu0.data 350 # number of overall MSHR misses 504system.cpu0.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses 505system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5844010 # number of ReadReq MSHR miss cycles 506system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5844010 # number of ReadReq MSHR miss cycles 507system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6652500 # number of WriteReq MSHR miss cycles 508system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6652500 # number of WriteReq MSHR miss cycles 509system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 438500 # number of SwapReq MSHR miss cycles 510system.cpu0.dcache.SwapReq_mshr_miss_latency::total 438500 # number of SwapReq MSHR miss cycles 511system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12496510 # number of demand (read+write) MSHR miss cycles 512system.cpu0.dcache.demand_mshr_miss_latency::total 12496510 # number of demand (read+write) MSHR miss cycles 513system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12496510 # number of overall MSHR miss cycles 514system.cpu0.dcache.overall_mshr_miss_latency::total 12496510 # number of overall MSHR miss cycles 515system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002143 # mshr miss rate for ReadReq accesses 516system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002143 # mshr miss rate for ReadReq accesses 517system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002056 # mshr miss rate for WriteReq accesses 518system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002056 # mshr miss rate for WriteReq accesses 519system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.595238 # mshr miss rate for SwapReq accesses 520system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.595238 # mshr miss rate for SwapReq accesses 521system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002100 # mshr miss rate for demand accesses 522system.cpu0.dcache.demand_mshr_miss_rate::total 0.002100 # mshr miss rate for demand accesses 523system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002100 # mshr miss rate for overall accesses 524system.cpu0.dcache.overall_mshr_miss_rate::total 0.002100 # mshr miss rate for overall accesses 525system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32287.348066 # average ReadReq mshr miss latency 526system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32287.348066 # average ReadReq mshr miss latency 527system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39363.905325 # average WriteReq mshr miss latency 528system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39363.905325 # average WriteReq mshr miss latency 529system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17540 # average SwapReq mshr miss latency 530system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17540 # average SwapReq mshr miss latency 531system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35704.314286 # average overall mshr miss latency 532system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35704.314286 # average overall mshr miss latency 533system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35704.314286 # average overall mshr miss latency 534system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35704.314286 # average overall mshr miss latency 535system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 536system.cpu1.numCycles 191317 # number of cpu cycles simulated 537system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 538system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 539system.cpu1.BPredUnit.lookups 53059 # Number of BP lookups 540system.cpu1.BPredUnit.condPredicted 50011 # Number of conditional branches predicted 541system.cpu1.BPredUnit.condIncorrect 1521 # Number of conditional branches incorrect 542system.cpu1.BPredUnit.BTBLookups 46382 # Number of BTB lookups 543system.cpu1.BPredUnit.BTBHits 45427 # Number of BTB hits 544system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 545system.cpu1.BPredUnit.usedRAS 803 # Number of times the RAS was used to get a target. 546system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. 547system.cpu1.fetch.icacheStallCycles 31318 # Number of cycles fetch is stalled on an Icache miss 548system.cpu1.fetch.Insts 294530 # Number of instructions fetch has processed 549system.cpu1.fetch.Branches 53059 # Number of branches that fetch encountered 550system.cpu1.fetch.predictedBranches 46230 # Number of branches that fetch has predicted taken 551system.cpu1.fetch.Cycles 104588 # Number of cycles fetch has run and was not squashing or blocked 552system.cpu1.fetch.SquashCycles 4407 # Number of cycles fetch has spent squashing 553system.cpu1.fetch.BlockedCycles 38684 # Number of cycles fetch has spent blocked 554system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 555system.cpu1.fetch.NoActiveThreadStallCycles 6733 # Number of stall cycles due to no active thread to fetch from 556system.cpu1.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps 557system.cpu1.fetch.CacheLines 21833 # Number of cache lines fetched 558system.cpu1.fetch.IcacheSquashes 319 # Number of outstanding Icache misses that were squashed 559system.cpu1.fetch.rateDist::samples 185209 # Number of instructions fetched each cycle (Total) 560system.cpu1.fetch.rateDist::mean 1.590257 # Number of instructions fetched each cycle (Total) 561system.cpu1.fetch.rateDist::stdev 2.119058 # Number of instructions fetched each cycle (Total) 562system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 563system.cpu1.fetch.rateDist::0 80621 43.53% 43.53% # Number of instructions fetched each cycle (Total) 564system.cpu1.fetch.rateDist::1 53529 28.90% 72.43% # Number of instructions fetched each cycle (Total) 565system.cpu1.fetch.rateDist::2 6903 3.73% 76.16% # Number of instructions fetched each cycle (Total) 566system.cpu1.fetch.rateDist::3 3276 1.77% 77.93% # Number of instructions fetched each cycle (Total) 567system.cpu1.fetch.rateDist::4 732 0.40% 78.32% # Number of instructions fetched each cycle (Total) 568system.cpu1.fetch.rateDist::5 34514 18.64% 96.96% # Number of instructions fetched each cycle (Total) 569system.cpu1.fetch.rateDist::6 1160 0.63% 97.58% # Number of instructions fetched each cycle (Total) 570system.cpu1.fetch.rateDist::7 883 0.48% 98.06% # Number of instructions fetched each cycle (Total) 571system.cpu1.fetch.rateDist::8 3591 1.94% 100.00% # Number of instructions fetched each cycle (Total) 572system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 573system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 574system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 575system.cpu1.fetch.rateDist::total 185209 # Number of instructions fetched each cycle (Total) 576system.cpu1.fetch.branchRate 0.277336 # Number of branch fetches per cycle 577system.cpu1.fetch.rate 1.539487 # Number of inst fetches per cycle 578system.cpu1.decode.IdleCycles 37437 # Number of cycles decode is idle 579system.cpu1.decode.BlockedCycles 34588 # Number of cycles decode is blocked 580system.cpu1.decode.RunCycles 97784 # Number of cycles decode is running 581system.cpu1.decode.UnblockCycles 5856 # Number of cycles decode is unblocking 582system.cpu1.decode.SquashCycles 2811 # Number of cycles decode is squashing 583system.cpu1.decode.DecodedInsts 290465 # Number of instructions handled by decode 584system.cpu1.rename.SquashCycles 2811 # Number of cycles rename is squashing 585system.cpu1.rename.IdleCycles 38251 # Number of cycles rename is idle 586system.cpu1.rename.BlockCycles 18737 # Number of cycles rename is blocking 587system.cpu1.rename.serializeStallCycles 14962 # count of cycles rename stalled for serializing inst 588system.cpu1.rename.RunCycles 92242 # Number of cycles rename is running 589system.cpu1.rename.UnblockCycles 11473 # Number of cycles rename is unblocking 590system.cpu1.rename.RenamedInsts 288015 # Number of instructions processed by rename 591system.cpu1.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full 592system.cpu1.rename.LSQFullEvents 60 # Number of times rename has blocked due to LSQ full 593system.cpu1.rename.RenamedOperands 201252 # Number of destination operands rename has renamed 594system.cpu1.rename.RenameLookups 549512 # Number of register rename lookups that rename has made 595system.cpu1.rename.int_rename_lookups 549512 # Number of integer rename lookups 596system.cpu1.rename.CommittedMaps 185544 # Number of HB maps that are committed 597system.cpu1.rename.UndoneMaps 15708 # Number of HB maps that are undone due to squashing 598system.cpu1.rename.serializingInsts 1231 # count of serializing insts renamed 599system.cpu1.rename.tempSerializingInsts 1359 # count of temporary serializing insts renamed 600system.cpu1.rename.skidInsts 14237 # count of insts added to the skid buffer 601system.cpu1.memDep0.insertedLoads 80834 # Number of loads inserted to the mem dependence unit. 602system.cpu1.memDep0.insertedStores 37999 # Number of stores inserted to the mem dependence unit. 603system.cpu1.memDep0.conflictingLoads 38862 # Number of conflicting loads. 604system.cpu1.memDep0.conflictingStores 32764 # Number of conflicting stores. 605system.cpu1.iq.iqInstsAdded 237666 # Number of instructions added to the IQ (excludes non-spec) 606system.cpu1.iq.iqNonSpecInstsAdded 7151 # Number of non-speculative instructions added to the IQ 607system.cpu1.iq.iqInstsIssued 239902 # Number of instructions issued 608system.cpu1.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued 609system.cpu1.iq.iqSquashedInstsExamined 12973 # Number of squashed instructions iterated over during squash; mainly for profiling 610system.cpu1.iq.iqSquashedOperandsExamined 11962 # Number of squashed operands that are examined and possibly removed from graph 611system.cpu1.iq.iqSquashedNonSpecRemoved 719 # Number of squashed non-spec instructions that were removed 612system.cpu1.iq.issued_per_cycle::samples 185209 # Number of insts issued each cycle 613system.cpu1.iq.issued_per_cycle::mean 1.295304 # Number of insts issued each cycle 614system.cpu1.iq.issued_per_cycle::stdev 1.311031 # Number of insts issued each cycle 615system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 616system.cpu1.iq.issued_per_cycle::0 78322 42.29% 42.29% # Number of insts issued each cycle 617system.cpu1.iq.issued_per_cycle::1 24974 13.48% 55.77% # Number of insts issued each cycle 618system.cpu1.iq.issued_per_cycle::2 38132 20.59% 76.36% # Number of insts issued each cycle 619system.cpu1.iq.issued_per_cycle::3 38761 20.93% 97.29% # Number of insts issued each cycle 620system.cpu1.iq.issued_per_cycle::4 3339 1.80% 99.09% # Number of insts issued each cycle 621system.cpu1.iq.issued_per_cycle::5 1231 0.66% 99.76% # Number of insts issued each cycle 622system.cpu1.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle 623system.cpu1.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle 624system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle 625system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 626system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 627system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 628system.cpu1.iq.issued_per_cycle::total 185209 # Number of insts issued each cycle 629system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 630system.cpu1.iq.fu_full::IntAlu 21 6.44% 6.44% # attempts to use FU when none available 631system.cpu1.iq.fu_full::IntMult 0 0.00% 6.44% # attempts to use FU when none available 632system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.44% # attempts to use FU when none available 633system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.44% # attempts to use FU when none available 634system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.44% # attempts to use FU when none available 635system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.44% # attempts to use FU when none available 636system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.44% # attempts to use FU when none available 637system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.44% # attempts to use FU when none available 638system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.44% # attempts to use FU when none available 639system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.44% # attempts to use FU when none available 640system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.44% # attempts to use FU when none available 641system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.44% # attempts to use FU when none available 642system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.44% # attempts to use FU when none available 643system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.44% # attempts to use FU when none available 644system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.44% # attempts to use FU when none available 645system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.44% # attempts to use FU when none available 646system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.44% # attempts to use FU when none available 647system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.44% # attempts to use FU when none available 648system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.44% # attempts to use FU when none available 649system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.44% # attempts to use FU when none available 650system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.44% # attempts to use FU when none available 651system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.44% # attempts to use FU when none available 652system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.44% # attempts to use FU when none available 653system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.44% # attempts to use FU when none available 654system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.44% # attempts to use FU when none available 655system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.44% # attempts to use FU when none available 656system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.44% # attempts to use FU when none available 657system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.44% # attempts to use FU when none available 658system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.44% # attempts to use FU when none available 659system.cpu1.iq.fu_full::MemRead 95 29.14% 35.58% # attempts to use FU when none available 660system.cpu1.iq.fu_full::MemWrite 210 64.42% 100.00% # attempts to use FU when none available 661system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 662system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 663system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 664system.cpu1.iq.FU_type_0::IntAlu 116849 48.71% 48.71% # Type of FU issued 665system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.71% # Type of FU issued 666system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.71% # Type of FU issued 667system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.71% # Type of FU issued 668system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.71% # Type of FU issued 669system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.71% # Type of FU issued 670system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.71% # Type of FU issued 671system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.71% # Type of FU issued 672system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.71% # Type of FU issued 673system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.71% # Type of FU issued 674system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.71% # Type of FU issued 675system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.71% # Type of FU issued 676system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.71% # Type of FU issued 677system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.71% # Type of FU issued 678system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.71% # Type of FU issued 679system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.71% # Type of FU issued 680system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.71% # Type of FU issued 681system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.71% # Type of FU issued 682system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.71% # Type of FU issued 683system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.71% # Type of FU issued 684system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.71% # Type of FU issued 685system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued 686system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.71% # Type of FU issued 687system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.71% # Type of FU issued 688system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.71% # Type of FU issued 689system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.71% # Type of FU issued 690system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued 691system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued 692system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued 693system.cpu1.iq.FU_type_0::MemRead 85748 35.74% 84.45% # Type of FU issued 694system.cpu1.iq.FU_type_0::MemWrite 37305 15.55% 100.00% # Type of FU issued 695system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 696system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 697system.cpu1.iq.FU_type_0::total 239902 # Type of FU issued 698system.cpu1.iq.rate 1.253950 # Inst issue rate 699system.cpu1.iq.fu_busy_cnt 326 # FU busy when requested 700system.cpu1.iq.fu_busy_rate 0.001359 # FU busy rate (busy events/executed inst) 701system.cpu1.iq.int_inst_queue_reads 665467 # Number of integer instruction queue reads 702system.cpu1.iq.int_inst_queue_writes 257831 # Number of integer instruction queue writes 703system.cpu1.iq.int_inst_queue_wakeup_accesses 237819 # Number of integer instruction queue wakeup accesses 704system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 705system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 706system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 707system.cpu1.iq.int_alu_accesses 240228 # Number of integer alu accesses 708system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 709system.cpu1.iew.lsq.thread0.forwLoads 32613 # Number of loads that had data forwarded from stores 710system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 711system.cpu1.iew.lsq.thread0.squashedLoads 2758 # Number of loads squashed 712system.cpu1.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed 713system.cpu1.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations 714system.cpu1.iew.lsq.thread0.squashedStores 1567 # Number of stores squashed 715system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 716system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 717system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 718system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 719system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 720system.cpu1.iew.iewSquashCycles 2811 # Number of cycles IEW is squashing 721system.cpu1.iew.iewBlockCycles 2340 # Number of cycles IEW is blocking 722system.cpu1.iew.iewUnblockCycles 107 # Number of cycles IEW is unblocking 723system.cpu1.iew.iewDispatchedInsts 284663 # Number of instructions dispatched to IQ 724system.cpu1.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch 725system.cpu1.iew.iewDispLoadInsts 80834 # Number of dispatched load instructions 726system.cpu1.iew.iewDispStoreInsts 37999 # Number of dispatched store instructions 727system.cpu1.iew.iewDispNonSpecInsts 1126 # Number of dispatched non-speculative instructions 728system.cpu1.iew.iewIQFullEvents 105 # Number of times the IQ has become full, causing a stall 729system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 730system.cpu1.iew.memOrderViolationEvents 41 # Number of memory order violations 731system.cpu1.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly 732system.cpu1.iew.predictedNotTakenIncorrect 1185 # Number of branches that were predicted not taken incorrectly 733system.cpu1.iew.branchMispredicts 1694 # Number of branch mispredicts detected at execute 734system.cpu1.iew.iewExecutedInsts 238552 # Number of executed instructions 735system.cpu1.iew.iewExecLoadInsts 79712 # Number of load instructions executed 736system.cpu1.iew.iewExecSquashedInsts 1350 # Number of squashed instructions skipped in execute 737system.cpu1.iew.exec_swp 0 # number of swp insts executed 738system.cpu1.iew.exec_nop 39846 # number of nop insts executed 739system.cpu1.iew.exec_refs 116931 # number of memory reference insts executed 740system.cpu1.iew.exec_branches 49232 # Number of branches executed 741system.cpu1.iew.exec_stores 37219 # Number of stores executed 742system.cpu1.iew.exec_rate 1.246894 # Inst execution rate 743system.cpu1.iew.wb_sent 238105 # cumulative count of insts sent to commit 744system.cpu1.iew.wb_count 237819 # cumulative count of insts written-back 745system.cpu1.iew.wb_producers 133762 # num instructions producing a value 746system.cpu1.iew.wb_consumers 138617 # num instructions consuming a value 747system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 748system.cpu1.iew.wb_rate 1.243063 # insts written-back per cycle 749system.cpu1.iew.wb_fanout 0.964975 # average fanout of values written-back 750system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 751system.cpu1.commit.commitCommittedInsts 269706 # The number of committed instructions 752system.cpu1.commit.commitCommittedOps 269706 # The number of committed instructions 753system.cpu1.commit.commitSquashedInsts 14936 # The number of squashed insts skipped by commit 754system.cpu1.commit.commitNonSpecStalls 6432 # The number of times commit has been forced to stall to communicate backwards 755system.cpu1.commit.branchMispredicts 1521 # The number of times a branch was mispredicted 756system.cpu1.commit.committed_per_cycle::samples 175666 # Number of insts commited each cycle 757system.cpu1.commit.committed_per_cycle::mean 1.535334 # Number of insts commited each cycle 758system.cpu1.commit.committed_per_cycle::stdev 1.989786 # Number of insts commited each cycle 759system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 760system.cpu1.commit.committed_per_cycle::0 78046 44.43% 44.43% # Number of insts commited each cycle 761system.cpu1.commit.committed_per_cycle::1 47129 26.83% 71.26% # Number of insts commited each cycle 762system.cpu1.commit.committed_per_cycle::2 6230 3.55% 74.80% # Number of insts commited each cycle 763system.cpu1.commit.committed_per_cycle::3 7351 4.18% 78.99% # Number of insts commited each cycle 764system.cpu1.commit.committed_per_cycle::4 1552 0.88% 79.87% # Number of insts commited each cycle 765system.cpu1.commit.committed_per_cycle::5 32915 18.74% 98.61% # Number of insts commited each cycle 766system.cpu1.commit.committed_per_cycle::6 634 0.36% 98.97% # Number of insts commited each cycle 767system.cpu1.commit.committed_per_cycle::7 995 0.57% 99.54% # Number of insts commited each cycle 768system.cpu1.commit.committed_per_cycle::8 814 0.46% 100.00% # Number of insts commited each cycle 769system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 770system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 771system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 772system.cpu1.commit.committed_per_cycle::total 175666 # Number of insts commited each cycle 773system.cpu1.commit.committedInsts 269706 # Number of instructions committed 774system.cpu1.commit.committedOps 269706 # Number of ops (including micro ops) committed 775system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 776system.cpu1.commit.refs 114508 # Number of memory references committed 777system.cpu1.commit.loads 78076 # Number of loads committed 778system.cpu1.commit.membars 5720 # Number of memory barriers committed 779system.cpu1.commit.branches 48115 # Number of branches committed 780system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. 781system.cpu1.commit.int_insts 184747 # Number of committed integer instructions. 782system.cpu1.commit.function_calls 322 # Number of function calls committed. 783system.cpu1.commit.bw_lim_events 814 # number cycles where commit BW limit reached 784system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 785system.cpu1.rob.rob_reads 458907 # The number of ROB reads 786system.cpu1.rob.rob_writes 572109 # The number of ROB writes 787system.cpu1.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself 788system.cpu1.idleCycles 6108 # Total number of cycles that the CPU has spent unscheduled due to idling 789system.cpu1.quiesceCycles 36503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 790system.cpu1.committedInsts 225079 # Number of Instructions Simulated 791system.cpu1.committedOps 225079 # Number of Ops (including micro ops) Simulated 792system.cpu1.committedInsts_total 225079 # Number of Instructions Simulated 793system.cpu1.cpi 0.849999 # CPI: Cycles Per Instruction 794system.cpu1.cpi_total 0.849999 # CPI: Total CPI of All Threads 795system.cpu1.ipc 1.176472 # IPC: Instructions Per Cycle 796system.cpu1.ipc_total 1.176472 # IPC: Total IPC of All Threads 797system.cpu1.int_regfile_reads 410678 # number of integer regfile reads 798system.cpu1.int_regfile_writes 191757 # number of integer regfile writes 799system.cpu1.fp_regfile_writes 64 # number of floating regfile writes 800system.cpu1.misc_regfile_reads 118640 # number of misc regfile reads 801system.cpu1.misc_regfile_writes 646 # number of misc regfile writes 802system.cpu1.icache.replacements 322 # number of replacements 803system.cpu1.icache.tagsinuse 90.918932 # Cycle average of tags in use 804system.cpu1.icache.total_refs 21316 # Total number of references to valid blocks. 805system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks. 806system.cpu1.icache.avg_refs 48.889908 # Average number of references to valid blocks. 807system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 808system.cpu1.icache.occ_blocks::cpu1.inst 90.918932 # Average occupied blocks per requestor 809system.cpu1.icache.occ_percent::cpu1.inst 0.177576 # Average percentage of cache occupancy 810system.cpu1.icache.occ_percent::total 0.177576 # Average percentage of cache occupancy 811system.cpu1.icache.ReadReq_hits::cpu1.inst 21316 # number of ReadReq hits 812system.cpu1.icache.ReadReq_hits::total 21316 # number of ReadReq hits 813system.cpu1.icache.demand_hits::cpu1.inst 21316 # number of demand (read+write) hits 814system.cpu1.icache.demand_hits::total 21316 # number of demand (read+write) hits 815system.cpu1.icache.overall_hits::cpu1.inst 21316 # number of overall hits 816system.cpu1.icache.overall_hits::total 21316 # number of overall hits 817system.cpu1.icache.ReadReq_misses::cpu1.inst 517 # number of ReadReq misses 818system.cpu1.icache.ReadReq_misses::total 517 # number of ReadReq misses 819system.cpu1.icache.demand_misses::cpu1.inst 517 # number of demand (read+write) misses 820system.cpu1.icache.demand_misses::total 517 # number of demand (read+write) misses 821system.cpu1.icache.overall_misses::cpu1.inst 517 # number of overall misses 822system.cpu1.icache.overall_misses::total 517 # number of overall misses 823system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11871000 # number of ReadReq miss cycles 824system.cpu1.icache.ReadReq_miss_latency::total 11871000 # number of ReadReq miss cycles 825system.cpu1.icache.demand_miss_latency::cpu1.inst 11871000 # number of demand (read+write) miss cycles 826system.cpu1.icache.demand_miss_latency::total 11871000 # number of demand (read+write) miss cycles 827system.cpu1.icache.overall_miss_latency::cpu1.inst 11871000 # number of overall miss cycles 828system.cpu1.icache.overall_miss_latency::total 11871000 # number of overall miss cycles 829system.cpu1.icache.ReadReq_accesses::cpu1.inst 21833 # number of ReadReq accesses(hits+misses) 830system.cpu1.icache.ReadReq_accesses::total 21833 # number of ReadReq accesses(hits+misses) 831system.cpu1.icache.demand_accesses::cpu1.inst 21833 # number of demand (read+write) accesses 832system.cpu1.icache.demand_accesses::total 21833 # number of demand (read+write) accesses 833system.cpu1.icache.overall_accesses::cpu1.inst 21833 # number of overall (read+write) accesses 834system.cpu1.icache.overall_accesses::total 21833 # number of overall (read+write) accesses 835system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023680 # miss rate for ReadReq accesses 836system.cpu1.icache.ReadReq_miss_rate::total 0.023680 # miss rate for ReadReq accesses 837system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023680 # miss rate for demand accesses 838system.cpu1.icache.demand_miss_rate::total 0.023680 # miss rate for demand accesses 839system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023680 # miss rate for overall accesses 840system.cpu1.icache.overall_miss_rate::total 0.023680 # miss rate for overall accesses 841system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22961.315280 # average ReadReq miss latency 842system.cpu1.icache.ReadReq_avg_miss_latency::total 22961.315280 # average ReadReq miss latency 843system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22961.315280 # average overall miss latency 844system.cpu1.icache.demand_avg_miss_latency::total 22961.315280 # average overall miss latency 845system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22961.315280 # average overall miss latency 846system.cpu1.icache.overall_avg_miss_latency::total 22961.315280 # average overall miss latency 847system.cpu1.icache.blocked_cycles::no_mshrs 32000 # number of cycles access was blocked 848system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 849system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked 850system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 851system.cpu1.icache.avg_blocked_cycles::no_mshrs 32000 # average number of cycles each access was blocked 852system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 853system.cpu1.icache.fast_writes 0 # number of fast writes performed 854system.cpu1.icache.cache_copies 0 # number of cache copies performed 855system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits 856system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits 857system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits 858system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits 859system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits 860system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits 861system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 436 # number of ReadReq MSHR misses 862system.cpu1.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses 863system.cpu1.icache.demand_mshr_misses::cpu1.inst 436 # number of demand (read+write) MSHR misses 864system.cpu1.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses 865system.cpu1.icache.overall_mshr_misses::cpu1.inst 436 # number of overall MSHR misses 866system.cpu1.icache.overall_mshr_misses::total 436 # number of overall MSHR misses 867system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8857500 # number of ReadReq MSHR miss cycles 868system.cpu1.icache.ReadReq_mshr_miss_latency::total 8857500 # number of ReadReq MSHR miss cycles 869system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8857500 # number of demand (read+write) MSHR miss cycles 870system.cpu1.icache.demand_mshr_miss_latency::total 8857500 # number of demand (read+write) MSHR miss cycles 871system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8857500 # number of overall MSHR miss cycles 872system.cpu1.icache.overall_mshr_miss_latency::total 8857500 # number of overall MSHR miss cycles 873system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for ReadReq accesses 874system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019970 # mshr miss rate for ReadReq accesses 875system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for demand accesses 876system.cpu1.icache.demand_mshr_miss_rate::total 0.019970 # mshr miss rate for demand accesses 877system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for overall accesses 878system.cpu1.icache.overall_mshr_miss_rate::total 0.019970 # mshr miss rate for overall accesses 879system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average ReadReq mshr miss latency 880system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 20315.366972 # average ReadReq mshr miss latency 881system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average overall mshr miss latency 882system.cpu1.icache.demand_avg_mshr_miss_latency::total 20315.366972 # average overall mshr miss latency 883system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average overall mshr miss latency 884system.cpu1.icache.overall_avg_mshr_miss_latency::total 20315.366972 # average overall mshr miss latency 885system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 886system.cpu1.dcache.replacements 0 # number of replacements 887system.cpu1.dcache.tagsinuse 27.526466 # Cycle average of tags in use 888system.cpu1.dcache.total_refs 42609 # Total number of references to valid blocks. 889system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. 890system.cpu1.dcache.avg_refs 1521.750000 # Average number of references to valid blocks. 891system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 892system.cpu1.dcache.occ_blocks::cpu1.data 27.526466 # Average occupied blocks per requestor 893system.cpu1.dcache.occ_percent::cpu1.data 0.053763 # Average percentage of cache occupancy 894system.cpu1.dcache.occ_percent::total 0.053763 # Average percentage of cache occupancy 895system.cpu1.dcache.ReadReq_hits::cpu1.data 46637 # number of ReadReq hits 896system.cpu1.dcache.ReadReq_hits::total 46637 # number of ReadReq hits 897system.cpu1.dcache.WriteReq_hits::cpu1.data 36226 # number of WriteReq hits 898system.cpu1.dcache.WriteReq_hits::total 36226 # number of WriteReq hits 899system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 900system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits 901system.cpu1.dcache.demand_hits::cpu1.data 82863 # number of demand (read+write) hits 902system.cpu1.dcache.demand_hits::total 82863 # number of demand (read+write) hits 903system.cpu1.dcache.overall_hits::cpu1.data 82863 # number of overall hits 904system.cpu1.dcache.overall_hits::total 82863 # number of overall hits 905system.cpu1.dcache.ReadReq_misses::cpu1.data 446 # number of ReadReq misses 906system.cpu1.dcache.ReadReq_misses::total 446 # number of ReadReq misses 907system.cpu1.dcache.WriteReq_misses::cpu1.data 140 # number of WriteReq misses 908system.cpu1.dcache.WriteReq_misses::total 140 # number of WriteReq misses 909system.cpu1.dcache.SwapReq_misses::cpu1.data 52 # number of SwapReq misses 910system.cpu1.dcache.SwapReq_misses::total 52 # number of SwapReq misses 911system.cpu1.dcache.demand_misses::cpu1.data 586 # number of demand (read+write) misses 912system.cpu1.dcache.demand_misses::total 586 # number of demand (read+write) misses 913system.cpu1.dcache.overall_misses::cpu1.data 586 # number of overall misses 914system.cpu1.dcache.overall_misses::total 586 # number of overall misses 915system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 12735500 # number of ReadReq miss cycles 916system.cpu1.dcache.ReadReq_miss_latency::total 12735500 # number of ReadReq miss cycles 917system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3574500 # number of WriteReq miss cycles 918system.cpu1.dcache.WriteReq_miss_latency::total 3574500 # number of WriteReq miss cycles 919system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1329500 # number of SwapReq miss cycles 920system.cpu1.dcache.SwapReq_miss_latency::total 1329500 # number of SwapReq miss cycles 921system.cpu1.dcache.demand_miss_latency::cpu1.data 16310000 # number of demand (read+write) miss cycles 922system.cpu1.dcache.demand_miss_latency::total 16310000 # number of demand (read+write) miss cycles 923system.cpu1.dcache.overall_miss_latency::cpu1.data 16310000 # number of overall miss cycles 924system.cpu1.dcache.overall_miss_latency::total 16310000 # number of overall miss cycles 925system.cpu1.dcache.ReadReq_accesses::cpu1.data 47083 # number of ReadReq accesses(hits+misses) 926system.cpu1.dcache.ReadReq_accesses::total 47083 # number of ReadReq accesses(hits+misses) 927system.cpu1.dcache.WriteReq_accesses::cpu1.data 36366 # number of WriteReq accesses(hits+misses) 928system.cpu1.dcache.WriteReq_accesses::total 36366 # number of WriteReq accesses(hits+misses) 929system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses) 930system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 931system.cpu1.dcache.demand_accesses::cpu1.data 83449 # number of demand (read+write) accesses 932system.cpu1.dcache.demand_accesses::total 83449 # number of demand (read+write) accesses 933system.cpu1.dcache.overall_accesses::cpu1.data 83449 # number of overall (read+write) accesses 934system.cpu1.dcache.overall_accesses::total 83449 # number of overall (read+write) accesses 935system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009473 # miss rate for ReadReq accesses 936system.cpu1.dcache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses 937system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003850 # miss rate for WriteReq accesses 938system.cpu1.dcache.WriteReq_miss_rate::total 0.003850 # miss rate for WriteReq accesses 939system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.787879 # miss rate for SwapReq accesses 940system.cpu1.dcache.SwapReq_miss_rate::total 0.787879 # miss rate for SwapReq accesses 941system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007022 # miss rate for demand accesses 942system.cpu1.dcache.demand_miss_rate::total 0.007022 # miss rate for demand accesses 943system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007022 # miss rate for overall accesses 944system.cpu1.dcache.overall_miss_rate::total 0.007022 # miss rate for overall accesses 945system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 28554.932735 # average ReadReq miss latency 946system.cpu1.dcache.ReadReq_avg_miss_latency::total 28554.932735 # average ReadReq miss latency 947system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25532.142857 # average WriteReq miss latency 948system.cpu1.dcache.WriteReq_avg_miss_latency::total 25532.142857 # average WriteReq miss latency 949system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 25567.307692 # average SwapReq miss latency 950system.cpu1.dcache.SwapReq_avg_miss_latency::total 25567.307692 # average SwapReq miss latency 951system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27832.764505 # average overall miss latency 952system.cpu1.dcache.demand_avg_miss_latency::total 27832.764505 # average overall miss latency 953system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27832.764505 # average overall miss latency 954system.cpu1.dcache.overall_avg_miss_latency::total 27832.764505 # average overall miss latency 955system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 956system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 957system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 958system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 959system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 960system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 961system.cpu1.dcache.fast_writes 0 # number of fast writes performed 962system.cpu1.dcache.cache_copies 0 # number of cache copies performed 963system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 286 # number of ReadReq MSHR hits 964system.cpu1.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits 965system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits 966system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits 967system.cpu1.dcache.demand_mshr_hits::cpu1.data 320 # number of demand (read+write) MSHR hits 968system.cpu1.dcache.demand_mshr_hits::total 320 # number of demand (read+write) MSHR hits 969system.cpu1.dcache.overall_mshr_hits::cpu1.data 320 # number of overall MSHR hits 970system.cpu1.dcache.overall_mshr_hits::total 320 # number of overall MSHR hits 971system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses 972system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses 973system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses 974system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 975system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses 976system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses 977system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses 978system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses 979system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses 980system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses 981system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3164503 # number of ReadReq MSHR miss cycles 982system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3164503 # number of ReadReq MSHR miss cycles 983system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1890000 # number of WriteReq MSHR miss cycles 984system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1890000 # number of WriteReq MSHR miss cycles 985system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1168500 # number of SwapReq MSHR miss cycles 986system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1168500 # number of SwapReq MSHR miss cycles 987system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5054503 # number of demand (read+write) MSHR miss cycles 988system.cpu1.dcache.demand_mshr_miss_latency::total 5054503 # number of demand (read+write) MSHR miss cycles 989system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5054503 # number of overall MSHR miss cycles 990system.cpu1.dcache.overall_mshr_miss_latency::total 5054503 # number of overall MSHR miss cycles 991system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003398 # mshr miss rate for ReadReq accesses 992system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003398 # mshr miss rate for ReadReq accesses 993system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002915 # mshr miss rate for WriteReq accesses 994system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002915 # mshr miss rate for WriteReq accesses 995system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.787879 # mshr miss rate for SwapReq accesses 996system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.787879 # mshr miss rate for SwapReq accesses 997system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003188 # mshr miss rate for demand accesses 998system.cpu1.dcache.demand_mshr_miss_rate::total 0.003188 # mshr miss rate for demand accesses 999system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003188 # mshr miss rate for overall accesses 1000system.cpu1.dcache.overall_mshr_miss_rate::total 0.003188 # mshr miss rate for overall accesses 1001system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 19778.143750 # average ReadReq mshr miss latency 1002system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 19778.143750 # average ReadReq mshr miss latency 1003system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17830.188679 # average WriteReq mshr miss latency 1004system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17830.188679 # average WriteReq mshr miss latency 1005system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 22471.153846 # average SwapReq mshr miss latency 1006system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 22471.153846 # average SwapReq mshr miss latency 1007system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19001.890977 # average overall mshr miss latency 1008system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19001.890977 # average overall mshr miss latency 1009system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19001.890977 # average overall mshr miss latency 1010system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19001.890977 # average overall mshr miss latency 1011system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1012system.cpu2.numCycles 191010 # number of cpu cycles simulated 1013system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1014system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 1015system.cpu2.BPredUnit.lookups 57179 # Number of BP lookups 1016system.cpu2.BPredUnit.condPredicted 53988 # Number of conditional branches predicted 1017system.cpu2.BPredUnit.condIncorrect 1553 # Number of conditional branches incorrect 1018system.cpu2.BPredUnit.BTBLookups 50487 # Number of BTB lookups 1019system.cpu2.BPredUnit.BTBHits 49441 # Number of BTB hits 1020system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1021system.cpu2.BPredUnit.usedRAS 815 # Number of times the RAS was used to get a target. 1022system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. 1023system.cpu2.fetch.icacheStallCycles 29527 # Number of cycles fetch is stalled on an Icache miss 1024system.cpu2.fetch.Insts 320031 # Number of instructions fetch has processed 1025system.cpu2.fetch.Branches 57179 # Number of branches that fetch encountered 1026system.cpu2.fetch.predictedBranches 50256 # Number of branches that fetch has predicted taken 1027system.cpu2.fetch.Cycles 111848 # Number of cycles fetch has run and was not squashing or blocked 1028system.cpu2.fetch.SquashCycles 4474 # Number of cycles fetch has spent squashing 1029system.cpu2.fetch.BlockedCycles 35937 # Number of cycles fetch has spent blocked 1030system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1031system.cpu2.fetch.NoActiveThreadStallCycles 6751 # Number of stall cycles due to no active thread to fetch from 1032system.cpu2.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps 1033system.cpu2.fetch.CacheLines 20539 # Number of cache lines fetched 1034system.cpu2.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed 1035system.cpu2.fetch.rateDist::samples 187993 # Number of instructions fetched each cycle (Total) 1036system.cpu2.fetch.rateDist::mean 1.702356 # Number of instructions fetched each cycle (Total) 1037system.cpu2.fetch.rateDist::stdev 2.156955 # Number of instructions fetched each cycle (Total) 1038system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1039system.cpu2.fetch.rateDist::0 76145 40.50% 40.50% # Number of instructions fetched each cycle (Total) 1040system.cpu2.fetch.rateDist::1 56782 30.20% 70.71% # Number of instructions fetched each cycle (Total) 1041system.cpu2.fetch.rateDist::2 6165 3.28% 73.99% # Number of instructions fetched each cycle (Total) 1042system.cpu2.fetch.rateDist::3 3347 1.78% 75.77% # Number of instructions fetched each cycle (Total) 1043system.cpu2.fetch.rateDist::4 731 0.39% 76.16% # Number of instructions fetched each cycle (Total) 1044system.cpu2.fetch.rateDist::5 39077 20.79% 96.94% # Number of instructions fetched each cycle (Total) 1045system.cpu2.fetch.rateDist::6 1243 0.66% 97.60% # Number of instructions fetched each cycle (Total) 1046system.cpu2.fetch.rateDist::7 913 0.49% 98.09% # Number of instructions fetched each cycle (Total) 1047system.cpu2.fetch.rateDist::8 3590 1.91% 100.00% # Number of instructions fetched each cycle (Total) 1048system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1049system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1050system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1051system.cpu2.fetch.rateDist::total 187993 # Number of instructions fetched each cycle (Total) 1052system.cpu2.fetch.branchRate 0.299351 # Number of branch fetches per cycle 1053system.cpu2.fetch.rate 1.675467 # Number of inst fetches per cycle 1054system.cpu2.decode.IdleCycles 35252 # Number of cycles decode is idle 1055system.cpu2.decode.BlockedCycles 32290 # Number of cycles decode is blocked 1056system.cpu2.decode.RunCycles 105597 # Number of cycles decode is running 1057system.cpu2.decode.UnblockCycles 5255 # Number of cycles decode is unblocking 1058system.cpu2.decode.SquashCycles 2848 # Number of cycles decode is squashing 1059system.cpu2.decode.DecodedInsts 315625 # Number of instructions handled by decode 1060system.cpu2.rename.SquashCycles 2848 # Number of cycles rename is squashing 1061system.cpu2.rename.IdleCycles 36036 # Number of cycles rename is idle 1062system.cpu2.rename.BlockCycles 16472 # Number of cycles rename is blocking 1063system.cpu2.rename.serializeStallCycles 14955 # count of cycles rename stalled for serializing inst 1064system.cpu2.rename.RunCycles 100655 # Number of cycles rename is running 1065system.cpu2.rename.UnblockCycles 10276 # Number of cycles rename is unblocking 1066system.cpu2.rename.RenamedInsts 313299 # Number of instructions processed by rename 1067system.cpu2.rename.IQFullEvents 22 # Number of times rename has blocked due to IQ full 1068system.cpu2.rename.LSQFullEvents 57 # Number of times rename has blocked due to LSQ full 1069system.cpu2.rename.RenamedOperands 219155 # Number of destination operands rename has renamed 1070system.cpu2.rename.RenameLookups 602465 # Number of register rename lookups that rename has made 1071system.cpu2.rename.int_rename_lookups 602465 # Number of integer rename lookups 1072system.cpu2.rename.CommittedMaps 203359 # Number of HB maps that are committed 1073system.cpu2.rename.UndoneMaps 15796 # Number of HB maps that are undone due to squashing 1074system.cpu2.rename.serializingInsts 1243 # count of serializing insts renamed 1075system.cpu2.rename.tempSerializingInsts 1365 # count of temporary serializing insts renamed 1076system.cpu2.rename.skidInsts 12944 # count of insts added to the skid buffer 1077system.cpu2.memDep0.insertedLoads 89370 # Number of loads inserted to the mem dependence unit. 1078system.cpu2.memDep0.insertedStores 42679 # Number of stores inserted to the mem dependence unit. 1079system.cpu2.memDep0.conflictingLoads 42734 # Number of conflicting loads. 1080system.cpu2.memDep0.conflictingStores 37374 # Number of conflicting stores. 1081system.cpu2.iq.iqInstsAdded 259618 # Number of instructions added to the IQ (excludes non-spec) 1082system.cpu2.iq.iqNonSpecInstsAdded 6531 # Number of non-speculative instructions added to the IQ 1083system.cpu2.iq.iqInstsIssued 261379 # Number of instructions issued 1084system.cpu2.iq.iqSquashedInstsIssued 134 # Number of squashed instructions issued 1085system.cpu2.iq.iqSquashedInstsExamined 13068 # Number of squashed instructions iterated over during squash; mainly for profiling 1086system.cpu2.iq.iqSquashedOperandsExamined 11786 # Number of squashed operands that are examined and possibly removed from graph 1087system.cpu2.iq.iqSquashedNonSpecRemoved 697 # Number of squashed non-spec instructions that were removed 1088system.cpu2.iq.issued_per_cycle::samples 187993 # Number of insts issued each cycle 1089system.cpu2.iq.issued_per_cycle::mean 1.390366 # Number of insts issued each cycle 1090system.cpu2.iq.issued_per_cycle::stdev 1.314588 # Number of insts issued each cycle 1091system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1092system.cpu2.iq.issued_per_cycle::0 73641 39.17% 39.17% # Number of insts issued each cycle 1093system.cpu2.iq.issued_per_cycle::1 23139 12.31% 51.48% # Number of insts issued each cycle 1094system.cpu2.iq.issued_per_cycle::2 42800 22.77% 74.25% # Number of insts issued each cycle 1095system.cpu2.iq.issued_per_cycle::3 43353 23.06% 97.31% # Number of insts issued each cycle 1096system.cpu2.iq.issued_per_cycle::4 3352 1.78% 99.09% # Number of insts issued each cycle 1097system.cpu2.iq.issued_per_cycle::5 1252 0.67% 99.76% # Number of insts issued each cycle 1098system.cpu2.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle 1099system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle 1100system.cpu2.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle 1101system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1102system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1103system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1104system.cpu2.iq.issued_per_cycle::total 187993 # Number of insts issued each cycle 1105system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1106system.cpu2.iq.fu_full::IntAlu 21 6.71% 6.71% # attempts to use FU when none available 1107system.cpu2.iq.fu_full::IntMult 0 0.00% 6.71% # attempts to use FU when none available 1108system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.71% # attempts to use FU when none available 1109system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.71% # attempts to use FU when none available 1110system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.71% # attempts to use FU when none available 1111system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.71% # attempts to use FU when none available 1112system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.71% # attempts to use FU when none available 1113system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.71% # attempts to use FU when none available 1114system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.71% # attempts to use FU when none available 1115system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.71% # attempts to use FU when none available 1116system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.71% # attempts to use FU when none available 1117system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.71% # attempts to use FU when none available 1118system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.71% # attempts to use FU when none available 1119system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.71% # attempts to use FU when none available 1120system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.71% # attempts to use FU when none available 1121system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.71% # attempts to use FU when none available 1122system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.71% # attempts to use FU when none available 1123system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.71% # attempts to use FU when none available 1124system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.71% # attempts to use FU when none available 1125system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.71% # attempts to use FU when none available 1126system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.71% # attempts to use FU when none available 1127system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.71% # attempts to use FU when none available 1128system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.71% # attempts to use FU when none available 1129system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.71% # attempts to use FU when none available 1130system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.71% # attempts to use FU when none available 1131system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.71% # attempts to use FU when none available 1132system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.71% # attempts to use FU when none available 1133system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.71% # attempts to use FU when none available 1134system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.71% # attempts to use FU when none available 1135system.cpu2.iq.fu_full::MemRead 82 26.20% 32.91% # attempts to use FU when none available 1136system.cpu2.iq.fu_full::MemWrite 210 67.09% 100.00% # attempts to use FU when none available 1137system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1138system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1139system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1140system.cpu2.iq.FU_type_0::IntAlu 125670 48.08% 48.08% # Type of FU issued 1141system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.08% # Type of FU issued 1142system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.08% # Type of FU issued 1143system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.08% # Type of FU issued 1144system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.08% # Type of FU issued 1145system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.08% # Type of FU issued 1146system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.08% # Type of FU issued 1147system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.08% # Type of FU issued 1148system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.08% # Type of FU issued 1149system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.08% # Type of FU issued 1150system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.08% # Type of FU issued 1151system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.08% # Type of FU issued 1152system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.08% # Type of FU issued 1153system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.08% # Type of FU issued 1154system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.08% # Type of FU issued 1155system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.08% # Type of FU issued 1156system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.08% # Type of FU issued 1157system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.08% # Type of FU issued 1158system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.08% # Type of FU issued 1159system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.08% # Type of FU issued 1160system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.08% # Type of FU issued 1161system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.08% # Type of FU issued 1162system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.08% # Type of FU issued 1163system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.08% # Type of FU issued 1164system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.08% # Type of FU issued 1165system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.08% # Type of FU issued 1166system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.08% # Type of FU issued 1167system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.08% # Type of FU issued 1168system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.08% # Type of FU issued 1169system.cpu2.iq.FU_type_0::MemRead 93767 35.87% 83.95% # Type of FU issued 1170system.cpu2.iq.FU_type_0::MemWrite 41942 16.05% 100.00% # Type of FU issued 1171system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1172system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1173system.cpu2.iq.FU_type_0::total 261379 # Type of FU issued 1174system.cpu2.iq.rate 1.368405 # Inst issue rate 1175system.cpu2.iq.fu_busy_cnt 313 # FU busy when requested 1176system.cpu2.iq.fu_busy_rate 0.001197 # FU busy rate (busy events/executed inst) 1177system.cpu2.iq.int_inst_queue_reads 711198 # Number of integer instruction queue reads 1178system.cpu2.iq.int_inst_queue_writes 279252 # Number of integer instruction queue writes 1179system.cpu2.iq.int_inst_queue_wakeup_accesses 259224 # Number of integer instruction queue wakeup accesses 1180system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1181system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1182system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1183system.cpu2.iq.int_alu_accesses 261692 # Number of integer alu accesses 1184system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1185system.cpu2.iew.lsq.thread0.forwLoads 37218 # Number of loads that had data forwarded from stores 1186system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1187system.cpu2.iew.lsq.thread0.squashedLoads 2690 # Number of loads squashed 1188system.cpu2.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed 1189system.cpu2.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations 1190system.cpu2.iew.lsq.thread0.squashedStores 1641 # Number of stores squashed 1191system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1192system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1193system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1194system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1195system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1196system.cpu2.iew.iewSquashCycles 2848 # Number of cycles IEW is squashing 1197system.cpu2.iew.iewBlockCycles 1926 # Number of cycles IEW is blocking 1198system.cpu2.iew.iewUnblockCycles 75 # Number of cycles IEW is unblocking 1199system.cpu2.iew.iewDispatchedInsts 309970 # Number of instructions dispatched to IQ 1200system.cpu2.iew.iewDispSquashedInsts 424 # Number of squashed instructions skipped by dispatch 1201system.cpu2.iew.iewDispLoadInsts 89370 # Number of dispatched load instructions 1202system.cpu2.iew.iewDispStoreInsts 42679 # Number of dispatched store instructions 1203system.cpu2.iew.iewDispNonSpecInsts 1173 # Number of dispatched non-speculative instructions 1204system.cpu2.iew.iewIQFullEvents 72 # Number of times the IQ has become full, causing a stall 1205system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1206system.cpu2.iew.memOrderViolationEvents 35 # Number of memory order violations 1207system.cpu2.iew.predictedTakenIncorrect 514 # Number of branches that were predicted taken incorrectly 1208system.cpu2.iew.predictedNotTakenIncorrect 1208 # Number of branches that were predicted not taken incorrectly 1209system.cpu2.iew.branchMispredicts 1722 # Number of branch mispredicts detected at execute 1210system.cpu2.iew.iewExecutedInsts 259980 # Number of executed instructions 1211system.cpu2.iew.iewExecLoadInsts 88335 # Number of load instructions executed 1212system.cpu2.iew.iewExecSquashedInsts 1399 # Number of squashed instructions skipped in execute 1213system.cpu2.iew.exec_swp 0 # number of swp insts executed 1214system.cpu2.iew.exec_nop 43821 # number of nop insts executed 1215system.cpu2.iew.exec_refs 130189 # number of memory reference insts executed 1216system.cpu2.iew.exec_branches 53302 # Number of branches executed 1217system.cpu2.iew.exec_stores 41854 # Number of stores executed 1218system.cpu2.iew.exec_rate 1.361081 # Inst execution rate 1219system.cpu2.iew.wb_sent 259524 # cumulative count of insts sent to commit 1220system.cpu2.iew.wb_count 259224 # cumulative count of insts written-back 1221system.cpu2.iew.wb_producers 147020 # num instructions producing a value 1222system.cpu2.iew.wb_consumers 151915 # num instructions consuming a value 1223system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1224system.cpu2.iew.wb_rate 1.357123 # insts written-back per cycle 1225system.cpu2.iew.wb_fanout 0.967778 # average fanout of values written-back 1226system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1227system.cpu2.commit.commitCommittedInsts 294930 # The number of committed instructions 1228system.cpu2.commit.commitCommittedOps 294930 # The number of committed instructions 1229system.cpu2.commit.commitSquashedInsts 15032 # The number of squashed insts skipped by commit 1230system.cpu2.commit.commitNonSpecStalls 5834 # The number of times commit has been forced to stall to communicate backwards 1231system.cpu2.commit.branchMispredicts 1553 # The number of times a branch was mispredicted 1232system.cpu2.commit.committed_per_cycle::samples 178395 # Number of insts commited each cycle 1233system.cpu2.commit.committed_per_cycle::mean 1.653241 # Number of insts commited each cycle 1234system.cpu2.commit.committed_per_cycle::stdev 2.030877 # Number of insts commited each cycle 1235system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1236system.cpu2.commit.committed_per_cycle::0 72759 40.79% 40.79% # Number of insts commited each cycle 1237system.cpu2.commit.committed_per_cycle::1 51159 28.68% 69.46% # Number of insts commited each cycle 1238system.cpu2.commit.committed_per_cycle::2 6241 3.50% 72.96% # Number of insts commited each cycle 1239system.cpu2.commit.committed_per_cycle::3 6697 3.75% 76.72% # Number of insts commited each cycle 1240system.cpu2.commit.committed_per_cycle::4 1549 0.87% 77.58% # Number of insts commited each cycle 1241system.cpu2.commit.committed_per_cycle::5 37557 21.05% 98.64% # Number of insts commited each cycle 1242system.cpu2.commit.committed_per_cycle::6 629 0.35% 98.99% # Number of insts commited each cycle 1243system.cpu2.commit.committed_per_cycle::7 989 0.55% 99.54% # Number of insts commited each cycle 1244system.cpu2.commit.committed_per_cycle::8 815 0.46% 100.00% # Number of insts commited each cycle 1245system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1246system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1247system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1248system.cpu2.commit.committed_per_cycle::total 178395 # Number of insts commited each cycle 1249system.cpu2.commit.committedInsts 294930 # Number of instructions committed 1250system.cpu2.commit.committedOps 294930 # Number of ops (including micro ops) committed 1251system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed 1252system.cpu2.commit.refs 127718 # Number of memory references committed 1253system.cpu2.commit.loads 86680 # Number of loads committed 1254system.cpu2.commit.membars 5119 # Number of memory barriers committed 1255system.cpu2.commit.branches 52122 # Number of branches committed 1256system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. 1257system.cpu2.commit.int_insts 201960 # Number of committed integer instructions. 1258system.cpu2.commit.function_calls 322 # Number of function calls committed. 1259system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached 1260system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits 1261system.cpu2.rob.rob_reads 486955 # The number of ROB reads 1262system.cpu2.rob.rob_writes 622786 # The number of ROB writes 1263system.cpu2.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself 1264system.cpu2.idleCycles 3017 # Total number of cycles that the CPU has spent unscheduled due to idling 1265system.cpu2.quiesceCycles 36810 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1266system.cpu2.committedInsts 246900 # Number of Instructions Simulated 1267system.cpu2.committedOps 246900 # Number of Ops (including micro ops) Simulated 1268system.cpu2.committedInsts_total 246900 # Number of Instructions Simulated 1269system.cpu2.cpi 0.773633 # CPI: Cycles Per Instruction 1270system.cpu2.cpi_total 0.773633 # CPI: Total CPI of All Threads 1271system.cpu2.ipc 1.292602 # IPC: Instructions Per Cycle 1272system.cpu2.ipc_total 1.292602 # IPC: Total IPC of All Threads 1273system.cpu2.int_regfile_reads 450556 # number of integer regfile reads 1274system.cpu2.int_regfile_writes 209704 # number of integer regfile writes 1275system.cpu2.fp_regfile_writes 64 # number of floating regfile writes 1276system.cpu2.misc_regfile_reads 131893 # number of misc regfile reads 1277system.cpu2.misc_regfile_writes 646 # number of misc regfile writes 1278system.cpu2.icache.replacements 322 # number of replacements 1279system.cpu2.icache.tagsinuse 84.177245 # Cycle average of tags in use 1280system.cpu2.icache.total_refs 20042 # Total number of references to valid blocks. 1281system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks. 1282system.cpu2.icache.avg_refs 45.757991 # Average number of references to valid blocks. 1283system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1284system.cpu2.icache.occ_blocks::cpu2.inst 84.177245 # Average occupied blocks per requestor 1285system.cpu2.icache.occ_percent::cpu2.inst 0.164409 # Average percentage of cache occupancy 1286system.cpu2.icache.occ_percent::total 0.164409 # Average percentage of cache occupancy 1287system.cpu2.icache.ReadReq_hits::cpu2.inst 20042 # number of ReadReq hits 1288system.cpu2.icache.ReadReq_hits::total 20042 # number of ReadReq hits 1289system.cpu2.icache.demand_hits::cpu2.inst 20042 # number of demand (read+write) hits 1290system.cpu2.icache.demand_hits::total 20042 # number of demand (read+write) hits 1291system.cpu2.icache.overall_hits::cpu2.inst 20042 # number of overall hits 1292system.cpu2.icache.overall_hits::total 20042 # number of overall hits 1293system.cpu2.icache.ReadReq_misses::cpu2.inst 497 # number of ReadReq misses 1294system.cpu2.icache.ReadReq_misses::total 497 # number of ReadReq misses 1295system.cpu2.icache.demand_misses::cpu2.inst 497 # number of demand (read+write) misses 1296system.cpu2.icache.demand_misses::total 497 # number of demand (read+write) misses 1297system.cpu2.icache.overall_misses::cpu2.inst 497 # number of overall misses 1298system.cpu2.icache.overall_misses::total 497 # number of overall misses 1299system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7614500 # number of ReadReq miss cycles 1300system.cpu2.icache.ReadReq_miss_latency::total 7614500 # number of ReadReq miss cycles 1301system.cpu2.icache.demand_miss_latency::cpu2.inst 7614500 # number of demand (read+write) miss cycles 1302system.cpu2.icache.demand_miss_latency::total 7614500 # number of demand (read+write) miss cycles 1303system.cpu2.icache.overall_miss_latency::cpu2.inst 7614500 # number of overall miss cycles 1304system.cpu2.icache.overall_miss_latency::total 7614500 # number of overall miss cycles 1305system.cpu2.icache.ReadReq_accesses::cpu2.inst 20539 # number of ReadReq accesses(hits+misses) 1306system.cpu2.icache.ReadReq_accesses::total 20539 # number of ReadReq accesses(hits+misses) 1307system.cpu2.icache.demand_accesses::cpu2.inst 20539 # number of demand (read+write) accesses 1308system.cpu2.icache.demand_accesses::total 20539 # number of demand (read+write) accesses 1309system.cpu2.icache.overall_accesses::cpu2.inst 20539 # number of overall (read+write) accesses 1310system.cpu2.icache.overall_accesses::total 20539 # number of overall (read+write) accesses 1311system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024198 # miss rate for ReadReq accesses 1312system.cpu2.icache.ReadReq_miss_rate::total 0.024198 # miss rate for ReadReq accesses 1313system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024198 # miss rate for demand accesses 1314system.cpu2.icache.demand_miss_rate::total 0.024198 # miss rate for demand accesses 1315system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024198 # miss rate for overall accesses 1316system.cpu2.icache.overall_miss_rate::total 0.024198 # miss rate for overall accesses 1317system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15320.925553 # average ReadReq miss latency 1318system.cpu2.icache.ReadReq_avg_miss_latency::total 15320.925553 # average ReadReq miss latency 1319system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15320.925553 # average overall miss latency 1320system.cpu2.icache.demand_avg_miss_latency::total 15320.925553 # average overall miss latency 1321system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15320.925553 # average overall miss latency 1322system.cpu2.icache.overall_avg_miss_latency::total 15320.925553 # average overall miss latency 1323system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1324system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1325system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1326system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1327system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1328system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1329system.cpu2.icache.fast_writes 0 # number of fast writes performed 1330system.cpu2.icache.cache_copies 0 # number of cache copies performed 1331system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 59 # number of ReadReq MSHR hits 1332system.cpu2.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits 1333system.cpu2.icache.demand_mshr_hits::cpu2.inst 59 # number of demand (read+write) MSHR hits 1334system.cpu2.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits 1335system.cpu2.icache.overall_mshr_hits::cpu2.inst 59 # number of overall MSHR hits 1336system.cpu2.icache.overall_mshr_hits::total 59 # number of overall MSHR hits 1337system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 438 # number of ReadReq MSHR misses 1338system.cpu2.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses 1339system.cpu2.icache.demand_mshr_misses::cpu2.inst 438 # number of demand (read+write) MSHR misses 1340system.cpu2.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses 1341system.cpu2.icache.overall_mshr_misses::cpu2.inst 438 # number of overall MSHR misses 1342system.cpu2.icache.overall_mshr_misses::total 438 # number of overall MSHR misses 1343system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5672000 # number of ReadReq MSHR miss cycles 1344system.cpu2.icache.ReadReq_mshr_miss_latency::total 5672000 # number of ReadReq MSHR miss cycles 1345system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5672000 # number of demand (read+write) MSHR miss cycles 1346system.cpu2.icache.demand_mshr_miss_latency::total 5672000 # number of demand (read+write) MSHR miss cycles 1347system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5672000 # number of overall MSHR miss cycles 1348system.cpu2.icache.overall_mshr_miss_latency::total 5672000 # number of overall MSHR miss cycles 1349system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021325 # mshr miss rate for ReadReq accesses 1350system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021325 # mshr miss rate for ReadReq accesses 1351system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021325 # mshr miss rate for demand accesses 1352system.cpu2.icache.demand_mshr_miss_rate::total 0.021325 # mshr miss rate for demand accesses 1353system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021325 # mshr miss rate for overall accesses 1354system.cpu2.icache.overall_mshr_miss_rate::total 0.021325 # mshr miss rate for overall accesses 1355system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12949.771689 # average ReadReq mshr miss latency 1356system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12949.771689 # average ReadReq mshr miss latency 1357system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12949.771689 # average overall mshr miss latency 1358system.cpu2.icache.demand_avg_mshr_miss_latency::total 12949.771689 # average overall mshr miss latency 1359system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12949.771689 # average overall mshr miss latency 1360system.cpu2.icache.overall_avg_mshr_miss_latency::total 12949.771689 # average overall mshr miss latency 1361system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1362system.cpu2.dcache.replacements 0 # number of replacements 1363system.cpu2.dcache.tagsinuse 24.875323 # Cycle average of tags in use 1364system.cpu2.dcache.total_refs 47216 # Total number of references to valid blocks. 1365system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. 1366system.cpu2.dcache.avg_refs 1686.285714 # Average number of references to valid blocks. 1367system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1368system.cpu2.dcache.occ_blocks::cpu2.data 24.875323 # Average occupied blocks per requestor 1369system.cpu2.dcache.occ_percent::cpu2.data 0.048585 # Average percentage of cache occupancy 1370system.cpu2.dcache.occ_percent::total 0.048585 # Average percentage of cache occupancy 1371system.cpu2.dcache.ReadReq_hits::cpu2.data 50709 # number of ReadReq hits 1372system.cpu2.dcache.ReadReq_hits::total 50709 # number of ReadReq hits 1373system.cpu2.dcache.WriteReq_hits::cpu2.data 40830 # number of WriteReq hits 1374system.cpu2.dcache.WriteReq_hits::total 40830 # number of WriteReq hits 1375system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits 1376system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits 1377system.cpu2.dcache.demand_hits::cpu2.data 91539 # number of demand (read+write) hits 1378system.cpu2.dcache.demand_hits::total 91539 # number of demand (read+write) hits 1379system.cpu2.dcache.overall_hits::cpu2.data 91539 # number of overall hits 1380system.cpu2.dcache.overall_hits::total 91539 # number of overall hits 1381system.cpu2.dcache.ReadReq_misses::cpu2.data 389 # number of ReadReq misses 1382system.cpu2.dcache.ReadReq_misses::total 389 # number of ReadReq misses 1383system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses 1384system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses 1385system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses 1386system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses 1387system.cpu2.dcache.demand_misses::cpu2.data 528 # number of demand (read+write) misses 1388system.cpu2.dcache.demand_misses::total 528 # number of demand (read+write) misses 1389system.cpu2.dcache.overall_misses::cpu2.data 528 # number of overall misses 1390system.cpu2.dcache.overall_misses::total 528 # number of overall misses 1391system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 10172000 # number of ReadReq miss cycles 1392system.cpu2.dcache.ReadReq_miss_latency::total 10172000 # number of ReadReq miss cycles 1393system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3390500 # number of WriteReq miss cycles 1394system.cpu2.dcache.WriteReq_miss_latency::total 3390500 # number of WriteReq miss cycles 1395system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1234500 # number of SwapReq miss cycles 1396system.cpu2.dcache.SwapReq_miss_latency::total 1234500 # number of SwapReq miss cycles 1397system.cpu2.dcache.demand_miss_latency::cpu2.data 13562500 # number of demand (read+write) miss cycles 1398system.cpu2.dcache.demand_miss_latency::total 13562500 # number of demand (read+write) miss cycles 1399system.cpu2.dcache.overall_miss_latency::cpu2.data 13562500 # number of overall miss cycles 1400system.cpu2.dcache.overall_miss_latency::total 13562500 # number of overall miss cycles 1401system.cpu2.dcache.ReadReq_accesses::cpu2.data 51098 # number of ReadReq accesses(hits+misses) 1402system.cpu2.dcache.ReadReq_accesses::total 51098 # number of ReadReq accesses(hits+misses) 1403system.cpu2.dcache.WriteReq_accesses::cpu2.data 40969 # number of WriteReq accesses(hits+misses) 1404system.cpu2.dcache.WriteReq_accesses::total 40969 # number of WriteReq accesses(hits+misses) 1405system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) 1406system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) 1407system.cpu2.dcache.demand_accesses::cpu2.data 92067 # number of demand (read+write) accesses 1408system.cpu2.dcache.demand_accesses::total 92067 # number of demand (read+write) accesses 1409system.cpu2.dcache.overall_accesses::cpu2.data 92067 # number of overall (read+write) accesses 1410system.cpu2.dcache.overall_accesses::total 92067 # number of overall (read+write) accesses 1411system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007613 # miss rate for ReadReq accesses 1412system.cpu2.dcache.ReadReq_miss_rate::total 0.007613 # miss rate for ReadReq accesses 1413system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003393 # miss rate for WriteReq accesses 1414system.cpu2.dcache.WriteReq_miss_rate::total 0.003393 # miss rate for WriteReq accesses 1415system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.826087 # miss rate for SwapReq accesses 1416system.cpu2.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses 1417system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005735 # miss rate for demand accesses 1418system.cpu2.dcache.demand_miss_rate::total 0.005735 # miss rate for demand accesses 1419system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005735 # miss rate for overall accesses 1420system.cpu2.dcache.overall_miss_rate::total 0.005735 # miss rate for overall accesses 1421system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 26149.100257 # average ReadReq miss latency 1422system.cpu2.dcache.ReadReq_avg_miss_latency::total 26149.100257 # average ReadReq miss latency 1423system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24392.086331 # average WriteReq miss latency 1424system.cpu2.dcache.WriteReq_avg_miss_latency::total 24392.086331 # average WriteReq miss latency 1425system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21657.894737 # average SwapReq miss latency 1426system.cpu2.dcache.SwapReq_avg_miss_latency::total 21657.894737 # average SwapReq miss latency 1427system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 25686.553030 # average overall miss latency 1428system.cpu2.dcache.demand_avg_miss_latency::total 25686.553030 # average overall miss latency 1429system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 25686.553030 # average overall miss latency 1430system.cpu2.dcache.overall_avg_miss_latency::total 25686.553030 # average overall miss latency 1431system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1432system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1433system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1434system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1435system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1436system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1437system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1438system.cpu2.dcache.cache_copies 0 # number of cache copies performed 1439system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 234 # number of ReadReq MSHR hits 1440system.cpu2.dcache.ReadReq_mshr_hits::total 234 # number of ReadReq MSHR hits 1441system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 35 # number of WriteReq MSHR hits 1442system.cpu2.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits 1443system.cpu2.dcache.demand_mshr_hits::cpu2.data 269 # number of demand (read+write) MSHR hits 1444system.cpu2.dcache.demand_mshr_hits::total 269 # number of demand (read+write) MSHR hits 1445system.cpu2.dcache.overall_mshr_hits::cpu2.data 269 # number of overall MSHR hits 1446system.cpu2.dcache.overall_mshr_hits::total 269 # number of overall MSHR hits 1447system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 155 # number of ReadReq MSHR misses 1448system.cpu2.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses 1449system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses 1450system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses 1451system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses 1452system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses 1453system.cpu2.dcache.demand_mshr_misses::cpu2.data 259 # number of demand (read+write) MSHR misses 1454system.cpu2.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses 1455system.cpu2.dcache.overall_mshr_misses::cpu2.data 259 # number of overall MSHR misses 1456system.cpu2.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses 1457system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2539505 # number of ReadReq MSHR miss cycles 1458system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2539505 # number of ReadReq MSHR miss cycles 1459system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1736500 # number of WriteReq MSHR miss cycles 1460system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1736500 # number of WriteReq MSHR miss cycles 1461system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1057000 # number of SwapReq MSHR miss cycles 1462system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1057000 # number of SwapReq MSHR miss cycles 1463system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4276005 # number of demand (read+write) MSHR miss cycles 1464system.cpu2.dcache.demand_mshr_miss_latency::total 4276005 # number of demand (read+write) MSHR miss cycles 1465system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4276005 # number of overall MSHR miss cycles 1466system.cpu2.dcache.overall_mshr_miss_latency::total 4276005 # number of overall MSHR miss cycles 1467system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003033 # mshr miss rate for ReadReq accesses 1468system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003033 # mshr miss rate for ReadReq accesses 1469system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002539 # mshr miss rate for WriteReq accesses 1470system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002539 # mshr miss rate for WriteReq accesses 1471system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses 1472system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses 1473system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002813 # mshr miss rate for demand accesses 1474system.cpu2.dcache.demand_mshr_miss_rate::total 0.002813 # mshr miss rate for demand accesses 1475system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002813 # mshr miss rate for overall accesses 1476system.cpu2.dcache.overall_mshr_miss_rate::total 0.002813 # mshr miss rate for overall accesses 1477system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16383.903226 # average ReadReq mshr miss latency 1478system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16383.903226 # average ReadReq mshr miss latency 1479system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16697.115385 # average WriteReq mshr miss latency 1480system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16697.115385 # average WriteReq mshr miss latency 1481system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18543.859649 # average SwapReq mshr miss latency 1482system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18543.859649 # average SwapReq mshr miss latency 1483system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16509.671815 # average overall mshr miss latency 1484system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16509.671815 # average overall mshr miss latency 1485system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16509.671815 # average overall mshr miss latency 1486system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16509.671815 # average overall mshr miss latency 1487system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1488system.cpu3.numCycles 190730 # number of cpu cycles simulated 1489system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1490system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 1491system.cpu3.BPredUnit.lookups 50135 # Number of BP lookups 1492system.cpu3.BPredUnit.condPredicted 46886 # Number of conditional branches predicted 1493system.cpu3.BPredUnit.condIncorrect 1563 # Number of conditional branches incorrect 1494system.cpu3.BPredUnit.BTBLookups 43380 # Number of BTB lookups 1495system.cpu3.BPredUnit.BTBHits 42368 # Number of BTB hits 1496system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1497system.cpu3.BPredUnit.usedRAS 844 # Number of times the RAS was used to get a target. 1498system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. 1499system.cpu3.fetch.icacheStallCycles 33373 # Number of cycles fetch is stalled on an Icache miss 1500system.cpu3.fetch.Insts 273510 # Number of instructions fetch has processed 1501system.cpu3.fetch.Branches 50135 # Number of branches that fetch encountered 1502system.cpu3.fetch.predictedBranches 43212 # Number of branches that fetch has predicted taken 1503system.cpu3.fetch.Cycles 99693 # Number of cycles fetch has run and was not squashing or blocked 1504system.cpu3.fetch.SquashCycles 4441 # Number of cycles fetch has spent squashing 1505system.cpu3.fetch.BlockedCycles 43703 # Number of cycles fetch has spent blocked 1506system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1507system.cpu3.fetch.NoActiveThreadStallCycles 6715 # Number of stall cycles due to no active thread to fetch from 1508system.cpu3.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps 1509system.cpu3.fetch.CacheLines 24485 # Number of cache lines fetched 1510system.cpu3.fetch.IcacheSquashes 321 # Number of outstanding Icache misses that were squashed 1511system.cpu3.fetch.rateDist::samples 187356 # Number of instructions fetched each cycle (Total) 1512system.cpu3.fetch.rateDist::mean 1.459841 # Number of instructions fetched each cycle (Total) 1513system.cpu3.fetch.rateDist::stdev 2.059659 # Number of instructions fetched each cycle (Total) 1514system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1515system.cpu3.fetch.rateDist::0 87663 46.79% 46.79% # Number of instructions fetched each cycle (Total) 1516system.cpu3.fetch.rateDist::1 51707 27.60% 74.39% # Number of instructions fetched each cycle (Total) 1517system.cpu3.fetch.rateDist::2 8154 4.35% 78.74% # Number of instructions fetched each cycle (Total) 1518system.cpu3.fetch.rateDist::3 3276 1.75% 80.49% # Number of instructions fetched each cycle (Total) 1519system.cpu3.fetch.rateDist::4 745 0.40% 80.89% # Number of instructions fetched each cycle (Total) 1520system.cpu3.fetch.rateDist::5 30183 16.11% 97.00% # Number of instructions fetched each cycle (Total) 1521system.cpu3.fetch.rateDist::6 1182 0.63% 97.63% # Number of instructions fetched each cycle (Total) 1522system.cpu3.fetch.rateDist::7 888 0.47% 98.10% # Number of instructions fetched each cycle (Total) 1523system.cpu3.fetch.rateDist::8 3558 1.90% 100.00% # Number of instructions fetched each cycle (Total) 1524system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1525system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1526system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1527system.cpu3.fetch.rateDist::total 187356 # Number of instructions fetched each cycle (Total) 1528system.cpu3.fetch.branchRate 0.262858 # Number of branch fetches per cycle 1529system.cpu3.fetch.rate 1.434017 # Number of inst fetches per cycle 1530system.cpu3.decode.IdleCycles 40875 # Number of cycles decode is idle 1531system.cpu3.decode.BlockedCycles 38262 # Number of cycles decode is blocked 1532system.cpu3.decode.RunCycles 91696 # Number of cycles decode is running 1533system.cpu3.decode.UnblockCycles 6999 # Number of cycles decode is unblocking 1534system.cpu3.decode.SquashCycles 2809 # Number of cycles decode is squashing 1535system.cpu3.decode.DecodedInsts 269218 # Number of instructions handled by decode 1536system.cpu3.rename.SquashCycles 2809 # Number of cycles rename is squashing 1537system.cpu3.rename.IdleCycles 41677 # Number of cycles rename is idle 1538system.cpu3.rename.BlockCycles 21676 # Number of cycles rename is blocking 1539system.cpu3.rename.serializeStallCycles 15745 # count of cycles rename stalled for serializing inst 1540system.cpu3.rename.RunCycles 84975 # Number of cycles rename is running 1541system.cpu3.rename.UnblockCycles 13759 # Number of cycles rename is unblocking 1542system.cpu3.rename.RenamedInsts 266737 # Number of instructions processed by rename 1543system.cpu3.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full 1544system.cpu3.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full 1545system.cpu3.rename.RenamedOperands 184789 # Number of destination operands rename has renamed 1546system.cpu3.rename.RenameLookups 501822 # Number of register rename lookups that rename has made 1547system.cpu3.rename.int_rename_lookups 501822 # Number of integer rename lookups 1548system.cpu3.rename.CommittedMaps 169578 # Number of HB maps that are committed 1549system.cpu3.rename.UndoneMaps 15211 # Number of HB maps that are undone due to squashing 1550system.cpu3.rename.serializingInsts 1292 # count of serializing insts renamed 1551system.cpu3.rename.tempSerializingInsts 1426 # count of temporary serializing insts renamed 1552system.cpu3.rename.skidInsts 16516 # count of insts added to the skid buffer 1553system.cpu3.memDep0.insertedLoads 73298 # Number of loads inserted to the mem dependence unit. 1554system.cpu3.memDep0.insertedStores 33720 # Number of stores inserted to the mem dependence unit. 1555system.cpu3.memDep0.conflictingLoads 35666 # Number of conflicting loads. 1556system.cpu3.memDep0.conflictingStores 28418 # Number of conflicting stores. 1557system.cpu3.iq.iqInstsAdded 218299 # Number of instructions added to the IQ (excludes non-spec) 1558system.cpu3.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ 1559system.cpu3.iq.iqInstsIssued 222114 # Number of instructions issued 1560system.cpu3.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 1561system.cpu3.iq.iqSquashedInstsExamined 12726 # Number of squashed instructions iterated over during squash; mainly for profiling 1562system.cpu3.iq.iqSquashedOperandsExamined 11163 # Number of squashed operands that are examined and possibly removed from graph 1563system.cpu3.iq.iqSquashedNonSpecRemoved 773 # Number of squashed non-spec instructions that were removed 1564system.cpu3.iq.issued_per_cycle::samples 187356 # Number of insts issued each cycle 1565system.cpu3.iq.issued_per_cycle::mean 1.185518 # Number of insts issued each cycle 1566system.cpu3.iq.issued_per_cycle::stdev 1.293170 # Number of insts issued each cycle 1567system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1568system.cpu3.iq.issued_per_cycle::0 85320 45.54% 45.54% # Number of insts issued each cycle 1569system.cpu3.iq.issued_per_cycle::1 28690 15.31% 60.85% # Number of insts issued each cycle 1570system.cpu3.iq.issued_per_cycle::2 33902 18.09% 78.95% # Number of insts issued each cycle 1571system.cpu3.iq.issued_per_cycle::3 34456 18.39% 97.34% # Number of insts issued each cycle 1572system.cpu3.iq.issued_per_cycle::4 3309 1.77% 99.10% # Number of insts issued each cycle 1573system.cpu3.iq.issued_per_cycle::5 1236 0.66% 99.76% # Number of insts issued each cycle 1574system.cpu3.iq.issued_per_cycle::6 327 0.17% 99.94% # Number of insts issued each cycle 1575system.cpu3.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle 1576system.cpu3.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle 1577system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1578system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1579system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1580system.cpu3.iq.issued_per_cycle::total 187356 # Number of insts issued each cycle 1581system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1582system.cpu3.iq.fu_full::IntAlu 22 7.17% 7.17% # attempts to use FU when none available 1583system.cpu3.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available 1584system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available 1585system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available 1586system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available 1587system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available 1588system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available 1589system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available 1590system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available 1591system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available 1592system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available 1593system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available 1594system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available 1595system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available 1596system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available 1597system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available 1598system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available 1599system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available 1600system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available 1601system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available 1602system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available 1603system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available 1604system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available 1605system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available 1606system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available 1607system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available 1608system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available 1609system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available 1610system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available 1611system.cpu3.iq.fu_full::MemRead 75 24.43% 31.60% # attempts to use FU when none available 1612system.cpu3.iq.fu_full::MemWrite 210 68.40% 100.00% # attempts to use FU when none available 1613system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1614system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1615system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1616system.cpu3.iq.FU_type_0::IntAlu 109540 49.32% 49.32% # Type of FU issued 1617system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.32% # Type of FU issued 1618system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.32% # Type of FU issued 1619system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.32% # Type of FU issued 1620system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.32% # Type of FU issued 1621system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.32% # Type of FU issued 1622system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.32% # Type of FU issued 1623system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.32% # Type of FU issued 1624system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.32% # Type of FU issued 1625system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.32% # Type of FU issued 1626system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.32% # Type of FU issued 1627system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.32% # Type of FU issued 1628system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.32% # Type of FU issued 1629system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.32% # Type of FU issued 1630system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.32% # Type of FU issued 1631system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.32% # Type of FU issued 1632system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.32% # Type of FU issued 1633system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.32% # Type of FU issued 1634system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.32% # Type of FU issued 1635system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.32% # Type of FU issued 1636system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.32% # Type of FU issued 1637system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued 1638system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.32% # Type of FU issued 1639system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.32% # Type of FU issued 1640system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.32% # Type of FU issued 1641system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.32% # Type of FU issued 1642system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.32% # Type of FU issued 1643system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.32% # Type of FU issued 1644system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.32% # Type of FU issued 1645system.cpu3.iq.FU_type_0::MemRead 79567 35.82% 85.14% # Type of FU issued 1646system.cpu3.iq.FU_type_0::MemWrite 33007 14.86% 100.00% # Type of FU issued 1647system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1648system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1649system.cpu3.iq.FU_type_0::total 222114 # Type of FU issued 1650system.cpu3.iq.rate 1.164547 # Inst issue rate 1651system.cpu3.iq.fu_busy_cnt 307 # FU busy when requested 1652system.cpu3.iq.fu_busy_rate 0.001382 # FU busy rate (busy events/executed inst) 1653system.cpu3.iq.int_inst_queue_reads 632004 # Number of integer instruction queue reads 1654system.cpu3.iq.int_inst_queue_writes 239536 # Number of integer instruction queue writes 1655system.cpu3.iq.int_inst_queue_wakeup_accesses 220090 # Number of integer instruction queue wakeup accesses 1656system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1657system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1658system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1659system.cpu3.iq.int_alu_accesses 222421 # Number of integer alu accesses 1660system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1661system.cpu3.iew.lsq.thread0.forwLoads 28294 # Number of loads that had data forwarded from stores 1662system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1663system.cpu3.iew.lsq.thread0.squashedLoads 2578 # Number of loads squashed 1664system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1665system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations 1666system.cpu3.iew.lsq.thread0.squashedStores 1587 # Number of stores squashed 1667system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1668system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1669system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1670system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1671system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1672system.cpu3.iew.iewSquashCycles 2809 # Number of cycles IEW is squashing 1673system.cpu3.iew.iewBlockCycles 1854 # Number of cycles IEW is blocking 1674system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking 1675system.cpu3.iew.iewDispatchedInsts 263586 # Number of instructions dispatched to IQ 1676system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch 1677system.cpu3.iew.iewDispLoadInsts 73298 # Number of dispatched load instructions 1678system.cpu3.iew.iewDispStoreInsts 33720 # Number of dispatched store instructions 1679system.cpu3.iew.iewDispNonSpecInsts 1219 # Number of dispatched non-speculative instructions 1680system.cpu3.iew.iewIQFullEvents 53 # Number of times the IQ has become full, causing a stall 1681system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1682system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations 1683system.cpu3.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly 1684system.cpu3.iew.predictedNotTakenIncorrect 1217 # Number of branches that were predicted not taken incorrectly 1685system.cpu3.iew.branchMispredicts 1726 # Number of branch mispredicts detected at execute 1686system.cpu3.iew.iewExecutedInsts 220807 # Number of executed instructions 1687system.cpu3.iew.iewExecLoadInsts 72290 # Number of load instructions executed 1688system.cpu3.iew.iewExecSquashedInsts 1307 # Number of squashed instructions skipped in execute 1689system.cpu3.iew.exec_swp 0 # number of swp insts executed 1690system.cpu3.iew.exec_nop 36810 # number of nop insts executed 1691system.cpu3.iew.exec_refs 105220 # number of memory reference insts executed 1692system.cpu3.iew.exec_branches 46242 # Number of branches executed 1693system.cpu3.iew.exec_stores 32930 # Number of stores executed 1694system.cpu3.iew.exec_rate 1.157694 # Inst execution rate 1695system.cpu3.iew.wb_sent 220376 # cumulative count of insts sent to commit 1696system.cpu3.iew.wb_count 220090 # cumulative count of insts written-back 1697system.cpu3.iew.wb_producers 122048 # num instructions producing a value 1698system.cpu3.iew.wb_consumers 126919 # num instructions consuming a value 1699system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1700system.cpu3.iew.wb_rate 1.153935 # insts written-back per cycle 1701system.cpu3.iew.wb_fanout 0.961621 # average fanout of values written-back 1702system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1703system.cpu3.commit.commitCommittedInsts 248929 # The number of committed instructions 1704system.cpu3.commit.commitCommittedOps 248929 # The number of committed instructions 1705system.cpu3.commit.commitSquashedInsts 14631 # The number of squashed insts skipped by commit 1706system.cpu3.commit.commitNonSpecStalls 7704 # The number of times commit has been forced to stall to communicate backwards 1707system.cpu3.commit.branchMispredicts 1563 # The number of times a branch was mispredicted 1708system.cpu3.commit.committed_per_cycle::samples 177833 # Number of insts commited each cycle 1709system.cpu3.commit.committed_per_cycle::mean 1.399791 # Number of insts commited each cycle 1710system.cpu3.commit.committed_per_cycle::stdev 1.928963 # Number of insts commited each cycle 1711system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1712system.cpu3.commit.committed_per_cycle::0 86250 48.50% 48.50% # Number of insts commited each cycle 1713system.cpu3.commit.committed_per_cycle::1 44177 24.84% 73.34% # Number of insts commited each cycle 1714system.cpu3.commit.committed_per_cycle::2 6214 3.49% 76.84% # Number of insts commited each cycle 1715system.cpu3.commit.committed_per_cycle::3 8561 4.81% 81.65% # Number of insts commited each cycle 1716system.cpu3.commit.committed_per_cycle::4 1535 0.86% 82.51% # Number of insts commited each cycle 1717system.cpu3.commit.committed_per_cycle::5 28697 16.14% 98.65% # Number of insts commited each cycle 1718system.cpu3.commit.committed_per_cycle::6 590 0.33% 98.98% # Number of insts commited each cycle 1719system.cpu3.commit.committed_per_cycle::7 996 0.56% 99.54% # Number of insts commited each cycle 1720system.cpu3.commit.committed_per_cycle::8 813 0.46% 100.00% # Number of insts commited each cycle 1721system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1722system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1723system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1724system.cpu3.commit.committed_per_cycle::total 177833 # Number of insts commited each cycle 1725system.cpu3.commit.committedInsts 248929 # Number of instructions committed 1726system.cpu3.commit.committedOps 248929 # Number of ops (including micro ops) committed 1727system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed 1728system.cpu3.commit.refs 102853 # Number of memory references committed 1729system.cpu3.commit.loads 70720 # Number of loads committed 1730system.cpu3.commit.membars 6986 # Number of memory barriers committed 1731system.cpu3.commit.branches 45078 # Number of branches committed 1732system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. 1733system.cpu3.commit.int_insts 170050 # Number of committed integer instructions. 1734system.cpu3.commit.function_calls 322 # Number of function calls committed. 1735system.cpu3.commit.bw_lim_events 813 # number cycles where commit BW limit reached 1736system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits 1737system.cpu3.rob.rob_reads 439993 # The number of ROB reads 1738system.cpu3.rob.rob_writes 529937 # The number of ROB writes 1739system.cpu3.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself 1740system.cpu3.idleCycles 3374 # Total number of cycles that the CPU has spent unscheduled due to idling 1741system.cpu3.quiesceCycles 37090 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1742system.cpu3.committedInsts 206079 # Number of Instructions Simulated 1743system.cpu3.committedOps 206079 # Number of Ops (including micro ops) Simulated 1744system.cpu3.committedInsts_total 206079 # Number of Instructions Simulated 1745system.cpu3.cpi 0.925519 # CPI: Cycles Per Instruction 1746system.cpu3.cpi_total 0.925519 # CPI: Total CPI of All Threads 1747system.cpu3.ipc 1.080475 # IPC: Instructions Per Cycle 1748system.cpu3.ipc_total 1.080475 # IPC: Total IPC of All Threads 1749system.cpu3.int_regfile_reads 375615 # number of integer regfile reads 1750system.cpu3.int_regfile_writes 175714 # number of integer regfile writes 1751system.cpu3.fp_regfile_writes 64 # number of floating regfile writes 1752system.cpu3.misc_regfile_reads 106918 # number of misc regfile reads 1753system.cpu3.misc_regfile_writes 646 # number of misc regfile writes 1754system.cpu3.icache.replacements 323 # number of replacements 1755system.cpu3.icache.tagsinuse 88.249587 # Cycle average of tags in use 1756system.cpu3.icache.total_refs 23982 # Total number of references to valid blocks. 1757system.cpu3.icache.sampled_refs 439 # Sample count of references to valid blocks. 1758system.cpu3.icache.avg_refs 54.628702 # Average number of references to valid blocks. 1759system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1760system.cpu3.icache.occ_blocks::cpu3.inst 88.249587 # Average occupied blocks per requestor 1761system.cpu3.icache.occ_percent::cpu3.inst 0.172362 # Average percentage of cache occupancy 1762system.cpu3.icache.occ_percent::total 0.172362 # Average percentage of cache occupancy 1763system.cpu3.icache.ReadReq_hits::cpu3.inst 23982 # number of ReadReq hits 1764system.cpu3.icache.ReadReq_hits::total 23982 # number of ReadReq hits 1765system.cpu3.icache.demand_hits::cpu3.inst 23982 # number of demand (read+write) hits 1766system.cpu3.icache.demand_hits::total 23982 # number of demand (read+write) hits 1767system.cpu3.icache.overall_hits::cpu3.inst 23982 # number of overall hits 1768system.cpu3.icache.overall_hits::total 23982 # number of overall hits 1769system.cpu3.icache.ReadReq_misses::cpu3.inst 503 # number of ReadReq misses 1770system.cpu3.icache.ReadReq_misses::total 503 # number of ReadReq misses 1771system.cpu3.icache.demand_misses::cpu3.inst 503 # number of demand (read+write) misses 1772system.cpu3.icache.demand_misses::total 503 # number of demand (read+write) misses 1773system.cpu3.icache.overall_misses::cpu3.inst 503 # number of overall misses 1774system.cpu3.icache.overall_misses::total 503 # number of overall misses 1775system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7707000 # number of ReadReq miss cycles 1776system.cpu3.icache.ReadReq_miss_latency::total 7707000 # number of ReadReq miss cycles 1777system.cpu3.icache.demand_miss_latency::cpu3.inst 7707000 # number of demand (read+write) miss cycles 1778system.cpu3.icache.demand_miss_latency::total 7707000 # number of demand (read+write) miss cycles 1779system.cpu3.icache.overall_miss_latency::cpu3.inst 7707000 # number of overall miss cycles 1780system.cpu3.icache.overall_miss_latency::total 7707000 # number of overall miss cycles 1781system.cpu3.icache.ReadReq_accesses::cpu3.inst 24485 # number of ReadReq accesses(hits+misses) 1782system.cpu3.icache.ReadReq_accesses::total 24485 # number of ReadReq accesses(hits+misses) 1783system.cpu3.icache.demand_accesses::cpu3.inst 24485 # number of demand (read+write) accesses 1784system.cpu3.icache.demand_accesses::total 24485 # number of demand (read+write) accesses 1785system.cpu3.icache.overall_accesses::cpu3.inst 24485 # number of overall (read+write) accesses 1786system.cpu3.icache.overall_accesses::total 24485 # number of overall (read+write) accesses 1787system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020543 # miss rate for ReadReq accesses 1788system.cpu3.icache.ReadReq_miss_rate::total 0.020543 # miss rate for ReadReq accesses 1789system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020543 # miss rate for demand accesses 1790system.cpu3.icache.demand_miss_rate::total 0.020543 # miss rate for demand accesses 1791system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020543 # miss rate for overall accesses 1792system.cpu3.icache.overall_miss_rate::total 0.020543 # miss rate for overall accesses 1793system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15322.067594 # average ReadReq miss latency 1794system.cpu3.icache.ReadReq_avg_miss_latency::total 15322.067594 # average ReadReq miss latency 1795system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15322.067594 # average overall miss latency 1796system.cpu3.icache.demand_avg_miss_latency::total 15322.067594 # average overall miss latency 1797system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15322.067594 # average overall miss latency 1798system.cpu3.icache.overall_avg_miss_latency::total 15322.067594 # average overall miss latency 1799system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1800system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1801system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1802system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1803system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1804system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1805system.cpu3.icache.fast_writes 0 # number of fast writes performed 1806system.cpu3.icache.cache_copies 0 # number of cache copies performed 1807system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 64 # number of ReadReq MSHR hits 1808system.cpu3.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits 1809system.cpu3.icache.demand_mshr_hits::cpu3.inst 64 # number of demand (read+write) MSHR hits 1810system.cpu3.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits 1811system.cpu3.icache.overall_mshr_hits::cpu3.inst 64 # number of overall MSHR hits 1812system.cpu3.icache.overall_mshr_hits::total 64 # number of overall MSHR hits 1813system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 439 # number of ReadReq MSHR misses 1814system.cpu3.icache.ReadReq_mshr_misses::total 439 # number of ReadReq MSHR misses 1815system.cpu3.icache.demand_mshr_misses::cpu3.inst 439 # number of demand (read+write) MSHR misses 1816system.cpu3.icache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses 1817system.cpu3.icache.overall_mshr_misses::cpu3.inst 439 # number of overall MSHR misses 1818system.cpu3.icache.overall_mshr_misses::total 439 # number of overall MSHR misses 1819system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5684000 # number of ReadReq MSHR miss cycles 1820system.cpu3.icache.ReadReq_mshr_miss_latency::total 5684000 # number of ReadReq MSHR miss cycles 1821system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5684000 # number of demand (read+write) MSHR miss cycles 1822system.cpu3.icache.demand_mshr_miss_latency::total 5684000 # number of demand (read+write) MSHR miss cycles 1823system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5684000 # number of overall MSHR miss cycles 1824system.cpu3.icache.overall_mshr_miss_latency::total 5684000 # number of overall MSHR miss cycles 1825system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017929 # mshr miss rate for ReadReq accesses 1826system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017929 # mshr miss rate for ReadReq accesses 1827system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017929 # mshr miss rate for demand accesses 1828system.cpu3.icache.demand_mshr_miss_rate::total 0.017929 # mshr miss rate for demand accesses 1829system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017929 # mshr miss rate for overall accesses 1830system.cpu3.icache.overall_mshr_miss_rate::total 0.017929 # mshr miss rate for overall accesses 1831system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12947.608200 # average ReadReq mshr miss latency 1832system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12947.608200 # average ReadReq mshr miss latency 1833system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12947.608200 # average overall mshr miss latency 1834system.cpu3.icache.demand_avg_mshr_miss_latency::total 12947.608200 # average overall mshr miss latency 1835system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12947.608200 # average overall mshr miss latency 1836system.cpu3.icache.overall_avg_mshr_miss_latency::total 12947.608200 # average overall mshr miss latency 1837system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1838system.cpu3.dcache.replacements 0 # number of replacements 1839system.cpu3.dcache.tagsinuse 26.048284 # Cycle average of tags in use 1840system.cpu3.dcache.total_refs 38388 # Total number of references to valid blocks. 1841system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. 1842system.cpu3.dcache.avg_refs 1323.724138 # Average number of references to valid blocks. 1843system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1844system.cpu3.dcache.occ_blocks::cpu3.data 26.048284 # Average occupied blocks per requestor 1845system.cpu3.dcache.occ_percent::cpu3.data 0.050876 # Average percentage of cache occupancy 1846system.cpu3.dcache.occ_percent::total 0.050876 # Average percentage of cache occupancy 1847system.cpu3.dcache.ReadReq_hits::cpu3.data 43625 # number of ReadReq hits 1848system.cpu3.dcache.ReadReq_hits::total 43625 # number of ReadReq hits 1849system.cpu3.dcache.WriteReq_hits::cpu3.data 31927 # number of WriteReq hits 1850system.cpu3.dcache.WriteReq_hits::total 31927 # number of WriteReq hits 1851system.cpu3.dcache.SwapReq_hits::cpu3.data 16 # number of SwapReq hits 1852system.cpu3.dcache.SwapReq_hits::total 16 # number of SwapReq hits 1853system.cpu3.dcache.demand_hits::cpu3.data 75552 # number of demand (read+write) hits 1854system.cpu3.dcache.demand_hits::total 75552 # number of demand (read+write) hits 1855system.cpu3.dcache.overall_hits::cpu3.data 75552 # number of overall hits 1856system.cpu3.dcache.overall_hits::total 75552 # number of overall hits 1857system.cpu3.dcache.ReadReq_misses::cpu3.data 356 # number of ReadReq misses 1858system.cpu3.dcache.ReadReq_misses::total 356 # number of ReadReq misses 1859system.cpu3.dcache.WriteReq_misses::cpu3.data 134 # number of WriteReq misses 1860system.cpu3.dcache.WriteReq_misses::total 134 # number of WriteReq misses 1861system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses 1862system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses 1863system.cpu3.dcache.demand_misses::cpu3.data 490 # number of demand (read+write) misses 1864system.cpu3.dcache.demand_misses::total 490 # number of demand (read+write) misses 1865system.cpu3.dcache.overall_misses::cpu3.data 490 # number of overall misses 1866system.cpu3.dcache.overall_misses::total 490 # number of overall misses 1867system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9997000 # number of ReadReq miss cycles 1868system.cpu3.dcache.ReadReq_miss_latency::total 9997000 # number of ReadReq miss cycles 1869system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3151500 # number of WriteReq miss cycles 1870system.cpu3.dcache.WriteReq_miss_latency::total 3151500 # number of WriteReq miss cycles 1871system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1323000 # number of SwapReq miss cycles 1872system.cpu3.dcache.SwapReq_miss_latency::total 1323000 # number of SwapReq miss cycles 1873system.cpu3.dcache.demand_miss_latency::cpu3.data 13148500 # number of demand (read+write) miss cycles 1874system.cpu3.dcache.demand_miss_latency::total 13148500 # number of demand (read+write) miss cycles 1875system.cpu3.dcache.overall_miss_latency::cpu3.data 13148500 # number of overall miss cycles 1876system.cpu3.dcache.overall_miss_latency::total 13148500 # number of overall miss cycles 1877system.cpu3.dcache.ReadReq_accesses::cpu3.data 43981 # number of ReadReq accesses(hits+misses) 1878system.cpu3.dcache.ReadReq_accesses::total 43981 # number of ReadReq accesses(hits+misses) 1879system.cpu3.dcache.WriteReq_accesses::cpu3.data 32061 # number of WriteReq accesses(hits+misses) 1880system.cpu3.dcache.WriteReq_accesses::total 32061 # number of WriteReq accesses(hits+misses) 1881system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) 1882system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) 1883system.cpu3.dcache.demand_accesses::cpu3.data 76042 # number of demand (read+write) accesses 1884system.cpu3.dcache.demand_accesses::total 76042 # number of demand (read+write) accesses 1885system.cpu3.dcache.overall_accesses::cpu3.data 76042 # number of overall (read+write) accesses 1886system.cpu3.dcache.overall_accesses::total 76042 # number of overall (read+write) accesses 1887system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008094 # miss rate for ReadReq accesses 1888system.cpu3.dcache.ReadReq_miss_rate::total 0.008094 # miss rate for ReadReq accesses 1889system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004180 # miss rate for WriteReq accesses 1890system.cpu3.dcache.WriteReq_miss_rate::total 0.004180 # miss rate for WriteReq accesses 1891system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.777778 # miss rate for SwapReq accesses 1892system.cpu3.dcache.SwapReq_miss_rate::total 0.777778 # miss rate for SwapReq accesses 1893system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006444 # miss rate for demand accesses 1894system.cpu3.dcache.demand_miss_rate::total 0.006444 # miss rate for demand accesses 1895system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006444 # miss rate for overall accesses 1896system.cpu3.dcache.overall_miss_rate::total 0.006444 # miss rate for overall accesses 1897system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 28081.460674 # average ReadReq miss latency 1898system.cpu3.dcache.ReadReq_avg_miss_latency::total 28081.460674 # average ReadReq miss latency 1899system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23518.656716 # average WriteReq miss latency 1900system.cpu3.dcache.WriteReq_avg_miss_latency::total 23518.656716 # average WriteReq miss latency 1901system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 23625 # average SwapReq miss latency 1902system.cpu3.dcache.SwapReq_avg_miss_latency::total 23625 # average SwapReq miss latency 1903system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 26833.673469 # average overall miss latency 1904system.cpu3.dcache.demand_avg_miss_latency::total 26833.673469 # average overall miss latency 1905system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 26833.673469 # average overall miss latency 1906system.cpu3.dcache.overall_avg_miss_latency::total 26833.673469 # average overall miss latency 1907system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1908system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1909system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1910system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 1911system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1912system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1913system.cpu3.dcache.fast_writes 0 # number of fast writes performed 1914system.cpu3.dcache.cache_copies 0 # number of cache copies performed 1915system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 195 # number of ReadReq MSHR hits 1916system.cpu3.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits 1917system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits 1918system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits 1919system.cpu3.dcache.demand_mshr_hits::cpu3.data 227 # number of demand (read+write) MSHR hits 1920system.cpu3.dcache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits 1921system.cpu3.dcache.overall_mshr_hits::cpu3.data 227 # number of overall MSHR hits 1922system.cpu3.dcache.overall_mshr_hits::total 227 # number of overall MSHR hits 1923system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses 1924system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses 1925system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 102 # number of WriteReq MSHR misses 1926system.cpu3.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses 1927system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses 1928system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 1929system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses 1930system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses 1931system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses 1932system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses 1933system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2771504 # number of ReadReq MSHR miss cycles 1934system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2771504 # number of ReadReq MSHR miss cycles 1935system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1583000 # number of WriteReq MSHR miss cycles 1936system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1583000 # number of WriteReq MSHR miss cycles 1937system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1148500 # number of SwapReq MSHR miss cycles 1938system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1148500 # number of SwapReq MSHR miss cycles 1939system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4354504 # number of demand (read+write) MSHR miss cycles 1940system.cpu3.dcache.demand_mshr_miss_latency::total 4354504 # number of demand (read+write) MSHR miss cycles 1941system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4354504 # number of overall MSHR miss cycles 1942system.cpu3.dcache.overall_mshr_miss_latency::total 4354504 # number of overall MSHR miss cycles 1943system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003661 # mshr miss rate for ReadReq accesses 1944system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003661 # mshr miss rate for ReadReq accesses 1945system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003181 # mshr miss rate for WriteReq accesses 1946system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003181 # mshr miss rate for WriteReq accesses 1947system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.777778 # mshr miss rate for SwapReq accesses 1948system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.777778 # mshr miss rate for SwapReq accesses 1949system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003459 # mshr miss rate for demand accesses 1950system.cpu3.dcache.demand_mshr_miss_rate::total 0.003459 # mshr miss rate for demand accesses 1951system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003459 # mshr miss rate for overall accesses 1952system.cpu3.dcache.overall_mshr_miss_rate::total 0.003459 # mshr miss rate for overall accesses 1953system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17214.310559 # average ReadReq mshr miss latency 1954system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 17214.310559 # average ReadReq mshr miss latency 1955system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15519.607843 # average WriteReq mshr miss latency 1956system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15519.607843 # average WriteReq mshr miss latency 1957system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 20508.928571 # average SwapReq mshr miss latency 1958system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 20508.928571 # average SwapReq mshr miss latency 1959system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16557.049430 # average overall mshr miss latency 1960system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16557.049430 # average overall mshr miss latency 1961system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16557.049430 # average overall mshr miss latency 1962system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16557.049430 # average overall mshr miss latency 1963system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1964system.l2c.replacements 0 # number of replacements 1965system.l2c.tagsinuse 436.337885 # Cycle average of tags in use 1966system.l2c.total_refs 1474 # Total number of references to valid blocks. 1967system.l2c.sampled_refs 537 # Sample count of references to valid blocks. 1968system.l2c.avg_refs 2.744879 # Average number of references to valid blocks. 1969system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1970system.l2c.occ_blocks::writebacks 0.838584 # Average occupied blocks per requestor 1971system.l2c.occ_blocks::cpu0.inst 294.109117 # Average occupied blocks per requestor 1972system.l2c.occ_blocks::cpu0.data 59.534191 # Average occupied blocks per requestor 1973system.l2c.occ_blocks::cpu1.inst 68.191567 # Average occupied blocks per requestor 1974system.l2c.occ_blocks::cpu1.data 5.703860 # Average occupied blocks per requestor 1975system.l2c.occ_blocks::cpu2.inst 2.346215 # Average occupied blocks per requestor 1976system.l2c.occ_blocks::cpu2.data 0.730565 # Average occupied blocks per requestor 1977system.l2c.occ_blocks::cpu3.inst 4.110047 # Average occupied blocks per requestor 1978system.l2c.occ_blocks::cpu3.data 0.773739 # Average occupied blocks per requestor 1979system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy 1980system.l2c.occ_percent::cpu0.inst 0.004488 # Average percentage of cache occupancy 1981system.l2c.occ_percent::cpu0.data 0.000908 # Average percentage of cache occupancy 1982system.l2c.occ_percent::cpu1.inst 0.001041 # Average percentage of cache occupancy 1983system.l2c.occ_percent::cpu1.data 0.000087 # Average percentage of cache occupancy 1984system.l2c.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy 1985system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy 1986system.l2c.occ_percent::cpu3.inst 0.000063 # Average percentage of cache occupancy 1987system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy 1988system.l2c.occ_percent::total 0.006658 # Average percentage of cache occupancy 1989system.l2c.ReadReq_hits::cpu0.inst 233 # number of ReadReq hits 1990system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 1991system.l2c.ReadReq_hits::cpu1.inst 350 # number of ReadReq hits 1992system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits 1993system.l2c.ReadReq_hits::cpu2.inst 428 # number of ReadReq hits 1994system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits 1995system.l2c.ReadReq_hits::cpu3.inst 431 # number of ReadReq hits 1996system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits 1997system.l2c.ReadReq_hits::total 1474 # number of ReadReq hits 1998system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 1999system.l2c.Writeback_hits::total 1 # number of Writeback hits 2000system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 2001system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 2002system.l2c.demand_hits::cpu0.inst 233 # number of demand (read+write) hits 2003system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 2004system.l2c.demand_hits::cpu1.inst 350 # number of demand (read+write) hits 2005system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits 2006system.l2c.demand_hits::cpu2.inst 428 # number of demand (read+write) hits 2007system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits 2008system.l2c.demand_hits::cpu3.inst 431 # number of demand (read+write) hits 2009system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 2010system.l2c.demand_hits::total 1474 # number of demand (read+write) hits 2011system.l2c.overall_hits::cpu0.inst 233 # number of overall hits 2012system.l2c.overall_hits::cpu0.data 5 # number of overall hits 2013system.l2c.overall_hits::cpu1.inst 350 # number of overall hits 2014system.l2c.overall_hits::cpu1.data 5 # number of overall hits 2015system.l2c.overall_hits::cpu2.inst 428 # number of overall hits 2016system.l2c.overall_hits::cpu2.data 11 # number of overall hits 2017system.l2c.overall_hits::cpu3.inst 431 # number of overall hits 2018system.l2c.overall_hits::cpu3.data 11 # number of overall hits 2019system.l2c.overall_hits::total 1474 # number of overall hits 2020system.l2c.ReadReq_misses::cpu0.inst 362 # number of ReadReq misses 2021system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses 2022system.l2c.ReadReq_misses::cpu1.inst 86 # number of ReadReq misses 2023system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses 2024system.l2c.ReadReq_misses::cpu2.inst 10 # number of ReadReq misses 2025system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses 2026system.l2c.ReadReq_misses::cpu3.inst 8 # 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number of UpgradeReq accesses(hits+misses) 2102system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses) 2103system.l2c.UpgradeReq_accesses::cpu3.data 15 # number of UpgradeReq accesses(hits+misses) 2104system.l2c.UpgradeReq_accesses::total 80 # number of UpgradeReq accesses(hits+misses) 2105system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 2106system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 2107system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 2108system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 2109system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) 2110system.l2c.demand_accesses::cpu0.inst 595 # number of demand (read+write) accesses 2111system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses 2112system.l2c.demand_accesses::cpu1.inst 436 # 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number of ReadReq MSHR miss cycles 2258system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 200000 # number of ReadReq MSHR miss cycles 2259system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles 2260system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 240000 # number of ReadReq MSHR miss cycles 2261system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles 2262system.l2c.ReadReq_mshr_miss_latency::total 22307500 # number of ReadReq MSHR miss cycles 2263system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 800000 # number of UpgradeReq MSHR miss cycles 2264system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 840000 # number of UpgradeReq MSHR miss cycles 2265system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 844000 # number of UpgradeReq MSHR miss cycles 2266system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 605000 # number of UpgradeReq MSHR miss cycles 2267system.l2c.UpgradeReq_mshr_miss_latency::total 3089000 # number of UpgradeReq MSHR miss cycles 2268system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4012500 # number of ReadExReq MSHR miss cycles 2269system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 593500 # number of ReadExReq MSHR miss cycles 2270system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 516500 # number of ReadExReq MSHR miss cycles 2271system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 511500 # number of ReadExReq MSHR miss cycles 2272system.l2c.ReadExReq_mshr_miss_latency::total 5634000 # number of ReadExReq MSHR miss cycles 2273system.l2c.demand_mshr_miss_latency::cpu0.inst 14801500 # number of demand (read+write) MSHR miss cycles 2274system.l2c.demand_mshr_miss_latency::cpu0.data 7286500 # number of demand (read+write) MSHR miss cycles 2275system.l2c.demand_mshr_miss_latency::cpu1.inst 3420500 # number of demand (read+write) MSHR miss cycles 2276system.l2c.demand_mshr_miss_latency::cpu1.data 885000 # number of demand (read+write) MSHR miss cycles 2277system.l2c.demand_mshr_miss_latency::cpu2.inst 200000 # number of demand (read+write) MSHR miss cycles 2278system.l2c.demand_mshr_miss_latency::cpu2.data 556500 # number of demand (read+write) MSHR miss cycles 2279system.l2c.demand_mshr_miss_latency::cpu3.inst 240000 # number of demand (read+write) MSHR miss cycles 2280system.l2c.demand_mshr_miss_latency::cpu3.data 551500 # number of demand (read+write) MSHR miss cycles 2281system.l2c.demand_mshr_miss_latency::total 27941500 # number of demand (read+write) MSHR miss cycles 2282system.l2c.overall_mshr_miss_latency::cpu0.inst 14801500 # number of overall MSHR miss cycles 2283system.l2c.overall_mshr_miss_latency::cpu0.data 7286500 # number of overall MSHR miss cycles 2284system.l2c.overall_mshr_miss_latency::cpu1.inst 3420500 # number of overall MSHR miss cycles 2285system.l2c.overall_mshr_miss_latency::cpu1.data 885000 # number of overall MSHR miss cycles 2286system.l2c.overall_mshr_miss_latency::cpu2.inst 200000 # number of overall MSHR miss cycles 2287system.l2c.overall_mshr_miss_latency::cpu2.data 556500 # number of overall MSHR miss cycles 2288system.l2c.overall_mshr_miss_latency::cpu3.inst 240000 # number of overall MSHR miss cycles 2289system.l2c.overall_mshr_miss_latency::cpu3.data 551500 # number of overall MSHR miss cycles 2290system.l2c.overall_mshr_miss_latency::total 27941500 # number of overall MSHR miss cycles 2291system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.608403 # mshr miss rate for ReadReq accesses 2292system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses 2293system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for ReadReq accesses 2294system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses 2295system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for ReadReq accesses 2296system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses 2297system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for ReadReq accesses 2298system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses 2299system.l2c.ReadReq_mshr_miss_rate::total 0.266930 # mshr miss rate for ReadReq accesses 2300system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.869565 # mshr miss rate for UpgradeReq accesses 2301system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2302system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 2303system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 2304system.l2c.UpgradeReq_mshr_miss_rate::total 0.962500 # mshr miss rate for UpgradeReq accesses 2305system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 2306system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 2307system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 2308system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 2309system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 2310system.l2c.demand_mshr_miss_rate::cpu0.inst 0.608403 # mshr miss rate for demand accesses 2311system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses 2312system.l2c.demand_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for demand accesses 2313system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses 2314system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for demand accesses 2315system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses 2316system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for demand accesses 2317system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses 2318system.l2c.demand_mshr_miss_rate::total 0.311513 # mshr miss rate for demand accesses 2319system.l2c.overall_mshr_miss_rate::cpu0.inst 0.608403 # mshr miss rate for overall accesses 2320system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses 2321system.l2c.overall_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for overall accesses 2322system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses 2323system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for overall accesses 2324system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses 2325system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for overall accesses 2326system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 2327system.l2c.overall_mshr_miss_rate::total 0.311513 # mshr miss rate for overall accesses 2328system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40888.121547 # average ReadReq mshr miss latency 2329system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44243.243243 # average ReadReq mshr miss latency 2330system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40720.238095 # average ReadReq mshr miss latency 2331system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41642.857143 # average ReadReq mshr miss latency 2332system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency 2333system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency 2334system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency 2335system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency 2336system.l2c.ReadReq_avg_mshr_miss_latency::total 41310.185185 # average ReadReq mshr miss latency 2337system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency 2338system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency 2339system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40190.476190 # average UpgradeReq mshr miss latency 2340system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40333.333333 # average UpgradeReq mshr miss latency 2341system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40116.883117 # average UpgradeReq mshr miss latency 2342system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42686.170213 # average ReadExReq mshr miss latency 2343system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 45653.846154 # average ReadExReq mshr miss latency 2344system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43041.666667 # average ReadExReq mshr miss latency 2345system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42625 # average ReadExReq mshr miss latency 2346system.l2c.ReadExReq_avg_mshr_miss_latency::total 43007.633588 # average ReadExReq mshr miss latency 2347system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40888.121547 # average overall mshr miss latency 2348system.l2c.demand_avg_mshr_miss_latency::cpu0.data 43372.023810 # average overall mshr miss latency 2349system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40720.238095 # average overall mshr miss latency 2350system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency 2351system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency 2352system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency 2353system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 2354system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency 2355system.l2c.demand_avg_mshr_miss_latency::total 41641.579732 # average overall mshr miss latency 2356system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40888.121547 # average overall mshr miss latency 2357system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43372.023810 # average overall mshr miss latency 2358system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40720.238095 # average overall mshr miss latency 2359system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency 2360system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency 2361system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency 2362system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 2363system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency 2364system.l2c.overall_avg_mshr_miss_latency::total 41641.579732 # average overall mshr miss latency 2365system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2366 2367---------- End Simulation Statistics ---------- 2368