xref: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000126                       # Number of seconds simulated
sim_ticks                                   125889000                       # Number of ticks simulated
final_tick                                  125889000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 196054                       # Simulator instruction rate (inst/s)
host_op_rate                                   196054                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               21072637                       # Simulator tick rate (ticks/s)
host_mem_usage                                 267156                       # Number of bytes of host memory used
host_seconds                                     5.97                       # Real time elapsed on the host
sim_insts                                     1171234                       # Number of instructions simulated
sim_ops                                       1171234                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst            24000                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst             1536                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data              896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst             5824                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data             1344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              960                       # Number of bytes read from this memory
system.physmem.bytes_read::total                45696                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        24000                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst         1536                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst         5824                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          256                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           31616                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               375                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               170                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                24                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                14                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                91                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                21                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                 4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   714                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst           190644139                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            86425343                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst            12201225                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             7117381                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst            46262978                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data            10676072                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             2033537                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             7625766                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               362986440                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst      190644139                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst       12201225                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst       46262978                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        2033537                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          251141879                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst          190644139                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           86425343                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst           12201225                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            7117381                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst           46262978                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data           10676072                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            2033537                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            7625766                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              362986440                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           714                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         714                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    45696                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     45696                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 120                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  45                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  34                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  62                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  68                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  28                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  19                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  28                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   7                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  31                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 23                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 13                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 69                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 47                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 19                       # Per bank write bursts
system.physmem.perBankRdBursts::15                101                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                       125655000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     714                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       431                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       209                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        54                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        16                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          181                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      245.392265                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     162.885057                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     238.848920                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             70     38.67%     38.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           41     22.65%     61.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           29     16.02%     77.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           15      8.29%     85.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            9      4.97%     90.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            7      3.87%     94.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            3      1.66%     96.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            2      1.10%     97.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            5      2.76%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            181                       # Bytes accessed per row activation
system.physmem.totQLat                        8022250                       # Total ticks spent queuing
system.physmem.totMemAccLat                  21409750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      3570000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11235.64                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29985.64                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         362.99                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      362.99                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.84                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.84                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.25                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        529                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.09                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                       175987.39                       # Average gap between requests
system.physmem.pageHitRate                      74.09                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     914760                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                     499125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                   3088800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy                8136960                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy               61236810                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy               21187500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy                 95063955                       # Total energy per rank (pJ)
system.physmem_0.averagePower              761.486343                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE       34878500                       # Time in different power states
system.physmem_0.memoryStateTime::REF         4160000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT        85815250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                     453600                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                     247500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                   2324400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy                8136960                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy               43234785                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy               36978750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy                 91375995                       # Total energy per rank (pJ)
system.physmem_1.averagePower              731.944849                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE       61171750                       # Time in different power states
system.physmem_1.memoryStateTime::REF         4160000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT        59522000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu0.branchPred.lookups                  99978                       # Number of BP lookups
system.cpu0.branchPred.condPredicted            95393                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect             1592                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups               97255                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                   1133                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect               128                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups          97255                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits             89772                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses            7483                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted         1066                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          251779                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles             22796                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        589750                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      99978                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             90905                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       197463                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   3483                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                        64                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         2183                       # Number of stall cycles due to pending traps
system.cpu0.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                     8051                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  854                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples            224259                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.629772                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.263592                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   34588     15.42%     15.42% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   92788     41.38%     56.80% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     690      0.31%     57.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                    1001      0.45%     57.55% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     509      0.23%     57.78% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   88318     39.38%     97.16% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     733      0.33%     97.49% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     501      0.22%     97.71% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    5131      2.29%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              224259                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.397086                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.342332                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   17767                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                19916                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   184006                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  829                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  1741                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                571897                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  1741                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   18447                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                   2370                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         16226                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   184143                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                 1332                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                566816                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                    11                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                    11                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents                   855                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands             387804                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups              1129387                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups          853087                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups                2                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps               368443                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   19361                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts              1077                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts          1101                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     5304                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              180818                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              91318                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            88191                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           87908                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    472586                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded               1109                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   468485                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued              119                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined          16710                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined        13548                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           550                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       224259                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.089035                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.110026                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              37572     16.75%     16.75% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               4453      1.99%     18.74% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              89499     39.91%     58.65% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              89119     39.74%     98.39% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1731      0.77%     99.16% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                984      0.44%     99.60% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                574      0.26%     99.85% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                227      0.10%     99.96% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                100      0.04%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         224259                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                    140     42.68%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     42.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                    69     21.04%     63.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  119     36.28%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               197740     42.21%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.21% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              180204     38.47%     80.67% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              90541     19.33%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                468485                       # Type of FU issued
system.cpu0.iq.rate                          1.860699                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        328                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000700                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads           1161676                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           490453                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       465867                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 4                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                468813                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           87651                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         3007                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            8                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           54                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1906                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked           11                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  1741                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                   2371                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   27                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             562514                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              182                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               180818                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               91318                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               990                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    27                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            54                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           236                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect         1703                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1939                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               466997                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               179835                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts             1488                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        88819                       # number of nop insts executed
system.cpu0.iew.exec_refs                      270170                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   92803                       # Number of branches executed
system.cpu0.iew.exec_stores                     90335                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.854789                       # Inst execution rate
system.cpu0.iew.wb_sent                        466340                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       465867                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   276291                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   279830                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      1.850301                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.987353                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts          17414                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1592                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       220844                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.467878                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.142709                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        37532     16.99%     16.99% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        91545     41.45%     58.45% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         2011      0.91%     59.36% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          623      0.28%     59.64% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          506      0.23%     59.87% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        87423     39.59%     99.45% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          455      0.21%     99.66% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          281      0.13%     99.79% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          468      0.21%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       220844                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              545016                       # Number of instructions committed
system.cpu0.commit.committedOps                545016                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        267223                       # Number of memory references committed
system.cpu0.commit.loads                       177811                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     91299                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   366774                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass        88031     16.15%     16.15% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu          189678     34.80%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult              0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     50.95% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead         177895     32.64%     83.59% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite         89412     16.41%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total           545016                       # Class of committed instruction
system.cpu0.commit.bw_lim_events                  468                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                      781645                       # The number of ROB reads
system.cpu0.rob.rob_writes                    1128336                       # The number of ROB writes
system.cpu0.timesIdled                            327                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          27520                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     456901                       # Number of Instructions Simulated
system.cpu0.committedOps                       456901                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              0.551058                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.551058                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.814691                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.814691                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  834795                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 376287                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 272308                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements                2                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          143.015419                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs             180238                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs              172                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs          1047.895349                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   143.015419                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.279327                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.279327                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          170                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          143                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.332031                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses           726286                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses          726286                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data        91504                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          91504                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        88818                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         88818                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           19                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             19                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       180322                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          180322                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       180322                       # number of overall hits
system.cpu0.dcache.overall_hits::total         180322                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          576                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          576                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          552                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          552                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           23                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           23                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data         1128                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total          1128                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data         1128                       # number of overall misses
system.cpu0.dcache.overall_misses::total         1128                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     18232000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     18232000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     36205990                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     36205990                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       589500                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       589500                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     54437990                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     54437990                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     54437990                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     54437990                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        92080                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        92080                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        89370                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        89370                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       181450                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       181450                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       181450                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       181450                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006255                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.006255                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006177                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.006177                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.547619                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.547619                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006217                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.006217                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006217                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.006217                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31652.777778                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 31652.777778                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65590.561594                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 65590.561594                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 25630.434783                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 25630.434783                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48260.629433                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 48260.629433                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48260.629433                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 48260.629433                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs          818                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               22                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    37.181818                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          380                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          380                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          386                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          386                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          766                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          766                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          766                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          766                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          196                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          196                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          166                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          166                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           23                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           23                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          362                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          362                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          362                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          362                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      7598500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      7598500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8576000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8576000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       566500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       566500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     16174500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     16174500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     16174500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     16174500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002129                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002129                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.001857                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.001857                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.547619                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.547619                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.001995                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.001995                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.001995                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.001995                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 38767.857143                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 38767.857143                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 51662.650602                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 51662.650602                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 24630.434783                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 24630.434783                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 44680.939227                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 44680.939227                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 44680.939227                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 44680.939227                       # average overall mshr miss latency
system.cpu0.icache.tags.replacements              403                       # number of replacements
system.cpu0.icache.tags.tagsinuse          251.059263                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs               7130                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs              705                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            10.113475                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   251.059263                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.490350                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.490350                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          302                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          193                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.589844                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses             8756                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses            8756                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst         7130                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           7130                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         7130                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            7130                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         7130                       # number of overall hits
system.cpu0.icache.overall_hits::total           7130                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          921                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          921                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          921                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           921                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          921                       # number of overall misses
system.cpu0.icache.overall_misses::total          921                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     43922000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     43922000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     43922000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     43922000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     43922000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     43922000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         8051                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         8051                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         8051                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         8051                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         8051                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         8051                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.114396                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.114396                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.114396                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.114396                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.114396                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.114396                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47689.467970                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 47689.467970                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47689.467970                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 47689.467970                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47689.467970                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 47689.467970                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs          113                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                4                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    28.250000                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks          403                       # number of writebacks
system.cpu0.icache.writebacks::total              403                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          215                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          215                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          215                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          215                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          215                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          215                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          706                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          706                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          706                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          706                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          706                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          706                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     33748500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     33748500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     33748500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     33748500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     33748500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     33748500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.087691                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.087691                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.087691                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.087691                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.087691                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.087691                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47802.407932                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47802.407932                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47802.407932                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 47802.407932                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47802.407932                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 47802.407932                       # average overall mshr miss latency
system.cpu1.branchPred.lookups                  75929                       # Number of BP lookups
system.cpu1.branchPred.condPredicted            68631                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect             2222                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups               68395                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                   1839                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups          68395                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits             58396                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses            9999                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted         1194                       # Number of mispredicted indirect branches.
system.cpu1.numCycles                          196540                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles             32617                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        424540                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      75929                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             60235                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                       157282                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   4599                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles         1756                       # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines                    22091                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  889                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            193967                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             2.188723                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.372433                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   56525     29.14%     29.14% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   66630     34.35%     63.49% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    5516      2.84%     66.34% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3688      1.90%     68.24% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     688      0.35%     68.59% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   50225     25.89%     94.49% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    1136      0.59%     95.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                    1351      0.70%     95.77% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    8208      4.23%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              193967                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.386328                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       2.160069                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   20990                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                50963                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                   116406                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 3299                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  2299                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                394135                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  2299                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   22042                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  22361                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         14616                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                   117990                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                14649                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                387817                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                 13215                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                    19                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.RenamedOperands             272713                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               753683                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          582463                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups               32                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps               245854                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                   26859                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1602                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1739                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                    20098                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads              111716                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              54519                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            52739                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           48254                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    321016                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               5993                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   319557                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued               54                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined          23622                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined        18296                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved          1159                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       193967                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.647481                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.362491                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              60994     31.45%     31.45% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              19742     10.18%     41.62% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              53241     27.45%     69.07% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              52847     27.25%     96.32% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3638      1.88%     98.19% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1763      0.91%     99.10% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6               1052      0.54%     99.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                407      0.21%     99.85% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                283      0.15%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         193967                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                    169     37.31%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     37.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    58     12.80%     50.11% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  226     49.89%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               151236     47.33%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.33% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead              114807     35.93%     83.25% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              53514     16.75%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                319557                       # Type of FU issued
system.cpu1.iq.rate                          1.625913                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        453                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001418                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            833588                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           350606                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       315974                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                64                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                320010                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           48132                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         4290                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses           32                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           39                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores         2608                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  2299                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                   7227                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   50                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             380950                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              338                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts               111716                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               54519                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1500                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            39                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           429                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect         2382                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                2811                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               317250                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts               110168                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts             2307                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        53941                       # number of nop insts executed
system.cpu1.iew.exec_refs                      163396                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   64160                       # Number of branches executed
system.cpu1.iew.exec_stores                     53228                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.614175                       # Inst execution rate
system.cpu1.iew.wb_sent                        316458                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       315974                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   181395                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   189019                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      1.607683                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.959665                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts          24733                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           4834                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             2222                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       189334                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.881189                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     2.115429                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        65341     34.51%     34.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        60499     31.95%     66.46% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         5361      2.83%     69.30% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         5469      2.89%     72.18% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1297      0.69%     72.87% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        48347     25.54%     98.40% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          750      0.40%     98.80% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7         1038      0.55%     99.35% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8         1232      0.65%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       189334                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              356173                       # Number of instructions committed
system.cpu1.commit.committedOps                356173                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        159337                       # Number of memory references committed
system.cpu1.commit.loads                       107426                       # Number of loads committed
system.cpu1.commit.membars                       4118                       # Number of memory barriers committed
system.cpu1.commit.branches                     61998                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   243452                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass        52786     14.82%     14.82% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu          139932     39.29%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult              0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     54.11% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead         111544     31.32%     85.43% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite         51911     14.57%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total           356173                       # Class of committed instruction
system.cpu1.commit.bw_lim_events                 1232                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                      568422                       # The number of ROB reads
system.cpu1.rob.rob_writes                     766486                       # The number of ROB writes
system.cpu1.timesIdled                            207                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           2573                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       46533                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     299269                       # Number of Instructions Simulated
system.cpu1.committedOps                       299269                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              0.656734                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.656734                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.522687                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.522687                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  554283                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 257020                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 165298                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu1.dcache.tags.replacements                0                       # number of replacements
system.cpu1.dcache.tags.tagsinuse           25.915239                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs              58936                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs          2032.275862                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data    25.915239                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.050616                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.050616                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses           455882                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses          455882                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data        61472                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          61472                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        51691                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         51691                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           10                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             10                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data       113163                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total          113163                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data       113163                       # number of overall hits
system.cpu1.dcache.overall_hits::total         113163                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          523                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          523                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          150                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          150                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           60                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           60                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          673                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           673                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          673                       # number of overall misses
system.cpu1.dcache.overall_misses::total          673                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      8464500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      8464500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2960500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      2960500                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       828000                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       828000                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data     11425000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total     11425000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data     11425000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total     11425000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        61995                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        61995                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        51841                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        51841                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           70                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data       113836                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total       113836                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data       113836                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total       113836                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.008436                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.008436                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.002893                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.002893                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.857143                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.857143                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005912                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.005912                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005912                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.005912                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16184.512428                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16184.512428                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19736.666667                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 19736.666667                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data        13800                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total        13800                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16976.225854                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 16976.225854                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16976.225854                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16976.225854                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          362                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          362                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           43                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           43                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          405                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          405                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          405                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          405                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          161                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          161                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          107                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           60                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           60                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          268                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          268                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          268                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          268                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1530000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1530000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1517000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1517000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       768000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       768000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3047000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      3047000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3047000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      3047000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.002597                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.002597                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002064                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002064                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.857143                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.857143                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002354                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.002354                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002354                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.002354                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  9503.105590                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  9503.105590                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14177.570093                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14177.570093                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data        12800                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total        12800                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11369.402985                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11369.402985                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11369.402985                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11369.402985                       # average overall mshr miss latency
system.cpu1.icache.tags.replacements              548                       # number of replacements
system.cpu1.icache.tags.tagsinuse           97.609803                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs              21265                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs              682                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            31.180352                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst    97.609803                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.190644                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.190644                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          134                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          113                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024     0.261719                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses            22773                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses           22773                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst        21265                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          21265                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        21265                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           21265                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        21265                       # number of overall hits
system.cpu1.icache.overall_hits::total          21265                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          826                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          826                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          826                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           826                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          826                       # number of overall misses
system.cpu1.icache.overall_misses::total          826                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     13533000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total     13533000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst     13533000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total     13533000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst     13533000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total     13533000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        22091                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        22091                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        22091                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        22091                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        22091                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        22091                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.037391                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.037391                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.037391                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.037391                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.037391                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.037391                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16383.777240                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 16383.777240                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16383.777240                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 16383.777240                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16383.777240                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 16383.777240                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs           15                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs           15                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks          548                       # number of writebacks
system.cpu1.icache.writebacks::total              548                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst          144                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total          144                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst          144                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total          144                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst          144                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total          144                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          682                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          682                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          682                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          682                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          682                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          682                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     10822000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total     10822000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     10822000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total     10822000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     10822000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total     10822000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.030872                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.030872                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.030872                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.030872                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.030872                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.030872                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15868.035191                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 15868.035191                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 15868.035191                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 15868.035191                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 15868.035191                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 15868.035191                       # average overall mshr miss latency
system.cpu2.branchPred.lookups                  65577                       # Number of BP lookups
system.cpu2.branchPred.condPredicted            57724                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect             2464                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups               57712                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                   1983                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu2.branchPred.indirectLookups          57712                       # Number of indirect predictor lookups.
system.cpu2.branchPred.indirectHits             46848                       # Number of indirect target hits.
system.cpu2.branchPred.indirectMisses           10864                       # Number of indirect misses.
system.cpu2.branchPredindirectMispredicted         1379                       # Number of mispredicted indirect branches.
system.cpu2.numCycles                          195641                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles             39175                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        357136                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      65577                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             48831                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                       146036                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   5085                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles         2246                       # Number of stall cycles due to pending traps
system.cpu2.fetch.IcacheWaitRetryStallCycles           31                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                    27545                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  945                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            190045                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.879218                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.350973                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   72125     37.95%     37.95% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   57864     30.45%     68.40% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    8007      4.21%     72.61% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3378      1.78%     74.39% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     697      0.37%     74.76% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   36524     19.22%     93.98% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1219      0.64%     94.62% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                    1446      0.76%     95.38% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    8785      4.62%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              190045                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.335190                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.825466                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   23115                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                69586                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                    90388                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 4404                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  2542                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                325134                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  2542                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   24144                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  33213                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         15151                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    91754                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                23231                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                318523                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                 20453                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                    14                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.FullRegisterEvents               3                       # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands             223607                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               605589                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          472031                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups               26                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps               193721                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   29886                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1685                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1831                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    29018                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               87037                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              41099                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            41296                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           34595                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    259686                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               8253                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   260132                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued              104                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined          25858                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined        19408                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved          1214                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       190045                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.368792                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.393545                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              77002     40.52%     40.52% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              26562     13.98%     54.49% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              39729     20.91%     75.40% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              39504     20.79%     96.19% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3584      1.89%     98.07% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5               1794      0.94%     99.02% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6               1114      0.59%     99.60% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                438      0.23%     99.83% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                318      0.17%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         190045                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                    198     41.51%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     41.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    44      9.22%     50.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  235     49.27%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu               127776     49.12%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.12% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               92295     35.48%     84.60% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              40061     15.40%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                260132                       # Type of FU issued
system.cpu2.iq.rate                          1.329639                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        477                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001834                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            710890                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           293781                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       256087                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                52                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                260609                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           34538                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         4572                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses           34                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           36                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores         2770                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  2542                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                   9787                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   53                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             310555                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              374                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                87037                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               41099                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1544                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    30                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            36                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           461                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect         2649                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                3110                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               257554                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                85462                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts             2578                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        42616                       # number of nop insts executed
system.cpu2.iew.exec_refs                      125205                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   53054                       # Number of branches executed
system.cpu2.iew.exec_stores                     39743                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.316462                       # Inst execution rate
system.cpu2.iew.wb_sent                        256619                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       256087                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   143359                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   151246                       # num instructions consuming a value
system.cpu2.iew.wb_rate                      1.308964                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.947853                       # average fanout of values written-back
system.cpu2.commit.commitSquashedInsts          27054                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           7039                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             2464                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       184962                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.532661                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.012592                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        83513     45.15%     45.15% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        49247     26.63%     71.78% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         5539      2.99%     74.77% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         7621      4.12%     78.89% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1289      0.70%     79.59% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        34776     18.80%     98.39% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          735      0.40%     98.79% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7         1086      0.59%     99.38% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8         1156      0.62%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       184962                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              283484                       # Number of instructions committed
system.cpu2.commit.committedOps                283484                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                        120794                       # Number of memory references committed
system.cpu2.commit.loads                        82465                       # Number of loads committed
system.cpu2.commit.membars                       6325                       # Number of memory barriers committed
system.cpu2.commit.branches                     50613                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   193531                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        41403     14.61%     14.61% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu          114962     40.55%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult              0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv               0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.16% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead          88790     31.32%     86.48% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite         38329     13.52%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total           283484                       # Class of committed instruction
system.cpu2.commit.bw_lim_events                 1156                       # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads                      493758                       # The number of ROB reads
system.cpu2.rob.rob_writes                     626207                       # The number of ROB writes
system.cpu2.timesIdled                            224                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           5596                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       47431                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     235756                       # Number of Instructions Simulated
system.cpu2.committedOps                       235756                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              0.829845                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.829845                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.205044                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.205044                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  440950                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 206257                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                 127194                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu2.dcache.tags.replacements                0                       # number of replacements
system.cpu2.dcache.tags.tagsinuse           26.976674                       # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs              45756                       # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs          1525.200000                       # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.976674                       # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data     0.052689                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total     0.052689                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses           357076                       # Number of tag accesses
system.cpu2.dcache.tags.data_accesses          357076                       # Number of data accesses
system.cpu2.dcache.ReadReq_hits::cpu2.data        50413                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          50413                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        38109                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         38109                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           15                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        88522                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           88522                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        88522                       # number of overall hits
system.cpu2.dcache.overall_hits::total          88522                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          463                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          463                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          152                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          152                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           53                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           53                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          615                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           615                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          615                       # number of overall misses
system.cpu2.dcache.overall_misses::total          615                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      8046000                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      8046000                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3843000                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      3843000                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       809500                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       809500                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data     11889000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total     11889000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data     11889000                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total     11889000                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        50876                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        50876                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        38261                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        38261                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           68                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        89137                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        89137                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        89137                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        89137                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.009101                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.009101                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003973                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.003973                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.779412                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.779412                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.006899                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.006899                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.006899                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.006899                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17377.969762                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 17377.969762                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 25282.894737                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 25282.894737                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 15273.584906                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total 15273.584906                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19331.707317                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 19331.707317                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19331.707317                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 19331.707317                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          298                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          298                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           47                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           47                       # number of WriteReq MSHR hits
system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data            5                       # number of SwapReq MSHR hits
system.cpu2.dcache.SwapReq_mshr_hits::total            5                       # number of SwapReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          345                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          345                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          345                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          345                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          165                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          165                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          105                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           48                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           48                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          270                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          270                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          270                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          270                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1997000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1997000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1762500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1762500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       756500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       756500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3759500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      3759500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3759500                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      3759500                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003243                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003243                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002744                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002744                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.705882                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.705882                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003029                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.003029                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003029                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.003029                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12103.030303                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12103.030303                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16785.714286                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16785.714286                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 15760.416667                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 15760.416667                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13924.074074                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13924.074074                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13924.074074                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13924.074074                       # average overall mshr miss latency
system.cpu2.icache.tags.replacements              555                       # number of replacements
system.cpu2.icache.tags.tagsinuse          101.261159                       # Cycle average of tags in use
system.cpu2.icache.tags.total_refs              26702                       # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs              694                       # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs            38.475504                       # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst   101.261159                       # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst     0.197776                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total     0.197776                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_task_id_blocks::1024          139                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::1           90                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
system.cpu2.icache.tags.occ_task_id_percent::1024     0.271484                       # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses            28239                       # Number of tag accesses
system.cpu2.icache.tags.data_accesses           28239                       # Number of data accesses
system.cpu2.icache.ReadReq_hits::cpu2.inst        26702                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          26702                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        26702                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           26702                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        26702                       # number of overall hits
system.cpu2.icache.overall_hits::total          26702                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          843                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          843                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          843                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           843                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          843                       # number of overall misses
system.cpu2.icache.overall_misses::total          843                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     19527000                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total     19527000                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst     19527000                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total     19527000                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst     19527000                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total     19527000                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        27545                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        27545                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        27545                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        27545                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        27545                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        27545                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.030604                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.030604                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.030604                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.030604                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.030604                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.030604                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23163.701068                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 23163.701068                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23163.701068                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 23163.701068                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23163.701068                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 23163.701068                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs          220                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                7                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs    31.428571                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.writebacks::writebacks          555                       # number of writebacks
system.cpu2.icache.writebacks::total              555                       # number of writebacks
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst          149                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total          149                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst          149                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total          149                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst          149                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total          149                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          694                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          694                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          694                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          694                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          694                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          694                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     15501500                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total     15501500                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     15501500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total     15501500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     15501500                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total     15501500                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.025195                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.025195                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.025195                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.025195                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.025195                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.025195                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 22336.455331                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 22336.455331                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 22336.455331                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 22336.455331                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 22336.455331                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 22336.455331                       # average overall mshr miss latency
system.cpu3.branchPred.lookups                  57182                       # Number of BP lookups
system.cpu3.branchPred.condPredicted            48797                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect             2586                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups               48362                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                   2121                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu3.branchPred.indirectLookups          48362                       # Number of indirect predictor lookups.
system.cpu3.branchPred.indirectHits             37349                       # Number of indirect target hits.
system.cpu3.branchPred.indirectMisses           11013                       # Number of indirect misses.
system.cpu3.branchPredindirectMispredicted         1473                       # Number of mispredicted indirect branches.
system.cpu3.numCycles                          195288                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles             45700                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        298023                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      57182                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             39470                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                       143366                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   5327                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles         1948                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    34377                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                 1007                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            193690                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.538660                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.252819                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   90820     46.89%     46.89% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   51773     26.73%     73.62% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                   11180      5.77%     79.39% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3385      1.75%     81.14% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     629      0.32%     81.46% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   24090     12.44%     93.90% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1143      0.59%     94.49% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                    1449      0.75%     95.24% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    9221      4.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              193690                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.292809                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.526069                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   23670                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                95373                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    66026                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 5948                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  2663                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                265184                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  2663                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   24704                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  48500                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         15195                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    67410                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                35208                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                258083                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                 30956                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents                    14                       # Number of times rename has blocked due to LQ full
system.cpu3.rename.RenamedOperands             178302                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               471983                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          372133                       # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups               28                       # Number of floating rename lookups
system.cpu3.rename.CommittedMaps               146703                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                   31599                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1744                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1884                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    41025                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               65361                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              28681                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            31955                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           22074                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    204469                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded              11525                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   207359                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued              114                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined          27267                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined        21384                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved          1390                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       193690                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.070572                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.351583                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              96267     49.70%     49.70% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              35951     18.56%     68.26% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              27208     14.05%     82.31% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              26919     13.90%     96.21% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3677      1.90%     98.11% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1713      0.88%     98.99% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6               1079      0.56%     99.55% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                520      0.27%     99.82% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                356      0.18%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         193690                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                    253     45.42%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     45.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    65     11.67%     57.09% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  239     42.91%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu               106203     51.22%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     51.22% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               73580     35.48%     86.70% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              27576     13.30%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                207359                       # Type of FU issued
system.cpu3.iq.rate                          1.061811                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        557                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.002686                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            609079                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           243241                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       202956                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                56                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                207916                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           22032                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         4860                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses           37                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           36                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores         2877                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  2663                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                  13076                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   57                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             249222                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              349                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                65361                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               28681                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts              1596                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    28                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            36                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           455                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect         2781                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                3236                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               204483                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                63509                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts             2876                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        33228                       # number of nop insts executed
system.cpu3.iew.exec_refs                       90738                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   43690                       # Number of branches executed
system.cpu3.iew.exec_stores                     27229                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.047084                       # Inst execution rate
system.cpu3.iew.wb_sent                        203493                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       202956                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                   108735                       # num instructions producing a value
system.cpu3.iew.wb_consumers                   116603                       # num instructions consuming a value
system.cpu3.iew.wb_rate                      1.039265                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.932523                       # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts          28499                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls          10135                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             2586                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       188297                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.172069                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.830514                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0       105729     56.15%     56.15% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        39844     21.16%     77.31% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         5499      2.92%     80.23% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3        10725      5.70%     85.93% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1244      0.66%     86.59% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        22268     11.83%     98.41% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          755      0.40%     98.81% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7         1030      0.55%     99.36% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8         1203      0.64%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       188297                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              220697                       # Number of instructions committed
system.cpu3.commit.committedOps                220697                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                         86305                       # Number of memory references committed
system.cpu3.commit.loads                        60501                       # Number of loads committed
system.cpu3.commit.membars                       9419                       # Number of memory barriers committed
system.cpu3.commit.branches                     41182                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   149608                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass        31970     14.49%     14.49% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu           93003     42.14%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult              0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv               0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult            0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult             0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift            0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.63% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead          69920     31.68%     88.31% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite         25804     11.69%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total           220697                       # Class of committed instruction
system.cpu3.commit.bw_lim_events                 1203                       # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads                      435704                       # The number of ROB reads
system.cpu3.rob.rob_writes                     503857                       # The number of ROB writes
system.cpu3.timesIdled                            220                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           1598                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       47785                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     179308                       # Number of Instructions Simulated
system.cpu3.committedOps                       179308                       # Number of Ops (including micro ops) Simulated
system.cpu3.cpi                              1.089120                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        1.089120                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              0.918172                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        0.918172                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  337868                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 159407                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                  92688                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu3.dcache.tags.replacements                0                       # number of replacements
system.cpu3.dcache.tags.tagsinuse           25.364861                       # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs              33092                       # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs          1103.066667                       # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data    25.364861                       # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data     0.049541                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total     0.049541                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses           269290                       # Number of tag accesses
system.cpu3.dcache.tags.data_accesses          269290                       # Number of data accesses
system.cpu3.dcache.ReadReq_hits::cpu3.data        40990                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          40990                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        25593                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         25593                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           15                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        66583                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           66583                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        66583                       # number of overall hits
system.cpu3.dcache.overall_hits::total          66583                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          463                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          463                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          141                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          141                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           55                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          604                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           604                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          604                       # number of overall misses
system.cpu3.dcache.overall_misses::total          604                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      7157000                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      7157000                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3001000                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      3001000                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       868000                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       868000                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data     10158000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total     10158000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data     10158000                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total     10158000                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        41453                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        41453                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        25734                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        25734                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           70                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        67187                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        67187                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        67187                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        67187                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.011169                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.011169                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.005479                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.005479                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.785714                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.785714                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.008990                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.008990                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.008990                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.008990                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15457.883369                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 15457.883369                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21283.687943                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 21283.687943                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 15781.818182                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total 15781.818182                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16817.880795                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 16817.880795                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16817.880795                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 16817.880795                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          291                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          291                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           35                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           35                       # number of WriteReq MSHR hits
system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data            4                       # number of SwapReq MSHR hits
system.cpu3.dcache.SwapReq_mshr_hits::total            4                       # number of SwapReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          326                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          326                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          326                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          326                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          172                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          172                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          106                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           51                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           51                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          278                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          278                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          278                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          278                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1798500                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1798500                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1645500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1645500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       813000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       813000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3444000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      3444000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3444000                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      3444000                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.004149                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.004149                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.004119                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.004119                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.728571                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.728571                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.004138                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.004138                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.004138                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.004138                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10456.395349                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10456.395349                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15523.584906                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15523.584906                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 15941.176471                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 15941.176471                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12388.489209                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12388.489209                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12388.489209                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12388.489209                       # average overall mshr miss latency
system.cpu3.icache.tags.replacements              608                       # number of replacements
system.cpu3.icache.tags.tagsinuse           93.738869                       # Cycle average of tags in use
system.cpu3.icache.tags.total_refs              33506                       # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs              743                       # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs            45.095559                       # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst    93.738869                       # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst     0.183084                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total     0.183084                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024          135                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1          105                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024     0.263672                       # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses            35120                       # Number of tag accesses
system.cpu3.icache.tags.data_accesses           35120                       # Number of data accesses
system.cpu3.icache.ReadReq_hits::cpu3.inst        33506                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          33506                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        33506                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           33506                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        33506                       # number of overall hits
system.cpu3.icache.overall_hits::total          33506                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          871                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          871                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          871                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           871                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          871                       # number of overall misses
system.cpu3.icache.overall_misses::total          871                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst     11659000                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total     11659000                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst     11659000                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total     11659000                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst     11659000                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total     11659000                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        34377                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        34377                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        34377                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        34377                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        34377                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        34377                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.025337                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.025337                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.025337                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.025337                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.025337                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.025337                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13385.763490                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 13385.763490                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13385.763490                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 13385.763490                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13385.763490                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 13385.763490                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.writebacks::writebacks          608                       # number of writebacks
system.cpu3.icache.writebacks::total              608                       # number of writebacks
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst          128                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total          128                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst          128                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total          128                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst          128                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total          128                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          743                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          743                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          743                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          743                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          743                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          743                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst     10055000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total     10055000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst     10055000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total     10055000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst     10055000                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total     10055000                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.021613                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.021613                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.021613                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.021613                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.021613                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.021613                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13532.974428                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13532.974428                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13532.974428                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 13532.974428                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13532.974428                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 13532.974428                       # average overall mshr miss latency
system.l2c.tags.replacements                        0                       # number of replacements
system.l2c.tags.tagsinuse                  458.562207                       # Cycle average of tags in use
system.l2c.tags.total_refs                       3097                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                      581                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     5.330465                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks       0.811695                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst      303.236105                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data       58.939439                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst       17.006196                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data        1.379366                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst       67.599671                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data        5.915132                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst        1.812120                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data        1.862482                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.000012                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.004627                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.000899                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.000259                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000021                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.001031                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.000090                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.000028                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.000028                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.006997                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024          581                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          428                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.008865                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                    32091                       # Number of tag accesses
system.l2c.tags.data_accesses                   32091                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks            1                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total               1                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks          751                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total             751                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst           329                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst           654                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst           595                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst           735                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total              2313                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data           11                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data            5                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data           11                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total               32                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst                 329                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 654                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 595                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 735                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    2345                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                329                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                654                       # number of overall hits
system.l2c.overall_hits::cpu1.data                 11                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                595                       # number of overall hits
system.l2c.overall_hits::cpu2.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                735                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
system.l2c.overall_hits::total                   2345                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data            23                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            20                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            22                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            24                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                89                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst          377                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst           28                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst           99                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst            8                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total             512                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data           76                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data            8                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data            3                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total             89                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst               377                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               170                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                28                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                14                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                99                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                21                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                 8                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                15                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   732                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              377                       # number of overall misses
system.l2c.overall_misses::cpu0.data              170                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               28                       # number of overall misses
system.l2c.overall_misses::cpu1.data               14                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               99                       # number of overall misses
system.l2c.overall_misses::cpu2.data               21                       # number of overall misses
system.l2c.overall_misses::cpu3.inst                8                       # number of overall misses
system.l2c.overall_misses::cpu3.data               15                       # number of overall misses
system.l2c.overall_misses::total                  732                       # number of overall misses
system.l2c.ReadExReq_miss_latency::cpu0.data      7972500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data       902000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data      1048000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       927000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total     10849500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst     29037500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst      2384000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst      7728000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst       627500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total     39777000                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data      6533500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data       165500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data       634500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data       262000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total      7595500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     29037500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data     14506000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      2384000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data      1067500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst      7728000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data      1682500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst       627500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data      1189000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        58222000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     29037500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data     14506000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      2384000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data      1067500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst      7728000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data      1682500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst       627500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data      1189000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       58222000                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks            1                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total            1                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks          751                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total          751                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           26                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           20                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           22                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           24                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              92                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst          706                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst          682                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst          694                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst          743                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total          2825                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data           81                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data           13                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data           13                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data           14                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total          121                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             706                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             175                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             682                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             694                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              26                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             743                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              26                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                3077                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            706                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            175                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            682                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            694                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             26                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            743                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             26                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               3077                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.884615                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.967391                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.533994                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.041056                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.142651                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.010767                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.181239                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.938272                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.153846                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.615385                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.214286                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.735537                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.533994                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971429                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.041056                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.560000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.142651                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.807692                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.010767                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.576923                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.237894                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.533994                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971429                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.041056                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.560000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.142651                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.807692                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.010767                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.576923                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.237894                       # miss rate for overall accesses
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84813.829787                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75166.666667                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 80615.384615                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data        77250                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 82820.610687                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 77022.546419                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 85142.857143                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 78060.606061                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 78437.500000                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 77689.453125                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 85967.105263                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data        82750                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 79312.500000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 87333.333333                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 85342.696629                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 77022.546419                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 85329.411765                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 85142.857143                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data        76250                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 78060.606061                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 80119.047619                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 78437.500000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 79266.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 79538.251366                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 77022.546419                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 85329.411765                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 85142.857143                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data        76250                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 78060.606061                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 80119.047619                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 78437.500000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 79266.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 79538.251366                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            8                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            4                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           17                       # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 17                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                17                       # number of overall MSHR hits
system.l2c.UpgradeReq_mshr_misses::cpu0.data           23                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           20                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           22                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           24                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           89                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          376                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           24                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst           91                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst            4                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total          495                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data           76                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data            2                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data            8                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data            3                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total           89                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          376                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          170                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           24                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst           91                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           21                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           15                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              715                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          376                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          170                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           24                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst           91                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           21                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           15                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             715                       # number of overall MSHR misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       437500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       380000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       419000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       457000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      1693500                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      7032500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       782000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       918000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       807000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      9539500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     25253500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst      1934500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst      6358500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst       309500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total     33856000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      5773500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data       145500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data       554500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data       232000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total      6705500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     25253500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data     12806000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst      1934500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data       927500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst      6358500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data      1472500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst       309500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data      1039000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     50101000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     25253500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data     12806000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst      1934500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data       927500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst      6358500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data      1472500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst       309500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data      1039000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     50101000                       # number of overall MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.884615                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.967391                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.532578                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.035191                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.131124                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.005384                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.175221                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.938272                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.153846                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.615385                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.214286                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.735537                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.532578                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971429                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.035191                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.560000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.131124                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.807692                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.005384                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.576923                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.232369                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.532578                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971429                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.035191                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.560000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.131124                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.807692                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.005384                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.576923                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.232369                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19021.739130                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        19000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19045.454545                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19041.666667                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19028.089888                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74813.829787                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65166.666667                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70615.384615                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        67250                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 72820.610687                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67163.563830                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 80604.166667                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 69873.626374                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst        77375                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 68395.959596                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 75967.105263                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data        72750                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 69312.500000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 77333.333333                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75342.696629                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67163.563830                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75329.411765                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80604.166667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data        66250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 69873.626374                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 70119.047619                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        77375                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 69266.666667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 70071.328671                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67163.563830                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75329.411765                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80604.166667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data        66250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 69873.626374                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70119.047619                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        77375                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 69266.666667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 70071.328671                       # average overall mshr miss latency
system.membus.trans_dist::ReadResp                583                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              286                       # Transaction distribution
system.membus.trans_dist::ReadExReq               182                       # Transaction distribution
system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           583                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1765                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1765                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        45696                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   45696                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              248                       # Total snoops (count)
system.membus.snoop_fanout::samples              1051                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                    1051    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                1051                       # Request fanout histogram
system.membus.reqLayer0.occupancy              998006                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
system.membus.respLayer1.occupancy            3803500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.0                       # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests         6324                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests         1712                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         3265                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadResp              3513                       # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate            6                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty            1                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean         2114                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict               1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq             289                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp            289                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq              399                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp             399                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq          2825                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq          695                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1814                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          602                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1912                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          373                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1943                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          371                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         2094                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          383                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total                  9492                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        70912                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11264                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        78720                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        79936                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        86464                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total                 332224                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                            1039                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples             4208                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.288736                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           1.116485                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                   1347     32.01%     32.01% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                   1142     27.14%     59.15% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    876     20.82%     79.97% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                    843     20.03%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total               4208                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy            5296461                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              4.2                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy           1058997                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.8                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy            523496                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.4                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           1025493                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.8                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy            437958                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy           1044987                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization             0.8                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy            431472                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy           1116994                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.9                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy            444965                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.4                       # Layer utilization (%)

---------- End Simulation Statistics   ----------