config.ini revision 9924
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= 23symbolfile= 24work_begin_ckpt_count=0 25work_begin_cpu_id_exit=-1 26work_begin_exit_count=0 27work_cpus_ckpt_count=0 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 36voltage_domain=system.voltage_domain 37 38[system.cpu0] 39type=DerivO3CPU 40children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 41LFSTSize=1024 42LQEntries=32 43LSQCheckLoads=true 44LSQDepCheckShift=4 45SQEntries=32 46SSITSize=1024 47activity=0 48backComSize=5 49branchPred=system.cpu0.branchPred 50cachePorts=200 51checker=Null 52clk_domain=system.cpu_clk_domain 53commitToDecodeDelay=1 54commitToFetchDelay=1 55commitToIEWDelay=1 56commitToRenameDelay=1 57commitWidth=8 58cpu_id=0 59decodeToFetchDelay=1 60decodeToRenameDelay=1 61decodeWidth=8 62dispatchWidth=8 63do_checkpoint_insts=true 64do_quiesce=true 65do_statistics_insts=true 66dtb=system.cpu0.dtb 67fetchToDecodeDelay=1 68fetchTrapLatency=1 69fetchWidth=8 70forwardComSize=5 71fuPool=system.cpu0.fuPool 72function_trace=false 73function_trace_start=0 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78interrupts=system.cpu0.interrupts 79isa=system.cpu0.isa 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu0.itb 83max_insts_all_threads=0 84max_insts_any_thread=0 85max_loads_all_threads=0 86max_loads_any_thread=0 87needsTSO=false 88numIQEntries=64 89numPhysCCRegs=0 90numPhysFloatRegs=256 91numPhysIntRegs=256 92numROBEntries=192 93numRobs=1 94numThreads=1 95profile=0 96progress_interval=0 97renameToDecodeDelay=1 98renameToFetchDelay=1 99renameToIEWDelay=2 100renameToROBDelay=1 101renameWidth=8 102simpoint_start_insts= 103smtCommitPolicy=RoundRobin 104smtFetchPolicy=SingleThread 105smtIQPolicy=Partitioned 106smtIQThreshold=100 107smtLSQPolicy=Partitioned 108smtLSQThreshold=100 109smtNumFetchingThreads=1 110smtROBPolicy=Partitioned 111smtROBThreshold=100 112squashWidth=8 113store_set_clear_period=250000 114switched_out=false 115system=system 116tracer=system.cpu0.tracer 117trapLatency=13 118wbDepth=1 119wbWidth=8 120workload=system.cpu0.workload 121dcache_port=system.cpu0.dcache.cpu_side 122icache_port=system.cpu0.icache.cpu_side 123 124[system.cpu0.branchPred] 125type=BranchPredictor 126BTBEntries=4096 127BTBTagSize=16 128RASSize=16 129choiceCtrBits=2 130choicePredictorSize=8192 131globalCtrBits=2 132globalPredictorSize=8192 133instShiftAmt=2 134localCtrBits=2 135localHistoryTableSize=2048 136localPredictorSize=2048 137numThreads=1 138predType=tournament 139 140[system.cpu0.dcache] 141type=BaseCache 142children=tags 143addr_ranges=0:18446744073709551615 144assoc=4 145clk_domain=system.cpu_clk_domain 146forward_snoops=true 147hit_latency=2 148is_top_level=true 149max_miss_count=0 150mshrs=4 151prefetch_on_access=false 152prefetcher=Null 153response_latency=2 154size=32768 155system=system 156tags=system.cpu0.dcache.tags 157tgts_per_mshr=20 158two_queue=false 159write_buffers=8 160cpu_side=system.cpu0.dcache_port 161mem_side=system.toL2Bus.slave[1] 162 163[system.cpu0.dcache.tags] 164type=LRU 165assoc=4 166block_size=64 167clk_domain=system.cpu_clk_domain 168hit_latency=2 169size=32768 170 171[system.cpu0.dtb] 172type=SparcTLB 173size=64 174 175[system.cpu0.fuPool] 176type=FUPool 177children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 178FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 179 180[system.cpu0.fuPool.FUList0] 181type=FUDesc 182children=opList 183count=6 184opList=system.cpu0.fuPool.FUList0.opList 185 186[system.cpu0.fuPool.FUList0.opList] 187type=OpDesc 188issueLat=1 189opClass=IntAlu 190opLat=1 191 192[system.cpu0.fuPool.FUList1] 193type=FUDesc 194children=opList0 opList1 195count=2 196opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 197 198[system.cpu0.fuPool.FUList1.opList0] 199type=OpDesc 200issueLat=1 201opClass=IntMult 202opLat=3 203 204[system.cpu0.fuPool.FUList1.opList1] 205type=OpDesc 206issueLat=19 207opClass=IntDiv 208opLat=20 209 210[system.cpu0.fuPool.FUList2] 211type=FUDesc 212children=opList0 opList1 opList2 213count=4 214opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 215 216[system.cpu0.fuPool.FUList2.opList0] 217type=OpDesc 218issueLat=1 219opClass=FloatAdd 220opLat=2 221 222[system.cpu0.fuPool.FUList2.opList1] 223type=OpDesc 224issueLat=1 225opClass=FloatCmp 226opLat=2 227 228[system.cpu0.fuPool.FUList2.opList2] 229type=OpDesc 230issueLat=1 231opClass=FloatCvt 232opLat=2 233 234[system.cpu0.fuPool.FUList3] 235type=FUDesc 236children=opList0 opList1 opList2 237count=2 238opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 239 240[system.cpu0.fuPool.FUList3.opList0] 241type=OpDesc 242issueLat=1 243opClass=FloatMult 244opLat=4 245 246[system.cpu0.fuPool.FUList3.opList1] 247type=OpDesc 248issueLat=12 249opClass=FloatDiv 250opLat=12 251 252[system.cpu0.fuPool.FUList3.opList2] 253type=OpDesc 254issueLat=24 255opClass=FloatSqrt 256opLat=24 257 258[system.cpu0.fuPool.FUList4] 259type=FUDesc 260children=opList 261count=0 262opList=system.cpu0.fuPool.FUList4.opList 263 264[system.cpu0.fuPool.FUList4.opList] 265type=OpDesc 266issueLat=1 267opClass=MemRead 268opLat=1 269 270[system.cpu0.fuPool.FUList5] 271type=FUDesc 272children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 273count=4 274opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 275 276[system.cpu0.fuPool.FUList5.opList00] 277type=OpDesc 278issueLat=1 279opClass=SimdAdd 280opLat=1 281 282[system.cpu0.fuPool.FUList5.opList01] 283type=OpDesc 284issueLat=1 285opClass=SimdAddAcc 286opLat=1 287 288[system.cpu0.fuPool.FUList5.opList02] 289type=OpDesc 290issueLat=1 291opClass=SimdAlu 292opLat=1 293 294[system.cpu0.fuPool.FUList5.opList03] 295type=OpDesc 296issueLat=1 297opClass=SimdCmp 298opLat=1 299 300[system.cpu0.fuPool.FUList5.opList04] 301type=OpDesc 302issueLat=1 303opClass=SimdCvt 304opLat=1 305 306[system.cpu0.fuPool.FUList5.opList05] 307type=OpDesc 308issueLat=1 309opClass=SimdMisc 310opLat=1 311 312[system.cpu0.fuPool.FUList5.opList06] 313type=OpDesc 314issueLat=1 315opClass=SimdMult 316opLat=1 317 318[system.cpu0.fuPool.FUList5.opList07] 319type=OpDesc 320issueLat=1 321opClass=SimdMultAcc 322opLat=1 323 324[system.cpu0.fuPool.FUList5.opList08] 325type=OpDesc 326issueLat=1 327opClass=SimdShift 328opLat=1 329 330[system.cpu0.fuPool.FUList5.opList09] 331type=OpDesc 332issueLat=1 333opClass=SimdShiftAcc 334opLat=1 335 336[system.cpu0.fuPool.FUList5.opList10] 337type=OpDesc 338issueLat=1 339opClass=SimdSqrt 340opLat=1 341 342[system.cpu0.fuPool.FUList5.opList11] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatAdd 346opLat=1 347 348[system.cpu0.fuPool.FUList5.opList12] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatAlu 352opLat=1 353 354[system.cpu0.fuPool.FUList5.opList13] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatCmp 358opLat=1 359 360[system.cpu0.fuPool.FUList5.opList14] 361type=OpDesc 362issueLat=1 363opClass=SimdFloatCvt 364opLat=1 365 366[system.cpu0.fuPool.FUList5.opList15] 367type=OpDesc 368issueLat=1 369opClass=SimdFloatDiv 370opLat=1 371 372[system.cpu0.fuPool.FUList5.opList16] 373type=OpDesc 374issueLat=1 375opClass=SimdFloatMisc 376opLat=1 377 378[system.cpu0.fuPool.FUList5.opList17] 379type=OpDesc 380issueLat=1 381opClass=SimdFloatMult 382opLat=1 383 384[system.cpu0.fuPool.FUList5.opList18] 385type=OpDesc 386issueLat=1 387opClass=SimdFloatMultAcc 388opLat=1 389 390[system.cpu0.fuPool.FUList5.opList19] 391type=OpDesc 392issueLat=1 393opClass=SimdFloatSqrt 394opLat=1 395 396[system.cpu0.fuPool.FUList6] 397type=FUDesc 398children=opList 399count=0 400opList=system.cpu0.fuPool.FUList6.opList 401 402[system.cpu0.fuPool.FUList6.opList] 403type=OpDesc 404issueLat=1 405opClass=MemWrite 406opLat=1 407 408[system.cpu0.fuPool.FUList7] 409type=FUDesc 410children=opList0 opList1 411count=4 412opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 413 414[system.cpu0.fuPool.FUList7.opList0] 415type=OpDesc 416issueLat=1 417opClass=MemRead 418opLat=1 419 420[system.cpu0.fuPool.FUList7.opList1] 421type=OpDesc 422issueLat=1 423opClass=MemWrite 424opLat=1 425 426[system.cpu0.fuPool.FUList8] 427type=FUDesc 428children=opList 429count=1 430opList=system.cpu0.fuPool.FUList8.opList 431 432[system.cpu0.fuPool.FUList8.opList] 433type=OpDesc 434issueLat=3 435opClass=IprAccess 436opLat=3 437 438[system.cpu0.icache] 439type=BaseCache 440children=tags 441addr_ranges=0:18446744073709551615 442assoc=1 443clk_domain=system.cpu_clk_domain 444forward_snoops=true 445hit_latency=2 446is_top_level=true 447max_miss_count=0 448mshrs=4 449prefetch_on_access=false 450prefetcher=Null 451response_latency=2 452size=32768 453system=system 454tags=system.cpu0.icache.tags 455tgts_per_mshr=20 456two_queue=false 457write_buffers=8 458cpu_side=system.cpu0.icache_port 459mem_side=system.toL2Bus.slave[0] 460 461[system.cpu0.icache.tags] 462type=LRU 463assoc=1 464block_size=64 465clk_domain=system.cpu_clk_domain 466hit_latency=2 467size=32768 468 469[system.cpu0.interrupts] 470type=SparcInterrupts 471 472[system.cpu0.isa] 473type=SparcISA 474 475[system.cpu0.itb] 476type=SparcTLB 477size=64 478 479[system.cpu0.tracer] 480type=ExeTracer 481 482[system.cpu0.workload] 483type=LiveProcess 484cmd=test_atomic 4 485cwd= 486egid=100 487env= 488errout=cerr 489euid=100 490executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic 491gid=100 492input=cin 493max_stack_size=67108864 494output=cout 495pid=100 496ppid=99 497simpoint=0 498system=system 499uid=100 500 501[system.cpu1] 502type=DerivO3CPU 503children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 504LFSTSize=1024 505LQEntries=32 506LSQCheckLoads=true 507LSQDepCheckShift=4 508SQEntries=32 509SSITSize=1024 510activity=0 511backComSize=5 512branchPred=system.cpu1.branchPred 513cachePorts=200 514checker=Null 515clk_domain=system.cpu_clk_domain 516commitToDecodeDelay=1 517commitToFetchDelay=1 518commitToIEWDelay=1 519commitToRenameDelay=1 520commitWidth=8 521cpu_id=1 522decodeToFetchDelay=1 523decodeToRenameDelay=1 524decodeWidth=8 525dispatchWidth=8 526do_checkpoint_insts=true 527do_quiesce=true 528do_statistics_insts=true 529dtb=system.cpu1.dtb 530fetchToDecodeDelay=1 531fetchTrapLatency=1 532fetchWidth=8 533forwardComSize=5 534fuPool=system.cpu1.fuPool 535function_trace=false 536function_trace_start=0 537iewToCommitDelay=1 538iewToDecodeDelay=1 539iewToFetchDelay=1 540iewToRenameDelay=1 541interrupts=system.cpu1.interrupts 542isa=system.cpu1.isa 543issueToExecuteDelay=1 544issueWidth=8 545itb=system.cpu1.itb 546max_insts_all_threads=0 547max_insts_any_thread=0 548max_loads_all_threads=0 549max_loads_any_thread=0 550needsTSO=false 551numIQEntries=64 552numPhysCCRegs=0 553numPhysFloatRegs=256 554numPhysIntRegs=256 555numROBEntries=192 556numRobs=1 557numThreads=1 558profile=0 559progress_interval=0 560renameToDecodeDelay=1 561renameToFetchDelay=1 562renameToIEWDelay=2 563renameToROBDelay=1 564renameWidth=8 565simpoint_start_insts= 566smtCommitPolicy=RoundRobin 567smtFetchPolicy=SingleThread 568smtIQPolicy=Partitioned 569smtIQThreshold=100 570smtLSQPolicy=Partitioned 571smtLSQThreshold=100 572smtNumFetchingThreads=1 573smtROBPolicy=Partitioned 574smtROBThreshold=100 575squashWidth=8 576store_set_clear_period=250000 577switched_out=false 578system=system 579tracer=system.cpu1.tracer 580trapLatency=13 581wbDepth=1 582wbWidth=8 583workload=system.cpu0.workload 584dcache_port=system.cpu1.dcache.cpu_side 585icache_port=system.cpu1.icache.cpu_side 586 587[system.cpu1.branchPred] 588type=BranchPredictor 589BTBEntries=4096 590BTBTagSize=16 591RASSize=16 592choiceCtrBits=2 593choicePredictorSize=8192 594globalCtrBits=2 595globalPredictorSize=8192 596instShiftAmt=2 597localCtrBits=2 598localHistoryTableSize=2048 599localPredictorSize=2048 600numThreads=1 601predType=tournament 602 603[system.cpu1.dcache] 604type=BaseCache 605children=tags 606addr_ranges=0:18446744073709551615 607assoc=4 608clk_domain=system.cpu_clk_domain 609forward_snoops=true 610hit_latency=2 611is_top_level=true 612max_miss_count=0 613mshrs=4 614prefetch_on_access=false 615prefetcher=Null 616response_latency=2 617size=32768 618system=system 619tags=system.cpu1.dcache.tags 620tgts_per_mshr=20 621two_queue=false 622write_buffers=8 623cpu_side=system.cpu1.dcache_port 624mem_side=system.toL2Bus.slave[3] 625 626[system.cpu1.dcache.tags] 627type=LRU 628assoc=4 629block_size=64 630clk_domain=system.cpu_clk_domain 631hit_latency=2 632size=32768 633 634[system.cpu1.dtb] 635type=SparcTLB 636size=64 637 638[system.cpu1.fuPool] 639type=FUPool 640children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 641FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 642 643[system.cpu1.fuPool.FUList0] 644type=FUDesc 645children=opList 646count=6 647opList=system.cpu1.fuPool.FUList0.opList 648 649[system.cpu1.fuPool.FUList0.opList] 650type=OpDesc 651issueLat=1 652opClass=IntAlu 653opLat=1 654 655[system.cpu1.fuPool.FUList1] 656type=FUDesc 657children=opList0 opList1 658count=2 659opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 660 661[system.cpu1.fuPool.FUList1.opList0] 662type=OpDesc 663issueLat=1 664opClass=IntMult 665opLat=3 666 667[system.cpu1.fuPool.FUList1.opList1] 668type=OpDesc 669issueLat=19 670opClass=IntDiv 671opLat=20 672 673[system.cpu1.fuPool.FUList2] 674type=FUDesc 675children=opList0 opList1 opList2 676count=4 677opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 678 679[system.cpu1.fuPool.FUList2.opList0] 680type=OpDesc 681issueLat=1 682opClass=FloatAdd 683opLat=2 684 685[system.cpu1.fuPool.FUList2.opList1] 686type=OpDesc 687issueLat=1 688opClass=FloatCmp 689opLat=2 690 691[system.cpu1.fuPool.FUList2.opList2] 692type=OpDesc 693issueLat=1 694opClass=FloatCvt 695opLat=2 696 697[system.cpu1.fuPool.FUList3] 698type=FUDesc 699children=opList0 opList1 opList2 700count=2 701opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 702 703[system.cpu1.fuPool.FUList3.opList0] 704type=OpDesc 705issueLat=1 706opClass=FloatMult 707opLat=4 708 709[system.cpu1.fuPool.FUList3.opList1] 710type=OpDesc 711issueLat=12 712opClass=FloatDiv 713opLat=12 714 715[system.cpu1.fuPool.FUList3.opList2] 716type=OpDesc 717issueLat=24 718opClass=FloatSqrt 719opLat=24 720 721[system.cpu1.fuPool.FUList4] 722type=FUDesc 723children=opList 724count=0 725opList=system.cpu1.fuPool.FUList4.opList 726 727[system.cpu1.fuPool.FUList4.opList] 728type=OpDesc 729issueLat=1 730opClass=MemRead 731opLat=1 732 733[system.cpu1.fuPool.FUList5] 734type=FUDesc 735children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 736count=4 737opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 738 739[system.cpu1.fuPool.FUList5.opList00] 740type=OpDesc 741issueLat=1 742opClass=SimdAdd 743opLat=1 744 745[system.cpu1.fuPool.FUList5.opList01] 746type=OpDesc 747issueLat=1 748opClass=SimdAddAcc 749opLat=1 750 751[system.cpu1.fuPool.FUList5.opList02] 752type=OpDesc 753issueLat=1 754opClass=SimdAlu 755opLat=1 756 757[system.cpu1.fuPool.FUList5.opList03] 758type=OpDesc 759issueLat=1 760opClass=SimdCmp 761opLat=1 762 763[system.cpu1.fuPool.FUList5.opList04] 764type=OpDesc 765issueLat=1 766opClass=SimdCvt 767opLat=1 768 769[system.cpu1.fuPool.FUList5.opList05] 770type=OpDesc 771issueLat=1 772opClass=SimdMisc 773opLat=1 774 775[system.cpu1.fuPool.FUList5.opList06] 776type=OpDesc 777issueLat=1 778opClass=SimdMult 779opLat=1 780 781[system.cpu1.fuPool.FUList5.opList07] 782type=OpDesc 783issueLat=1 784opClass=SimdMultAcc 785opLat=1 786 787[system.cpu1.fuPool.FUList5.opList08] 788type=OpDesc 789issueLat=1 790opClass=SimdShift 791opLat=1 792 793[system.cpu1.fuPool.FUList5.opList09] 794type=OpDesc 795issueLat=1 796opClass=SimdShiftAcc 797opLat=1 798 799[system.cpu1.fuPool.FUList5.opList10] 800type=OpDesc 801issueLat=1 802opClass=SimdSqrt 803opLat=1 804 805[system.cpu1.fuPool.FUList5.opList11] 806type=OpDesc 807issueLat=1 808opClass=SimdFloatAdd 809opLat=1 810 811[system.cpu1.fuPool.FUList5.opList12] 812type=OpDesc 813issueLat=1 814opClass=SimdFloatAlu 815opLat=1 816 817[system.cpu1.fuPool.FUList5.opList13] 818type=OpDesc 819issueLat=1 820opClass=SimdFloatCmp 821opLat=1 822 823[system.cpu1.fuPool.FUList5.opList14] 824type=OpDesc 825issueLat=1 826opClass=SimdFloatCvt 827opLat=1 828 829[system.cpu1.fuPool.FUList5.opList15] 830type=OpDesc 831issueLat=1 832opClass=SimdFloatDiv 833opLat=1 834 835[system.cpu1.fuPool.FUList5.opList16] 836type=OpDesc 837issueLat=1 838opClass=SimdFloatMisc 839opLat=1 840 841[system.cpu1.fuPool.FUList5.opList17] 842type=OpDesc 843issueLat=1 844opClass=SimdFloatMult 845opLat=1 846 847[system.cpu1.fuPool.FUList5.opList18] 848type=OpDesc 849issueLat=1 850opClass=SimdFloatMultAcc 851opLat=1 852 853[system.cpu1.fuPool.FUList5.opList19] 854type=OpDesc 855issueLat=1 856opClass=SimdFloatSqrt 857opLat=1 858 859[system.cpu1.fuPool.FUList6] 860type=FUDesc 861children=opList 862count=0 863opList=system.cpu1.fuPool.FUList6.opList 864 865[system.cpu1.fuPool.FUList6.opList] 866type=OpDesc 867issueLat=1 868opClass=MemWrite 869opLat=1 870 871[system.cpu1.fuPool.FUList7] 872type=FUDesc 873children=opList0 opList1 874count=4 875opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 876 877[system.cpu1.fuPool.FUList7.opList0] 878type=OpDesc 879issueLat=1 880opClass=MemRead 881opLat=1 882 883[system.cpu1.fuPool.FUList7.opList1] 884type=OpDesc 885issueLat=1 886opClass=MemWrite 887opLat=1 888 889[system.cpu1.fuPool.FUList8] 890type=FUDesc 891children=opList 892count=1 893opList=system.cpu1.fuPool.FUList8.opList 894 895[system.cpu1.fuPool.FUList8.opList] 896type=OpDesc 897issueLat=3 898opClass=IprAccess 899opLat=3 900 901[system.cpu1.icache] 902type=BaseCache 903children=tags 904addr_ranges=0:18446744073709551615 905assoc=1 906clk_domain=system.cpu_clk_domain 907forward_snoops=true 908hit_latency=2 909is_top_level=true 910max_miss_count=0 911mshrs=4 912prefetch_on_access=false 913prefetcher=Null 914response_latency=2 915size=32768 916system=system 917tags=system.cpu1.icache.tags 918tgts_per_mshr=20 919two_queue=false 920write_buffers=8 921cpu_side=system.cpu1.icache_port 922mem_side=system.toL2Bus.slave[2] 923 924[system.cpu1.icache.tags] 925type=LRU 926assoc=1 927block_size=64 928clk_domain=system.cpu_clk_domain 929hit_latency=2 930size=32768 931 932[system.cpu1.interrupts] 933type=SparcInterrupts 934 935[system.cpu1.isa] 936type=SparcISA 937 938[system.cpu1.itb] 939type=SparcTLB 940size=64 941 942[system.cpu1.tracer] 943type=ExeTracer 944 945[system.cpu2] 946type=DerivO3CPU 947children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 948LFSTSize=1024 949LQEntries=32 950LSQCheckLoads=true 951LSQDepCheckShift=4 952SQEntries=32 953SSITSize=1024 954activity=0 955backComSize=5 956branchPred=system.cpu2.branchPred 957cachePorts=200 958checker=Null 959clk_domain=system.cpu_clk_domain 960commitToDecodeDelay=1 961commitToFetchDelay=1 962commitToIEWDelay=1 963commitToRenameDelay=1 964commitWidth=8 965cpu_id=2 966decodeToFetchDelay=1 967decodeToRenameDelay=1 968decodeWidth=8 969dispatchWidth=8 970do_checkpoint_insts=true 971do_quiesce=true 972do_statistics_insts=true 973dtb=system.cpu2.dtb 974fetchToDecodeDelay=1 975fetchTrapLatency=1 976fetchWidth=8 977forwardComSize=5 978fuPool=system.cpu2.fuPool 979function_trace=false 980function_trace_start=0 981iewToCommitDelay=1 982iewToDecodeDelay=1 983iewToFetchDelay=1 984iewToRenameDelay=1 985interrupts=system.cpu2.interrupts 986isa=system.cpu2.isa 987issueToExecuteDelay=1 988issueWidth=8 989itb=system.cpu2.itb 990max_insts_all_threads=0 991max_insts_any_thread=0 992max_loads_all_threads=0 993max_loads_any_thread=0 994needsTSO=false 995numIQEntries=64 996numPhysCCRegs=0 997numPhysFloatRegs=256 998numPhysIntRegs=256 999numROBEntries=192 1000numRobs=1 1001numThreads=1 1002profile=0 1003progress_interval=0 1004renameToDecodeDelay=1 1005renameToFetchDelay=1 1006renameToIEWDelay=2 1007renameToROBDelay=1 1008renameWidth=8 1009simpoint_start_insts= 1010smtCommitPolicy=RoundRobin 1011smtFetchPolicy=SingleThread 1012smtIQPolicy=Partitioned 1013smtIQThreshold=100 1014smtLSQPolicy=Partitioned 1015smtLSQThreshold=100 1016smtNumFetchingThreads=1 1017smtROBPolicy=Partitioned 1018smtROBThreshold=100 1019squashWidth=8 1020store_set_clear_period=250000 1021switched_out=false 1022system=system 1023tracer=system.cpu2.tracer 1024trapLatency=13 1025wbDepth=1 1026wbWidth=8 1027workload=system.cpu0.workload 1028dcache_port=system.cpu2.dcache.cpu_side 1029icache_port=system.cpu2.icache.cpu_side 1030 1031[system.cpu2.branchPred] 1032type=BranchPredictor 1033BTBEntries=4096 1034BTBTagSize=16 1035RASSize=16 1036choiceCtrBits=2 1037choicePredictorSize=8192 1038globalCtrBits=2 1039globalPredictorSize=8192 1040instShiftAmt=2 1041localCtrBits=2 1042localHistoryTableSize=2048 1043localPredictorSize=2048 1044numThreads=1 1045predType=tournament 1046 1047[system.cpu2.dcache] 1048type=BaseCache 1049children=tags 1050addr_ranges=0:18446744073709551615 1051assoc=4 1052clk_domain=system.cpu_clk_domain 1053forward_snoops=true 1054hit_latency=2 1055is_top_level=true 1056max_miss_count=0 1057mshrs=4 1058prefetch_on_access=false 1059prefetcher=Null 1060response_latency=2 1061size=32768 1062system=system 1063tags=system.cpu2.dcache.tags 1064tgts_per_mshr=20 1065two_queue=false 1066write_buffers=8 1067cpu_side=system.cpu2.dcache_port 1068mem_side=system.toL2Bus.slave[5] 1069 1070[system.cpu2.dcache.tags] 1071type=LRU 1072assoc=4 1073block_size=64 1074clk_domain=system.cpu_clk_domain 1075hit_latency=2 1076size=32768 1077 1078[system.cpu2.dtb] 1079type=SparcTLB 1080size=64 1081 1082[system.cpu2.fuPool] 1083type=FUPool 1084children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1085FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1086 1087[system.cpu2.fuPool.FUList0] 1088type=FUDesc 1089children=opList 1090count=6 1091opList=system.cpu2.fuPool.FUList0.opList 1092 1093[system.cpu2.fuPool.FUList0.opList] 1094type=OpDesc 1095issueLat=1 1096opClass=IntAlu 1097opLat=1 1098 1099[system.cpu2.fuPool.FUList1] 1100type=FUDesc 1101children=opList0 opList1 1102count=2 1103opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1104 1105[system.cpu2.fuPool.FUList1.opList0] 1106type=OpDesc 1107issueLat=1 1108opClass=IntMult 1109opLat=3 1110 1111[system.cpu2.fuPool.FUList1.opList1] 1112type=OpDesc 1113issueLat=19 1114opClass=IntDiv 1115opLat=20 1116 1117[system.cpu2.fuPool.FUList2] 1118type=FUDesc 1119children=opList0 opList1 opList2 1120count=4 1121opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1122 1123[system.cpu2.fuPool.FUList2.opList0] 1124type=OpDesc 1125issueLat=1 1126opClass=FloatAdd 1127opLat=2 1128 1129[system.cpu2.fuPool.FUList2.opList1] 1130type=OpDesc 1131issueLat=1 1132opClass=FloatCmp 1133opLat=2 1134 1135[system.cpu2.fuPool.FUList2.opList2] 1136type=OpDesc 1137issueLat=1 1138opClass=FloatCvt 1139opLat=2 1140 1141[system.cpu2.fuPool.FUList3] 1142type=FUDesc 1143children=opList0 opList1 opList2 1144count=2 1145opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1146 1147[system.cpu2.fuPool.FUList3.opList0] 1148type=OpDesc 1149issueLat=1 1150opClass=FloatMult 1151opLat=4 1152 1153[system.cpu2.fuPool.FUList3.opList1] 1154type=OpDesc 1155issueLat=12 1156opClass=FloatDiv 1157opLat=12 1158 1159[system.cpu2.fuPool.FUList3.opList2] 1160type=OpDesc 1161issueLat=24 1162opClass=FloatSqrt 1163opLat=24 1164 1165[system.cpu2.fuPool.FUList4] 1166type=FUDesc 1167children=opList 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1276opClass=SimdFloatDiv 1277opLat=1 1278 1279[system.cpu2.fuPool.FUList5.opList16] 1280type=OpDesc 1281issueLat=1 1282opClass=SimdFloatMisc 1283opLat=1 1284 1285[system.cpu2.fuPool.FUList5.opList17] 1286type=OpDesc 1287issueLat=1 1288opClass=SimdFloatMult 1289opLat=1 1290 1291[system.cpu2.fuPool.FUList5.opList18] 1292type=OpDesc 1293issueLat=1 1294opClass=SimdFloatMultAcc 1295opLat=1 1296 1297[system.cpu2.fuPool.FUList5.opList19] 1298type=OpDesc 1299issueLat=1 1300opClass=SimdFloatSqrt 1301opLat=1 1302 1303[system.cpu2.fuPool.FUList6] 1304type=FUDesc 1305children=opList 1306count=0 1307opList=system.cpu2.fuPool.FUList6.opList 1308 1309[system.cpu2.fuPool.FUList6.opList] 1310type=OpDesc 1311issueLat=1 1312opClass=MemWrite 1313opLat=1 1314 1315[system.cpu2.fuPool.FUList7] 1316type=FUDesc 1317children=opList0 opList1 1318count=4 1319opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1320 1321[system.cpu2.fuPool.FUList7.opList0] 1322type=OpDesc 1323issueLat=1 1324opClass=MemRead 1325opLat=1 1326 1327[system.cpu2.fuPool.FUList7.opList1] 1328type=OpDesc 1329issueLat=1 1330opClass=MemWrite 1331opLat=1 1332 1333[system.cpu2.fuPool.FUList8] 1334type=FUDesc 1335children=opList 1336count=1 1337opList=system.cpu2.fuPool.FUList8.opList 1338 1339[system.cpu2.fuPool.FUList8.opList] 1340type=OpDesc 1341issueLat=3 1342opClass=IprAccess 1343opLat=3 1344 1345[system.cpu2.icache] 1346type=BaseCache 1347children=tags 1348addr_ranges=0:18446744073709551615 1349assoc=1 1350clk_domain=system.cpu_clk_domain 1351forward_snoops=true 1352hit_latency=2 1353is_top_level=true 1354max_miss_count=0 1355mshrs=4 1356prefetch_on_access=false 1357prefetcher=Null 1358response_latency=2 1359size=32768 1360system=system 1361tags=system.cpu2.icache.tags 1362tgts_per_mshr=20 1363two_queue=false 1364write_buffers=8 1365cpu_side=system.cpu2.icache_port 1366mem_side=system.toL2Bus.slave[4] 1367 1368[system.cpu2.icache.tags] 1369type=LRU 1370assoc=1 1371block_size=64 1372clk_domain=system.cpu_clk_domain 1373hit_latency=2 1374size=32768 1375 1376[system.cpu2.interrupts] 1377type=SparcInterrupts 1378 1379[system.cpu2.isa] 1380type=SparcISA 1381 1382[system.cpu2.itb] 1383type=SparcTLB 1384size=64 1385 1386[system.cpu2.tracer] 1387type=ExeTracer 1388 1389[system.cpu3] 1390type=DerivO3CPU 1391children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1392LFSTSize=1024 1393LQEntries=32 1394LSQCheckLoads=true 1395LSQDepCheckShift=4 1396SQEntries=32 1397SSITSize=1024 1398activity=0 1399backComSize=5 1400branchPred=system.cpu3.branchPred 1401cachePorts=200 1402checker=Null 1403clk_domain=system.cpu_clk_domain 1404commitToDecodeDelay=1 1405commitToFetchDelay=1 1406commitToIEWDelay=1 1407commitToRenameDelay=1 1408commitWidth=8 1409cpu_id=3 1410decodeToFetchDelay=1 1411decodeToRenameDelay=1 1412decodeWidth=8 1413dispatchWidth=8 1414do_checkpoint_insts=true 1415do_quiesce=true 1416do_statistics_insts=true 1417dtb=system.cpu3.dtb 1418fetchToDecodeDelay=1 1419fetchTrapLatency=1 1420fetchWidth=8 1421forwardComSize=5 1422fuPool=system.cpu3.fuPool 1423function_trace=false 1424function_trace_start=0 1425iewToCommitDelay=1 1426iewToDecodeDelay=1 1427iewToFetchDelay=1 1428iewToRenameDelay=1 1429interrupts=system.cpu3.interrupts 1430isa=system.cpu3.isa 1431issueToExecuteDelay=1 1432issueWidth=8 1433itb=system.cpu3.itb 1434max_insts_all_threads=0 1435max_insts_any_thread=0 1436max_loads_all_threads=0 1437max_loads_any_thread=0 1438needsTSO=false 1439numIQEntries=64 1440numPhysCCRegs=0 1441numPhysFloatRegs=256 1442numPhysIntRegs=256 1443numROBEntries=192 1444numRobs=1 1445numThreads=1 1446profile=0 1447progress_interval=0 1448renameToDecodeDelay=1 1449renameToFetchDelay=1 1450renameToIEWDelay=2 1451renameToROBDelay=1 1452renameWidth=8 1453simpoint_start_insts= 1454smtCommitPolicy=RoundRobin 1455smtFetchPolicy=SingleThread 1456smtIQPolicy=Partitioned 1457smtIQThreshold=100 1458smtLSQPolicy=Partitioned 1459smtLSQThreshold=100 1460smtNumFetchingThreads=1 1461smtROBPolicy=Partitioned 1462smtROBThreshold=100 1463squashWidth=8 1464store_set_clear_period=250000 1465switched_out=false 1466system=system 1467tracer=system.cpu3.tracer 1468trapLatency=13 1469wbDepth=1 1470wbWidth=8 1471workload=system.cpu0.workload 1472dcache_port=system.cpu3.dcache.cpu_side 1473icache_port=system.cpu3.icache.cpu_side 1474 1475[system.cpu3.branchPred] 1476type=BranchPredictor 1477BTBEntries=4096 1478BTBTagSize=16 1479RASSize=16 1480choiceCtrBits=2 1481choicePredictorSize=8192 1482globalCtrBits=2 1483globalPredictorSize=8192 1484instShiftAmt=2 1485localCtrBits=2 1486localHistoryTableSize=2048 1487localPredictorSize=2048 1488numThreads=1 1489predType=tournament 1490 1491[system.cpu3.dcache] 1492type=BaseCache 1493children=tags 1494addr_ranges=0:18446744073709551615 1495assoc=4 1496clk_domain=system.cpu_clk_domain 1497forward_snoops=true 1498hit_latency=2 1499is_top_level=true 1500max_miss_count=0 1501mshrs=4 1502prefetch_on_access=false 1503prefetcher=Null 1504response_latency=2 1505size=32768 1506system=system 1507tags=system.cpu3.dcache.tags 1508tgts_per_mshr=20 1509two_queue=false 1510write_buffers=8 1511cpu_side=system.cpu3.dcache_port 1512mem_side=system.toL2Bus.slave[7] 1513 1514[system.cpu3.dcache.tags] 1515type=LRU 1516assoc=4 1517block_size=64 1518clk_domain=system.cpu_clk_domain 1519hit_latency=2 1520size=32768 1521 1522[system.cpu3.dtb] 1523type=SparcTLB 1524size=64 1525 1526[system.cpu3.fuPool] 1527type=FUPool 1528children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1529FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1530 1531[system.cpu3.fuPool.FUList0] 1532type=FUDesc 1533children=opList 1534count=6 1535opList=system.cpu3.fuPool.FUList0.opList 1536 1537[system.cpu3.fuPool.FUList0.opList] 1538type=OpDesc 1539issueLat=1 1540opClass=IntAlu 1541opLat=1 1542 1543[system.cpu3.fuPool.FUList1] 1544type=FUDesc 1545children=opList0 opList1 1546count=2 1547opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1548 1549[system.cpu3.fuPool.FUList1.opList0] 1550type=OpDesc 1551issueLat=1 1552opClass=IntMult 1553opLat=3 1554 1555[system.cpu3.fuPool.FUList1.opList1] 1556type=OpDesc 1557issueLat=19 1558opClass=IntDiv 1559opLat=20 1560 1561[system.cpu3.fuPool.FUList2] 1562type=FUDesc 1563children=opList0 opList1 opList2 1564count=4 1565opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1566 1567[system.cpu3.fuPool.FUList2.opList0] 1568type=OpDesc 1569issueLat=1 1570opClass=FloatAdd 1571opLat=2 1572 1573[system.cpu3.fuPool.FUList2.opList1] 1574type=OpDesc 1575issueLat=1 1576opClass=FloatCmp 1577opLat=2 1578 1579[system.cpu3.fuPool.FUList2.opList2] 1580type=OpDesc 1581issueLat=1 1582opClass=FloatCvt 1583opLat=2 1584 1585[system.cpu3.fuPool.FUList3] 1586type=FUDesc 1587children=opList0 opList1 opList2 1588count=2 1589opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1590 1591[system.cpu3.fuPool.FUList3.opList0] 1592type=OpDesc 1593issueLat=1 1594opClass=FloatMult 1595opLat=4 1596 1597[system.cpu3.fuPool.FUList3.opList1] 1598type=OpDesc 1599issueLat=12 1600opClass=FloatDiv 1601opLat=12 1602 1603[system.cpu3.fuPool.FUList3.opList2] 1604type=OpDesc 1605issueLat=24 1606opClass=FloatSqrt 1607opLat=24 1608 1609[system.cpu3.fuPool.FUList4] 1610type=FUDesc 1611children=opList 1612count=0 1613opList=system.cpu3.fuPool.FUList4.opList 1614 1615[system.cpu3.fuPool.FUList4.opList] 1616type=OpDesc 1617issueLat=1 1618opClass=MemRead 1619opLat=1 1620 1621[system.cpu3.fuPool.FUList5] 1622type=FUDesc 1623children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1624count=4 1625opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1626 1627[system.cpu3.fuPool.FUList5.opList00] 1628type=OpDesc 1629issueLat=1 1630opClass=SimdAdd 1631opLat=1 1632 1633[system.cpu3.fuPool.FUList5.opList01] 1634type=OpDesc 1635issueLat=1 1636opClass=SimdAddAcc 1637opLat=1 1638 1639[system.cpu3.fuPool.FUList5.opList02] 1640type=OpDesc 1641issueLat=1 1642opClass=SimdAlu 1643opLat=1 1644 1645[system.cpu3.fuPool.FUList5.opList03] 1646type=OpDesc 1647issueLat=1 1648opClass=SimdCmp 1649opLat=1 1650 1651[system.cpu3.fuPool.FUList5.opList04] 1652type=OpDesc 1653issueLat=1 1654opClass=SimdCvt 1655opLat=1 1656 1657[system.cpu3.fuPool.FUList5.opList05] 1658type=OpDesc 1659issueLat=1 1660opClass=SimdMisc 1661opLat=1 1662 1663[system.cpu3.fuPool.FUList5.opList06] 1664type=OpDesc 1665issueLat=1 1666opClass=SimdMult 1667opLat=1 1668 1669[system.cpu3.fuPool.FUList5.opList07] 1670type=OpDesc 1671issueLat=1 1672opClass=SimdMultAcc 1673opLat=1 1674 1675[system.cpu3.fuPool.FUList5.opList08] 1676type=OpDesc 1677issueLat=1 1678opClass=SimdShift 1679opLat=1 1680 1681[system.cpu3.fuPool.FUList5.opList09] 1682type=OpDesc 1683issueLat=1 1684opClass=SimdShiftAcc 1685opLat=1 1686 1687[system.cpu3.fuPool.FUList5.opList10] 1688type=OpDesc 1689issueLat=1 1690opClass=SimdSqrt 1691opLat=1 1692 1693[system.cpu3.fuPool.FUList5.opList11] 1694type=OpDesc 1695issueLat=1 1696opClass=SimdFloatAdd 1697opLat=1 1698 1699[system.cpu3.fuPool.FUList5.opList12] 1700type=OpDesc 1701issueLat=1 1702opClass=SimdFloatAlu 1703opLat=1 1704 1705[system.cpu3.fuPool.FUList5.opList13] 1706type=OpDesc 1707issueLat=1 1708opClass=SimdFloatCmp 1709opLat=1 1710 1711[system.cpu3.fuPool.FUList5.opList14] 1712type=OpDesc 1713issueLat=1 1714opClass=SimdFloatCvt 1715opLat=1 1716 1717[system.cpu3.fuPool.FUList5.opList15] 1718type=OpDesc 1719issueLat=1 1720opClass=SimdFloatDiv 1721opLat=1 1722 1723[system.cpu3.fuPool.FUList5.opList16] 1724type=OpDesc 1725issueLat=1 1726opClass=SimdFloatMisc 1727opLat=1 1728 1729[system.cpu3.fuPool.FUList5.opList17] 1730type=OpDesc 1731issueLat=1 1732opClass=SimdFloatMult 1733opLat=1 1734 1735[system.cpu3.fuPool.FUList5.opList18] 1736type=OpDesc 1737issueLat=1 1738opClass=SimdFloatMultAcc 1739opLat=1 1740 1741[system.cpu3.fuPool.FUList5.opList19] 1742type=OpDesc 1743issueLat=1 1744opClass=SimdFloatSqrt 1745opLat=1 1746 1747[system.cpu3.fuPool.FUList6] 1748type=FUDesc 1749children=opList 1750count=0 1751opList=system.cpu3.fuPool.FUList6.opList 1752 1753[system.cpu3.fuPool.FUList6.opList] 1754type=OpDesc 1755issueLat=1 1756opClass=MemWrite 1757opLat=1 1758 1759[system.cpu3.fuPool.FUList7] 1760type=FUDesc 1761children=opList0 opList1 1762count=4 1763opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 1764 1765[system.cpu3.fuPool.FUList7.opList0] 1766type=OpDesc 1767issueLat=1 1768opClass=MemRead 1769opLat=1 1770 1771[system.cpu3.fuPool.FUList7.opList1] 1772type=OpDesc 1773issueLat=1 1774opClass=MemWrite 1775opLat=1 1776 1777[system.cpu3.fuPool.FUList8] 1778type=FUDesc 1779children=opList 1780count=1 1781opList=system.cpu3.fuPool.FUList8.opList 1782 1783[system.cpu3.fuPool.FUList8.opList] 1784type=OpDesc 1785issueLat=3 1786opClass=IprAccess 1787opLat=3 1788 1789[system.cpu3.icache] 1790type=BaseCache 1791children=tags 1792addr_ranges=0:18446744073709551615 1793assoc=1 1794clk_domain=system.cpu_clk_domain 1795forward_snoops=true 1796hit_latency=2 1797is_top_level=true 1798max_miss_count=0 1799mshrs=4 1800prefetch_on_access=false 1801prefetcher=Null 1802response_latency=2 1803size=32768 1804system=system 1805tags=system.cpu3.icache.tags 1806tgts_per_mshr=20 1807two_queue=false 1808write_buffers=8 1809cpu_side=system.cpu3.icache_port 1810mem_side=system.toL2Bus.slave[6] 1811 1812[system.cpu3.icache.tags] 1813type=LRU 1814assoc=1 1815block_size=64 1816clk_domain=system.cpu_clk_domain 1817hit_latency=2 1818size=32768 1819 1820[system.cpu3.interrupts] 1821type=SparcInterrupts 1822 1823[system.cpu3.isa] 1824type=SparcISA 1825 1826[system.cpu3.itb] 1827type=SparcTLB 1828size=64 1829 1830[system.cpu3.tracer] 1831type=ExeTracer 1832 1833[system.cpu_clk_domain] 1834type=SrcClockDomain 1835clock=500 1836voltage_domain=system.voltage_domain 1837 1838[system.l2c] 1839type=BaseCache 1840children=tags 1841addr_ranges=0:18446744073709551615 1842assoc=8 1843clk_domain=system.cpu_clk_domain 1844forward_snoops=true 1845hit_latency=20 1846is_top_level=false 1847max_miss_count=0 1848mshrs=20 1849prefetch_on_access=false 1850prefetcher=Null 1851response_latency=20 1852size=4194304 1853system=system 1854tags=system.l2c.tags 1855tgts_per_mshr=12 1856two_queue=false 1857write_buffers=8 1858cpu_side=system.toL2Bus.master[0] 1859mem_side=system.membus.slave[1] 1860 1861[system.l2c.tags] 1862type=LRU 1863assoc=8 1864block_size=64 1865clk_domain=system.cpu_clk_domain 1866hit_latency=20 1867size=4194304 1868 1869[system.membus] 1870type=CoherentBus 1871clk_domain=system.clk_domain 1872header_cycles=1 1873system=system 1874use_default_range=false 1875width=8 1876master=system.physmem.port 1877slave=system.system_port system.l2c.mem_side 1878 1879[system.physmem] 1880type=SimpleDRAM 1881activation_limit=4 1882addr_mapping=RaBaChCo 1883banks_per_rank=8 1884burst_length=8 1885channels=1 1886clk_domain=system.clk_domain 1887conf_table_reported=true 1888device_bus_width=8 1889device_rowbuffer_size=1024 1890devices_per_rank=8 1891in_addr_map=true 1892mem_sched_policy=frfcfs 1893null=false 1894page_policy=open 1895range=0:134217727 1896ranks_per_channel=2 1897read_buffer_size=32 1898static_backend_latency=10000 1899static_frontend_latency=10000 1900tBURST=5000 1901tCL=13750 1902tRCD=13750 1903tREFI=7800000 1904tRFC=300000 1905tRP=13750 1906tWTR=7500 1907tXAW=40000 1908write_buffer_size=32 1909write_thresh_perc=70 1910port=system.membus.master[0] 1911 1912[system.toL2Bus] 1913type=CoherentBus 1914clk_domain=system.cpu_clk_domain 1915header_cycles=1 1916system=system 1917use_default_range=false 1918width=8 1919master=system.l2c.cpu_side 1920slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 1921 1922[system.voltage_domain] 1923type=VoltageDomain 1924voltage=1.000000 1925 1926