config.ini revision 9885
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= 23symbolfile= 24work_begin_ckpt_count=0 25work_begin_cpu_id_exit=-1 26work_begin_exit_count=0 27work_cpus_ckpt_count=0 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 36voltage_domain=system.voltage_domain 37 38[system.cpu0] 39type=DerivO3CPU 40children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 41LFSTSize=1024 42LQEntries=32 43LSQCheckLoads=true 44LSQDepCheckShift=4 45SQEntries=32 46SSITSize=1024 47activity=0 48backComSize=5 49branchPred=system.cpu0.branchPred 50cachePorts=200 51checker=Null 52clk_domain=system.cpu_clk_domain 53commitToDecodeDelay=1 54commitToFetchDelay=1 55commitToIEWDelay=1 56commitToRenameDelay=1 57commitWidth=8 58cpu_id=0 59decodeToFetchDelay=1 60decodeToRenameDelay=1 61decodeWidth=8 62dispatchWidth=8 63do_checkpoint_insts=true 64do_quiesce=true 65do_statistics_insts=true 66dtb=system.cpu0.dtb 67fetchToDecodeDelay=1 68fetchTrapLatency=1 69fetchWidth=8 70forwardComSize=5 71fuPool=system.cpu0.fuPool 72function_trace=false 73function_trace_start=0 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78interrupts=system.cpu0.interrupts 79isa=system.cpu0.isa 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu0.itb 83max_insts_all_threads=0 84max_insts_any_thread=0 85max_loads_all_threads=0 86max_loads_any_thread=0 87needsTSO=false 88numIQEntries=64 89numPhysFloatRegs=256 90numPhysIntRegs=256 91numROBEntries=192 92numRobs=1 93numThreads=1 94profile=0 95progress_interval=0 96renameToDecodeDelay=1 97renameToFetchDelay=1 98renameToIEWDelay=2 99renameToROBDelay=1 100renameWidth=8 101simpoint_start_insts= 102smtCommitPolicy=RoundRobin 103smtFetchPolicy=SingleThread 104smtIQPolicy=Partitioned 105smtIQThreshold=100 106smtLSQPolicy=Partitioned 107smtLSQThreshold=100 108smtNumFetchingThreads=1 109smtROBPolicy=Partitioned 110smtROBThreshold=100 111squashWidth=8 112store_set_clear_period=250000 113switched_out=false 114system=system 115tracer=system.cpu0.tracer 116trapLatency=13 117wbDepth=1 118wbWidth=8 119workload=system.cpu0.workload 120dcache_port=system.cpu0.dcache.cpu_side 121icache_port=system.cpu0.icache.cpu_side 122 123[system.cpu0.branchPred] 124type=BranchPredictor 125BTBEntries=4096 126BTBTagSize=16 127RASSize=16 128choiceCtrBits=2 129choicePredictorSize=8192 130globalCtrBits=2 131globalPredictorSize=8192 132instShiftAmt=2 133localCtrBits=2 134localHistoryTableSize=2048 135localPredictorSize=2048 136numThreads=1 137predType=tournament 138 139[system.cpu0.dcache] 140type=BaseCache 141children=tags 142addr_ranges=0:18446744073709551615 143assoc=4 144clk_domain=system.cpu_clk_domain 145forward_snoops=true 146hit_latency=2 147is_top_level=true 148max_miss_count=0 149mshrs=4 150prefetch_on_access=false 151prefetcher=Null 152response_latency=2 153size=32768 154system=system 155tags=system.cpu0.dcache.tags 156tgts_per_mshr=20 157two_queue=false 158write_buffers=8 159cpu_side=system.cpu0.dcache_port 160mem_side=system.toL2Bus.slave[1] 161 162[system.cpu0.dcache.tags] 163type=LRU 164assoc=4 165block_size=64 166clk_domain=system.cpu_clk_domain 167hit_latency=2 168size=32768 169 170[system.cpu0.dtb] 171type=SparcTLB 172size=64 173 174[system.cpu0.fuPool] 175type=FUPool 176children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 177FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 178 179[system.cpu0.fuPool.FUList0] 180type=FUDesc 181children=opList 182count=6 183opList=system.cpu0.fuPool.FUList0.opList 184 185[system.cpu0.fuPool.FUList0.opList] 186type=OpDesc 187issueLat=1 188opClass=IntAlu 189opLat=1 190 191[system.cpu0.fuPool.FUList1] 192type=FUDesc 193children=opList0 opList1 194count=2 195opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 196 197[system.cpu0.fuPool.FUList1.opList0] 198type=OpDesc 199issueLat=1 200opClass=IntMult 201opLat=3 202 203[system.cpu0.fuPool.FUList1.opList1] 204type=OpDesc 205issueLat=19 206opClass=IntDiv 207opLat=20 208 209[system.cpu0.fuPool.FUList2] 210type=FUDesc 211children=opList0 opList1 opList2 212count=4 213opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 214 215[system.cpu0.fuPool.FUList2.opList0] 216type=OpDesc 217issueLat=1 218opClass=FloatAdd 219opLat=2 220 221[system.cpu0.fuPool.FUList2.opList1] 222type=OpDesc 223issueLat=1 224opClass=FloatCmp 225opLat=2 226 227[system.cpu0.fuPool.FUList2.opList2] 228type=OpDesc 229issueLat=1 230opClass=FloatCvt 231opLat=2 232 233[system.cpu0.fuPool.FUList3] 234type=FUDesc 235children=opList0 opList1 opList2 236count=2 237opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 238 239[system.cpu0.fuPool.FUList3.opList0] 240type=OpDesc 241issueLat=1 242opClass=FloatMult 243opLat=4 244 245[system.cpu0.fuPool.FUList3.opList1] 246type=OpDesc 247issueLat=12 248opClass=FloatDiv 249opLat=12 250 251[system.cpu0.fuPool.FUList3.opList2] 252type=OpDesc 253issueLat=24 254opClass=FloatSqrt 255opLat=24 256 257[system.cpu0.fuPool.FUList4] 258type=FUDesc 259children=opList 260count=0 261opList=system.cpu0.fuPool.FUList4.opList 262 263[system.cpu0.fuPool.FUList4.opList] 264type=OpDesc 265issueLat=1 266opClass=MemRead 267opLat=1 268 269[system.cpu0.fuPool.FUList5] 270type=FUDesc 271children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 272count=4 273opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 274 275[system.cpu0.fuPool.FUList5.opList00] 276type=OpDesc 277issueLat=1 278opClass=SimdAdd 279opLat=1 280 281[system.cpu0.fuPool.FUList5.opList01] 282type=OpDesc 283issueLat=1 284opClass=SimdAddAcc 285opLat=1 286 287[system.cpu0.fuPool.FUList5.opList02] 288type=OpDesc 289issueLat=1 290opClass=SimdAlu 291opLat=1 292 293[system.cpu0.fuPool.FUList5.opList03] 294type=OpDesc 295issueLat=1 296opClass=SimdCmp 297opLat=1 298 299[system.cpu0.fuPool.FUList5.opList04] 300type=OpDesc 301issueLat=1 302opClass=SimdCvt 303opLat=1 304 305[system.cpu0.fuPool.FUList5.opList05] 306type=OpDesc 307issueLat=1 308opClass=SimdMisc 309opLat=1 310 311[system.cpu0.fuPool.FUList5.opList06] 312type=OpDesc 313issueLat=1 314opClass=SimdMult 315opLat=1 316 317[system.cpu0.fuPool.FUList5.opList07] 318type=OpDesc 319issueLat=1 320opClass=SimdMultAcc 321opLat=1 322 323[system.cpu0.fuPool.FUList5.opList08] 324type=OpDesc 325issueLat=1 326opClass=SimdShift 327opLat=1 328 329[system.cpu0.fuPool.FUList5.opList09] 330type=OpDesc 331issueLat=1 332opClass=SimdShiftAcc 333opLat=1 334 335[system.cpu0.fuPool.FUList5.opList10] 336type=OpDesc 337issueLat=1 338opClass=SimdSqrt 339opLat=1 340 341[system.cpu0.fuPool.FUList5.opList11] 342type=OpDesc 343issueLat=1 344opClass=SimdFloatAdd 345opLat=1 346 347[system.cpu0.fuPool.FUList5.opList12] 348type=OpDesc 349issueLat=1 350opClass=SimdFloatAlu 351opLat=1 352 353[system.cpu0.fuPool.FUList5.opList13] 354type=OpDesc 355issueLat=1 356opClass=SimdFloatCmp 357opLat=1 358 359[system.cpu0.fuPool.FUList5.opList14] 360type=OpDesc 361issueLat=1 362opClass=SimdFloatCvt 363opLat=1 364 365[system.cpu0.fuPool.FUList5.opList15] 366type=OpDesc 367issueLat=1 368opClass=SimdFloatDiv 369opLat=1 370 371[system.cpu0.fuPool.FUList5.opList16] 372type=OpDesc 373issueLat=1 374opClass=SimdFloatMisc 375opLat=1 376 377[system.cpu0.fuPool.FUList5.opList17] 378type=OpDesc 379issueLat=1 380opClass=SimdFloatMult 381opLat=1 382 383[system.cpu0.fuPool.FUList5.opList18] 384type=OpDesc 385issueLat=1 386opClass=SimdFloatMultAcc 387opLat=1 388 389[system.cpu0.fuPool.FUList5.opList19] 390type=OpDesc 391issueLat=1 392opClass=SimdFloatSqrt 393opLat=1 394 395[system.cpu0.fuPool.FUList6] 396type=FUDesc 397children=opList 398count=0 399opList=system.cpu0.fuPool.FUList6.opList 400 401[system.cpu0.fuPool.FUList6.opList] 402type=OpDesc 403issueLat=1 404opClass=MemWrite 405opLat=1 406 407[system.cpu0.fuPool.FUList7] 408type=FUDesc 409children=opList0 opList1 410count=4 411opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 412 413[system.cpu0.fuPool.FUList7.opList0] 414type=OpDesc 415issueLat=1 416opClass=MemRead 417opLat=1 418 419[system.cpu0.fuPool.FUList7.opList1] 420type=OpDesc 421issueLat=1 422opClass=MemWrite 423opLat=1 424 425[system.cpu0.fuPool.FUList8] 426type=FUDesc 427children=opList 428count=1 429opList=system.cpu0.fuPool.FUList8.opList 430 431[system.cpu0.fuPool.FUList8.opList] 432type=OpDesc 433issueLat=3 434opClass=IprAccess 435opLat=3 436 437[system.cpu0.icache] 438type=BaseCache 439children=tags 440addr_ranges=0:18446744073709551615 441assoc=1 442clk_domain=system.cpu_clk_domain 443forward_snoops=true 444hit_latency=2 445is_top_level=true 446max_miss_count=0 447mshrs=4 448prefetch_on_access=false 449prefetcher=Null 450response_latency=2 451size=32768 452system=system 453tags=system.cpu0.icache.tags 454tgts_per_mshr=20 455two_queue=false 456write_buffers=8 457cpu_side=system.cpu0.icache_port 458mem_side=system.toL2Bus.slave[0] 459 460[system.cpu0.icache.tags] 461type=LRU 462assoc=1 463block_size=64 464clk_domain=system.cpu_clk_domain 465hit_latency=2 466size=32768 467 468[system.cpu0.interrupts] 469type=SparcInterrupts 470 471[system.cpu0.isa] 472type=SparcISA 473 474[system.cpu0.itb] 475type=SparcTLB 476size=64 477 478[system.cpu0.tracer] 479type=ExeTracer 480 481[system.cpu0.workload] 482type=LiveProcess 483cmd=test_atomic 4 484cwd= 485egid=100 486env= 487errout=cerr 488euid=100 489executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic 490gid=100 491input=cin 492max_stack_size=67108864 493output=cout 494pid=100 495ppid=99 496simpoint=0 497system=system 498uid=100 499 500[system.cpu1] 501type=DerivO3CPU 502children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 503LFSTSize=1024 504LQEntries=32 505LSQCheckLoads=true 506LSQDepCheckShift=4 507SQEntries=32 508SSITSize=1024 509activity=0 510backComSize=5 511branchPred=system.cpu1.branchPred 512cachePorts=200 513checker=Null 514clk_domain=system.cpu_clk_domain 515commitToDecodeDelay=1 516commitToFetchDelay=1 517commitToIEWDelay=1 518commitToRenameDelay=1 519commitWidth=8 520cpu_id=1 521decodeToFetchDelay=1 522decodeToRenameDelay=1 523decodeWidth=8 524dispatchWidth=8 525do_checkpoint_insts=true 526do_quiesce=true 527do_statistics_insts=true 528dtb=system.cpu1.dtb 529fetchToDecodeDelay=1 530fetchTrapLatency=1 531fetchWidth=8 532forwardComSize=5 533fuPool=system.cpu1.fuPool 534function_trace=false 535function_trace_start=0 536iewToCommitDelay=1 537iewToDecodeDelay=1 538iewToFetchDelay=1 539iewToRenameDelay=1 540interrupts=system.cpu1.interrupts 541isa=system.cpu1.isa 542issueToExecuteDelay=1 543issueWidth=8 544itb=system.cpu1.itb 545max_insts_all_threads=0 546max_insts_any_thread=0 547max_loads_all_threads=0 548max_loads_any_thread=0 549needsTSO=false 550numIQEntries=64 551numPhysFloatRegs=256 552numPhysIntRegs=256 553numROBEntries=192 554numRobs=1 555numThreads=1 556profile=0 557progress_interval=0 558renameToDecodeDelay=1 559renameToFetchDelay=1 560renameToIEWDelay=2 561renameToROBDelay=1 562renameWidth=8 563simpoint_start_insts= 564smtCommitPolicy=RoundRobin 565smtFetchPolicy=SingleThread 566smtIQPolicy=Partitioned 567smtIQThreshold=100 568smtLSQPolicy=Partitioned 569smtLSQThreshold=100 570smtNumFetchingThreads=1 571smtROBPolicy=Partitioned 572smtROBThreshold=100 573squashWidth=8 574store_set_clear_period=250000 575switched_out=false 576system=system 577tracer=system.cpu1.tracer 578trapLatency=13 579wbDepth=1 580wbWidth=8 581workload=system.cpu0.workload 582dcache_port=system.cpu1.dcache.cpu_side 583icache_port=system.cpu1.icache.cpu_side 584 585[system.cpu1.branchPred] 586type=BranchPredictor 587BTBEntries=4096 588BTBTagSize=16 589RASSize=16 590choiceCtrBits=2 591choicePredictorSize=8192 592globalCtrBits=2 593globalPredictorSize=8192 594instShiftAmt=2 595localCtrBits=2 596localHistoryTableSize=2048 597localPredictorSize=2048 598numThreads=1 599predType=tournament 600 601[system.cpu1.dcache] 602type=BaseCache 603children=tags 604addr_ranges=0:18446744073709551615 605assoc=4 606clk_domain=system.cpu_clk_domain 607forward_snoops=true 608hit_latency=2 609is_top_level=true 610max_miss_count=0 611mshrs=4 612prefetch_on_access=false 613prefetcher=Null 614response_latency=2 615size=32768 616system=system 617tags=system.cpu1.dcache.tags 618tgts_per_mshr=20 619two_queue=false 620write_buffers=8 621cpu_side=system.cpu1.dcache_port 622mem_side=system.toL2Bus.slave[3] 623 624[system.cpu1.dcache.tags] 625type=LRU 626assoc=4 627block_size=64 628clk_domain=system.cpu_clk_domain 629hit_latency=2 630size=32768 631 632[system.cpu1.dtb] 633type=SparcTLB 634size=64 635 636[system.cpu1.fuPool] 637type=FUPool 638children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 639FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 640 641[system.cpu1.fuPool.FUList0] 642type=FUDesc 643children=opList 644count=6 645opList=system.cpu1.fuPool.FUList0.opList 646 647[system.cpu1.fuPool.FUList0.opList] 648type=OpDesc 649issueLat=1 650opClass=IntAlu 651opLat=1 652 653[system.cpu1.fuPool.FUList1] 654type=FUDesc 655children=opList0 opList1 656count=2 657opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 658 659[system.cpu1.fuPool.FUList1.opList0] 660type=OpDesc 661issueLat=1 662opClass=IntMult 663opLat=3 664 665[system.cpu1.fuPool.FUList1.opList1] 666type=OpDesc 667issueLat=19 668opClass=IntDiv 669opLat=20 670 671[system.cpu1.fuPool.FUList2] 672type=FUDesc 673children=opList0 opList1 opList2 674count=4 675opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 676 677[system.cpu1.fuPool.FUList2.opList0] 678type=OpDesc 679issueLat=1 680opClass=FloatAdd 681opLat=2 682 683[system.cpu1.fuPool.FUList2.opList1] 684type=OpDesc 685issueLat=1 686opClass=FloatCmp 687opLat=2 688 689[system.cpu1.fuPool.FUList2.opList2] 690type=OpDesc 691issueLat=1 692opClass=FloatCvt 693opLat=2 694 695[system.cpu1.fuPool.FUList3] 696type=FUDesc 697children=opList0 opList1 opList2 698count=2 699opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 700 701[system.cpu1.fuPool.FUList3.opList0] 702type=OpDesc 703issueLat=1 704opClass=FloatMult 705opLat=4 706 707[system.cpu1.fuPool.FUList3.opList1] 708type=OpDesc 709issueLat=12 710opClass=FloatDiv 711opLat=12 712 713[system.cpu1.fuPool.FUList3.opList2] 714type=OpDesc 715issueLat=24 716opClass=FloatSqrt 717opLat=24 718 719[system.cpu1.fuPool.FUList4] 720type=FUDesc 721children=opList 722count=0 723opList=system.cpu1.fuPool.FUList4.opList 724 725[system.cpu1.fuPool.FUList4.opList] 726type=OpDesc 727issueLat=1 728opClass=MemRead 729opLat=1 730 731[system.cpu1.fuPool.FUList5] 732type=FUDesc 733children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 734count=4 735opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 736 737[system.cpu1.fuPool.FUList5.opList00] 738type=OpDesc 739issueLat=1 740opClass=SimdAdd 741opLat=1 742 743[system.cpu1.fuPool.FUList5.opList01] 744type=OpDesc 745issueLat=1 746opClass=SimdAddAcc 747opLat=1 748 749[system.cpu1.fuPool.FUList5.opList02] 750type=OpDesc 751issueLat=1 752opClass=SimdAlu 753opLat=1 754 755[system.cpu1.fuPool.FUList5.opList03] 756type=OpDesc 757issueLat=1 758opClass=SimdCmp 759opLat=1 760 761[system.cpu1.fuPool.FUList5.opList04] 762type=OpDesc 763issueLat=1 764opClass=SimdCvt 765opLat=1 766 767[system.cpu1.fuPool.FUList5.opList05] 768type=OpDesc 769issueLat=1 770opClass=SimdMisc 771opLat=1 772 773[system.cpu1.fuPool.FUList5.opList06] 774type=OpDesc 775issueLat=1 776opClass=SimdMult 777opLat=1 778 779[system.cpu1.fuPool.FUList5.opList07] 780type=OpDesc 781issueLat=1 782opClass=SimdMultAcc 783opLat=1 784 785[system.cpu1.fuPool.FUList5.opList08] 786type=OpDesc 787issueLat=1 788opClass=SimdShift 789opLat=1 790 791[system.cpu1.fuPool.FUList5.opList09] 792type=OpDesc 793issueLat=1 794opClass=SimdShiftAcc 795opLat=1 796 797[system.cpu1.fuPool.FUList5.opList10] 798type=OpDesc 799issueLat=1 800opClass=SimdSqrt 801opLat=1 802 803[system.cpu1.fuPool.FUList5.opList11] 804type=OpDesc 805issueLat=1 806opClass=SimdFloatAdd 807opLat=1 808 809[system.cpu1.fuPool.FUList5.opList12] 810type=OpDesc 811issueLat=1 812opClass=SimdFloatAlu 813opLat=1 814 815[system.cpu1.fuPool.FUList5.opList13] 816type=OpDesc 817issueLat=1 818opClass=SimdFloatCmp 819opLat=1 820 821[system.cpu1.fuPool.FUList5.opList14] 822type=OpDesc 823issueLat=1 824opClass=SimdFloatCvt 825opLat=1 826 827[system.cpu1.fuPool.FUList5.opList15] 828type=OpDesc 829issueLat=1 830opClass=SimdFloatDiv 831opLat=1 832 833[system.cpu1.fuPool.FUList5.opList16] 834type=OpDesc 835issueLat=1 836opClass=SimdFloatMisc 837opLat=1 838 839[system.cpu1.fuPool.FUList5.opList17] 840type=OpDesc 841issueLat=1 842opClass=SimdFloatMult 843opLat=1 844 845[system.cpu1.fuPool.FUList5.opList18] 846type=OpDesc 847issueLat=1 848opClass=SimdFloatMultAcc 849opLat=1 850 851[system.cpu1.fuPool.FUList5.opList19] 852type=OpDesc 853issueLat=1 854opClass=SimdFloatSqrt 855opLat=1 856 857[system.cpu1.fuPool.FUList6] 858type=FUDesc 859children=opList 860count=0 861opList=system.cpu1.fuPool.FUList6.opList 862 863[system.cpu1.fuPool.FUList6.opList] 864type=OpDesc 865issueLat=1 866opClass=MemWrite 867opLat=1 868 869[system.cpu1.fuPool.FUList7] 870type=FUDesc 871children=opList0 opList1 872count=4 873opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 874 875[system.cpu1.fuPool.FUList7.opList0] 876type=OpDesc 877issueLat=1 878opClass=MemRead 879opLat=1 880 881[system.cpu1.fuPool.FUList7.opList1] 882type=OpDesc 883issueLat=1 884opClass=MemWrite 885opLat=1 886 887[system.cpu1.fuPool.FUList8] 888type=FUDesc 889children=opList 890count=1 891opList=system.cpu1.fuPool.FUList8.opList 892 893[system.cpu1.fuPool.FUList8.opList] 894type=OpDesc 895issueLat=3 896opClass=IprAccess 897opLat=3 898 899[system.cpu1.icache] 900type=BaseCache 901children=tags 902addr_ranges=0:18446744073709551615 903assoc=1 904clk_domain=system.cpu_clk_domain 905forward_snoops=true 906hit_latency=2 907is_top_level=true 908max_miss_count=0 909mshrs=4 910prefetch_on_access=false 911prefetcher=Null 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961commitToRenameDelay=1 962commitWidth=8 963cpu_id=2 964decodeToFetchDelay=1 965decodeToRenameDelay=1 966decodeWidth=8 967dispatchWidth=8 968do_checkpoint_insts=true 969do_quiesce=true 970do_statistics_insts=true 971dtb=system.cpu2.dtb 972fetchToDecodeDelay=1 973fetchTrapLatency=1 974fetchWidth=8 975forwardComSize=5 976fuPool=system.cpu2.fuPool 977function_trace=false 978function_trace_start=0 979iewToCommitDelay=1 980iewToDecodeDelay=1 981iewToFetchDelay=1 982iewToRenameDelay=1 983interrupts=system.cpu2.interrupts 984isa=system.cpu2.isa 985issueToExecuteDelay=1 986issueWidth=8 987itb=system.cpu2.itb 988max_insts_all_threads=0 989max_insts_any_thread=0 990max_loads_all_threads=0 991max_loads_any_thread=0 992needsTSO=false 993numIQEntries=64 994numPhysFloatRegs=256 995numPhysIntRegs=256 996numROBEntries=192 997numRobs=1 998numThreads=1 999profile=0 1000progress_interval=0 1001renameToDecodeDelay=1 1002renameToFetchDelay=1 1003renameToIEWDelay=2 1004renameToROBDelay=1 1005renameWidth=8 1006simpoint_start_insts= 1007smtCommitPolicy=RoundRobin 1008smtFetchPolicy=SingleThread 1009smtIQPolicy=Partitioned 1010smtIQThreshold=100 1011smtLSQPolicy=Partitioned 1012smtLSQThreshold=100 1013smtNumFetchingThreads=1 1014smtROBPolicy=Partitioned 1015smtROBThreshold=100 1016squashWidth=8 1017store_set_clear_period=250000 1018switched_out=false 1019system=system 1020tracer=system.cpu2.tracer 1021trapLatency=13 1022wbDepth=1 1023wbWidth=8 1024workload=system.cpu0.workload 1025dcache_port=system.cpu2.dcache.cpu_side 1026icache_port=system.cpu2.icache.cpu_side 1027 1028[system.cpu2.branchPred] 1029type=BranchPredictor 1030BTBEntries=4096 1031BTBTagSize=16 1032RASSize=16 1033choiceCtrBits=2 1034choicePredictorSize=8192 1035globalCtrBits=2 1036globalPredictorSize=8192 1037instShiftAmt=2 1038localCtrBits=2 1039localHistoryTableSize=2048 1040localPredictorSize=2048 1041numThreads=1 1042predType=tournament 1043 1044[system.cpu2.dcache] 1045type=BaseCache 1046children=tags 1047addr_ranges=0:18446744073709551615 1048assoc=4 1049clk_domain=system.cpu_clk_domain 1050forward_snoops=true 1051hit_latency=2 1052is_top_level=true 1053max_miss_count=0 1054mshrs=4 1055prefetch_on_access=false 1056prefetcher=Null 1057response_latency=2 1058size=32768 1059system=system 1060tags=system.cpu2.dcache.tags 1061tgts_per_mshr=20 1062two_queue=false 1063write_buffers=8 1064cpu_side=system.cpu2.dcache_port 1065mem_side=system.toL2Bus.slave[5] 1066 1067[system.cpu2.dcache.tags] 1068type=LRU 1069assoc=4 1070block_size=64 1071clk_domain=system.cpu_clk_domain 1072hit_latency=2 1073size=32768 1074 1075[system.cpu2.dtb] 1076type=SparcTLB 1077size=64 1078 1079[system.cpu2.fuPool] 1080type=FUPool 1081children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1082FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 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1282[system.cpu2.fuPool.FUList5.opList17] 1283type=OpDesc 1284issueLat=1 1285opClass=SimdFloatMult 1286opLat=1 1287 1288[system.cpu2.fuPool.FUList5.opList18] 1289type=OpDesc 1290issueLat=1 1291opClass=SimdFloatMultAcc 1292opLat=1 1293 1294[system.cpu2.fuPool.FUList5.opList19] 1295type=OpDesc 1296issueLat=1 1297opClass=SimdFloatSqrt 1298opLat=1 1299 1300[system.cpu2.fuPool.FUList6] 1301type=FUDesc 1302children=opList 1303count=0 1304opList=system.cpu2.fuPool.FUList6.opList 1305 1306[system.cpu2.fuPool.FUList6.opList] 1307type=OpDesc 1308issueLat=1 1309opClass=MemWrite 1310opLat=1 1311 1312[system.cpu2.fuPool.FUList7] 1313type=FUDesc 1314children=opList0 opList1 1315count=4 1316opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1317 1318[system.cpu2.fuPool.FUList7.opList0] 1319type=OpDesc 1320issueLat=1 1321opClass=MemRead 1322opLat=1 1323 1324[system.cpu2.fuPool.FUList7.opList1] 1325type=OpDesc 1326issueLat=1 1327opClass=MemWrite 1328opLat=1 1329 1330[system.cpu2.fuPool.FUList8] 1331type=FUDesc 1332children=opList 1333count=1 1334opList=system.cpu2.fuPool.FUList8.opList 1335 1336[system.cpu2.fuPool.FUList8.opList] 1337type=OpDesc 1338issueLat=3 1339opClass=IprAccess 1340opLat=3 1341 1342[system.cpu2.icache] 1343type=BaseCache 1344children=tags 1345addr_ranges=0:18446744073709551615 1346assoc=1 1347clk_domain=system.cpu_clk_domain 1348forward_snoops=true 1349hit_latency=2 1350is_top_level=true 1351max_miss_count=0 1352mshrs=4 1353prefetch_on_access=false 1354prefetcher=Null 1355response_latency=2 1356size=32768 1357system=system 1358tags=system.cpu2.icache.tags 1359tgts_per_mshr=20 1360two_queue=false 1361write_buffers=8 1362cpu_side=system.cpu2.icache_port 1363mem_side=system.toL2Bus.slave[4] 1364 1365[system.cpu2.icache.tags] 1366type=LRU 1367assoc=1 1368block_size=64 1369clk_domain=system.cpu_clk_domain 1370hit_latency=2 1371size=32768 1372 1373[system.cpu2.interrupts] 1374type=SparcInterrupts 1375 1376[system.cpu2.isa] 1377type=SparcISA 1378 1379[system.cpu2.itb] 1380type=SparcTLB 1381size=64 1382 1383[system.cpu2.tracer] 1384type=ExeTracer 1385 1386[system.cpu3] 1387type=DerivO3CPU 1388children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1389LFSTSize=1024 1390LQEntries=32 1391LSQCheckLoads=true 1392LSQDepCheckShift=4 1393SQEntries=32 1394SSITSize=1024 1395activity=0 1396backComSize=5 1397branchPred=system.cpu3.branchPred 1398cachePorts=200 1399checker=Null 1400clk_domain=system.cpu_clk_domain 1401commitToDecodeDelay=1 1402commitToFetchDelay=1 1403commitToIEWDelay=1 1404commitToRenameDelay=1 1405commitWidth=8 1406cpu_id=3 1407decodeToFetchDelay=1 1408decodeToRenameDelay=1 1409decodeWidth=8 1410dispatchWidth=8 1411do_checkpoint_insts=true 1412do_quiesce=true 1413do_statistics_insts=true 1414dtb=system.cpu3.dtb 1415fetchToDecodeDelay=1 1416fetchTrapLatency=1 1417fetchWidth=8 1418forwardComSize=5 1419fuPool=system.cpu3.fuPool 1420function_trace=false 1421function_trace_start=0 1422iewToCommitDelay=1 1423iewToDecodeDelay=1 1424iewToFetchDelay=1 1425iewToRenameDelay=1 1426interrupts=system.cpu3.interrupts 1427isa=system.cpu3.isa 1428issueToExecuteDelay=1 1429issueWidth=8 1430itb=system.cpu3.itb 1431max_insts_all_threads=0 1432max_insts_any_thread=0 1433max_loads_all_threads=0 1434max_loads_any_thread=0 1435needsTSO=false 1436numIQEntries=64 1437numPhysFloatRegs=256 1438numPhysIntRegs=256 1439numROBEntries=192 1440numRobs=1 1441numThreads=1 1442profile=0 1443progress_interval=0 1444renameToDecodeDelay=1 1445renameToFetchDelay=1 1446renameToIEWDelay=2 1447renameToROBDelay=1 1448renameWidth=8 1449simpoint_start_insts= 1450smtCommitPolicy=RoundRobin 1451smtFetchPolicy=SingleThread 1452smtIQPolicy=Partitioned 1453smtIQThreshold=100 1454smtLSQPolicy=Partitioned 1455smtLSQThreshold=100 1456smtNumFetchingThreads=1 1457smtROBPolicy=Partitioned 1458smtROBThreshold=100 1459squashWidth=8 1460store_set_clear_period=250000 1461switched_out=false 1462system=system 1463tracer=system.cpu3.tracer 1464trapLatency=13 1465wbDepth=1 1466wbWidth=8 1467workload=system.cpu0.workload 1468dcache_port=system.cpu3.dcache.cpu_side 1469icache_port=system.cpu3.icache.cpu_side 1470 1471[system.cpu3.branchPred] 1472type=BranchPredictor 1473BTBEntries=4096 1474BTBTagSize=16 1475RASSize=16 1476choiceCtrBits=2 1477choicePredictorSize=8192 1478globalCtrBits=2 1479globalPredictorSize=8192 1480instShiftAmt=2 1481localCtrBits=2 1482localHistoryTableSize=2048 1483localPredictorSize=2048 1484numThreads=1 1485predType=tournament 1486 1487[system.cpu3.dcache] 1488type=BaseCache 1489children=tags 1490addr_ranges=0:18446744073709551615 1491assoc=4 1492clk_domain=system.cpu_clk_domain 1493forward_snoops=true 1494hit_latency=2 1495is_top_level=true 1496max_miss_count=0 1497mshrs=4 1498prefetch_on_access=false 1499prefetcher=Null 1500response_latency=2 1501size=32768 1502system=system 1503tags=system.cpu3.dcache.tags 1504tgts_per_mshr=20 1505two_queue=false 1506write_buffers=8 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system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1586 1587[system.cpu3.fuPool.FUList3.opList0] 1588type=OpDesc 1589issueLat=1 1590opClass=FloatMult 1591opLat=4 1592 1593[system.cpu3.fuPool.FUList3.opList1] 1594type=OpDesc 1595issueLat=12 1596opClass=FloatDiv 1597opLat=12 1598 1599[system.cpu3.fuPool.FUList3.opList2] 1600type=OpDesc 1601issueLat=24 1602opClass=FloatSqrt 1603opLat=24 1604 1605[system.cpu3.fuPool.FUList4] 1606type=FUDesc 1607children=opList 1608count=0 1609opList=system.cpu3.fuPool.FUList4.opList 1610 1611[system.cpu3.fuPool.FUList4.opList] 1612type=OpDesc 1613issueLat=1 1614opClass=MemRead 1615opLat=1 1616 1617[system.cpu3.fuPool.FUList5] 1618type=FUDesc 1619children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1620count=4 1621opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1622 1623[system.cpu3.fuPool.FUList5.opList00] 1624type=OpDesc 1625issueLat=1 1626opClass=SimdAdd 1627opLat=1 1628 1629[system.cpu3.fuPool.FUList5.opList01] 1630type=OpDesc 1631issueLat=1 1632opClass=SimdAddAcc 1633opLat=1 1634 1635[system.cpu3.fuPool.FUList5.opList02] 1636type=OpDesc 1637issueLat=1 1638opClass=SimdAlu 1639opLat=1 1640 1641[system.cpu3.fuPool.FUList5.opList03] 1642type=OpDesc 1643issueLat=1 1644opClass=SimdCmp 1645opLat=1 1646 1647[system.cpu3.fuPool.FUList5.opList04] 1648type=OpDesc 1649issueLat=1 1650opClass=SimdCvt 1651opLat=1 1652 1653[system.cpu3.fuPool.FUList5.opList05] 1654type=OpDesc 1655issueLat=1 1656opClass=SimdMisc 1657opLat=1 1658 1659[system.cpu3.fuPool.FUList5.opList06] 1660type=OpDesc 1661issueLat=1 1662opClass=SimdMult 1663opLat=1 1664 1665[system.cpu3.fuPool.FUList5.opList07] 1666type=OpDesc 1667issueLat=1 1668opClass=SimdMultAcc 1669opLat=1 1670 1671[system.cpu3.fuPool.FUList5.opList08] 1672type=OpDesc 1673issueLat=1 1674opClass=SimdShift 1675opLat=1 1676 1677[system.cpu3.fuPool.FUList5.opList09] 1678type=OpDesc 1679issueLat=1 1680opClass=SimdShiftAcc 1681opLat=1 1682 1683[system.cpu3.fuPool.FUList5.opList10] 1684type=OpDesc 1685issueLat=1 1686opClass=SimdSqrt 1687opLat=1 1688 1689[system.cpu3.fuPool.FUList5.opList11] 1690type=OpDesc 1691issueLat=1 1692opClass=SimdFloatAdd 1693opLat=1 1694 1695[system.cpu3.fuPool.FUList5.opList12] 1696type=OpDesc 1697issueLat=1 1698opClass=SimdFloatAlu 1699opLat=1 1700 1701[system.cpu3.fuPool.FUList5.opList13] 1702type=OpDesc 1703issueLat=1 1704opClass=SimdFloatCmp 1705opLat=1 1706 1707[system.cpu3.fuPool.FUList5.opList14] 1708type=OpDesc 1709issueLat=1 1710opClass=SimdFloatCvt 1711opLat=1 1712 1713[system.cpu3.fuPool.FUList5.opList15] 1714type=OpDesc 1715issueLat=1 1716opClass=SimdFloatDiv 1717opLat=1 1718 1719[system.cpu3.fuPool.FUList5.opList16] 1720type=OpDesc 1721issueLat=1 1722opClass=SimdFloatMisc 1723opLat=1 1724 1725[system.cpu3.fuPool.FUList5.opList17] 1726type=OpDesc 1727issueLat=1 1728opClass=SimdFloatMult 1729opLat=1 1730 1731[system.cpu3.fuPool.FUList5.opList18] 1732type=OpDesc 1733issueLat=1 1734opClass=SimdFloatMultAcc 1735opLat=1 1736 1737[system.cpu3.fuPool.FUList5.opList19] 1738type=OpDesc 1739issueLat=1 1740opClass=SimdFloatSqrt 1741opLat=1 1742 1743[system.cpu3.fuPool.FUList6] 1744type=FUDesc 1745children=opList 1746count=0 1747opList=system.cpu3.fuPool.FUList6.opList 1748 1749[system.cpu3.fuPool.FUList6.opList] 1750type=OpDesc 1751issueLat=1 1752opClass=MemWrite 1753opLat=1 1754 1755[system.cpu3.fuPool.FUList7] 1756type=FUDesc 1757children=opList0 opList1 1758count=4 1759opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 1760 1761[system.cpu3.fuPool.FUList7.opList0] 1762type=OpDesc 1763issueLat=1 1764opClass=MemRead 1765opLat=1 1766 1767[system.cpu3.fuPool.FUList7.opList1] 1768type=OpDesc 1769issueLat=1 1770opClass=MemWrite 1771opLat=1 1772 1773[system.cpu3.fuPool.FUList8] 1774type=FUDesc 1775children=opList 1776count=1 1777opList=system.cpu3.fuPool.FUList8.opList 1778 1779[system.cpu3.fuPool.FUList8.opList] 1780type=OpDesc 1781issueLat=3 1782opClass=IprAccess 1783opLat=3 1784 1785[system.cpu3.icache] 1786type=BaseCache 1787children=tags 1788addr_ranges=0:18446744073709551615 1789assoc=1 1790clk_domain=system.cpu_clk_domain 1791forward_snoops=true 1792hit_latency=2 1793is_top_level=true 1794max_miss_count=0 1795mshrs=4 1796prefetch_on_access=false 1797prefetcher=Null 1798response_latency=2 1799size=32768 1800system=system 1801tags=system.cpu3.icache.tags 1802tgts_per_mshr=20 1803two_queue=false 1804write_buffers=8 1805cpu_side=system.cpu3.icache_port 1806mem_side=system.toL2Bus.slave[6] 1807 1808[system.cpu3.icache.tags] 1809type=LRU 1810assoc=1 1811block_size=64 1812clk_domain=system.cpu_clk_domain 1813hit_latency=2 1814size=32768 1815 1816[system.cpu3.interrupts] 1817type=SparcInterrupts 1818 1819[system.cpu3.isa] 1820type=SparcISA 1821 1822[system.cpu3.itb] 1823type=SparcTLB 1824size=64 1825 1826[system.cpu3.tracer] 1827type=ExeTracer 1828 1829[system.cpu_clk_domain] 1830type=SrcClockDomain 1831clock=500 1832voltage_domain=system.voltage_domain 1833 1834[system.l2c] 1835type=BaseCache 1836children=tags 1837addr_ranges=0:18446744073709551615 1838assoc=8 1839clk_domain=system.cpu_clk_domain 1840forward_snoops=true 1841hit_latency=20 1842is_top_level=false 1843max_miss_count=0 1844mshrs=20 1845prefetch_on_access=false 1846prefetcher=Null 1847response_latency=20 1848size=4194304 1849system=system 1850tags=system.l2c.tags 1851tgts_per_mshr=12 1852two_queue=false 1853write_buffers=8 1854cpu_side=system.toL2Bus.master[0] 1855mem_side=system.membus.slave[1] 1856 1857[system.l2c.tags] 1858type=LRU 1859assoc=8 1860block_size=64 1861clk_domain=system.cpu_clk_domain 1862hit_latency=20 1863size=4194304 1864 1865[system.membus] 1866type=CoherentBus 1867clk_domain=system.clk_domain 1868header_cycles=1 1869system=system 1870use_default_range=false 1871width=8 1872master=system.physmem.port 1873slave=system.system_port system.l2c.mem_side 1874 1875[system.physmem] 1876type=SimpleDRAM 1877activation_limit=4 1878addr_mapping=RaBaChCo 1879banks_per_rank=8 1880burst_length=8 1881channels=1 1882clk_domain=system.clk_domain 1883conf_table_reported=true 1884device_bus_width=8 1885device_rowbuffer_size=1024 1886devices_per_rank=8 1887in_addr_map=true 1888mem_sched_policy=frfcfs 1889null=false 1890page_policy=open 1891range=0:134217727 1892ranks_per_channel=2 1893read_buffer_size=32 1894static_backend_latency=10000 1895static_frontend_latency=10000 1896tBURST=5000 1897tCL=13750 1898tRCD=13750 1899tREFI=7800000 1900tRFC=300000 1901tRP=13750 1902tWTR=7500 1903tXAW=40000 1904write_buffer_size=32 1905write_thresh_perc=70 1906port=system.membus.master[0] 1907 1908[system.toL2Bus] 1909type=CoherentBus 1910clk_domain=system.cpu_clk_domain 1911header_cycles=1 1912system=system 1913use_default_range=false 1914width=8 1915master=system.l2c.cpu_side 1916slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 1917 1918[system.voltage_domain] 1919type=VoltageDomain 1920voltage=1.000000 1921 1922