config.ini revision 9510
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=timing 18mem_ranges= 19memories=system.physmem 20num_work_ids=16 21readfile= 22symbolfile= 23work_begin_ckpt_count=0 24work_begin_cpu_id_exit=-1 25work_begin_exit_count=0 26work_cpus_ckpt_count=0 27work_end_ckpt_count=0 28work_end_exit_count=0 29work_item_id=-1 30system_port=system.membus.slave[1] 31 32[system.cpu0] 33type=DerivO3CPU 34children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 35LFSTSize=1024 36LQEntries=32 37LSQCheckLoads=true 38LSQDepCheckShift=4 39SQEntries=32 40SSITSize=1024 41activity=0 42backComSize=5 43branchPred=system.cpu0.branchPred 44cachePorts=200 45checker=Null 46clock=500 47commitToDecodeDelay=1 48commitToFetchDelay=1 49commitToIEWDelay=1 50commitToRenameDelay=1 51commitWidth=8 52cpu_id=0 53decodeToFetchDelay=1 54decodeToRenameDelay=1 55decodeWidth=8 56dispatchWidth=8 57do_checkpoint_insts=true 58do_quiesce=true 59do_statistics_insts=true 60dtb=system.cpu0.dtb 61fetchToDecodeDelay=1 62fetchTrapLatency=1 63fetchWidth=8 64forwardComSize=5 65fuPool=system.cpu0.fuPool 66function_trace=false 67function_trace_start=0 68iewToCommitDelay=1 69iewToDecodeDelay=1 70iewToFetchDelay=1 71iewToRenameDelay=1 72interrupts=system.cpu0.interrupts 73isa=system.cpu0.isa 74issueToExecuteDelay=1 75issueWidth=8 76itb=system.cpu0.itb 77max_insts_all_threads=0 78max_insts_any_thread=0 79max_loads_all_threads=0 80max_loads_any_thread=0 81needsTSO=false 82numIQEntries=64 83numPhysFloatRegs=256 84numPhysIntRegs=256 85numROBEntries=192 86numRobs=1 87numThreads=1 88profile=0 89progress_interval=0 90renameToDecodeDelay=1 91renameToFetchDelay=1 92renameToIEWDelay=2 93renameToROBDelay=1 94renameWidth=8 95smtCommitPolicy=RoundRobin 96smtFetchPolicy=SingleThread 97smtIQPolicy=Partitioned 98smtIQThreshold=100 99smtLSQPolicy=Partitioned 100smtLSQThreshold=100 101smtNumFetchingThreads=1 102smtROBPolicy=Partitioned 103smtROBThreshold=100 104squashWidth=8 105store_set_clear_period=250000 106switched_out=false 107system=system 108tracer=system.cpu0.tracer 109trapLatency=13 110wbDepth=1 111wbWidth=8 112workload=system.cpu0.workload 113dcache_port=system.cpu0.dcache.cpu_side 114icache_port=system.cpu0.icache.cpu_side 115 116[system.cpu0.branchPred] 117type=BranchPredictor 118BTBEntries=4096 119BTBTagSize=16 120RASSize=16 121choiceCtrBits=2 122choicePredictorSize=8192 123globalCtrBits=2 124globalHistoryBits=13 125globalPredictorSize=8192 126instShiftAmt=2 127localCtrBits=2 128localHistoryBits=11 129localHistoryTableSize=2048 130localPredictorSize=2048 131numThreads=1 132predType=tournament 133 134[system.cpu0.dcache] 135type=BaseCache 136addr_ranges=0:18446744073709551615 137assoc=4 138block_size=64 139clock=500 140forward_snoops=true 141hit_latency=2 142is_top_level=true 143max_miss_count=0 144mshrs=4 145prefetch_on_access=false 146prefetcher=Null 147response_latency=2 148size=32768 149system=system 150tgts_per_mshr=20 151two_queue=false 152write_buffers=8 153cpu_side=system.cpu0.dcache_port 154mem_side=system.toL2Bus.slave[1] 155 156[system.cpu0.dtb] 157type=SparcTLB 158size=64 159 160[system.cpu0.fuPool] 161type=FUPool 162children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 163FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 164 165[system.cpu0.fuPool.FUList0] 166type=FUDesc 167children=opList 168count=6 169opList=system.cpu0.fuPool.FUList0.opList 170 171[system.cpu0.fuPool.FUList0.opList] 172type=OpDesc 173issueLat=1 174opClass=IntAlu 175opLat=1 176 177[system.cpu0.fuPool.FUList1] 178type=FUDesc 179children=opList0 opList1 180count=2 181opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 182 183[system.cpu0.fuPool.FUList1.opList0] 184type=OpDesc 185issueLat=1 186opClass=IntMult 187opLat=3 188 189[system.cpu0.fuPool.FUList1.opList1] 190type=OpDesc 191issueLat=19 192opClass=IntDiv 193opLat=20 194 195[system.cpu0.fuPool.FUList2] 196type=FUDesc 197children=opList0 opList1 opList2 198count=4 199opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 200 201[system.cpu0.fuPool.FUList2.opList0] 202type=OpDesc 203issueLat=1 204opClass=FloatAdd 205opLat=2 206 207[system.cpu0.fuPool.FUList2.opList1] 208type=OpDesc 209issueLat=1 210opClass=FloatCmp 211opLat=2 212 213[system.cpu0.fuPool.FUList2.opList2] 214type=OpDesc 215issueLat=1 216opClass=FloatCvt 217opLat=2 218 219[system.cpu0.fuPool.FUList3] 220type=FUDesc 221children=opList0 opList1 opList2 222count=2 223opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 224 225[system.cpu0.fuPool.FUList3.opList0] 226type=OpDesc 227issueLat=1 228opClass=FloatMult 229opLat=4 230 231[system.cpu0.fuPool.FUList3.opList1] 232type=OpDesc 233issueLat=12 234opClass=FloatDiv 235opLat=12 236 237[system.cpu0.fuPool.FUList3.opList2] 238type=OpDesc 239issueLat=24 240opClass=FloatSqrt 241opLat=24 242 243[system.cpu0.fuPool.FUList4] 244type=FUDesc 245children=opList 246count=0 247opList=system.cpu0.fuPool.FUList4.opList 248 249[system.cpu0.fuPool.FUList4.opList] 250type=OpDesc 251issueLat=1 252opClass=MemRead 253opLat=1 254 255[system.cpu0.fuPool.FUList5] 256type=FUDesc 257children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 258count=4 259opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 260 261[system.cpu0.fuPool.FUList5.opList00] 262type=OpDesc 263issueLat=1 264opClass=SimdAdd 265opLat=1 266 267[system.cpu0.fuPool.FUList5.opList01] 268type=OpDesc 269issueLat=1 270opClass=SimdAddAcc 271opLat=1 272 273[system.cpu0.fuPool.FUList5.opList02] 274type=OpDesc 275issueLat=1 276opClass=SimdAlu 277opLat=1 278 279[system.cpu0.fuPool.FUList5.opList03] 280type=OpDesc 281issueLat=1 282opClass=SimdCmp 283opLat=1 284 285[system.cpu0.fuPool.FUList5.opList04] 286type=OpDesc 287issueLat=1 288opClass=SimdCvt 289opLat=1 290 291[system.cpu0.fuPool.FUList5.opList05] 292type=OpDesc 293issueLat=1 294opClass=SimdMisc 295opLat=1 296 297[system.cpu0.fuPool.FUList5.opList06] 298type=OpDesc 299issueLat=1 300opClass=SimdMult 301opLat=1 302 303[system.cpu0.fuPool.FUList5.opList07] 304type=OpDesc 305issueLat=1 306opClass=SimdMultAcc 307opLat=1 308 309[system.cpu0.fuPool.FUList5.opList08] 310type=OpDesc 311issueLat=1 312opClass=SimdShift 313opLat=1 314 315[system.cpu0.fuPool.FUList5.opList09] 316type=OpDesc 317issueLat=1 318opClass=SimdShiftAcc 319opLat=1 320 321[system.cpu0.fuPool.FUList5.opList10] 322type=OpDesc 323issueLat=1 324opClass=SimdSqrt 325opLat=1 326 327[system.cpu0.fuPool.FUList5.opList11] 328type=OpDesc 329issueLat=1 330opClass=SimdFloatAdd 331opLat=1 332 333[system.cpu0.fuPool.FUList5.opList12] 334type=OpDesc 335issueLat=1 336opClass=SimdFloatAlu 337opLat=1 338 339[system.cpu0.fuPool.FUList5.opList13] 340type=OpDesc 341issueLat=1 342opClass=SimdFloatCmp 343opLat=1 344 345[system.cpu0.fuPool.FUList5.opList14] 346type=OpDesc 347issueLat=1 348opClass=SimdFloatCvt 349opLat=1 350 351[system.cpu0.fuPool.FUList5.opList15] 352type=OpDesc 353issueLat=1 354opClass=SimdFloatDiv 355opLat=1 356 357[system.cpu0.fuPool.FUList5.opList16] 358type=OpDesc 359issueLat=1 360opClass=SimdFloatMisc 361opLat=1 362 363[system.cpu0.fuPool.FUList5.opList17] 364type=OpDesc 365issueLat=1 366opClass=SimdFloatMult 367opLat=1 368 369[system.cpu0.fuPool.FUList5.opList18] 370type=OpDesc 371issueLat=1 372opClass=SimdFloatMultAcc 373opLat=1 374 375[system.cpu0.fuPool.FUList5.opList19] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatSqrt 379opLat=1 380 381[system.cpu0.fuPool.FUList6] 382type=FUDesc 383children=opList 384count=0 385opList=system.cpu0.fuPool.FUList6.opList 386 387[system.cpu0.fuPool.FUList6.opList] 388type=OpDesc 389issueLat=1 390opClass=MemWrite 391opLat=1 392 393[system.cpu0.fuPool.FUList7] 394type=FUDesc 395children=opList0 opList1 396count=4 397opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 398 399[system.cpu0.fuPool.FUList7.opList0] 400type=OpDesc 401issueLat=1 402opClass=MemRead 403opLat=1 404 405[system.cpu0.fuPool.FUList7.opList1] 406type=OpDesc 407issueLat=1 408opClass=MemWrite 409opLat=1 410 411[system.cpu0.fuPool.FUList8] 412type=FUDesc 413children=opList 414count=1 415opList=system.cpu0.fuPool.FUList8.opList 416 417[system.cpu0.fuPool.FUList8.opList] 418type=OpDesc 419issueLat=3 420opClass=IprAccess 421opLat=3 422 423[system.cpu0.icache] 424type=BaseCache 425addr_ranges=0:18446744073709551615 426assoc=1 427block_size=64 428clock=500 429forward_snoops=true 430hit_latency=2 431is_top_level=true 432max_miss_count=0 433mshrs=4 434prefetch_on_access=false 435prefetcher=Null 436response_latency=2 437size=32768 438system=system 439tgts_per_mshr=20 440two_queue=false 441write_buffers=8 442cpu_side=system.cpu0.icache_port 443mem_side=system.toL2Bus.slave[0] 444 445[system.cpu0.interrupts] 446type=SparcInterrupts 447 448[system.cpu0.isa] 449type=SparcISA 450 451[system.cpu0.itb] 452type=SparcTLB 453size=64 454 455[system.cpu0.tracer] 456type=ExeTracer 457 458[system.cpu0.workload] 459type=LiveProcess 460cmd=test_atomic 4 461cwd= 462egid=100 463env= 464errout=cerr 465euid=100 466executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic 467gid=100 468input=cin 469max_stack_size=67108864 470output=cout 471pid=100 472ppid=99 473simpoint=0 474system=system 475uid=100 476 477[system.cpu1] 478type=DerivO3CPU 479children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 480LFSTSize=1024 481LQEntries=32 482LSQCheckLoads=true 483LSQDepCheckShift=4 484SQEntries=32 485SSITSize=1024 486activity=0 487backComSize=5 488branchPred=system.cpu1.branchPred 489cachePorts=200 490checker=Null 491clock=500 492commitToDecodeDelay=1 493commitToFetchDelay=1 494commitToIEWDelay=1 495commitToRenameDelay=1 496commitWidth=8 497cpu_id=1 498decodeToFetchDelay=1 499decodeToRenameDelay=1 500decodeWidth=8 501dispatchWidth=8 502do_checkpoint_insts=true 503do_quiesce=true 504do_statistics_insts=true 505dtb=system.cpu1.dtb 506fetchToDecodeDelay=1 507fetchTrapLatency=1 508fetchWidth=8 509forwardComSize=5 510fuPool=system.cpu1.fuPool 511function_trace=false 512function_trace_start=0 513iewToCommitDelay=1 514iewToDecodeDelay=1 515iewToFetchDelay=1 516iewToRenameDelay=1 517interrupts=system.cpu1.interrupts 518isa=system.cpu1.isa 519issueToExecuteDelay=1 520issueWidth=8 521itb=system.cpu1.itb 522max_insts_all_threads=0 523max_insts_any_thread=0 524max_loads_all_threads=0 525max_loads_any_thread=0 526needsTSO=false 527numIQEntries=64 528numPhysFloatRegs=256 529numPhysIntRegs=256 530numROBEntries=192 531numRobs=1 532numThreads=1 533profile=0 534progress_interval=0 535renameToDecodeDelay=1 536renameToFetchDelay=1 537renameToIEWDelay=2 538renameToROBDelay=1 539renameWidth=8 540smtCommitPolicy=RoundRobin 541smtFetchPolicy=SingleThread 542smtIQPolicy=Partitioned 543smtIQThreshold=100 544smtLSQPolicy=Partitioned 545smtLSQThreshold=100 546smtNumFetchingThreads=1 547smtROBPolicy=Partitioned 548smtROBThreshold=100 549squashWidth=8 550store_set_clear_period=250000 551switched_out=false 552system=system 553tracer=system.cpu1.tracer 554trapLatency=13 555wbDepth=1 556wbWidth=8 557workload=system.cpu0.workload 558dcache_port=system.cpu1.dcache.cpu_side 559icache_port=system.cpu1.icache.cpu_side 560 561[system.cpu1.branchPred] 562type=BranchPredictor 563BTBEntries=4096 564BTBTagSize=16 565RASSize=16 566choiceCtrBits=2 567choicePredictorSize=8192 568globalCtrBits=2 569globalHistoryBits=13 570globalPredictorSize=8192 571instShiftAmt=2 572localCtrBits=2 573localHistoryBits=11 574localHistoryTableSize=2048 575localPredictorSize=2048 576numThreads=1 577predType=tournament 578 579[system.cpu1.dcache] 580type=BaseCache 581addr_ranges=0:18446744073709551615 582assoc=4 583block_size=64 584clock=500 585forward_snoops=true 586hit_latency=2 587is_top_level=true 588max_miss_count=0 589mshrs=4 590prefetch_on_access=false 591prefetcher=Null 592response_latency=2 593size=32768 594system=system 595tgts_per_mshr=20 596two_queue=false 597write_buffers=8 598cpu_side=system.cpu1.dcache_port 599mem_side=system.toL2Bus.slave[3] 600 601[system.cpu1.dtb] 602type=SparcTLB 603size=64 604 605[system.cpu1.fuPool] 606type=FUPool 607children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 608FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 609 610[system.cpu1.fuPool.FUList0] 611type=FUDesc 612children=opList 613count=6 614opList=system.cpu1.fuPool.FUList0.opList 615 616[system.cpu1.fuPool.FUList0.opList] 617type=OpDesc 618issueLat=1 619opClass=IntAlu 620opLat=1 621 622[system.cpu1.fuPool.FUList1] 623type=FUDesc 624children=opList0 opList1 625count=2 626opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 627 628[system.cpu1.fuPool.FUList1.opList0] 629type=OpDesc 630issueLat=1 631opClass=IntMult 632opLat=3 633 634[system.cpu1.fuPool.FUList1.opList1] 635type=OpDesc 636issueLat=19 637opClass=IntDiv 638opLat=20 639 640[system.cpu1.fuPool.FUList2] 641type=FUDesc 642children=opList0 opList1 opList2 643count=4 644opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 645 646[system.cpu1.fuPool.FUList2.opList0] 647type=OpDesc 648issueLat=1 649opClass=FloatAdd 650opLat=2 651 652[system.cpu1.fuPool.FUList2.opList1] 653type=OpDesc 654issueLat=1 655opClass=FloatCmp 656opLat=2 657 658[system.cpu1.fuPool.FUList2.opList2] 659type=OpDesc 660issueLat=1 661opClass=FloatCvt 662opLat=2 663 664[system.cpu1.fuPool.FUList3] 665type=FUDesc 666children=opList0 opList1 opList2 667count=2 668opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 669 670[system.cpu1.fuPool.FUList3.opList0] 671type=OpDesc 672issueLat=1 673opClass=FloatMult 674opLat=4 675 676[system.cpu1.fuPool.FUList3.opList1] 677type=OpDesc 678issueLat=12 679opClass=FloatDiv 680opLat=12 681 682[system.cpu1.fuPool.FUList3.opList2] 683type=OpDesc 684issueLat=24 685opClass=FloatSqrt 686opLat=24 687 688[system.cpu1.fuPool.FUList4] 689type=FUDesc 690children=opList 691count=0 692opList=system.cpu1.fuPool.FUList4.opList 693 694[system.cpu1.fuPool.FUList4.opList] 695type=OpDesc 696issueLat=1 697opClass=MemRead 698opLat=1 699 700[system.cpu1.fuPool.FUList5] 701type=FUDesc 702children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 703count=4 704opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 705 706[system.cpu1.fuPool.FUList5.opList00] 707type=OpDesc 708issueLat=1 709opClass=SimdAdd 710opLat=1 711 712[system.cpu1.fuPool.FUList5.opList01] 713type=OpDesc 714issueLat=1 715opClass=SimdAddAcc 716opLat=1 717 718[system.cpu1.fuPool.FUList5.opList02] 719type=OpDesc 720issueLat=1 721opClass=SimdAlu 722opLat=1 723 724[system.cpu1.fuPool.FUList5.opList03] 725type=OpDesc 726issueLat=1 727opClass=SimdCmp 728opLat=1 729 730[system.cpu1.fuPool.FUList5.opList04] 731type=OpDesc 732issueLat=1 733opClass=SimdCvt 734opLat=1 735 736[system.cpu1.fuPool.FUList5.opList05] 737type=OpDesc 738issueLat=1 739opClass=SimdMisc 740opLat=1 741 742[system.cpu1.fuPool.FUList5.opList06] 743type=OpDesc 744issueLat=1 745opClass=SimdMult 746opLat=1 747 748[system.cpu1.fuPool.FUList5.opList07] 749type=OpDesc 750issueLat=1 751opClass=SimdMultAcc 752opLat=1 753 754[system.cpu1.fuPool.FUList5.opList08] 755type=OpDesc 756issueLat=1 757opClass=SimdShift 758opLat=1 759 760[system.cpu1.fuPool.FUList5.opList09] 761type=OpDesc 762issueLat=1 763opClass=SimdShiftAcc 764opLat=1 765 766[system.cpu1.fuPool.FUList5.opList10] 767type=OpDesc 768issueLat=1 769opClass=SimdSqrt 770opLat=1 771 772[system.cpu1.fuPool.FUList5.opList11] 773type=OpDesc 774issueLat=1 775opClass=SimdFloatAdd 776opLat=1 777 778[system.cpu1.fuPool.FUList5.opList12] 779type=OpDesc 780issueLat=1 781opClass=SimdFloatAlu 782opLat=1 783 784[system.cpu1.fuPool.FUList5.opList13] 785type=OpDesc 786issueLat=1 787opClass=SimdFloatCmp 788opLat=1 789 790[system.cpu1.fuPool.FUList5.opList14] 791type=OpDesc 792issueLat=1 793opClass=SimdFloatCvt 794opLat=1 795 796[system.cpu1.fuPool.FUList5.opList15] 797type=OpDesc 798issueLat=1 799opClass=SimdFloatDiv 800opLat=1 801 802[system.cpu1.fuPool.FUList5.opList16] 803type=OpDesc 804issueLat=1 805opClass=SimdFloatMisc 806opLat=1 807 808[system.cpu1.fuPool.FUList5.opList17] 809type=OpDesc 810issueLat=1 811opClass=SimdFloatMult 812opLat=1 813 814[system.cpu1.fuPool.FUList5.opList18] 815type=OpDesc 816issueLat=1 817opClass=SimdFloatMultAcc 818opLat=1 819 820[system.cpu1.fuPool.FUList5.opList19] 821type=OpDesc 822issueLat=1 823opClass=SimdFloatSqrt 824opLat=1 825 826[system.cpu1.fuPool.FUList6] 827type=FUDesc 828children=opList 829count=0 830opList=system.cpu1.fuPool.FUList6.opList 831 832[system.cpu1.fuPool.FUList6.opList] 833type=OpDesc 834issueLat=1 835opClass=MemWrite 836opLat=1 837 838[system.cpu1.fuPool.FUList7] 839type=FUDesc 840children=opList0 opList1 841count=4 842opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 843 844[system.cpu1.fuPool.FUList7.opList0] 845type=OpDesc 846issueLat=1 847opClass=MemRead 848opLat=1 849 850[system.cpu1.fuPool.FUList7.opList1] 851type=OpDesc 852issueLat=1 853opClass=MemWrite 854opLat=1 855 856[system.cpu1.fuPool.FUList8] 857type=FUDesc 858children=opList 859count=1 860opList=system.cpu1.fuPool.FUList8.opList 861 862[system.cpu1.fuPool.FUList8.opList] 863type=OpDesc 864issueLat=3 865opClass=IprAccess 866opLat=3 867 868[system.cpu1.icache] 869type=BaseCache 870addr_ranges=0:18446744073709551615 871assoc=1 872block_size=64 873clock=500 874forward_snoops=true 875hit_latency=2 876is_top_level=true 877max_miss_count=0 878mshrs=4 879prefetch_on_access=false 880prefetcher=Null 881response_latency=2 882size=32768 883system=system 884tgts_per_mshr=20 885two_queue=false 886write_buffers=8 887cpu_side=system.cpu1.icache_port 888mem_side=system.toL2Bus.slave[2] 889 890[system.cpu1.interrupts] 891type=SparcInterrupts 892 893[system.cpu1.isa] 894type=SparcISA 895 896[system.cpu1.itb] 897type=SparcTLB 898size=64 899 900[system.cpu1.tracer] 901type=ExeTracer 902 903[system.cpu2] 904type=DerivO3CPU 905children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 906LFSTSize=1024 907LQEntries=32 908LSQCheckLoads=true 909LSQDepCheckShift=4 910SQEntries=32 911SSITSize=1024 912activity=0 913backComSize=5 914branchPred=system.cpu2.branchPred 915cachePorts=200 916checker=Null 917clock=500 918commitToDecodeDelay=1 919commitToFetchDelay=1 920commitToIEWDelay=1 921commitToRenameDelay=1 922commitWidth=8 923cpu_id=2 924decodeToFetchDelay=1 925decodeToRenameDelay=1 926decodeWidth=8 927dispatchWidth=8 928do_checkpoint_insts=true 929do_quiesce=true 930do_statistics_insts=true 931dtb=system.cpu2.dtb 932fetchToDecodeDelay=1 933fetchTrapLatency=1 934fetchWidth=8 935forwardComSize=5 936fuPool=system.cpu2.fuPool 937function_trace=false 938function_trace_start=0 939iewToCommitDelay=1 940iewToDecodeDelay=1 941iewToFetchDelay=1 942iewToRenameDelay=1 943interrupts=system.cpu2.interrupts 944isa=system.cpu2.isa 945issueToExecuteDelay=1 946issueWidth=8 947itb=system.cpu2.itb 948max_insts_all_threads=0 949max_insts_any_thread=0 950max_loads_all_threads=0 951max_loads_any_thread=0 952needsTSO=false 953numIQEntries=64 954numPhysFloatRegs=256 955numPhysIntRegs=256 956numROBEntries=192 957numRobs=1 958numThreads=1 959profile=0 960progress_interval=0 961renameToDecodeDelay=1 962renameToFetchDelay=1 963renameToIEWDelay=2 964renameToROBDelay=1 965renameWidth=8 966smtCommitPolicy=RoundRobin 967smtFetchPolicy=SingleThread 968smtIQPolicy=Partitioned 969smtIQThreshold=100 970smtLSQPolicy=Partitioned 971smtLSQThreshold=100 972smtNumFetchingThreads=1 973smtROBPolicy=Partitioned 974smtROBThreshold=100 975squashWidth=8 976store_set_clear_period=250000 977switched_out=false 978system=system 979tracer=system.cpu2.tracer 980trapLatency=13 981wbDepth=1 982wbWidth=8 983workload=system.cpu0.workload 984dcache_port=system.cpu2.dcache.cpu_side 985icache_port=system.cpu2.icache.cpu_side 986 987[system.cpu2.branchPred] 988type=BranchPredictor 989BTBEntries=4096 990BTBTagSize=16 991RASSize=16 992choiceCtrBits=2 993choicePredictorSize=8192 994globalCtrBits=2 995globalHistoryBits=13 996globalPredictorSize=8192 997instShiftAmt=2 998localCtrBits=2 999localHistoryBits=11 1000localHistoryTableSize=2048 1001localPredictorSize=2048 1002numThreads=1 1003predType=tournament 1004 1005[system.cpu2.dcache] 1006type=BaseCache 1007addr_ranges=0:18446744073709551615 1008assoc=4 1009block_size=64 1010clock=500 1011forward_snoops=true 1012hit_latency=2 1013is_top_level=true 1014max_miss_count=0 1015mshrs=4 1016prefetch_on_access=false 1017prefetcher=Null 1018response_latency=2 1019size=32768 1020system=system 1021tgts_per_mshr=20 1022two_queue=false 1023write_buffers=8 1024cpu_side=system.cpu2.dcache_port 1025mem_side=system.toL2Bus.slave[5] 1026 1027[system.cpu2.dtb] 1028type=SparcTLB 1029size=64 1030 1031[system.cpu2.fuPool] 1032type=FUPool 1033children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1034FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1035 1036[system.cpu2.fuPool.FUList0] 1037type=FUDesc 1038children=opList 1039count=6 1040opList=system.cpu2.fuPool.FUList0.opList 1041 1042[system.cpu2.fuPool.FUList0.opList] 1043type=OpDesc 1044issueLat=1 1045opClass=IntAlu 1046opLat=1 1047 1048[system.cpu2.fuPool.FUList1] 1049type=FUDesc 1050children=opList0 opList1 1051count=2 1052opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1053 1054[system.cpu2.fuPool.FUList1.opList0] 1055type=OpDesc 1056issueLat=1 1057opClass=IntMult 1058opLat=3 1059 1060[system.cpu2.fuPool.FUList1.opList1] 1061type=OpDesc 1062issueLat=19 1063opClass=IntDiv 1064opLat=20 1065 1066[system.cpu2.fuPool.FUList2] 1067type=FUDesc 1068children=opList0 opList1 opList2 1069count=4 1070opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1071 1072[system.cpu2.fuPool.FUList2.opList0] 1073type=OpDesc 1074issueLat=1 1075opClass=FloatAdd 1076opLat=2 1077 1078[system.cpu2.fuPool.FUList2.opList1] 1079type=OpDesc 1080issueLat=1 1081opClass=FloatCmp 1082opLat=2 1083 1084[system.cpu2.fuPool.FUList2.opList2] 1085type=OpDesc 1086issueLat=1 1087opClass=FloatCvt 1088opLat=2 1089 1090[system.cpu2.fuPool.FUList3] 1091type=FUDesc 1092children=opList0 opList1 opList2 1093count=2 1094opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1095 1096[system.cpu2.fuPool.FUList3.opList0] 1097type=OpDesc 1098issueLat=1 1099opClass=FloatMult 1100opLat=4 1101 1102[system.cpu2.fuPool.FUList3.opList1] 1103type=OpDesc 1104issueLat=12 1105opClass=FloatDiv 1106opLat=12 1107 1108[system.cpu2.fuPool.FUList3.opList2] 1109type=OpDesc 1110issueLat=24 1111opClass=FloatSqrt 1112opLat=24 1113 1114[system.cpu2.fuPool.FUList4] 1115type=FUDesc 1116children=opList 1117count=0 1118opList=system.cpu2.fuPool.FUList4.opList 1119 1120[system.cpu2.fuPool.FUList4.opList] 1121type=OpDesc 1122issueLat=1 1123opClass=MemRead 1124opLat=1 1125 1126[system.cpu2.fuPool.FUList5] 1127type=FUDesc 1128children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1129count=4 1130opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1131 1132[system.cpu2.fuPool.FUList5.opList00] 1133type=OpDesc 1134issueLat=1 1135opClass=SimdAdd 1136opLat=1 1137 1138[system.cpu2.fuPool.FUList5.opList01] 1139type=OpDesc 1140issueLat=1 1141opClass=SimdAddAcc 1142opLat=1 1143 1144[system.cpu2.fuPool.FUList5.opList02] 1145type=OpDesc 1146issueLat=1 1147opClass=SimdAlu 1148opLat=1 1149 1150[system.cpu2.fuPool.FUList5.opList03] 1151type=OpDesc 1152issueLat=1 1153opClass=SimdCmp 1154opLat=1 1155 1156[system.cpu2.fuPool.FUList5.opList04] 1157type=OpDesc 1158issueLat=1 1159opClass=SimdCvt 1160opLat=1 1161 1162[system.cpu2.fuPool.FUList5.opList05] 1163type=OpDesc 1164issueLat=1 1165opClass=SimdMisc 1166opLat=1 1167 1168[system.cpu2.fuPool.FUList5.opList06] 1169type=OpDesc 1170issueLat=1 1171opClass=SimdMult 1172opLat=1 1173 1174[system.cpu2.fuPool.FUList5.opList07] 1175type=OpDesc 1176issueLat=1 1177opClass=SimdMultAcc 1178opLat=1 1179 1180[system.cpu2.fuPool.FUList5.opList08] 1181type=OpDesc 1182issueLat=1 1183opClass=SimdShift 1184opLat=1 1185 1186[system.cpu2.fuPool.FUList5.opList09] 1187type=OpDesc 1188issueLat=1 1189opClass=SimdShiftAcc 1190opLat=1 1191 1192[system.cpu2.fuPool.FUList5.opList10] 1193type=OpDesc 1194issueLat=1 1195opClass=SimdSqrt 1196opLat=1 1197 1198[system.cpu2.fuPool.FUList5.opList11] 1199type=OpDesc 1200issueLat=1 1201opClass=SimdFloatAdd 1202opLat=1 1203 1204[system.cpu2.fuPool.FUList5.opList12] 1205type=OpDesc 1206issueLat=1 1207opClass=SimdFloatAlu 1208opLat=1 1209 1210[system.cpu2.fuPool.FUList5.opList13] 1211type=OpDesc 1212issueLat=1 1213opClass=SimdFloatCmp 1214opLat=1 1215 1216[system.cpu2.fuPool.FUList5.opList14] 1217type=OpDesc 1218issueLat=1 1219opClass=SimdFloatCvt 1220opLat=1 1221 1222[system.cpu2.fuPool.FUList5.opList15] 1223type=OpDesc 1224issueLat=1 1225opClass=SimdFloatDiv 1226opLat=1 1227 1228[system.cpu2.fuPool.FUList5.opList16] 1229type=OpDesc 1230issueLat=1 1231opClass=SimdFloatMisc 1232opLat=1 1233 1234[system.cpu2.fuPool.FUList5.opList17] 1235type=OpDesc 1236issueLat=1 1237opClass=SimdFloatMult 1238opLat=1 1239 1240[system.cpu2.fuPool.FUList5.opList18] 1241type=OpDesc 1242issueLat=1 1243opClass=SimdFloatMultAcc 1244opLat=1 1245 1246[system.cpu2.fuPool.FUList5.opList19] 1247type=OpDesc 1248issueLat=1 1249opClass=SimdFloatSqrt 1250opLat=1 1251 1252[system.cpu2.fuPool.FUList6] 1253type=FUDesc 1254children=opList 1255count=0 1256opList=system.cpu2.fuPool.FUList6.opList 1257 1258[system.cpu2.fuPool.FUList6.opList] 1259type=OpDesc 1260issueLat=1 1261opClass=MemWrite 1262opLat=1 1263 1264[system.cpu2.fuPool.FUList7] 1265type=FUDesc 1266children=opList0 opList1 1267count=4 1268opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1269 1270[system.cpu2.fuPool.FUList7.opList0] 1271type=OpDesc 1272issueLat=1 1273opClass=MemRead 1274opLat=1 1275 1276[system.cpu2.fuPool.FUList7.opList1] 1277type=OpDesc 1278issueLat=1 1279opClass=MemWrite 1280opLat=1 1281 1282[system.cpu2.fuPool.FUList8] 1283type=FUDesc 1284children=opList 1285count=1 1286opList=system.cpu2.fuPool.FUList8.opList 1287 1288[system.cpu2.fuPool.FUList8.opList] 1289type=OpDesc 1290issueLat=3 1291opClass=IprAccess 1292opLat=3 1293 1294[system.cpu2.icache] 1295type=BaseCache 1296addr_ranges=0:18446744073709551615 1297assoc=1 1298block_size=64 1299clock=500 1300forward_snoops=true 1301hit_latency=2 1302is_top_level=true 1303max_miss_count=0 1304mshrs=4 1305prefetch_on_access=false 1306prefetcher=Null 1307response_latency=2 1308size=32768 1309system=system 1310tgts_per_mshr=20 1311two_queue=false 1312write_buffers=8 1313cpu_side=system.cpu2.icache_port 1314mem_side=system.toL2Bus.slave[4] 1315 1316[system.cpu2.interrupts] 1317type=SparcInterrupts 1318 1319[system.cpu2.isa] 1320type=SparcISA 1321 1322[system.cpu2.itb] 1323type=SparcTLB 1324size=64 1325 1326[system.cpu2.tracer] 1327type=ExeTracer 1328 1329[system.cpu3] 1330type=DerivO3CPU 1331children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1332LFSTSize=1024 1333LQEntries=32 1334LSQCheckLoads=true 1335LSQDepCheckShift=4 1336SQEntries=32 1337SSITSize=1024 1338activity=0 1339backComSize=5 1340branchPred=system.cpu3.branchPred 1341cachePorts=200 1342checker=Null 1343clock=500 1344commitToDecodeDelay=1 1345commitToFetchDelay=1 1346commitToIEWDelay=1 1347commitToRenameDelay=1 1348commitWidth=8 1349cpu_id=3 1350decodeToFetchDelay=1 1351decodeToRenameDelay=1 1352decodeWidth=8 1353dispatchWidth=8 1354do_checkpoint_insts=true 1355do_quiesce=true 1356do_statistics_insts=true 1357dtb=system.cpu3.dtb 1358fetchToDecodeDelay=1 1359fetchTrapLatency=1 1360fetchWidth=8 1361forwardComSize=5 1362fuPool=system.cpu3.fuPool 1363function_trace=false 1364function_trace_start=0 1365iewToCommitDelay=1 1366iewToDecodeDelay=1 1367iewToFetchDelay=1 1368iewToRenameDelay=1 1369interrupts=system.cpu3.interrupts 1370isa=system.cpu3.isa 1371issueToExecuteDelay=1 1372issueWidth=8 1373itb=system.cpu3.itb 1374max_insts_all_threads=0 1375max_insts_any_thread=0 1376max_loads_all_threads=0 1377max_loads_any_thread=0 1378needsTSO=false 1379numIQEntries=64 1380numPhysFloatRegs=256 1381numPhysIntRegs=256 1382numROBEntries=192 1383numRobs=1 1384numThreads=1 1385profile=0 1386progress_interval=0 1387renameToDecodeDelay=1 1388renameToFetchDelay=1 1389renameToIEWDelay=2 1390renameToROBDelay=1 1391renameWidth=8 1392smtCommitPolicy=RoundRobin 1393smtFetchPolicy=SingleThread 1394smtIQPolicy=Partitioned 1395smtIQThreshold=100 1396smtLSQPolicy=Partitioned 1397smtLSQThreshold=100 1398smtNumFetchingThreads=1 1399smtROBPolicy=Partitioned 1400smtROBThreshold=100 1401squashWidth=8 1402store_set_clear_period=250000 1403switched_out=false 1404system=system 1405tracer=system.cpu3.tracer 1406trapLatency=13 1407wbDepth=1 1408wbWidth=8 1409workload=system.cpu0.workload 1410dcache_port=system.cpu3.dcache.cpu_side 1411icache_port=system.cpu3.icache.cpu_side 1412 1413[system.cpu3.branchPred] 1414type=BranchPredictor 1415BTBEntries=4096 1416BTBTagSize=16 1417RASSize=16 1418choiceCtrBits=2 1419choicePredictorSize=8192 1420globalCtrBits=2 1421globalHistoryBits=13 1422globalPredictorSize=8192 1423instShiftAmt=2 1424localCtrBits=2 1425localHistoryBits=11 1426localHistoryTableSize=2048 1427localPredictorSize=2048 1428numThreads=1 1429predType=tournament 1430 1431[system.cpu3.dcache] 1432type=BaseCache 1433addr_ranges=0:18446744073709551615 1434assoc=4 1435block_size=64 1436clock=500 1437forward_snoops=true 1438hit_latency=2 1439is_top_level=true 1440max_miss_count=0 1441mshrs=4 1442prefetch_on_access=false 1443prefetcher=Null 1444response_latency=2 1445size=32768 1446system=system 1447tgts_per_mshr=20 1448two_queue=false 1449write_buffers=8 1450cpu_side=system.cpu3.dcache_port 1451mem_side=system.toL2Bus.slave[7] 1452 1453[system.cpu3.dtb] 1454type=SparcTLB 1455size=64 1456 1457[system.cpu3.fuPool] 1458type=FUPool 1459children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1460FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1461 1462[system.cpu3.fuPool.FUList0] 1463type=FUDesc 1464children=opList 1465count=6 1466opList=system.cpu3.fuPool.FUList0.opList 1467 1468[system.cpu3.fuPool.FUList0.opList] 1469type=OpDesc 1470issueLat=1 1471opClass=IntAlu 1472opLat=1 1473 1474[system.cpu3.fuPool.FUList1] 1475type=FUDesc 1476children=opList0 opList1 1477count=2 1478opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1479 1480[system.cpu3.fuPool.FUList1.opList0] 1481type=OpDesc 1482issueLat=1 1483opClass=IntMult 1484opLat=3 1485 1486[system.cpu3.fuPool.FUList1.opList1] 1487type=OpDesc 1488issueLat=19 1489opClass=IntDiv 1490opLat=20 1491 1492[system.cpu3.fuPool.FUList2] 1493type=FUDesc 1494children=opList0 opList1 opList2 1495count=4 1496opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1497 1498[system.cpu3.fuPool.FUList2.opList0] 1499type=OpDesc 1500issueLat=1 1501opClass=FloatAdd 1502opLat=2 1503 1504[system.cpu3.fuPool.FUList2.opList1] 1505type=OpDesc 1506issueLat=1 1507opClass=FloatCmp 1508opLat=2 1509 1510[system.cpu3.fuPool.FUList2.opList2] 1511type=OpDesc 1512issueLat=1 1513opClass=FloatCvt 1514opLat=2 1515 1516[system.cpu3.fuPool.FUList3] 1517type=FUDesc 1518children=opList0 opList1 opList2 1519count=2 1520opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1521 1522[system.cpu3.fuPool.FUList3.opList0] 1523type=OpDesc 1524issueLat=1 1525opClass=FloatMult 1526opLat=4 1527 1528[system.cpu3.fuPool.FUList3.opList1] 1529type=OpDesc 1530issueLat=12 1531opClass=FloatDiv 1532opLat=12 1533 1534[system.cpu3.fuPool.FUList3.opList2] 1535type=OpDesc 1536issueLat=24 1537opClass=FloatSqrt 1538opLat=24 1539 1540[system.cpu3.fuPool.FUList4] 1541type=FUDesc 1542children=opList 1543count=0 1544opList=system.cpu3.fuPool.FUList4.opList 1545 1546[system.cpu3.fuPool.FUList4.opList] 1547type=OpDesc 1548issueLat=1 1549opClass=MemRead 1550opLat=1 1551 1552[system.cpu3.fuPool.FUList5] 1553type=FUDesc 1554children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1555count=4 1556opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1557 1558[system.cpu3.fuPool.FUList5.opList00] 1559type=OpDesc 1560issueLat=1 1561opClass=SimdAdd 1562opLat=1 1563 1564[system.cpu3.fuPool.FUList5.opList01] 1565type=OpDesc 1566issueLat=1 1567opClass=SimdAddAcc 1568opLat=1 1569 1570[system.cpu3.fuPool.FUList5.opList02] 1571type=OpDesc 1572issueLat=1 1573opClass=SimdAlu 1574opLat=1 1575 1576[system.cpu3.fuPool.FUList5.opList03] 1577type=OpDesc 1578issueLat=1 1579opClass=SimdCmp 1580opLat=1 1581 1582[system.cpu3.fuPool.FUList5.opList04] 1583type=OpDesc 1584issueLat=1 1585opClass=SimdCvt 1586opLat=1 1587 1588[system.cpu3.fuPool.FUList5.opList05] 1589type=OpDesc 1590issueLat=1 1591opClass=SimdMisc 1592opLat=1 1593 1594[system.cpu3.fuPool.FUList5.opList06] 1595type=OpDesc 1596issueLat=1 1597opClass=SimdMult 1598opLat=1 1599 1600[system.cpu3.fuPool.FUList5.opList07] 1601type=OpDesc 1602issueLat=1 1603opClass=SimdMultAcc 1604opLat=1 1605 1606[system.cpu3.fuPool.FUList5.opList08] 1607type=OpDesc 1608issueLat=1 1609opClass=SimdShift 1610opLat=1 1611 1612[system.cpu3.fuPool.FUList5.opList09] 1613type=OpDesc 1614issueLat=1 1615opClass=SimdShiftAcc 1616opLat=1 1617 1618[system.cpu3.fuPool.FUList5.opList10] 1619type=OpDesc 1620issueLat=1 1621opClass=SimdSqrt 1622opLat=1 1623 1624[system.cpu3.fuPool.FUList5.opList11] 1625type=OpDesc 1626issueLat=1 1627opClass=SimdFloatAdd 1628opLat=1 1629 1630[system.cpu3.fuPool.FUList5.opList12] 1631type=OpDesc 1632issueLat=1 1633opClass=SimdFloatAlu 1634opLat=1 1635 1636[system.cpu3.fuPool.FUList5.opList13] 1637type=OpDesc 1638issueLat=1 1639opClass=SimdFloatCmp 1640opLat=1 1641 1642[system.cpu3.fuPool.FUList5.opList14] 1643type=OpDesc 1644issueLat=1 1645opClass=SimdFloatCvt 1646opLat=1 1647 1648[system.cpu3.fuPool.FUList5.opList15] 1649type=OpDesc 1650issueLat=1 1651opClass=SimdFloatDiv 1652opLat=1 1653 1654[system.cpu3.fuPool.FUList5.opList16] 1655type=OpDesc 1656issueLat=1 1657opClass=SimdFloatMisc 1658opLat=1 1659 1660[system.cpu3.fuPool.FUList5.opList17] 1661type=OpDesc 1662issueLat=1 1663opClass=SimdFloatMult 1664opLat=1 1665 1666[system.cpu3.fuPool.FUList5.opList18] 1667type=OpDesc 1668issueLat=1 1669opClass=SimdFloatMultAcc 1670opLat=1 1671 1672[system.cpu3.fuPool.FUList5.opList19] 1673type=OpDesc 1674issueLat=1 1675opClass=SimdFloatSqrt 1676opLat=1 1677 1678[system.cpu3.fuPool.FUList6] 1679type=FUDesc 1680children=opList 1681count=0 1682opList=system.cpu3.fuPool.FUList6.opList 1683 1684[system.cpu3.fuPool.FUList6.opList] 1685type=OpDesc 1686issueLat=1 1687opClass=MemWrite 1688opLat=1 1689 1690[system.cpu3.fuPool.FUList7] 1691type=FUDesc 1692children=opList0 opList1 1693count=4 1694opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 1695 1696[system.cpu3.fuPool.FUList7.opList0] 1697type=OpDesc 1698issueLat=1 1699opClass=MemRead 1700opLat=1 1701 1702[system.cpu3.fuPool.FUList7.opList1] 1703type=OpDesc 1704issueLat=1 1705opClass=MemWrite 1706opLat=1 1707 1708[system.cpu3.fuPool.FUList8] 1709type=FUDesc 1710children=opList 1711count=1 1712opList=system.cpu3.fuPool.FUList8.opList 1713 1714[system.cpu3.fuPool.FUList8.opList] 1715type=OpDesc 1716issueLat=3 1717opClass=IprAccess 1718opLat=3 1719 1720[system.cpu3.icache] 1721type=BaseCache 1722addr_ranges=0:18446744073709551615 1723assoc=1 1724block_size=64 1725clock=500 1726forward_snoops=true 1727hit_latency=2 1728is_top_level=true 1729max_miss_count=0 1730mshrs=4 1731prefetch_on_access=false 1732prefetcher=Null 1733response_latency=2 1734size=32768 1735system=system 1736tgts_per_mshr=20 1737two_queue=false 1738write_buffers=8 1739cpu_side=system.cpu3.icache_port 1740mem_side=system.toL2Bus.slave[6] 1741 1742[system.cpu3.interrupts] 1743type=SparcInterrupts 1744 1745[system.cpu3.isa] 1746type=SparcISA 1747 1748[system.cpu3.itb] 1749type=SparcTLB 1750size=64 1751 1752[system.cpu3.tracer] 1753type=ExeTracer 1754 1755[system.l2c] 1756type=BaseCache 1757addr_ranges=0:18446744073709551615 1758assoc=8 1759block_size=64 1760clock=500 1761forward_snoops=true 1762hit_latency=20 1763is_top_level=false 1764max_miss_count=0 1765mshrs=20 1766prefetch_on_access=false 1767prefetcher=Null 1768response_latency=20 1769size=4194304 1770system=system 1771tgts_per_mshr=12 1772two_queue=false 1773write_buffers=8 1774cpu_side=system.toL2Bus.master[0] 1775mem_side=system.membus.slave[0] 1776 1777[system.membus] 1778type=CoherentBus 1779block_size=64 1780clock=1000 1781header_cycles=1 1782use_default_range=false 1783width=8 1784master=system.physmem.port 1785slave=system.l2c.mem_side system.system_port 1786 1787[system.physmem] 1788type=SimpleDRAM 1789activation_limit=4 1790addr_mapping=openmap 1791banks_per_rank=8 1792clock=1000 1793conf_table_reported=false 1794in_addr_map=true 1795lines_per_rowbuffer=32 1796mem_sched_policy=frfcfs 1797null=false 1798page_policy=open 1799range=0:134217727 1800ranks_per_channel=2 1801read_buffer_size=32 1802tBURST=5000 1803tCL=13750 1804tRCD=13750 1805tREFI=7800000 1806tRFC=300000 1807tRP=13750 1808tWTR=7500 1809tXAW=40000 1810write_buffer_size=32 1811write_thresh_perc=70 1812zero=false 1813port=system.membus.master[0] 1814 1815[system.toL2Bus] 1816type=CoherentBus 1817block_size=64 1818clock=500 1819header_cycles=1 1820use_default_range=false 1821width=8 1822master=system.l2c.cpu_side 1823slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 1824 1825