config.ini revision 9449:56610ab73040
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=timing 18mem_ranges= 19memories=system.physmem 20num_work_ids=16 21readfile= 22symbolfile= 23work_begin_ckpt_count=0 24work_begin_cpu_id_exit=-1 25work_begin_exit_count=0 26work_cpus_ckpt_count=0 27work_end_ckpt_count=0 28work_end_exit_count=0 29work_item_id=-1 30system_port=system.membus.slave[1] 31 32[system.cpu0] 33type=DerivO3CPU 34children=dcache dtb fuPool icache interrupts isa itb tracer workload 35BTBEntries=4096 36BTBTagSize=16 37LFSTSize=1024 38LQEntries=32 39LSQCheckLoads=true 40LSQDepCheckShift=4 41RASSize=16 42SQEntries=32 43SSITSize=1024 44activity=0 45backComSize=5 46cachePorts=200 47checker=Null 48choiceCtrBits=2 49choicePredictorSize=8192 50clock=500 51commitToDecodeDelay=1 52commitToFetchDelay=1 53commitToIEWDelay=1 54commitToRenameDelay=1 55commitWidth=8 56cpu_id=0 57decodeToFetchDelay=1 58decodeToRenameDelay=1 59decodeWidth=8 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu0.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu0.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu0.interrupts 81isa=system.cpu0.isa 82issueToExecuteDelay=1 83issueWidth=8 84itb=system.cpu0.itb 85localCtrBits=2 86localHistoryBits=11 87localHistoryTableSize=2048 88localPredictorSize=2048 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=false 94numIQEntries=64 95numPhysFloatRegs=256 96numPhysIntRegs=256 97numROBEntries=192 98numRobs=1 99numThreads=1 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000 119switched_out=false 120system=system 121tracer=system.cpu0.tracer 122trapLatency=13 123wbDepth=1 124wbWidth=8 125workload=system.cpu0.workload 126dcache_port=system.cpu0.dcache.cpu_side 127icache_port=system.cpu0.icache.cpu_side 128 129[system.cpu0.dcache] 130type=BaseCache 131addr_ranges=0:18446744073709551615 132assoc=4 133block_size=64 134clock=500 135forward_snoops=true 136hit_latency=2 137is_top_level=true 138max_miss_count=0 139mshrs=4 140prefetch_on_access=false 141prefetcher=Null 142response_latency=2 143size=32768 144system=system 145tgts_per_mshr=20 146two_queue=false 147write_buffers=8 148cpu_side=system.cpu0.dcache_port 149mem_side=system.toL2Bus.slave[1] 150 151[system.cpu0.dtb] 152type=SparcTLB 153size=64 154 155[system.cpu0.fuPool] 156type=FUPool 157children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 158FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 159 160[system.cpu0.fuPool.FUList0] 161type=FUDesc 162children=opList 163count=6 164opList=system.cpu0.fuPool.FUList0.opList 165 166[system.cpu0.fuPool.FUList0.opList] 167type=OpDesc 168issueLat=1 169opClass=IntAlu 170opLat=1 171 172[system.cpu0.fuPool.FUList1] 173type=FUDesc 174children=opList0 opList1 175count=2 176opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 177 178[system.cpu0.fuPool.FUList1.opList0] 179type=OpDesc 180issueLat=1 181opClass=IntMult 182opLat=3 183 184[system.cpu0.fuPool.FUList1.opList1] 185type=OpDesc 186issueLat=19 187opClass=IntDiv 188opLat=20 189 190[system.cpu0.fuPool.FUList2] 191type=FUDesc 192children=opList0 opList1 opList2 193count=4 194opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 195 196[system.cpu0.fuPool.FUList2.opList0] 197type=OpDesc 198issueLat=1 199opClass=FloatAdd 200opLat=2 201 202[system.cpu0.fuPool.FUList2.opList1] 203type=OpDesc 204issueLat=1 205opClass=FloatCmp 206opLat=2 207 208[system.cpu0.fuPool.FUList2.opList2] 209type=OpDesc 210issueLat=1 211opClass=FloatCvt 212opLat=2 213 214[system.cpu0.fuPool.FUList3] 215type=FUDesc 216children=opList0 opList1 opList2 217count=2 218opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 219 220[system.cpu0.fuPool.FUList3.opList0] 221type=OpDesc 222issueLat=1 223opClass=FloatMult 224opLat=4 225 226[system.cpu0.fuPool.FUList3.opList1] 227type=OpDesc 228issueLat=12 229opClass=FloatDiv 230opLat=12 231 232[system.cpu0.fuPool.FUList3.opList2] 233type=OpDesc 234issueLat=24 235opClass=FloatSqrt 236opLat=24 237 238[system.cpu0.fuPool.FUList4] 239type=FUDesc 240children=opList 241count=0 242opList=system.cpu0.fuPool.FUList4.opList 243 244[system.cpu0.fuPool.FUList4.opList] 245type=OpDesc 246issueLat=1 247opClass=MemRead 248opLat=1 249 250[system.cpu0.fuPool.FUList5] 251type=FUDesc 252children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 253count=4 254opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 255 256[system.cpu0.fuPool.FUList5.opList00] 257type=OpDesc 258issueLat=1 259opClass=SimdAdd 260opLat=1 261 262[system.cpu0.fuPool.FUList5.opList01] 263type=OpDesc 264issueLat=1 265opClass=SimdAddAcc 266opLat=1 267 268[system.cpu0.fuPool.FUList5.opList02] 269type=OpDesc 270issueLat=1 271opClass=SimdAlu 272opLat=1 273 274[system.cpu0.fuPool.FUList5.opList03] 275type=OpDesc 276issueLat=1 277opClass=SimdCmp 278opLat=1 279 280[system.cpu0.fuPool.FUList5.opList04] 281type=OpDesc 282issueLat=1 283opClass=SimdCvt 284opLat=1 285 286[system.cpu0.fuPool.FUList5.opList05] 287type=OpDesc 288issueLat=1 289opClass=SimdMisc 290opLat=1 291 292[system.cpu0.fuPool.FUList5.opList06] 293type=OpDesc 294issueLat=1 295opClass=SimdMult 296opLat=1 297 298[system.cpu0.fuPool.FUList5.opList07] 299type=OpDesc 300issueLat=1 301opClass=SimdMultAcc 302opLat=1 303 304[system.cpu0.fuPool.FUList5.opList08] 305type=OpDesc 306issueLat=1 307opClass=SimdShift 308opLat=1 309 310[system.cpu0.fuPool.FUList5.opList09] 311type=OpDesc 312issueLat=1 313opClass=SimdShiftAcc 314opLat=1 315 316[system.cpu0.fuPool.FUList5.opList10] 317type=OpDesc 318issueLat=1 319opClass=SimdSqrt 320opLat=1 321 322[system.cpu0.fuPool.FUList5.opList11] 323type=OpDesc 324issueLat=1 325opClass=SimdFloatAdd 326opLat=1 327 328[system.cpu0.fuPool.FUList5.opList12] 329type=OpDesc 330issueLat=1 331opClass=SimdFloatAlu 332opLat=1 333 334[system.cpu0.fuPool.FUList5.opList13] 335type=OpDesc 336issueLat=1 337opClass=SimdFloatCmp 338opLat=1 339 340[system.cpu0.fuPool.FUList5.opList14] 341type=OpDesc 342issueLat=1 343opClass=SimdFloatCvt 344opLat=1 345 346[system.cpu0.fuPool.FUList5.opList15] 347type=OpDesc 348issueLat=1 349opClass=SimdFloatDiv 350opLat=1 351 352[system.cpu0.fuPool.FUList5.opList16] 353type=OpDesc 354issueLat=1 355opClass=SimdFloatMisc 356opLat=1 357 358[system.cpu0.fuPool.FUList5.opList17] 359type=OpDesc 360issueLat=1 361opClass=SimdFloatMult 362opLat=1 363 364[system.cpu0.fuPool.FUList5.opList18] 365type=OpDesc 366issueLat=1 367opClass=SimdFloatMultAcc 368opLat=1 369 370[system.cpu0.fuPool.FUList5.opList19] 371type=OpDesc 372issueLat=1 373opClass=SimdFloatSqrt 374opLat=1 375 376[system.cpu0.fuPool.FUList6] 377type=FUDesc 378children=opList 379count=0 380opList=system.cpu0.fuPool.FUList6.opList 381 382[system.cpu0.fuPool.FUList6.opList] 383type=OpDesc 384issueLat=1 385opClass=MemWrite 386opLat=1 387 388[system.cpu0.fuPool.FUList7] 389type=FUDesc 390children=opList0 opList1 391count=4 392opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 393 394[system.cpu0.fuPool.FUList7.opList0] 395type=OpDesc 396issueLat=1 397opClass=MemRead 398opLat=1 399 400[system.cpu0.fuPool.FUList7.opList1] 401type=OpDesc 402issueLat=1 403opClass=MemWrite 404opLat=1 405 406[system.cpu0.fuPool.FUList8] 407type=FUDesc 408children=opList 409count=1 410opList=system.cpu0.fuPool.FUList8.opList 411 412[system.cpu0.fuPool.FUList8.opList] 413type=OpDesc 414issueLat=3 415opClass=IprAccess 416opLat=3 417 418[system.cpu0.icache] 419type=BaseCache 420addr_ranges=0:18446744073709551615 421assoc=1 422block_size=64 423clock=500 424forward_snoops=true 425hit_latency=2 426is_top_level=true 427max_miss_count=0 428mshrs=4 429prefetch_on_access=false 430prefetcher=Null 431response_latency=2 432size=32768 433system=system 434tgts_per_mshr=20 435two_queue=false 436write_buffers=8 437cpu_side=system.cpu0.icache_port 438mem_side=system.toL2Bus.slave[0] 439 440[system.cpu0.interrupts] 441type=SparcInterrupts 442 443[system.cpu0.isa] 444type=SparcISA 445 446[system.cpu0.itb] 447type=SparcTLB 448size=64 449 450[system.cpu0.tracer] 451type=ExeTracer 452 453[system.cpu0.workload] 454type=LiveProcess 455cmd=test_atomic 4 456cwd= 457egid=100 458env= 459errout=cerr 460euid=100 461executable=/gem5/dist/test-progs/m5threads/bin/sparc/linux/test_atomic 462gid=100 463input=cin 464max_stack_size=67108864 465output=cout 466pid=100 467ppid=99 468simpoint=0 469system=system 470uid=100 471 472[system.cpu1] 473type=DerivO3CPU 474children=dcache dtb fuPool icache interrupts isa itb tracer 475BTBEntries=4096 476BTBTagSize=16 477LFSTSize=1024 478LQEntries=32 479LSQCheckLoads=true 480LSQDepCheckShift=4 481RASSize=16 482SQEntries=32 483SSITSize=1024 484activity=0 485backComSize=5 486cachePorts=200 487checker=Null 488choiceCtrBits=2 489choicePredictorSize=8192 490clock=500 491commitToDecodeDelay=1 492commitToFetchDelay=1 493commitToIEWDelay=1 494commitToRenameDelay=1 495commitWidth=8 496cpu_id=1 497decodeToFetchDelay=1 498decodeToRenameDelay=1 499decodeWidth=8 500dispatchWidth=8 501do_checkpoint_insts=true 502do_quiesce=true 503do_statistics_insts=true 504dtb=system.cpu1.dtb 505fetchToDecodeDelay=1 506fetchTrapLatency=1 507fetchWidth=8 508forwardComSize=5 509fuPool=system.cpu1.fuPool 510function_trace=false 511function_trace_start=0 512globalCtrBits=2 513globalHistoryBits=13 514globalPredictorSize=8192 515iewToCommitDelay=1 516iewToDecodeDelay=1 517iewToFetchDelay=1 518iewToRenameDelay=1 519instShiftAmt=2 520interrupts=system.cpu1.interrupts 521isa=system.cpu1.isa 522issueToExecuteDelay=1 523issueWidth=8 524itb=system.cpu1.itb 525localCtrBits=2 526localHistoryBits=11 527localHistoryTableSize=2048 528localPredictorSize=2048 529max_insts_all_threads=0 530max_insts_any_thread=0 531max_loads_all_threads=0 532max_loads_any_thread=0 533needsTSO=false 534numIQEntries=64 535numPhysFloatRegs=256 536numPhysIntRegs=256 537numROBEntries=192 538numRobs=1 539numThreads=1 540predType=tournament 541profile=0 542progress_interval=0 543renameToDecodeDelay=1 544renameToFetchDelay=1 545renameToIEWDelay=2 546renameToROBDelay=1 547renameWidth=8 548smtCommitPolicy=RoundRobin 549smtFetchPolicy=SingleThread 550smtIQPolicy=Partitioned 551smtIQThreshold=100 552smtLSQPolicy=Partitioned 553smtLSQThreshold=100 554smtNumFetchingThreads=1 555smtROBPolicy=Partitioned 556smtROBThreshold=100 557squashWidth=8 558store_set_clear_period=250000 559switched_out=false 560system=system 561tracer=system.cpu1.tracer 562trapLatency=13 563wbDepth=1 564wbWidth=8 565workload=system.cpu0.workload 566dcache_port=system.cpu1.dcache.cpu_side 567icache_port=system.cpu1.icache.cpu_side 568 569[system.cpu1.dcache] 570type=BaseCache 571addr_ranges=0:18446744073709551615 572assoc=4 573block_size=64 574clock=500 575forward_snoops=true 576hit_latency=2 577is_top_level=true 578max_miss_count=0 579mshrs=4 580prefetch_on_access=false 581prefetcher=Null 582response_latency=2 583size=32768 584system=system 585tgts_per_mshr=20 586two_queue=false 587write_buffers=8 588cpu_side=system.cpu1.dcache_port 589mem_side=system.toL2Bus.slave[3] 590 591[system.cpu1.dtb] 592type=SparcTLB 593size=64 594 595[system.cpu1.fuPool] 596type=FUPool 597children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 598FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 599 600[system.cpu1.fuPool.FUList0] 601type=FUDesc 602children=opList 603count=6 604opList=system.cpu1.fuPool.FUList0.opList 605 606[system.cpu1.fuPool.FUList0.opList] 607type=OpDesc 608issueLat=1 609opClass=IntAlu 610opLat=1 611 612[system.cpu1.fuPool.FUList1] 613type=FUDesc 614children=opList0 opList1 615count=2 616opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 617 618[system.cpu1.fuPool.FUList1.opList0] 619type=OpDesc 620issueLat=1 621opClass=IntMult 622opLat=3 623 624[system.cpu1.fuPool.FUList1.opList1] 625type=OpDesc 626issueLat=19 627opClass=IntDiv 628opLat=20 629 630[system.cpu1.fuPool.FUList2] 631type=FUDesc 632children=opList0 opList1 opList2 633count=4 634opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 635 636[system.cpu1.fuPool.FUList2.opList0] 637type=OpDesc 638issueLat=1 639opClass=FloatAdd 640opLat=2 641 642[system.cpu1.fuPool.FUList2.opList1] 643type=OpDesc 644issueLat=1 645opClass=FloatCmp 646opLat=2 647 648[system.cpu1.fuPool.FUList2.opList2] 649type=OpDesc 650issueLat=1 651opClass=FloatCvt 652opLat=2 653 654[system.cpu1.fuPool.FUList3] 655type=FUDesc 656children=opList0 opList1 opList2 657count=2 658opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 659 660[system.cpu1.fuPool.FUList3.opList0] 661type=OpDesc 662issueLat=1 663opClass=FloatMult 664opLat=4 665 666[system.cpu1.fuPool.FUList3.opList1] 667type=OpDesc 668issueLat=12 669opClass=FloatDiv 670opLat=12 671 672[system.cpu1.fuPool.FUList3.opList2] 673type=OpDesc 674issueLat=24 675opClass=FloatSqrt 676opLat=24 677 678[system.cpu1.fuPool.FUList4] 679type=FUDesc 680children=opList 681count=0 682opList=system.cpu1.fuPool.FUList4.opList 683 684[system.cpu1.fuPool.FUList4.opList] 685type=OpDesc 686issueLat=1 687opClass=MemRead 688opLat=1 689 690[system.cpu1.fuPool.FUList5] 691type=FUDesc 692children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 693count=4 694opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 695 696[system.cpu1.fuPool.FUList5.opList00] 697type=OpDesc 698issueLat=1 699opClass=SimdAdd 700opLat=1 701 702[system.cpu1.fuPool.FUList5.opList01] 703type=OpDesc 704issueLat=1 705opClass=SimdAddAcc 706opLat=1 707 708[system.cpu1.fuPool.FUList5.opList02] 709type=OpDesc 710issueLat=1 711opClass=SimdAlu 712opLat=1 713 714[system.cpu1.fuPool.FUList5.opList03] 715type=OpDesc 716issueLat=1 717opClass=SimdCmp 718opLat=1 719 720[system.cpu1.fuPool.FUList5.opList04] 721type=OpDesc 722issueLat=1 723opClass=SimdCvt 724opLat=1 725 726[system.cpu1.fuPool.FUList5.opList05] 727type=OpDesc 728issueLat=1 729opClass=SimdMisc 730opLat=1 731 732[system.cpu1.fuPool.FUList5.opList06] 733type=OpDesc 734issueLat=1 735opClass=SimdMult 736opLat=1 737 738[system.cpu1.fuPool.FUList5.opList07] 739type=OpDesc 740issueLat=1 741opClass=SimdMultAcc 742opLat=1 743 744[system.cpu1.fuPool.FUList5.opList08] 745type=OpDesc 746issueLat=1 747opClass=SimdShift 748opLat=1 749 750[system.cpu1.fuPool.FUList5.opList09] 751type=OpDesc 752issueLat=1 753opClass=SimdShiftAcc 754opLat=1 755 756[system.cpu1.fuPool.FUList5.opList10] 757type=OpDesc 758issueLat=1 759opClass=SimdSqrt 760opLat=1 761 762[system.cpu1.fuPool.FUList5.opList11] 763type=OpDesc 764issueLat=1 765opClass=SimdFloatAdd 766opLat=1 767 768[system.cpu1.fuPool.FUList5.opList12] 769type=OpDesc 770issueLat=1 771opClass=SimdFloatAlu 772opLat=1 773 774[system.cpu1.fuPool.FUList5.opList13] 775type=OpDesc 776issueLat=1 777opClass=SimdFloatCmp 778opLat=1 779 780[system.cpu1.fuPool.FUList5.opList14] 781type=OpDesc 782issueLat=1 783opClass=SimdFloatCvt 784opLat=1 785 786[system.cpu1.fuPool.FUList5.opList15] 787type=OpDesc 788issueLat=1 789opClass=SimdFloatDiv 790opLat=1 791 792[system.cpu1.fuPool.FUList5.opList16] 793type=OpDesc 794issueLat=1 795opClass=SimdFloatMisc 796opLat=1 797 798[system.cpu1.fuPool.FUList5.opList17] 799type=OpDesc 800issueLat=1 801opClass=SimdFloatMult 802opLat=1 803 804[system.cpu1.fuPool.FUList5.opList18] 805type=OpDesc 806issueLat=1 807opClass=SimdFloatMultAcc 808opLat=1 809 810[system.cpu1.fuPool.FUList5.opList19] 811type=OpDesc 812issueLat=1 813opClass=SimdFloatSqrt 814opLat=1 815 816[system.cpu1.fuPool.FUList6] 817type=FUDesc 818children=opList 819count=0 820opList=system.cpu1.fuPool.FUList6.opList 821 822[system.cpu1.fuPool.FUList6.opList] 823type=OpDesc 824issueLat=1 825opClass=MemWrite 826opLat=1 827 828[system.cpu1.fuPool.FUList7] 829type=FUDesc 830children=opList0 opList1 831count=4 832opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 833 834[system.cpu1.fuPool.FUList7.opList0] 835type=OpDesc 836issueLat=1 837opClass=MemRead 838opLat=1 839 840[system.cpu1.fuPool.FUList7.opList1] 841type=OpDesc 842issueLat=1 843opClass=MemWrite 844opLat=1 845 846[system.cpu1.fuPool.FUList8] 847type=FUDesc 848children=opList 849count=1 850opList=system.cpu1.fuPool.FUList8.opList 851 852[system.cpu1.fuPool.FUList8.opList] 853type=OpDesc 854issueLat=3 855opClass=IprAccess 856opLat=3 857 858[system.cpu1.icache] 859type=BaseCache 860addr_ranges=0:18446744073709551615 861assoc=1 862block_size=64 863clock=500 864forward_snoops=true 865hit_latency=2 866is_top_level=true 867max_miss_count=0 868mshrs=4 869prefetch_on_access=false 870prefetcher=Null 871response_latency=2 872size=32768 873system=system 874tgts_per_mshr=20 875two_queue=false 876write_buffers=8 877cpu_side=system.cpu1.icache_port 878mem_side=system.toL2Bus.slave[2] 879 880[system.cpu1.interrupts] 881type=SparcInterrupts 882 883[system.cpu1.isa] 884type=SparcISA 885 886[system.cpu1.itb] 887type=SparcTLB 888size=64 889 890[system.cpu1.tracer] 891type=ExeTracer 892 893[system.cpu2] 894type=DerivO3CPU 895children=dcache dtb fuPool icache interrupts isa itb tracer 896BTBEntries=4096 897BTBTagSize=16 898LFSTSize=1024 899LQEntries=32 900LSQCheckLoads=true 901LSQDepCheckShift=4 902RASSize=16 903SQEntries=32 904SSITSize=1024 905activity=0 906backComSize=5 907cachePorts=200 908checker=Null 909choiceCtrBits=2 910choicePredictorSize=8192 911clock=500 912commitToDecodeDelay=1 913commitToFetchDelay=1 914commitToIEWDelay=1 915commitToRenameDelay=1 916commitWidth=8 917cpu_id=2 918decodeToFetchDelay=1 919decodeToRenameDelay=1 920decodeWidth=8 921dispatchWidth=8 922do_checkpoint_insts=true 923do_quiesce=true 924do_statistics_insts=true 925dtb=system.cpu2.dtb 926fetchToDecodeDelay=1 927fetchTrapLatency=1 928fetchWidth=8 929forwardComSize=5 930fuPool=system.cpu2.fuPool 931function_trace=false 932function_trace_start=0 933globalCtrBits=2 934globalHistoryBits=13 935globalPredictorSize=8192 936iewToCommitDelay=1 937iewToDecodeDelay=1 938iewToFetchDelay=1 939iewToRenameDelay=1 940instShiftAmt=2 941interrupts=system.cpu2.interrupts 942isa=system.cpu2.isa 943issueToExecuteDelay=1 944issueWidth=8 945itb=system.cpu2.itb 946localCtrBits=2 947localHistoryBits=11 948localHistoryTableSize=2048 949localPredictorSize=2048 950max_insts_all_threads=0 951max_insts_any_thread=0 952max_loads_all_threads=0 953max_loads_any_thread=0 954needsTSO=false 955numIQEntries=64 956numPhysFloatRegs=256 957numPhysIntRegs=256 958numROBEntries=192 959numRobs=1 960numThreads=1 961predType=tournament 962profile=0 963progress_interval=0 964renameToDecodeDelay=1 965renameToFetchDelay=1 966renameToIEWDelay=2 967renameToROBDelay=1 968renameWidth=8 969smtCommitPolicy=RoundRobin 970smtFetchPolicy=SingleThread 971smtIQPolicy=Partitioned 972smtIQThreshold=100 973smtLSQPolicy=Partitioned 974smtLSQThreshold=100 975smtNumFetchingThreads=1 976smtROBPolicy=Partitioned 977smtROBThreshold=100 978squashWidth=8 979store_set_clear_period=250000 980switched_out=false 981system=system 982tracer=system.cpu2.tracer 983trapLatency=13 984wbDepth=1 985wbWidth=8 986workload=system.cpu0.workload 987dcache_port=system.cpu2.dcache.cpu_side 988icache_port=system.cpu2.icache.cpu_side 989 990[system.cpu2.dcache] 991type=BaseCache 992addr_ranges=0:18446744073709551615 993assoc=4 994block_size=64 995clock=500 996forward_snoops=true 997hit_latency=2 998is_top_level=true 999max_miss_count=0 1000mshrs=4 1001prefetch_on_access=false 1002prefetcher=Null 1003response_latency=2 1004size=32768 1005system=system 1006tgts_per_mshr=20 1007two_queue=false 1008write_buffers=8 1009cpu_side=system.cpu2.dcache_port 1010mem_side=system.toL2Bus.slave[5] 1011 1012[system.cpu2.dtb] 1013type=SparcTLB 1014size=64 1015 1016[system.cpu2.fuPool] 1017type=FUPool 1018children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1019FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1020 1021[system.cpu2.fuPool.FUList0] 1022type=FUDesc 1023children=opList 1024count=6 1025opList=system.cpu2.fuPool.FUList0.opList 1026 1027[system.cpu2.fuPool.FUList0.opList] 1028type=OpDesc 1029issueLat=1 1030opClass=IntAlu 1031opLat=1 1032 1033[system.cpu2.fuPool.FUList1] 1034type=FUDesc 1035children=opList0 opList1 1036count=2 1037opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1038 1039[system.cpu2.fuPool.FUList1.opList0] 1040type=OpDesc 1041issueLat=1 1042opClass=IntMult 1043opLat=3 1044 1045[system.cpu2.fuPool.FUList1.opList1] 1046type=OpDesc 1047issueLat=19 1048opClass=IntDiv 1049opLat=20 1050 1051[system.cpu2.fuPool.FUList2] 1052type=FUDesc 1053children=opList0 opList1 opList2 1054count=4 1055opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1056 1057[system.cpu2.fuPool.FUList2.opList0] 1058type=OpDesc 1059issueLat=1 1060opClass=FloatAdd 1061opLat=2 1062 1063[system.cpu2.fuPool.FUList2.opList1] 1064type=OpDesc 1065issueLat=1 1066opClass=FloatCmp 1067opLat=2 1068 1069[system.cpu2.fuPool.FUList2.opList2] 1070type=OpDesc 1071issueLat=1 1072opClass=FloatCvt 1073opLat=2 1074 1075[system.cpu2.fuPool.FUList3] 1076type=FUDesc 1077children=opList0 opList1 opList2 1078count=2 1079opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1080 1081[system.cpu2.fuPool.FUList3.opList0] 1082type=OpDesc 1083issueLat=1 1084opClass=FloatMult 1085opLat=4 1086 1087[system.cpu2.fuPool.FUList3.opList1] 1088type=OpDesc 1089issueLat=12 1090opClass=FloatDiv 1091opLat=12 1092 1093[system.cpu2.fuPool.FUList3.opList2] 1094type=OpDesc 1095issueLat=24 1096opClass=FloatSqrt 1097opLat=24 1098 1099[system.cpu2.fuPool.FUList4] 1100type=FUDesc 1101children=opList 1102count=0 1103opList=system.cpu2.fuPool.FUList4.opList 1104 1105[system.cpu2.fuPool.FUList4.opList] 1106type=OpDesc 1107issueLat=1 1108opClass=MemRead 1109opLat=1 1110 1111[system.cpu2.fuPool.FUList5] 1112type=FUDesc 1113children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1114count=4 1115opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1116 1117[system.cpu2.fuPool.FUList5.opList00] 1118type=OpDesc 1119issueLat=1 1120opClass=SimdAdd 1121opLat=1 1122 1123[system.cpu2.fuPool.FUList5.opList01] 1124type=OpDesc 1125issueLat=1 1126opClass=SimdAddAcc 1127opLat=1 1128 1129[system.cpu2.fuPool.FUList5.opList02] 1130type=OpDesc 1131issueLat=1 1132opClass=SimdAlu 1133opLat=1 1134 1135[system.cpu2.fuPool.FUList5.opList03] 1136type=OpDesc 1137issueLat=1 1138opClass=SimdCmp 1139opLat=1 1140 1141[system.cpu2.fuPool.FUList5.opList04] 1142type=OpDesc 1143issueLat=1 1144opClass=SimdCvt 1145opLat=1 1146 1147[system.cpu2.fuPool.FUList5.opList05] 1148type=OpDesc 1149issueLat=1 1150opClass=SimdMisc 1151opLat=1 1152 1153[system.cpu2.fuPool.FUList5.opList06] 1154type=OpDesc 1155issueLat=1 1156opClass=SimdMult 1157opLat=1 1158 1159[system.cpu2.fuPool.FUList5.opList07] 1160type=OpDesc 1161issueLat=1 1162opClass=SimdMultAcc 1163opLat=1 1164 1165[system.cpu2.fuPool.FUList5.opList08] 1166type=OpDesc 1167issueLat=1 1168opClass=SimdShift 1169opLat=1 1170 1171[system.cpu2.fuPool.FUList5.opList09] 1172type=OpDesc 1173issueLat=1 1174opClass=SimdShiftAcc 1175opLat=1 1176 1177[system.cpu2.fuPool.FUList5.opList10] 1178type=OpDesc 1179issueLat=1 1180opClass=SimdSqrt 1181opLat=1 1182 1183[system.cpu2.fuPool.FUList5.opList11] 1184type=OpDesc 1185issueLat=1 1186opClass=SimdFloatAdd 1187opLat=1 1188 1189[system.cpu2.fuPool.FUList5.opList12] 1190type=OpDesc 1191issueLat=1 1192opClass=SimdFloatAlu 1193opLat=1 1194 1195[system.cpu2.fuPool.FUList5.opList13] 1196type=OpDesc 1197issueLat=1 1198opClass=SimdFloatCmp 1199opLat=1 1200 1201[system.cpu2.fuPool.FUList5.opList14] 1202type=OpDesc 1203issueLat=1 1204opClass=SimdFloatCvt 1205opLat=1 1206 1207[system.cpu2.fuPool.FUList5.opList15] 1208type=OpDesc 1209issueLat=1 1210opClass=SimdFloatDiv 1211opLat=1 1212 1213[system.cpu2.fuPool.FUList5.opList16] 1214type=OpDesc 1215issueLat=1 1216opClass=SimdFloatMisc 1217opLat=1 1218 1219[system.cpu2.fuPool.FUList5.opList17] 1220type=OpDesc 1221issueLat=1 1222opClass=SimdFloatMult 1223opLat=1 1224 1225[system.cpu2.fuPool.FUList5.opList18] 1226type=OpDesc 1227issueLat=1 1228opClass=SimdFloatMultAcc 1229opLat=1 1230 1231[system.cpu2.fuPool.FUList5.opList19] 1232type=OpDesc 1233issueLat=1 1234opClass=SimdFloatSqrt 1235opLat=1 1236 1237[system.cpu2.fuPool.FUList6] 1238type=FUDesc 1239children=opList 1240count=0 1241opList=system.cpu2.fuPool.FUList6.opList 1242 1243[system.cpu2.fuPool.FUList6.opList] 1244type=OpDesc 1245issueLat=1 1246opClass=MemWrite 1247opLat=1 1248 1249[system.cpu2.fuPool.FUList7] 1250type=FUDesc 1251children=opList0 opList1 1252count=4 1253opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1254 1255[system.cpu2.fuPool.FUList7.opList0] 1256type=OpDesc 1257issueLat=1 1258opClass=MemRead 1259opLat=1 1260 1261[system.cpu2.fuPool.FUList7.opList1] 1262type=OpDesc 1263issueLat=1 1264opClass=MemWrite 1265opLat=1 1266 1267[system.cpu2.fuPool.FUList8] 1268type=FUDesc 1269children=opList 1270count=1 1271opList=system.cpu2.fuPool.FUList8.opList 1272 1273[system.cpu2.fuPool.FUList8.opList] 1274type=OpDesc 1275issueLat=3 1276opClass=IprAccess 1277opLat=3 1278 1279[system.cpu2.icache] 1280type=BaseCache 1281addr_ranges=0:18446744073709551615 1282assoc=1 1283block_size=64 1284clock=500 1285forward_snoops=true 1286hit_latency=2 1287is_top_level=true 1288max_miss_count=0 1289mshrs=4 1290prefetch_on_access=false 1291prefetcher=Null 1292response_latency=2 1293size=32768 1294system=system 1295tgts_per_mshr=20 1296two_queue=false 1297write_buffers=8 1298cpu_side=system.cpu2.icache_port 1299mem_side=system.toL2Bus.slave[4] 1300 1301[system.cpu2.interrupts] 1302type=SparcInterrupts 1303 1304[system.cpu2.isa] 1305type=SparcISA 1306 1307[system.cpu2.itb] 1308type=SparcTLB 1309size=64 1310 1311[system.cpu2.tracer] 1312type=ExeTracer 1313 1314[system.cpu3] 1315type=DerivO3CPU 1316children=dcache dtb fuPool icache interrupts isa itb tracer 1317BTBEntries=4096 1318BTBTagSize=16 1319LFSTSize=1024 1320LQEntries=32 1321LSQCheckLoads=true 1322LSQDepCheckShift=4 1323RASSize=16 1324SQEntries=32 1325SSITSize=1024 1326activity=0 1327backComSize=5 1328cachePorts=200 1329checker=Null 1330choiceCtrBits=2 1331choicePredictorSize=8192 1332clock=500 1333commitToDecodeDelay=1 1334commitToFetchDelay=1 1335commitToIEWDelay=1 1336commitToRenameDelay=1 1337commitWidth=8 1338cpu_id=3 1339decodeToFetchDelay=1 1340decodeToRenameDelay=1 1341decodeWidth=8 1342dispatchWidth=8 1343do_checkpoint_insts=true 1344do_quiesce=true 1345do_statistics_insts=true 1346dtb=system.cpu3.dtb 1347fetchToDecodeDelay=1 1348fetchTrapLatency=1 1349fetchWidth=8 1350forwardComSize=5 1351fuPool=system.cpu3.fuPool 1352function_trace=false 1353function_trace_start=0 1354globalCtrBits=2 1355globalHistoryBits=13 1356globalPredictorSize=8192 1357iewToCommitDelay=1 1358iewToDecodeDelay=1 1359iewToFetchDelay=1 1360iewToRenameDelay=1 1361instShiftAmt=2 1362interrupts=system.cpu3.interrupts 1363isa=system.cpu3.isa 1364issueToExecuteDelay=1 1365issueWidth=8 1366itb=system.cpu3.itb 1367localCtrBits=2 1368localHistoryBits=11 1369localHistoryTableSize=2048 1370localPredictorSize=2048 1371max_insts_all_threads=0 1372max_insts_any_thread=0 1373max_loads_all_threads=0 1374max_loads_any_thread=0 1375needsTSO=false 1376numIQEntries=64 1377numPhysFloatRegs=256 1378numPhysIntRegs=256 1379numROBEntries=192 1380numRobs=1 1381numThreads=1 1382predType=tournament 1383profile=0 1384progress_interval=0 1385renameToDecodeDelay=1 1386renameToFetchDelay=1 1387renameToIEWDelay=2 1388renameToROBDelay=1 1389renameWidth=8 1390smtCommitPolicy=RoundRobin 1391smtFetchPolicy=SingleThread 1392smtIQPolicy=Partitioned 1393smtIQThreshold=100 1394smtLSQPolicy=Partitioned 1395smtLSQThreshold=100 1396smtNumFetchingThreads=1 1397smtROBPolicy=Partitioned 1398smtROBThreshold=100 1399squashWidth=8 1400store_set_clear_period=250000 1401switched_out=false 1402system=system 1403tracer=system.cpu3.tracer 1404trapLatency=13 1405wbDepth=1 1406wbWidth=8 1407workload=system.cpu0.workload 1408dcache_port=system.cpu3.dcache.cpu_side 1409icache_port=system.cpu3.icache.cpu_side 1410 1411[system.cpu3.dcache] 1412type=BaseCache 1413addr_ranges=0:18446744073709551615 1414assoc=4 1415block_size=64 1416clock=500 1417forward_snoops=true 1418hit_latency=2 1419is_top_level=true 1420max_miss_count=0 1421mshrs=4 1422prefetch_on_access=false 1423prefetcher=Null 1424response_latency=2 1425size=32768 1426system=system 1427tgts_per_mshr=20 1428two_queue=false 1429write_buffers=8 1430cpu_side=system.cpu3.dcache_port 1431mem_side=system.toL2Bus.slave[7] 1432 1433[system.cpu3.dtb] 1434type=SparcTLB 1435size=64 1436 1437[system.cpu3.fuPool] 1438type=FUPool 1439children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1440FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1441 1442[system.cpu3.fuPool.FUList0] 1443type=FUDesc 1444children=opList 1445count=6 1446opList=system.cpu3.fuPool.FUList0.opList 1447 1448[system.cpu3.fuPool.FUList0.opList] 1449type=OpDesc 1450issueLat=1 1451opClass=IntAlu 1452opLat=1 1453 1454[system.cpu3.fuPool.FUList1] 1455type=FUDesc 1456children=opList0 opList1 1457count=2 1458opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1459 1460[system.cpu3.fuPool.FUList1.opList0] 1461type=OpDesc 1462issueLat=1 1463opClass=IntMult 1464opLat=3 1465 1466[system.cpu3.fuPool.FUList1.opList1] 1467type=OpDesc 1468issueLat=19 1469opClass=IntDiv 1470opLat=20 1471 1472[system.cpu3.fuPool.FUList2] 1473type=FUDesc 1474children=opList0 opList1 opList2 1475count=4 1476opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1477 1478[system.cpu3.fuPool.FUList2.opList0] 1479type=OpDesc 1480issueLat=1 1481opClass=FloatAdd 1482opLat=2 1483 1484[system.cpu3.fuPool.FUList2.opList1] 1485type=OpDesc 1486issueLat=1 1487opClass=FloatCmp 1488opLat=2 1489 1490[system.cpu3.fuPool.FUList2.opList2] 1491type=OpDesc 1492issueLat=1 1493opClass=FloatCvt 1494opLat=2 1495 1496[system.cpu3.fuPool.FUList3] 1497type=FUDesc 1498children=opList0 opList1 opList2 1499count=2 1500opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1501 1502[system.cpu3.fuPool.FUList3.opList0] 1503type=OpDesc 1504issueLat=1 1505opClass=FloatMult 1506opLat=4 1507 1508[system.cpu3.fuPool.FUList3.opList1] 1509type=OpDesc 1510issueLat=12 1511opClass=FloatDiv 1512opLat=12 1513 1514[system.cpu3.fuPool.FUList3.opList2] 1515type=OpDesc 1516issueLat=24 1517opClass=FloatSqrt 1518opLat=24 1519 1520[system.cpu3.fuPool.FUList4] 1521type=FUDesc 1522children=opList 1523count=0 1524opList=system.cpu3.fuPool.FUList4.opList 1525 1526[system.cpu3.fuPool.FUList4.opList] 1527type=OpDesc 1528issueLat=1 1529opClass=MemRead 1530opLat=1 1531 1532[system.cpu3.fuPool.FUList5] 1533type=FUDesc 1534children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1535count=4 1536opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1537 1538[system.cpu3.fuPool.FUList5.opList00] 1539type=OpDesc 1540issueLat=1 1541opClass=SimdAdd 1542opLat=1 1543 1544[system.cpu3.fuPool.FUList5.opList01] 1545type=OpDesc 1546issueLat=1 1547opClass=SimdAddAcc 1548opLat=1 1549 1550[system.cpu3.fuPool.FUList5.opList02] 1551type=OpDesc 1552issueLat=1 1553opClass=SimdAlu 1554opLat=1 1555 1556[system.cpu3.fuPool.FUList5.opList03] 1557type=OpDesc 1558issueLat=1 1559opClass=SimdCmp 1560opLat=1 1561 1562[system.cpu3.fuPool.FUList5.opList04] 1563type=OpDesc 1564issueLat=1 1565opClass=SimdCvt 1566opLat=1 1567 1568[system.cpu3.fuPool.FUList5.opList05] 1569type=OpDesc 1570issueLat=1 1571opClass=SimdMisc 1572opLat=1 1573 1574[system.cpu3.fuPool.FUList5.opList06] 1575type=OpDesc 1576issueLat=1 1577opClass=SimdMult 1578opLat=1 1579 1580[system.cpu3.fuPool.FUList5.opList07] 1581type=OpDesc 1582issueLat=1 1583opClass=SimdMultAcc 1584opLat=1 1585 1586[system.cpu3.fuPool.FUList5.opList08] 1587type=OpDesc 1588issueLat=1 1589opClass=SimdShift 1590opLat=1 1591 1592[system.cpu3.fuPool.FUList5.opList09] 1593type=OpDesc 1594issueLat=1 1595opClass=SimdShiftAcc 1596opLat=1 1597 1598[system.cpu3.fuPool.FUList5.opList10] 1599type=OpDesc 1600issueLat=1 1601opClass=SimdSqrt 1602opLat=1 1603 1604[system.cpu3.fuPool.FUList5.opList11] 1605type=OpDesc 1606issueLat=1 1607opClass=SimdFloatAdd 1608opLat=1 1609 1610[system.cpu3.fuPool.FUList5.opList12] 1611type=OpDesc 1612issueLat=1 1613opClass=SimdFloatAlu 1614opLat=1 1615 1616[system.cpu3.fuPool.FUList5.opList13] 1617type=OpDesc 1618issueLat=1 1619opClass=SimdFloatCmp 1620opLat=1 1621 1622[system.cpu3.fuPool.FUList5.opList14] 1623type=OpDesc 1624issueLat=1 1625opClass=SimdFloatCvt 1626opLat=1 1627 1628[system.cpu3.fuPool.FUList5.opList15] 1629type=OpDesc 1630issueLat=1 1631opClass=SimdFloatDiv 1632opLat=1 1633 1634[system.cpu3.fuPool.FUList5.opList16] 1635type=OpDesc 1636issueLat=1 1637opClass=SimdFloatMisc 1638opLat=1 1639 1640[system.cpu3.fuPool.FUList5.opList17] 1641type=OpDesc 1642issueLat=1 1643opClass=SimdFloatMult 1644opLat=1 1645 1646[system.cpu3.fuPool.FUList5.opList18] 1647type=OpDesc 1648issueLat=1 1649opClass=SimdFloatMultAcc 1650opLat=1 1651 1652[system.cpu3.fuPool.FUList5.opList19] 1653type=OpDesc 1654issueLat=1 1655opClass=SimdFloatSqrt 1656opLat=1 1657 1658[system.cpu3.fuPool.FUList6] 1659type=FUDesc 1660children=opList 1661count=0 1662opList=system.cpu3.fuPool.FUList6.opList 1663 1664[system.cpu3.fuPool.FUList6.opList] 1665type=OpDesc 1666issueLat=1 1667opClass=MemWrite 1668opLat=1 1669 1670[system.cpu3.fuPool.FUList7] 1671type=FUDesc 1672children=opList0 opList1 1673count=4 1674opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 1675 1676[system.cpu3.fuPool.FUList7.opList0] 1677type=OpDesc 1678issueLat=1 1679opClass=MemRead 1680opLat=1 1681 1682[system.cpu3.fuPool.FUList7.opList1] 1683type=OpDesc 1684issueLat=1 1685opClass=MemWrite 1686opLat=1 1687 1688[system.cpu3.fuPool.FUList8] 1689type=FUDesc 1690children=opList 1691count=1 1692opList=system.cpu3.fuPool.FUList8.opList 1693 1694[system.cpu3.fuPool.FUList8.opList] 1695type=OpDesc 1696issueLat=3 1697opClass=IprAccess 1698opLat=3 1699 1700[system.cpu3.icache] 1701type=BaseCache 1702addr_ranges=0:18446744073709551615 1703assoc=1 1704block_size=64 1705clock=500 1706forward_snoops=true 1707hit_latency=2 1708is_top_level=true 1709max_miss_count=0 1710mshrs=4 1711prefetch_on_access=false 1712prefetcher=Null 1713response_latency=2 1714size=32768 1715system=system 1716tgts_per_mshr=20 1717two_queue=false 1718write_buffers=8 1719cpu_side=system.cpu3.icache_port 1720mem_side=system.toL2Bus.slave[6] 1721 1722[system.cpu3.interrupts] 1723type=SparcInterrupts 1724 1725[system.cpu3.isa] 1726type=SparcISA 1727 1728[system.cpu3.itb] 1729type=SparcTLB 1730size=64 1731 1732[system.cpu3.tracer] 1733type=ExeTracer 1734 1735[system.l2c] 1736type=BaseCache 1737addr_ranges=0:18446744073709551615 1738assoc=8 1739block_size=64 1740clock=500 1741forward_snoops=true 1742hit_latency=20 1743is_top_level=false 1744max_miss_count=0 1745mshrs=20 1746prefetch_on_access=false 1747prefetcher=Null 1748response_latency=20 1749size=4194304 1750system=system 1751tgts_per_mshr=12 1752two_queue=false 1753write_buffers=8 1754cpu_side=system.toL2Bus.master[0] 1755mem_side=system.membus.slave[0] 1756 1757[system.membus] 1758type=CoherentBus 1759block_size=64 1760clock=1000 1761header_cycles=1 1762use_default_range=false 1763width=8 1764master=system.physmem.port 1765slave=system.l2c.mem_side system.system_port 1766 1767[system.physmem] 1768type=SimpleDRAM 1769addr_mapping=openmap 1770banks_per_rank=8 1771clock=1000 1772conf_table_reported=false 1773in_addr_map=true 1774lines_per_rowbuffer=64 1775mem_sched_policy=fcfs 1776null=false 1777page_policy=open 1778range=0:134217727 1779ranks_per_channel=2 1780read_buffer_size=32 1781tBURST=4000 1782tCL=14000 1783tRCD=14000 1784tREFI=7800000 1785tRFC=300000 1786tRP=14000 1787tWTR=1000 1788write_buffer_size=32 1789write_thresh_perc=70 1790zero=false 1791port=system.membus.master[0] 1792 1793[system.toL2Bus] 1794type=CoherentBus 1795block_size=64 1796clock=500 1797header_cycles=1 1798use_default_range=false 1799width=8 1800master=system.l2c.cpu_side 1801slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 1802 1803