config.ini revision 11440
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 38work_end_ckpt_count=0 39work_end_exit_count=0 40work_item_id=-1 41system_port=system.membus.slave[0] 42 43[system.clk_domain] 44type=SrcClockDomain 45clock=1000 46domain_id=-1 47eventq_index=0 48init_perf_level=0 49voltage_domain=system.voltage_domain 50 51[system.cpu0] 52type=DerivO3CPU 53children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 54LFSTSize=1024 55LQEntries=32 56LSQCheckLoads=true 57LSQDepCheckShift=4 58SQEntries=32 59SSITSize=1024 60activity=0 61backComSize=5 62branchPred=system.cpu0.branchPred 63cachePorts=200 64checker=Null 65clk_domain=system.cpu_clk_domain 66commitToDecodeDelay=1 67commitToFetchDelay=1 68commitToIEWDelay=1 69commitToRenameDelay=1 70commitWidth=8 71cpu_id=0 72decodeToFetchDelay=1 73decodeToRenameDelay=1 74decodeWidth=8 75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dtb=system.cpu0.dtb 80eventq_index=0 81fetchBufferSize=64 82fetchQueueSize=32 83fetchToDecodeDelay=1 84fetchTrapLatency=1 85fetchWidth=8 86forwardComSize=5 87fuPool=system.cpu0.fuPool 88function_trace=false 89function_trace_start=0 90iewToCommitDelay=1 91iewToDecodeDelay=1 92iewToFetchDelay=1 93iewToRenameDelay=1 94interrupts=system.cpu0.interrupts 95isa=system.cpu0.isa 96issueToExecuteDelay=1 97issueWidth=8 98itb=system.cpu0.itb 99max_insts_all_threads=0 100max_insts_any_thread=0 101max_loads_all_threads=0 102max_loads_any_thread=0 103needsTSO=false 104numIQEntries=64 105numPhysCCRegs=0 106numPhysFloatRegs=256 107numPhysIntRegs=256 108numROBEntries=192 109numRobs=1 110numThreads=1 111profile=0 112progress_interval=0 113renameToDecodeDelay=1 114renameToFetchDelay=1 115renameToIEWDelay=2 116renameToROBDelay=1 117renameWidth=8 118simpoint_start_insts= 119smtCommitPolicy=RoundRobin 120smtFetchPolicy=SingleThread 121smtIQPolicy=Partitioned 122smtIQThreshold=100 123smtLSQPolicy=Partitioned 124smtLSQThreshold=100 125smtNumFetchingThreads=1 126smtROBPolicy=Partitioned 127smtROBThreshold=100 128socket_id=0 129squashWidth=8 130store_set_clear_period=250000 131switched_out=false 132system=system 133tracer=system.cpu0.tracer 134trapLatency=13 135wbWidth=8 136workload=system.cpu0.workload 137dcache_port=system.cpu0.dcache.cpu_side 138icache_port=system.cpu0.icache.cpu_side 139 140[system.cpu0.branchPred] 141type=TournamentBP 142BTBEntries=4096 143BTBTagSize=16 144RASSize=16 145choiceCtrBits=2 146choicePredictorSize=8192 147eventq_index=0 148globalCtrBits=2 149globalPredictorSize=8192 150indirectHashGHR=true 151indirectHashTargets=true 152indirectPathLength=3 153indirectSets=256 154indirectTagSize=16 155indirectWays=2 156instShiftAmt=2 157localCtrBits=2 158localHistoryTableSize=2048 159localPredictorSize=2048 160numThreads=1 161useIndirect=true 162 163[system.cpu0.dcache] 164type=Cache 165children=tags 166addr_ranges=0:18446744073709551615 167assoc=4 168clk_domain=system.cpu_clk_domain 169clusivity=mostly_incl 170demand_mshr_reserve=1 171eventq_index=0 172hit_latency=2 173is_read_only=false 174max_miss_count=0 175mshrs=4 176prefetch_on_access=false 177prefetcher=Null 178response_latency=2 179sequential_access=false 180size=32768 181system=system 182tags=system.cpu0.dcache.tags 183tgts_per_mshr=20 184write_buffers=8 185writeback_clean=false 186cpu_side=system.cpu0.dcache_port 187mem_side=system.toL2Bus.slave[1] 188 189[system.cpu0.dcache.tags] 190type=LRU 191assoc=4 192block_size=64 193clk_domain=system.cpu_clk_domain 194eventq_index=0 195hit_latency=2 196sequential_access=false 197size=32768 198 199[system.cpu0.dtb] 200type=SparcTLB 201eventq_index=0 202size=64 203 204[system.cpu0.fuPool] 205type=FUPool 206children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 207FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 208eventq_index=0 209 210[system.cpu0.fuPool.FUList0] 211type=FUDesc 212children=opList 213count=6 214eventq_index=0 215opList=system.cpu0.fuPool.FUList0.opList 216 217[system.cpu0.fuPool.FUList0.opList] 218type=OpDesc 219eventq_index=0 220opClass=IntAlu 221opLat=1 222pipelined=true 223 224[system.cpu0.fuPool.FUList1] 225type=FUDesc 226children=opList0 opList1 227count=2 228eventq_index=0 229opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 230 231[system.cpu0.fuPool.FUList1.opList0] 232type=OpDesc 233eventq_index=0 234opClass=IntMult 235opLat=3 236pipelined=true 237 238[system.cpu0.fuPool.FUList1.opList1] 239type=OpDesc 240eventq_index=0 241opClass=IntDiv 242opLat=20 243pipelined=false 244 245[system.cpu0.fuPool.FUList2] 246type=FUDesc 247children=opList0 opList1 opList2 248count=4 249eventq_index=0 250opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 251 252[system.cpu0.fuPool.FUList2.opList0] 253type=OpDesc 254eventq_index=0 255opClass=FloatAdd 256opLat=2 257pipelined=true 258 259[system.cpu0.fuPool.FUList2.opList1] 260type=OpDesc 261eventq_index=0 262opClass=FloatCmp 263opLat=2 264pipelined=true 265 266[system.cpu0.fuPool.FUList2.opList2] 267type=OpDesc 268eventq_index=0 269opClass=FloatCvt 270opLat=2 271pipelined=true 272 273[system.cpu0.fuPool.FUList3] 274type=FUDesc 275children=opList0 opList1 opList2 276count=2 277eventq_index=0 278opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 279 280[system.cpu0.fuPool.FUList3.opList0] 281type=OpDesc 282eventq_index=0 283opClass=FloatMult 284opLat=4 285pipelined=true 286 287[system.cpu0.fuPool.FUList3.opList1] 288type=OpDesc 289eventq_index=0 290opClass=FloatDiv 291opLat=12 292pipelined=false 293 294[system.cpu0.fuPool.FUList3.opList2] 295type=OpDesc 296eventq_index=0 297opClass=FloatSqrt 298opLat=24 299pipelined=false 300 301[system.cpu0.fuPool.FUList4] 302type=FUDesc 303children=opList 304count=0 305eventq_index=0 306opList=system.cpu0.fuPool.FUList4.opList 307 308[system.cpu0.fuPool.FUList4.opList] 309type=OpDesc 310eventq_index=0 311opClass=MemRead 312opLat=1 313pipelined=true 314 315[system.cpu0.fuPool.FUList5] 316type=FUDesc 317children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 318count=4 319eventq_index=0 320opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 321 322[system.cpu0.fuPool.FUList5.opList00] 323type=OpDesc 324eventq_index=0 325opClass=SimdAdd 326opLat=1 327pipelined=true 328 329[system.cpu0.fuPool.FUList5.opList01] 330type=OpDesc 331eventq_index=0 332opClass=SimdAddAcc 333opLat=1 334pipelined=true 335 336[system.cpu0.fuPool.FUList5.opList02] 337type=OpDesc 338eventq_index=0 339opClass=SimdAlu 340opLat=1 341pipelined=true 342 343[system.cpu0.fuPool.FUList5.opList03] 344type=OpDesc 345eventq_index=0 346opClass=SimdCmp 347opLat=1 348pipelined=true 349 350[system.cpu0.fuPool.FUList5.opList04] 351type=OpDesc 352eventq_index=0 353opClass=SimdCvt 354opLat=1 355pipelined=true 356 357[system.cpu0.fuPool.FUList5.opList05] 358type=OpDesc 359eventq_index=0 360opClass=SimdMisc 361opLat=1 362pipelined=true 363 364[system.cpu0.fuPool.FUList5.opList06] 365type=OpDesc 366eventq_index=0 367opClass=SimdMult 368opLat=1 369pipelined=true 370 371[system.cpu0.fuPool.FUList5.opList07] 372type=OpDesc 373eventq_index=0 374opClass=SimdMultAcc 375opLat=1 376pipelined=true 377 378[system.cpu0.fuPool.FUList5.opList08] 379type=OpDesc 380eventq_index=0 381opClass=SimdShift 382opLat=1 383pipelined=true 384 385[system.cpu0.fuPool.FUList5.opList09] 386type=OpDesc 387eventq_index=0 388opClass=SimdShiftAcc 389opLat=1 390pipelined=true 391 392[system.cpu0.fuPool.FUList5.opList10] 393type=OpDesc 394eventq_index=0 395opClass=SimdSqrt 396opLat=1 397pipelined=true 398 399[system.cpu0.fuPool.FUList5.opList11] 400type=OpDesc 401eventq_index=0 402opClass=SimdFloatAdd 403opLat=1 404pipelined=true 405 406[system.cpu0.fuPool.FUList5.opList12] 407type=OpDesc 408eventq_index=0 409opClass=SimdFloatAlu 410opLat=1 411pipelined=true 412 413[system.cpu0.fuPool.FUList5.opList13] 414type=OpDesc 415eventq_index=0 416opClass=SimdFloatCmp 417opLat=1 418pipelined=true 419 420[system.cpu0.fuPool.FUList5.opList14] 421type=OpDesc 422eventq_index=0 423opClass=SimdFloatCvt 424opLat=1 425pipelined=true 426 427[system.cpu0.fuPool.FUList5.opList15] 428type=OpDesc 429eventq_index=0 430opClass=SimdFloatDiv 431opLat=1 432pipelined=true 433 434[system.cpu0.fuPool.FUList5.opList16] 435type=OpDesc 436eventq_index=0 437opClass=SimdFloatMisc 438opLat=1 439pipelined=true 440 441[system.cpu0.fuPool.FUList5.opList17] 442type=OpDesc 443eventq_index=0 444opClass=SimdFloatMult 445opLat=1 446pipelined=true 447 448[system.cpu0.fuPool.FUList5.opList18] 449type=OpDesc 450eventq_index=0 451opClass=SimdFloatMultAcc 452opLat=1 453pipelined=true 454 455[system.cpu0.fuPool.FUList5.opList19] 456type=OpDesc 457eventq_index=0 458opClass=SimdFloatSqrt 459opLat=1 460pipelined=true 461 462[system.cpu0.fuPool.FUList6] 463type=FUDesc 464children=opList 465count=0 466eventq_index=0 467opList=system.cpu0.fuPool.FUList6.opList 468 469[system.cpu0.fuPool.FUList6.opList] 470type=OpDesc 471eventq_index=0 472opClass=MemWrite 473opLat=1 474pipelined=true 475 476[system.cpu0.fuPool.FUList7] 477type=FUDesc 478children=opList0 opList1 479count=4 480eventq_index=0 481opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 482 483[system.cpu0.fuPool.FUList7.opList0] 484type=OpDesc 485eventq_index=0 486opClass=MemRead 487opLat=1 488pipelined=true 489 490[system.cpu0.fuPool.FUList7.opList1] 491type=OpDesc 492eventq_index=0 493opClass=MemWrite 494opLat=1 495pipelined=true 496 497[system.cpu0.fuPool.FUList8] 498type=FUDesc 499children=opList 500count=1 501eventq_index=0 502opList=system.cpu0.fuPool.FUList8.opList 503 504[system.cpu0.fuPool.FUList8.opList] 505type=OpDesc 506eventq_index=0 507opClass=IprAccess 508opLat=3 509pipelined=false 510 511[system.cpu0.icache] 512type=Cache 513children=tags 514addr_ranges=0:18446744073709551615 515assoc=1 516clk_domain=system.cpu_clk_domain 517clusivity=mostly_incl 518demand_mshr_reserve=1 519eventq_index=0 520hit_latency=2 521is_read_only=true 522max_miss_count=0 523mshrs=4 524prefetch_on_access=false 525prefetcher=Null 526response_latency=2 527sequential_access=false 528size=32768 529system=system 530tags=system.cpu0.icache.tags 531tgts_per_mshr=20 532write_buffers=8 533writeback_clean=true 534cpu_side=system.cpu0.icache_port 535mem_side=system.toL2Bus.slave[0] 536 537[system.cpu0.icache.tags] 538type=LRU 539assoc=1 540block_size=64 541clk_domain=system.cpu_clk_domain 542eventq_index=0 543hit_latency=2 544sequential_access=false 545size=32768 546 547[system.cpu0.interrupts] 548type=SparcInterrupts 549eventq_index=0 550 551[system.cpu0.isa] 552type=SparcISA 553eventq_index=0 554 555[system.cpu0.itb] 556type=SparcTLB 557eventq_index=0 558size=64 559 560[system.cpu0.tracer] 561type=ExeTracer 562eventq_index=0 563 564[system.cpu0.workload] 565type=LiveProcess 566cmd=test_atomic 4 567cwd= 568drivers= 569egid=100 570env= 571errout=cerr 572euid=100 573eventq_index=0 574executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic 575gid=100 576input=cin 577kvmInSE=false 578max_stack_size=67108864 579output=cout 580pid=100 581ppid=99 582simpoint=0 583system=system 584uid=100 585useArchPT=false 586 587[system.cpu1] 588type=DerivO3CPU 589children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 590LFSTSize=1024 591LQEntries=32 592LSQCheckLoads=true 593LSQDepCheckShift=4 594SQEntries=32 595SSITSize=1024 596activity=0 597backComSize=5 598branchPred=system.cpu1.branchPred 599cachePorts=200 600checker=Null 601clk_domain=system.cpu_clk_domain 602commitToDecodeDelay=1 603commitToFetchDelay=1 604commitToIEWDelay=1 605commitToRenameDelay=1 606commitWidth=8 607cpu_id=1 608decodeToFetchDelay=1 609decodeToRenameDelay=1 610decodeWidth=8 611dispatchWidth=8 612do_checkpoint_insts=true 613do_quiesce=true 614do_statistics_insts=true 615dtb=system.cpu1.dtb 616eventq_index=0 617fetchBufferSize=64 618fetchQueueSize=32 619fetchToDecodeDelay=1 620fetchTrapLatency=1 621fetchWidth=8 622forwardComSize=5 623fuPool=system.cpu1.fuPool 624function_trace=false 625function_trace_start=0 626iewToCommitDelay=1 627iewToDecodeDelay=1 628iewToFetchDelay=1 629iewToRenameDelay=1 630interrupts=system.cpu1.interrupts 631isa=system.cpu1.isa 632issueToExecuteDelay=1 633issueWidth=8 634itb=system.cpu1.itb 635max_insts_all_threads=0 636max_insts_any_thread=0 637max_loads_all_threads=0 638max_loads_any_thread=0 639needsTSO=false 640numIQEntries=64 641numPhysCCRegs=0 642numPhysFloatRegs=256 643numPhysIntRegs=256 644numROBEntries=192 645numRobs=1 646numThreads=1 647profile=0 648progress_interval=0 649renameToDecodeDelay=1 650renameToFetchDelay=1 651renameToIEWDelay=2 652renameToROBDelay=1 653renameWidth=8 654simpoint_start_insts= 655smtCommitPolicy=RoundRobin 656smtFetchPolicy=SingleThread 657smtIQPolicy=Partitioned 658smtIQThreshold=100 659smtLSQPolicy=Partitioned 660smtLSQThreshold=100 661smtNumFetchingThreads=1 662smtROBPolicy=Partitioned 663smtROBThreshold=100 664socket_id=0 665squashWidth=8 666store_set_clear_period=250000 667switched_out=false 668system=system 669tracer=system.cpu1.tracer 670trapLatency=13 671wbWidth=8 672workload=system.cpu0.workload 673dcache_port=system.cpu1.dcache.cpu_side 674icache_port=system.cpu1.icache.cpu_side 675 676[system.cpu1.branchPred] 677type=TournamentBP 678BTBEntries=4096 679BTBTagSize=16 680RASSize=16 681choiceCtrBits=2 682choicePredictorSize=8192 683eventq_index=0 684globalCtrBits=2 685globalPredictorSize=8192 686indirectHashGHR=true 687indirectHashTargets=true 688indirectPathLength=3 689indirectSets=256 690indirectTagSize=16 691indirectWays=2 692instShiftAmt=2 693localCtrBits=2 694localHistoryTableSize=2048 695localPredictorSize=2048 696numThreads=1 697useIndirect=true 698 699[system.cpu1.dcache] 700type=Cache 701children=tags 702addr_ranges=0:18446744073709551615 703assoc=4 704clk_domain=system.cpu_clk_domain 705clusivity=mostly_incl 706demand_mshr_reserve=1 707eventq_index=0 708hit_latency=2 709is_read_only=false 710max_miss_count=0 711mshrs=4 712prefetch_on_access=false 713prefetcher=Null 714response_latency=2 715sequential_access=false 716size=32768 717system=system 718tags=system.cpu1.dcache.tags 719tgts_per_mshr=20 720write_buffers=8 721writeback_clean=false 722cpu_side=system.cpu1.dcache_port 723mem_side=system.toL2Bus.slave[3] 724 725[system.cpu1.dcache.tags] 726type=LRU 727assoc=4 728block_size=64 729clk_domain=system.cpu_clk_domain 730eventq_index=0 731hit_latency=2 732sequential_access=false 733size=32768 734 735[system.cpu1.dtb] 736type=SparcTLB 737eventq_index=0 738size=64 739 740[system.cpu1.fuPool] 741type=FUPool 742children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 743FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 744eventq_index=0 745 746[system.cpu1.fuPool.FUList0] 747type=FUDesc 748children=opList 749count=6 750eventq_index=0 751opList=system.cpu1.fuPool.FUList0.opList 752 753[system.cpu1.fuPool.FUList0.opList] 754type=OpDesc 755eventq_index=0 756opClass=IntAlu 757opLat=1 758pipelined=true 759 760[system.cpu1.fuPool.FUList1] 761type=FUDesc 762children=opList0 opList1 763count=2 764eventq_index=0 765opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 766 767[system.cpu1.fuPool.FUList1.opList0] 768type=OpDesc 769eventq_index=0 770opClass=IntMult 771opLat=3 772pipelined=true 773 774[system.cpu1.fuPool.FUList1.opList1] 775type=OpDesc 776eventq_index=0 777opClass=IntDiv 778opLat=20 779pipelined=false 780 781[system.cpu1.fuPool.FUList2] 782type=FUDesc 783children=opList0 opList1 opList2 784count=4 785eventq_index=0 786opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 787 788[system.cpu1.fuPool.FUList2.opList0] 789type=OpDesc 790eventq_index=0 791opClass=FloatAdd 792opLat=2 793pipelined=true 794 795[system.cpu1.fuPool.FUList2.opList1] 796type=OpDesc 797eventq_index=0 798opClass=FloatCmp 799opLat=2 800pipelined=true 801 802[system.cpu1.fuPool.FUList2.opList2] 803type=OpDesc 804eventq_index=0 805opClass=FloatCvt 806opLat=2 807pipelined=true 808 809[system.cpu1.fuPool.FUList3] 810type=FUDesc 811children=opList0 opList1 opList2 812count=2 813eventq_index=0 814opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 815 816[system.cpu1.fuPool.FUList3.opList0] 817type=OpDesc 818eventq_index=0 819opClass=FloatMult 820opLat=4 821pipelined=true 822 823[system.cpu1.fuPool.FUList3.opList1] 824type=OpDesc 825eventq_index=0 826opClass=FloatDiv 827opLat=12 828pipelined=false 829 830[system.cpu1.fuPool.FUList3.opList2] 831type=OpDesc 832eventq_index=0 833opClass=FloatSqrt 834opLat=24 835pipelined=false 836 837[system.cpu1.fuPool.FUList4] 838type=FUDesc 839children=opList 840count=0 841eventq_index=0 842opList=system.cpu1.fuPool.FUList4.opList 843 844[system.cpu1.fuPool.FUList4.opList] 845type=OpDesc 846eventq_index=0 847opClass=MemRead 848opLat=1 849pipelined=true 850 851[system.cpu1.fuPool.FUList5] 852type=FUDesc 853children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 854count=4 855eventq_index=0 856opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 857 858[system.cpu1.fuPool.FUList5.opList00] 859type=OpDesc 860eventq_index=0 861opClass=SimdAdd 862opLat=1 863pipelined=true 864 865[system.cpu1.fuPool.FUList5.opList01] 866type=OpDesc 867eventq_index=0 868opClass=SimdAddAcc 869opLat=1 870pipelined=true 871 872[system.cpu1.fuPool.FUList5.opList02] 873type=OpDesc 874eventq_index=0 875opClass=SimdAlu 876opLat=1 877pipelined=true 878 879[system.cpu1.fuPool.FUList5.opList03] 880type=OpDesc 881eventq_index=0 882opClass=SimdCmp 883opLat=1 884pipelined=true 885 886[system.cpu1.fuPool.FUList5.opList04] 887type=OpDesc 888eventq_index=0 889opClass=SimdCvt 890opLat=1 891pipelined=true 892 893[system.cpu1.fuPool.FUList5.opList05] 894type=OpDesc 895eventq_index=0 896opClass=SimdMisc 897opLat=1 898pipelined=true 899 900[system.cpu1.fuPool.FUList5.opList06] 901type=OpDesc 902eventq_index=0 903opClass=SimdMult 904opLat=1 905pipelined=true 906 907[system.cpu1.fuPool.FUList5.opList07] 908type=OpDesc 909eventq_index=0 910opClass=SimdMultAcc 911opLat=1 912pipelined=true 913 914[system.cpu1.fuPool.FUList5.opList08] 915type=OpDesc 916eventq_index=0 917opClass=SimdShift 918opLat=1 919pipelined=true 920 921[system.cpu1.fuPool.FUList5.opList09] 922type=OpDesc 923eventq_index=0 924opClass=SimdShiftAcc 925opLat=1 926pipelined=true 927 928[system.cpu1.fuPool.FUList5.opList10] 929type=OpDesc 930eventq_index=0 931opClass=SimdSqrt 932opLat=1 933pipelined=true 934 935[system.cpu1.fuPool.FUList5.opList11] 936type=OpDesc 937eventq_index=0 938opClass=SimdFloatAdd 939opLat=1 940pipelined=true 941 942[system.cpu1.fuPool.FUList5.opList12] 943type=OpDesc 944eventq_index=0 945opClass=SimdFloatAlu 946opLat=1 947pipelined=true 948 949[system.cpu1.fuPool.FUList5.opList13] 950type=OpDesc 951eventq_index=0 952opClass=SimdFloatCmp 953opLat=1 954pipelined=true 955 956[system.cpu1.fuPool.FUList5.opList14] 957type=OpDesc 958eventq_index=0 959opClass=SimdFloatCvt 960opLat=1 961pipelined=true 962 963[system.cpu1.fuPool.FUList5.opList15] 964type=OpDesc 965eventq_index=0 966opClass=SimdFloatDiv 967opLat=1 968pipelined=true 969 970[system.cpu1.fuPool.FUList5.opList16] 971type=OpDesc 972eventq_index=0 973opClass=SimdFloatMisc 974opLat=1 975pipelined=true 976 977[system.cpu1.fuPool.FUList5.opList17] 978type=OpDesc 979eventq_index=0 980opClass=SimdFloatMult 981opLat=1 982pipelined=true 983 984[system.cpu1.fuPool.FUList5.opList18] 985type=OpDesc 986eventq_index=0 987opClass=SimdFloatMultAcc 988opLat=1 989pipelined=true 990 991[system.cpu1.fuPool.FUList5.opList19] 992type=OpDesc 993eventq_index=0 994opClass=SimdFloatSqrt 995opLat=1 996pipelined=true 997 998[system.cpu1.fuPool.FUList6] 999type=FUDesc 1000children=opList 1001count=0 1002eventq_index=0 1003opList=system.cpu1.fuPool.FUList6.opList 1004 1005[system.cpu1.fuPool.FUList6.opList] 1006type=OpDesc 1007eventq_index=0 1008opClass=MemWrite 1009opLat=1 1010pipelined=true 1011 1012[system.cpu1.fuPool.FUList7] 1013type=FUDesc 1014children=opList0 opList1 1015count=4 1016eventq_index=0 1017opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 1018 1019[system.cpu1.fuPool.FUList7.opList0] 1020type=OpDesc 1021eventq_index=0 1022opClass=MemRead 1023opLat=1 1024pipelined=true 1025 1026[system.cpu1.fuPool.FUList7.opList1] 1027type=OpDesc 1028eventq_index=0 1029opClass=MemWrite 1030opLat=1 1031pipelined=true 1032 1033[system.cpu1.fuPool.FUList8] 1034type=FUDesc 1035children=opList 1036count=1 1037eventq_index=0 1038opList=system.cpu1.fuPool.FUList8.opList 1039 1040[system.cpu1.fuPool.FUList8.opList] 1041type=OpDesc 1042eventq_index=0 1043opClass=IprAccess 1044opLat=3 1045pipelined=false 1046 1047[system.cpu1.icache] 1048type=Cache 1049children=tags 1050addr_ranges=0:18446744073709551615 1051assoc=1 1052clk_domain=system.cpu_clk_domain 1053clusivity=mostly_incl 1054demand_mshr_reserve=1 1055eventq_index=0 1056hit_latency=2 1057is_read_only=true 1058max_miss_count=0 1059mshrs=4 1060prefetch_on_access=false 1061prefetcher=Null 1062response_latency=2 1063sequential_access=false 1064size=32768 1065system=system 1066tags=system.cpu1.icache.tags 1067tgts_per_mshr=20 1068write_buffers=8 1069writeback_clean=true 1070cpu_side=system.cpu1.icache_port 1071mem_side=system.toL2Bus.slave[2] 1072 1073[system.cpu1.icache.tags] 1074type=LRU 1075assoc=1 1076block_size=64 1077clk_domain=system.cpu_clk_domain 1078eventq_index=0 1079hit_latency=2 1080sequential_access=false 1081size=32768 1082 1083[system.cpu1.interrupts] 1084type=SparcInterrupts 1085eventq_index=0 1086 1087[system.cpu1.isa] 1088type=SparcISA 1089eventq_index=0 1090 1091[system.cpu1.itb] 1092type=SparcTLB 1093eventq_index=0 1094size=64 1095 1096[system.cpu1.tracer] 1097type=ExeTracer 1098eventq_index=0 1099 1100[system.cpu2] 1101type=DerivO3CPU 1102children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1103LFSTSize=1024 1104LQEntries=32 1105LSQCheckLoads=true 1106LSQDepCheckShift=4 1107SQEntries=32 1108SSITSize=1024 1109activity=0 1110backComSize=5 1111branchPred=system.cpu2.branchPred 1112cachePorts=200 1113checker=Null 1114clk_domain=system.cpu_clk_domain 1115commitToDecodeDelay=1 1116commitToFetchDelay=1 1117commitToIEWDelay=1 1118commitToRenameDelay=1 1119commitWidth=8 1120cpu_id=2 1121decodeToFetchDelay=1 1122decodeToRenameDelay=1 1123decodeWidth=8 1124dispatchWidth=8 1125do_checkpoint_insts=true 1126do_quiesce=true 1127do_statistics_insts=true 1128dtb=system.cpu2.dtb 1129eventq_index=0 1130fetchBufferSize=64 1131fetchQueueSize=32 1132fetchToDecodeDelay=1 1133fetchTrapLatency=1 1134fetchWidth=8 1135forwardComSize=5 1136fuPool=system.cpu2.fuPool 1137function_trace=false 1138function_trace_start=0 1139iewToCommitDelay=1 1140iewToDecodeDelay=1 1141iewToFetchDelay=1 1142iewToRenameDelay=1 1143interrupts=system.cpu2.interrupts 1144isa=system.cpu2.isa 1145issueToExecuteDelay=1 1146issueWidth=8 1147itb=system.cpu2.itb 1148max_insts_all_threads=0 1149max_insts_any_thread=0 1150max_loads_all_threads=0 1151max_loads_any_thread=0 1152needsTSO=false 1153numIQEntries=64 1154numPhysCCRegs=0 1155numPhysFloatRegs=256 1156numPhysIntRegs=256 1157numROBEntries=192 1158numRobs=1 1159numThreads=1 1160profile=0 1161progress_interval=0 1162renameToDecodeDelay=1 1163renameToFetchDelay=1 1164renameToIEWDelay=2 1165renameToROBDelay=1 1166renameWidth=8 1167simpoint_start_insts= 1168smtCommitPolicy=RoundRobin 1169smtFetchPolicy=SingleThread 1170smtIQPolicy=Partitioned 1171smtIQThreshold=100 1172smtLSQPolicy=Partitioned 1173smtLSQThreshold=100 1174smtNumFetchingThreads=1 1175smtROBPolicy=Partitioned 1176smtROBThreshold=100 1177socket_id=0 1178squashWidth=8 1179store_set_clear_period=250000 1180switched_out=false 1181system=system 1182tracer=system.cpu2.tracer 1183trapLatency=13 1184wbWidth=8 1185workload=system.cpu0.workload 1186dcache_port=system.cpu2.dcache.cpu_side 1187icache_port=system.cpu2.icache.cpu_side 1188 1189[system.cpu2.branchPred] 1190type=TournamentBP 1191BTBEntries=4096 1192BTBTagSize=16 1193RASSize=16 1194choiceCtrBits=2 1195choicePredictorSize=8192 1196eventq_index=0 1197globalCtrBits=2 1198globalPredictorSize=8192 1199indirectHashGHR=true 1200indirectHashTargets=true 1201indirectPathLength=3 1202indirectSets=256 1203indirectTagSize=16 1204indirectWays=2 1205instShiftAmt=2 1206localCtrBits=2 1207localHistoryTableSize=2048 1208localPredictorSize=2048 1209numThreads=1 1210useIndirect=true 1211 1212[system.cpu2.dcache] 1213type=Cache 1214children=tags 1215addr_ranges=0:18446744073709551615 1216assoc=4 1217clk_domain=system.cpu_clk_domain 1218clusivity=mostly_incl 1219demand_mshr_reserve=1 1220eventq_index=0 1221hit_latency=2 1222is_read_only=false 1223max_miss_count=0 1224mshrs=4 1225prefetch_on_access=false 1226prefetcher=Null 1227response_latency=2 1228sequential_access=false 1229size=32768 1230system=system 1231tags=system.cpu2.dcache.tags 1232tgts_per_mshr=20 1233write_buffers=8 1234writeback_clean=false 1235cpu_side=system.cpu2.dcache_port 1236mem_side=system.toL2Bus.slave[5] 1237 1238[system.cpu2.dcache.tags] 1239type=LRU 1240assoc=4 1241block_size=64 1242clk_domain=system.cpu_clk_domain 1243eventq_index=0 1244hit_latency=2 1245sequential_access=false 1246size=32768 1247 1248[system.cpu2.dtb] 1249type=SparcTLB 1250eventq_index=0 1251size=64 1252 1253[system.cpu2.fuPool] 1254type=FUPool 1255children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1256FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 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system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1300 1301[system.cpu2.fuPool.FUList2.opList0] 1302type=OpDesc 1303eventq_index=0 1304opClass=FloatAdd 1305opLat=2 1306pipelined=true 1307 1308[system.cpu2.fuPool.FUList2.opList1] 1309type=OpDesc 1310eventq_index=0 1311opClass=FloatCmp 1312opLat=2 1313pipelined=true 1314 1315[system.cpu2.fuPool.FUList2.opList2] 1316type=OpDesc 1317eventq_index=0 1318opClass=FloatCvt 1319opLat=2 1320pipelined=true 1321 1322[system.cpu2.fuPool.FUList3] 1323type=FUDesc 1324children=opList0 opList1 opList2 1325count=2 1326eventq_index=0 1327opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1328 1329[system.cpu2.fuPool.FUList3.opList0] 1330type=OpDesc 1331eventq_index=0 1332opClass=FloatMult 1333opLat=4 1334pipelined=true 1335 1336[system.cpu2.fuPool.FUList3.opList1] 1337type=OpDesc 1338eventq_index=0 1339opClass=FloatDiv 1340opLat=12 1341pipelined=false 1342 1343[system.cpu2.fuPool.FUList3.opList2] 1344type=OpDesc 1345eventq_index=0 1346opClass=FloatSqrt 1347opLat=24 1348pipelined=false 1349 1350[system.cpu2.fuPool.FUList4] 1351type=FUDesc 1352children=opList 1353count=0 1354eventq_index=0 1355opList=system.cpu2.fuPool.FUList4.opList 1356 1357[system.cpu2.fuPool.FUList4.opList] 1358type=OpDesc 1359eventq_index=0 1360opClass=MemRead 1361opLat=1 1362pipelined=true 1363 1364[system.cpu2.fuPool.FUList5] 1365type=FUDesc 1366children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1367count=4 1368eventq_index=0 1369opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1370 1371[system.cpu2.fuPool.FUList5.opList00] 1372type=OpDesc 1373eventq_index=0 1374opClass=SimdAdd 1375opLat=1 1376pipelined=true 1377 1378[system.cpu2.fuPool.FUList5.opList01] 1379type=OpDesc 1380eventq_index=0 1381opClass=SimdAddAcc 1382opLat=1 1383pipelined=true 1384 1385[system.cpu2.fuPool.FUList5.opList02] 1386type=OpDesc 1387eventq_index=0 1388opClass=SimdAlu 1389opLat=1 1390pipelined=true 1391 1392[system.cpu2.fuPool.FUList5.opList03] 1393type=OpDesc 1394eventq_index=0 1395opClass=SimdCmp 1396opLat=1 1397pipelined=true 1398 1399[system.cpu2.fuPool.FUList5.opList04] 1400type=OpDesc 1401eventq_index=0 1402opClass=SimdCvt 1403opLat=1 1404pipelined=true 1405 1406[system.cpu2.fuPool.FUList5.opList05] 1407type=OpDesc 1408eventq_index=0 1409opClass=SimdMisc 1410opLat=1 1411pipelined=true 1412 1413[system.cpu2.fuPool.FUList5.opList06] 1414type=OpDesc 1415eventq_index=0 1416opClass=SimdMult 1417opLat=1 1418pipelined=true 1419 1420[system.cpu2.fuPool.FUList5.opList07] 1421type=OpDesc 1422eventq_index=0 1423opClass=SimdMultAcc 1424opLat=1 1425pipelined=true 1426 1427[system.cpu2.fuPool.FUList5.opList08] 1428type=OpDesc 1429eventq_index=0 1430opClass=SimdShift 1431opLat=1 1432pipelined=true 1433 1434[system.cpu2.fuPool.FUList5.opList09] 1435type=OpDesc 1436eventq_index=0 1437opClass=SimdShiftAcc 1438opLat=1 1439pipelined=true 1440 1441[system.cpu2.fuPool.FUList5.opList10] 1442type=OpDesc 1443eventq_index=0 1444opClass=SimdSqrt 1445opLat=1 1446pipelined=true 1447 1448[system.cpu2.fuPool.FUList5.opList11] 1449type=OpDesc 1450eventq_index=0 1451opClass=SimdFloatAdd 1452opLat=1 1453pipelined=true 1454 1455[system.cpu2.fuPool.FUList5.opList12] 1456type=OpDesc 1457eventq_index=0 1458opClass=SimdFloatAlu 1459opLat=1 1460pipelined=true 1461 1462[system.cpu2.fuPool.FUList5.opList13] 1463type=OpDesc 1464eventq_index=0 1465opClass=SimdFloatCmp 1466opLat=1 1467pipelined=true 1468 1469[system.cpu2.fuPool.FUList5.opList14] 1470type=OpDesc 1471eventq_index=0 1472opClass=SimdFloatCvt 1473opLat=1 1474pipelined=true 1475 1476[system.cpu2.fuPool.FUList5.opList15] 1477type=OpDesc 1478eventq_index=0 1479opClass=SimdFloatDiv 1480opLat=1 1481pipelined=true 1482 1483[system.cpu2.fuPool.FUList5.opList16] 1484type=OpDesc 1485eventq_index=0 1486opClass=SimdFloatMisc 1487opLat=1 1488pipelined=true 1489 1490[system.cpu2.fuPool.FUList5.opList17] 1491type=OpDesc 1492eventq_index=0 1493opClass=SimdFloatMult 1494opLat=1 1495pipelined=true 1496 1497[system.cpu2.fuPool.FUList5.opList18] 1498type=OpDesc 1499eventq_index=0 1500opClass=SimdFloatMultAcc 1501opLat=1 1502pipelined=true 1503 1504[system.cpu2.fuPool.FUList5.opList19] 1505type=OpDesc 1506eventq_index=0 1507opClass=SimdFloatSqrt 1508opLat=1 1509pipelined=true 1510 1511[system.cpu2.fuPool.FUList6] 1512type=FUDesc 1513children=opList 1514count=0 1515eventq_index=0 1516opList=system.cpu2.fuPool.FUList6.opList 1517 1518[system.cpu2.fuPool.FUList6.opList] 1519type=OpDesc 1520eventq_index=0 1521opClass=MemWrite 1522opLat=1 1523pipelined=true 1524 1525[system.cpu2.fuPool.FUList7] 1526type=FUDesc 1527children=opList0 opList1 1528count=4 1529eventq_index=0 1530opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1531 1532[system.cpu2.fuPool.FUList7.opList0] 1533type=OpDesc 1534eventq_index=0 1535opClass=MemRead 1536opLat=1 1537pipelined=true 1538 1539[system.cpu2.fuPool.FUList7.opList1] 1540type=OpDesc 1541eventq_index=0 1542opClass=MemWrite 1543opLat=1 1544pipelined=true 1545 1546[system.cpu2.fuPool.FUList8] 1547type=FUDesc 1548children=opList 1549count=1 1550eventq_index=0 1551opList=system.cpu2.fuPool.FUList8.opList 1552 1553[system.cpu2.fuPool.FUList8.opList] 1554type=OpDesc 1555eventq_index=0 1556opClass=IprAccess 1557opLat=3 1558pipelined=false 1559 1560[system.cpu2.icache] 1561type=Cache 1562children=tags 1563addr_ranges=0:18446744073709551615 1564assoc=1 1565clk_domain=system.cpu_clk_domain 1566clusivity=mostly_incl 1567demand_mshr_reserve=1 1568eventq_index=0 1569hit_latency=2 1570is_read_only=true 1571max_miss_count=0 1572mshrs=4 1573prefetch_on_access=false 1574prefetcher=Null 1575response_latency=2 1576sequential_access=false 1577size=32768 1578system=system 1579tags=system.cpu2.icache.tags 1580tgts_per_mshr=20 1581write_buffers=8 1582writeback_clean=true 1583cpu_side=system.cpu2.icache_port 1584mem_side=system.toL2Bus.slave[4] 1585 1586[system.cpu2.icache.tags] 1587type=LRU 1588assoc=1 1589block_size=64 1590clk_domain=system.cpu_clk_domain 1591eventq_index=0 1592hit_latency=2 1593sequential_access=false 1594size=32768 1595 1596[system.cpu2.interrupts] 1597type=SparcInterrupts 1598eventq_index=0 1599 1600[system.cpu2.isa] 1601type=SparcISA 1602eventq_index=0 1603 1604[system.cpu2.itb] 1605type=SparcTLB 1606eventq_index=0 1607size=64 1608 1609[system.cpu2.tracer] 1610type=ExeTracer 1611eventq_index=0 1612 1613[system.cpu3] 1614type=DerivO3CPU 1615children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1616LFSTSize=1024 1617LQEntries=32 1618LSQCheckLoads=true 1619LSQDepCheckShift=4 1620SQEntries=32 1621SSITSize=1024 1622activity=0 1623backComSize=5 1624branchPred=system.cpu3.branchPred 1625cachePorts=200 1626checker=Null 1627clk_domain=system.cpu_clk_domain 1628commitToDecodeDelay=1 1629commitToFetchDelay=1 1630commitToIEWDelay=1 1631commitToRenameDelay=1 1632commitWidth=8 1633cpu_id=3 1634decodeToFetchDelay=1 1635decodeToRenameDelay=1 1636decodeWidth=8 1637dispatchWidth=8 1638do_checkpoint_insts=true 1639do_quiesce=true 1640do_statistics_insts=true 1641dtb=system.cpu3.dtb 1642eventq_index=0 1643fetchBufferSize=64 1644fetchQueueSize=32 1645fetchToDecodeDelay=1 1646fetchTrapLatency=1 1647fetchWidth=8 1648forwardComSize=5 1649fuPool=system.cpu3.fuPool 1650function_trace=false 1651function_trace_start=0 1652iewToCommitDelay=1 1653iewToDecodeDelay=1 1654iewToFetchDelay=1 1655iewToRenameDelay=1 1656interrupts=system.cpu3.interrupts 1657isa=system.cpu3.isa 1658issueToExecuteDelay=1 1659issueWidth=8 1660itb=system.cpu3.itb 1661max_insts_all_threads=0 1662max_insts_any_thread=0 1663max_loads_all_threads=0 1664max_loads_any_thread=0 1665needsTSO=false 1666numIQEntries=64 1667numPhysCCRegs=0 1668numPhysFloatRegs=256 1669numPhysIntRegs=256 1670numROBEntries=192 1671numRobs=1 1672numThreads=1 1673profile=0 1674progress_interval=0 1675renameToDecodeDelay=1 1676renameToFetchDelay=1 1677renameToIEWDelay=2 1678renameToROBDelay=1 1679renameWidth=8 1680simpoint_start_insts= 1681smtCommitPolicy=RoundRobin 1682smtFetchPolicy=SingleThread 1683smtIQPolicy=Partitioned 1684smtIQThreshold=100 1685smtLSQPolicy=Partitioned 1686smtLSQThreshold=100 1687smtNumFetchingThreads=1 1688smtROBPolicy=Partitioned 1689smtROBThreshold=100 1690socket_id=0 1691squashWidth=8 1692store_set_clear_period=250000 1693switched_out=false 1694system=system 1695tracer=system.cpu3.tracer 1696trapLatency=13 1697wbWidth=8 1698workload=system.cpu0.workload 1699dcache_port=system.cpu3.dcache.cpu_side 1700icache_port=system.cpu3.icache.cpu_side 1701 1702[system.cpu3.branchPred] 1703type=TournamentBP 1704BTBEntries=4096 1705BTBTagSize=16 1706RASSize=16 1707choiceCtrBits=2 1708choicePredictorSize=8192 1709eventq_index=0 1710globalCtrBits=2 1711globalPredictorSize=8192 1712indirectHashGHR=true 1713indirectHashTargets=true 1714indirectPathLength=3 1715indirectSets=256 1716indirectTagSize=16 1717indirectWays=2 1718instShiftAmt=2 1719localCtrBits=2 1720localHistoryTableSize=2048 1721localPredictorSize=2048 1722numThreads=1 1723useIndirect=true 1724 1725[system.cpu3.dcache] 1726type=Cache 1727children=tags 1728addr_ranges=0:18446744073709551615 1729assoc=4 1730clk_domain=system.cpu_clk_domain 1731clusivity=mostly_incl 1732demand_mshr_reserve=1 1733eventq_index=0 1734hit_latency=2 1735is_read_only=false 1736max_miss_count=0 1737mshrs=4 1738prefetch_on_access=false 1739prefetcher=Null 1740response_latency=2 1741sequential_access=false 1742size=32768 1743system=system 1744tags=system.cpu3.dcache.tags 1745tgts_per_mshr=20 1746write_buffers=8 1747writeback_clean=false 1748cpu_side=system.cpu3.dcache_port 1749mem_side=system.toL2Bus.slave[7] 1750 1751[system.cpu3.dcache.tags] 1752type=LRU 1753assoc=4 1754block_size=64 1755clk_domain=system.cpu_clk_domain 1756eventq_index=0 1757hit_latency=2 1758sequential_access=false 1759size=32768 1760 1761[system.cpu3.dtb] 1762type=SparcTLB 1763eventq_index=0 1764size=64 1765 1766[system.cpu3.fuPool] 1767type=FUPool 1768children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1769FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1770eventq_index=0 1771 1772[system.cpu3.fuPool.FUList0] 1773type=FUDesc 1774children=opList 1775count=6 1776eventq_index=0 1777opList=system.cpu3.fuPool.FUList0.opList 1778 1779[system.cpu3.fuPool.FUList0.opList] 1780type=OpDesc 1781eventq_index=0 1782opClass=IntAlu 1783opLat=1 1784pipelined=true 1785 1786[system.cpu3.fuPool.FUList1] 1787type=FUDesc 1788children=opList0 opList1 1789count=2 1790eventq_index=0 1791opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1792 1793[system.cpu3.fuPool.FUList1.opList0] 1794type=OpDesc 1795eventq_index=0 1796opClass=IntMult 1797opLat=3 1798pipelined=true 1799 1800[system.cpu3.fuPool.FUList1.opList1] 1801type=OpDesc 1802eventq_index=0 1803opClass=IntDiv 1804opLat=20 1805pipelined=false 1806 1807[system.cpu3.fuPool.FUList2] 1808type=FUDesc 1809children=opList0 opList1 opList2 1810count=4 1811eventq_index=0 1812opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1813 1814[system.cpu3.fuPool.FUList2.opList0] 1815type=OpDesc 1816eventq_index=0 1817opClass=FloatAdd 1818opLat=2 1819pipelined=true 1820 1821[system.cpu3.fuPool.FUList2.opList1] 1822type=OpDesc 1823eventq_index=0 1824opClass=FloatCmp 1825opLat=2 1826pipelined=true 1827 1828[system.cpu3.fuPool.FUList2.opList2] 1829type=OpDesc 1830eventq_index=0 1831opClass=FloatCvt 1832opLat=2 1833pipelined=true 1834 1835[system.cpu3.fuPool.FUList3] 1836type=FUDesc 1837children=opList0 opList1 opList2 1838count=2 1839eventq_index=0 1840opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1841 1842[system.cpu3.fuPool.FUList3.opList0] 1843type=OpDesc 1844eventq_index=0 1845opClass=FloatMult 1846opLat=4 1847pipelined=true 1848 1849[system.cpu3.fuPool.FUList3.opList1] 1850type=OpDesc 1851eventq_index=0 1852opClass=FloatDiv 1853opLat=12 1854pipelined=false 1855 1856[system.cpu3.fuPool.FUList3.opList2] 1857type=OpDesc 1858eventq_index=0 1859opClass=FloatSqrt 1860opLat=24 1861pipelined=false 1862 1863[system.cpu3.fuPool.FUList4] 1864type=FUDesc 1865children=opList 1866count=0 1867eventq_index=0 1868opList=system.cpu3.fuPool.FUList4.opList 1869 1870[system.cpu3.fuPool.FUList4.opList] 1871type=OpDesc 1872eventq_index=0 1873opClass=MemRead 1874opLat=1 1875pipelined=true 1876 1877[system.cpu3.fuPool.FUList5] 1878type=FUDesc 1879children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1880count=4 1881eventq_index=0 1882opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1883 1884[system.cpu3.fuPool.FUList5.opList00] 1885type=OpDesc 1886eventq_index=0 1887opClass=SimdAdd 1888opLat=1 1889pipelined=true 1890 1891[system.cpu3.fuPool.FUList5.opList01] 1892type=OpDesc 1893eventq_index=0 1894opClass=SimdAddAcc 1895opLat=1 1896pipelined=true 1897 1898[system.cpu3.fuPool.FUList5.opList02] 1899type=OpDesc 1900eventq_index=0 1901opClass=SimdAlu 1902opLat=1 1903pipelined=true 1904 1905[system.cpu3.fuPool.FUList5.opList03] 1906type=OpDesc 1907eventq_index=0 1908opClass=SimdCmp 1909opLat=1 1910pipelined=true 1911 1912[system.cpu3.fuPool.FUList5.opList04] 1913type=OpDesc 1914eventq_index=0 1915opClass=SimdCvt 1916opLat=1 1917pipelined=true 1918 1919[system.cpu3.fuPool.FUList5.opList05] 1920type=OpDesc 1921eventq_index=0 1922opClass=SimdMisc 1923opLat=1 1924pipelined=true 1925 1926[system.cpu3.fuPool.FUList5.opList06] 1927type=OpDesc 1928eventq_index=0 1929opClass=SimdMult 1930opLat=1 1931pipelined=true 1932 1933[system.cpu3.fuPool.FUList5.opList07] 1934type=OpDesc 1935eventq_index=0 1936opClass=SimdMultAcc 1937opLat=1 1938pipelined=true 1939 1940[system.cpu3.fuPool.FUList5.opList08] 1941type=OpDesc 1942eventq_index=0 1943opClass=SimdShift 1944opLat=1 1945pipelined=true 1946 1947[system.cpu3.fuPool.FUList5.opList09] 1948type=OpDesc 1949eventq_index=0 1950opClass=SimdShiftAcc 1951opLat=1 1952pipelined=true 1953 1954[system.cpu3.fuPool.FUList5.opList10] 1955type=OpDesc 1956eventq_index=0 1957opClass=SimdSqrt 1958opLat=1 1959pipelined=true 1960 1961[system.cpu3.fuPool.FUList5.opList11] 1962type=OpDesc 1963eventq_index=0 1964opClass=SimdFloatAdd 1965opLat=1 1966pipelined=true 1967 1968[system.cpu3.fuPool.FUList5.opList12] 1969type=OpDesc 1970eventq_index=0 1971opClass=SimdFloatAlu 1972opLat=1 1973pipelined=true 1974 1975[system.cpu3.fuPool.FUList5.opList13] 1976type=OpDesc 1977eventq_index=0 1978opClass=SimdFloatCmp 1979opLat=1 1980pipelined=true 1981 1982[system.cpu3.fuPool.FUList5.opList14] 1983type=OpDesc 1984eventq_index=0 1985opClass=SimdFloatCvt 1986opLat=1 1987pipelined=true 1988 1989[system.cpu3.fuPool.FUList5.opList15] 1990type=OpDesc 1991eventq_index=0 1992opClass=SimdFloatDiv 1993opLat=1 1994pipelined=true 1995 1996[system.cpu3.fuPool.FUList5.opList16] 1997type=OpDesc 1998eventq_index=0 1999opClass=SimdFloatMisc 2000opLat=1 2001pipelined=true 2002 2003[system.cpu3.fuPool.FUList5.opList17] 2004type=OpDesc 2005eventq_index=0 2006opClass=SimdFloatMult 2007opLat=1 2008pipelined=true 2009 2010[system.cpu3.fuPool.FUList5.opList18] 2011type=OpDesc 2012eventq_index=0 2013opClass=SimdFloatMultAcc 2014opLat=1 2015pipelined=true 2016 2017[system.cpu3.fuPool.FUList5.opList19] 2018type=OpDesc 2019eventq_index=0 2020opClass=SimdFloatSqrt 2021opLat=1 2022pipelined=true 2023 2024[system.cpu3.fuPool.FUList6] 2025type=FUDesc 2026children=opList 2027count=0 2028eventq_index=0 2029opList=system.cpu3.fuPool.FUList6.opList 2030 2031[system.cpu3.fuPool.FUList6.opList] 2032type=OpDesc 2033eventq_index=0 2034opClass=MemWrite 2035opLat=1 2036pipelined=true 2037 2038[system.cpu3.fuPool.FUList7] 2039type=FUDesc 2040children=opList0 opList1 2041count=4 2042eventq_index=0 2043opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 2044 2045[system.cpu3.fuPool.FUList7.opList0] 2046type=OpDesc 2047eventq_index=0 2048opClass=MemRead 2049opLat=1 2050pipelined=true 2051 2052[system.cpu3.fuPool.FUList7.opList1] 2053type=OpDesc 2054eventq_index=0 2055opClass=MemWrite 2056opLat=1 2057pipelined=true 2058 2059[system.cpu3.fuPool.FUList8] 2060type=FUDesc 2061children=opList 2062count=1 2063eventq_index=0 2064opList=system.cpu3.fuPool.FUList8.opList 2065 2066[system.cpu3.fuPool.FUList8.opList] 2067type=OpDesc 2068eventq_index=0 2069opClass=IprAccess 2070opLat=3 2071pipelined=false 2072 2073[system.cpu3.icache] 2074type=Cache 2075children=tags 2076addr_ranges=0:18446744073709551615 2077assoc=1 2078clk_domain=system.cpu_clk_domain 2079clusivity=mostly_incl 2080demand_mshr_reserve=1 2081eventq_index=0 2082hit_latency=2 2083is_read_only=true 2084max_miss_count=0 2085mshrs=4 2086prefetch_on_access=false 2087prefetcher=Null 2088response_latency=2 2089sequential_access=false 2090size=32768 2091system=system 2092tags=system.cpu3.icache.tags 2093tgts_per_mshr=20 2094write_buffers=8 2095writeback_clean=true 2096cpu_side=system.cpu3.icache_port 2097mem_side=system.toL2Bus.slave[6] 2098 2099[system.cpu3.icache.tags] 2100type=LRU 2101assoc=1 2102block_size=64 2103clk_domain=system.cpu_clk_domain 2104eventq_index=0 2105hit_latency=2 2106sequential_access=false 2107size=32768 2108 2109[system.cpu3.interrupts] 2110type=SparcInterrupts 2111eventq_index=0 2112 2113[system.cpu3.isa] 2114type=SparcISA 2115eventq_index=0 2116 2117[system.cpu3.itb] 2118type=SparcTLB 2119eventq_index=0 2120size=64 2121 2122[system.cpu3.tracer] 2123type=ExeTracer 2124eventq_index=0 2125 2126[system.cpu_clk_domain] 2127type=SrcClockDomain 2128clock=500 2129domain_id=-1 2130eventq_index=0 2131init_perf_level=0 2132voltage_domain=system.voltage_domain 2133 2134[system.dvfs_handler] 2135type=DVFSHandler 2136domains= 2137enable=false 2138eventq_index=0 2139sys_clk_domain=system.clk_domain 2140transition_latency=100000000 2141 2142[system.l2c] 2143type=Cache 2144children=tags 2145addr_ranges=0:18446744073709551615 2146assoc=8 2147clk_domain=system.cpu_clk_domain 2148clusivity=mostly_incl 2149demand_mshr_reserve=1 2150eventq_index=0 2151hit_latency=20 2152is_read_only=false 2153max_miss_count=0 2154mshrs=20 2155prefetch_on_access=false 2156prefetcher=Null 2157response_latency=20 2158sequential_access=false 2159size=4194304 2160system=system 2161tags=system.l2c.tags 2162tgts_per_mshr=12 2163write_buffers=8 2164writeback_clean=false 2165cpu_side=system.toL2Bus.master[0] 2166mem_side=system.membus.slave[1] 2167 2168[system.l2c.tags] 2169type=LRU 2170assoc=8 2171block_size=64 2172clk_domain=system.cpu_clk_domain 2173eventq_index=0 2174hit_latency=20 2175sequential_access=false 2176size=4194304 2177 2178[system.membus] 2179type=CoherentXBar 2180clk_domain=system.clk_domain 2181eventq_index=0 2182forward_latency=4 2183frontend_latency=3 2184point_of_coherency=true 2185response_latency=2 2186snoop_filter=Null 2187snoop_response_latency=4 2188system=system 2189use_default_range=false 2190width=16 2191master=system.physmem.port 2192slave=system.system_port system.l2c.mem_side 2193 2194[system.physmem] 2195type=DRAMCtrl 2196IDD0=0.075000 2197IDD02=0.000000 2198IDD2N=0.050000 2199IDD2N2=0.000000 2200IDD2P0=0.000000 2201IDD2P02=0.000000 2202IDD2P1=0.000000 2203IDD2P12=0.000000 2204IDD3N=0.057000 2205IDD3N2=0.000000 2206IDD3P0=0.000000 2207IDD3P02=0.000000 2208IDD3P1=0.000000 2209IDD3P12=0.000000 2210IDD4R=0.187000 2211IDD4R2=0.000000 2212IDD4W=0.165000 2213IDD4W2=0.000000 2214IDD5=0.220000 2215IDD52=0.000000 2216IDD6=0.000000 2217IDD62=0.000000 2218VDD=1.500000 2219VDD2=0.000000 2220activation_limit=4 2221addr_mapping=RoRaBaCoCh 2222bank_groups_per_rank=0 2223banks_per_rank=8 2224burst_length=8 2225channels=1 2226clk_domain=system.clk_domain 2227conf_table_reported=true 2228device_bus_width=8 2229device_rowbuffer_size=1024 2230device_size=536870912 2231devices_per_rank=8 2232dll=true 2233eventq_index=0 2234in_addr_map=true 2235max_accesses_per_row=16 2236mem_sched_policy=frfcfs 2237min_writes_per_switch=16 2238null=false 2239page_policy=open_adaptive 2240range=0:134217727 2241ranks_per_channel=2 2242read_buffer_size=32 2243static_backend_latency=10000 2244static_frontend_latency=10000 2245tBURST=5000 2246tCCD_L=0 2247tCK=1250 2248tCL=13750 2249tCS=2500 2250tRAS=35000 2251tRCD=13750 2252tREFI=7800000 2253tRFC=260000 2254tRP=13750 2255tRRD=6000 2256tRRD_L=0 2257tRTP=7500 2258tRTW=2500 2259tWR=15000 2260tWTR=7500 2261tXAW=30000 2262tXP=0 2263tXPDLL=0 2264tXS=0 2265tXSDLL=0 2266write_buffer_size=64 2267write_high_thresh_perc=85 2268write_low_thresh_perc=50 2269port=system.membus.master[0] 2270 2271[system.toL2Bus] 2272type=CoherentXBar 2273children=snoop_filter 2274clk_domain=system.cpu_clk_domain 2275eventq_index=0 2276forward_latency=0 2277frontend_latency=1 2278point_of_coherency=false 2279response_latency=1 2280snoop_filter=system.toL2Bus.snoop_filter 2281snoop_response_latency=1 2282system=system 2283use_default_range=false 2284width=32 2285master=system.l2c.cpu_side 2286slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2287 2288[system.toL2Bus.snoop_filter] 2289type=SnoopFilter 2290eventq_index=0 2291lookup_latency=0 2292max_capacity=8388608 2293system=system 2294 2295[system.voltage_domain] 2296type=VoltageDomain 2297eventq_index=0 2298voltage=1.000000 2299 2300