config.ini revision 11066
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu0] 48type=DerivO3CPU 49children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu0.branchPred 59cachePorts=200 60checker=Null 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dtb=system.cpu0.dtb 76eventq_index=0 77fetchBufferSize=64 78fetchQueueSize=32 79fetchToDecodeDelay=1 80fetchTrapLatency=1 81fetchWidth=8 82forwardComSize=5 83fuPool=system.cpu0.fuPool 84function_trace=false 85function_trace_start=0 86iewToCommitDelay=1 87iewToDecodeDelay=1 88iewToFetchDelay=1 89iewToRenameDelay=1 90interrupts=system.cpu0.interrupts 91isa=system.cpu0.isa 92issueToExecuteDelay=1 93issueWidth=8 94itb=system.cpu0.itb 95max_insts_all_threads=0 96max_insts_any_thread=0 97max_loads_all_threads=0 98max_loads_any_thread=0 99needsTSO=false 100numIQEntries=64 101numPhysCCRegs=0 102numPhysFloatRegs=256 103numPhysIntRegs=256 104numROBEntries=192 105numRobs=1 106numThreads=1 107profile=0 108progress_interval=0 109renameToDecodeDelay=1 110renameToFetchDelay=1 111renameToIEWDelay=2 112renameToROBDelay=1 113renameWidth=8 114simpoint_start_insts= 115smtCommitPolicy=RoundRobin 116smtFetchPolicy=SingleThread 117smtIQPolicy=Partitioned 118smtIQThreshold=100 119smtLSQPolicy=Partitioned 120smtLSQThreshold=100 121smtNumFetchingThreads=1 122smtROBPolicy=Partitioned 123smtROBThreshold=100 124socket_id=0 125squashWidth=8 126store_set_clear_period=250000 127switched_out=false 128system=system 129tracer=system.cpu0.tracer 130trapLatency=13 131wbWidth=8 132workload=system.cpu0.workload 133dcache_port=system.cpu0.dcache.cpu_side 134icache_port=system.cpu0.icache.cpu_side 135 136[system.cpu0.branchPred] 137type=TournamentBP 138BTBEntries=4096 139BTBTagSize=16 140RASSize=16 141choiceCtrBits=2 142choicePredictorSize=8192 143eventq_index=0 144globalCtrBits=2 145globalPredictorSize=8192 146instShiftAmt=2 147localCtrBits=2 148localHistoryTableSize=2048 149localPredictorSize=2048 150numThreads=1 151 152[system.cpu0.dcache] 153type=Cache 154children=tags 155addr_ranges=0:18446744073709551615 156assoc=4 157clk_domain=system.cpu_clk_domain 158demand_mshr_reserve=1 159eventq_index=0 160forward_snoops=true 161hit_latency=2 162is_read_only=false 163max_miss_count=0 164mshrs=4 165prefetch_on_access=false 166prefetcher=Null 167response_latency=2 168sequential_access=false 169size=32768 170system=system 171tags=system.cpu0.dcache.tags 172tgts_per_mshr=20 173write_buffers=8 174cpu_side=system.cpu0.dcache_port 175mem_side=system.toL2Bus.slave[1] 176 177[system.cpu0.dcache.tags] 178type=LRU 179assoc=4 180block_size=64 181clk_domain=system.cpu_clk_domain 182eventq_index=0 183hit_latency=2 184sequential_access=false 185size=32768 186 187[system.cpu0.dtb] 188type=SparcTLB 189eventq_index=0 190size=64 191 192[system.cpu0.fuPool] 193type=FUPool 194children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 195FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 196eventq_index=0 197 198[system.cpu0.fuPool.FUList0] 199type=FUDesc 200children=opList 201count=6 202eventq_index=0 203opList=system.cpu0.fuPool.FUList0.opList 204 205[system.cpu0.fuPool.FUList0.opList] 206type=OpDesc 207eventq_index=0 208opClass=IntAlu 209opLat=1 210pipelined=true 211 212[system.cpu0.fuPool.FUList1] 213type=FUDesc 214children=opList0 opList1 215count=2 216eventq_index=0 217opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 218 219[system.cpu0.fuPool.FUList1.opList0] 220type=OpDesc 221eventq_index=0 222opClass=IntMult 223opLat=3 224pipelined=true 225 226[system.cpu0.fuPool.FUList1.opList1] 227type=OpDesc 228eventq_index=0 229opClass=IntDiv 230opLat=20 231pipelined=false 232 233[system.cpu0.fuPool.FUList2] 234type=FUDesc 235children=opList0 opList1 opList2 236count=4 237eventq_index=0 238opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 239 240[system.cpu0.fuPool.FUList2.opList0] 241type=OpDesc 242eventq_index=0 243opClass=FloatAdd 244opLat=2 245pipelined=true 246 247[system.cpu0.fuPool.FUList2.opList1] 248type=OpDesc 249eventq_index=0 250opClass=FloatCmp 251opLat=2 252pipelined=true 253 254[system.cpu0.fuPool.FUList2.opList2] 255type=OpDesc 256eventq_index=0 257opClass=FloatCvt 258opLat=2 259pipelined=true 260 261[system.cpu0.fuPool.FUList3] 262type=FUDesc 263children=opList0 opList1 opList2 264count=2 265eventq_index=0 266opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 267 268[system.cpu0.fuPool.FUList3.opList0] 269type=OpDesc 270eventq_index=0 271opClass=FloatMult 272opLat=4 273pipelined=true 274 275[system.cpu0.fuPool.FUList3.opList1] 276type=OpDesc 277eventq_index=0 278opClass=FloatDiv 279opLat=12 280pipelined=false 281 282[system.cpu0.fuPool.FUList3.opList2] 283type=OpDesc 284eventq_index=0 285opClass=FloatSqrt 286opLat=24 287pipelined=false 288 289[system.cpu0.fuPool.FUList4] 290type=FUDesc 291children=opList 292count=0 293eventq_index=0 294opList=system.cpu0.fuPool.FUList4.opList 295 296[system.cpu0.fuPool.FUList4.opList] 297type=OpDesc 298eventq_index=0 299opClass=MemRead 300opLat=1 301pipelined=true 302 303[system.cpu0.fuPool.FUList5] 304type=FUDesc 305children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 306count=4 307eventq_index=0 308opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 309 310[system.cpu0.fuPool.FUList5.opList00] 311type=OpDesc 312eventq_index=0 313opClass=SimdAdd 314opLat=1 315pipelined=true 316 317[system.cpu0.fuPool.FUList5.opList01] 318type=OpDesc 319eventq_index=0 320opClass=SimdAddAcc 321opLat=1 322pipelined=true 323 324[system.cpu0.fuPool.FUList5.opList02] 325type=OpDesc 326eventq_index=0 327opClass=SimdAlu 328opLat=1 329pipelined=true 330 331[system.cpu0.fuPool.FUList5.opList03] 332type=OpDesc 333eventq_index=0 334opClass=SimdCmp 335opLat=1 336pipelined=true 337 338[system.cpu0.fuPool.FUList5.opList04] 339type=OpDesc 340eventq_index=0 341opClass=SimdCvt 342opLat=1 343pipelined=true 344 345[system.cpu0.fuPool.FUList5.opList05] 346type=OpDesc 347eventq_index=0 348opClass=SimdMisc 349opLat=1 350pipelined=true 351 352[system.cpu0.fuPool.FUList5.opList06] 353type=OpDesc 354eventq_index=0 355opClass=SimdMult 356opLat=1 357pipelined=true 358 359[system.cpu0.fuPool.FUList5.opList07] 360type=OpDesc 361eventq_index=0 362opClass=SimdMultAcc 363opLat=1 364pipelined=true 365 366[system.cpu0.fuPool.FUList5.opList08] 367type=OpDesc 368eventq_index=0 369opClass=SimdShift 370opLat=1 371pipelined=true 372 373[system.cpu0.fuPool.FUList5.opList09] 374type=OpDesc 375eventq_index=0 376opClass=SimdShiftAcc 377opLat=1 378pipelined=true 379 380[system.cpu0.fuPool.FUList5.opList10] 381type=OpDesc 382eventq_index=0 383opClass=SimdSqrt 384opLat=1 385pipelined=true 386 387[system.cpu0.fuPool.FUList5.opList11] 388type=OpDesc 389eventq_index=0 390opClass=SimdFloatAdd 391opLat=1 392pipelined=true 393 394[system.cpu0.fuPool.FUList5.opList12] 395type=OpDesc 396eventq_index=0 397opClass=SimdFloatAlu 398opLat=1 399pipelined=true 400 401[system.cpu0.fuPool.FUList5.opList13] 402type=OpDesc 403eventq_index=0 404opClass=SimdFloatCmp 405opLat=1 406pipelined=true 407 408[system.cpu0.fuPool.FUList5.opList14] 409type=OpDesc 410eventq_index=0 411opClass=SimdFloatCvt 412opLat=1 413pipelined=true 414 415[system.cpu0.fuPool.FUList5.opList15] 416type=OpDesc 417eventq_index=0 418opClass=SimdFloatDiv 419opLat=1 420pipelined=true 421 422[system.cpu0.fuPool.FUList5.opList16] 423type=OpDesc 424eventq_index=0 425opClass=SimdFloatMisc 426opLat=1 427pipelined=true 428 429[system.cpu0.fuPool.FUList5.opList17] 430type=OpDesc 431eventq_index=0 432opClass=SimdFloatMult 433opLat=1 434pipelined=true 435 436[system.cpu0.fuPool.FUList5.opList18] 437type=OpDesc 438eventq_index=0 439opClass=SimdFloatMultAcc 440opLat=1 441pipelined=true 442 443[system.cpu0.fuPool.FUList5.opList19] 444type=OpDesc 445eventq_index=0 446opClass=SimdFloatSqrt 447opLat=1 448pipelined=true 449 450[system.cpu0.fuPool.FUList6] 451type=FUDesc 452children=opList 453count=0 454eventq_index=0 455opList=system.cpu0.fuPool.FUList6.opList 456 457[system.cpu0.fuPool.FUList6.opList] 458type=OpDesc 459eventq_index=0 460opClass=MemWrite 461opLat=1 462pipelined=true 463 464[system.cpu0.fuPool.FUList7] 465type=FUDesc 466children=opList0 opList1 467count=4 468eventq_index=0 469opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 470 471[system.cpu0.fuPool.FUList7.opList0] 472type=OpDesc 473eventq_index=0 474opClass=MemRead 475opLat=1 476pipelined=true 477 478[system.cpu0.fuPool.FUList7.opList1] 479type=OpDesc 480eventq_index=0 481opClass=MemWrite 482opLat=1 483pipelined=true 484 485[system.cpu0.fuPool.FUList8] 486type=FUDesc 487children=opList 488count=1 489eventq_index=0 490opList=system.cpu0.fuPool.FUList8.opList 491 492[system.cpu0.fuPool.FUList8.opList] 493type=OpDesc 494eventq_index=0 495opClass=IprAccess 496opLat=3 497pipelined=false 498 499[system.cpu0.icache] 500type=Cache 501children=tags 502addr_ranges=0:18446744073709551615 503assoc=1 504clk_domain=system.cpu_clk_domain 505demand_mshr_reserve=1 506eventq_index=0 507forward_snoops=true 508hit_latency=2 509is_read_only=true 510max_miss_count=0 511mshrs=4 512prefetch_on_access=false 513prefetcher=Null 514response_latency=2 515sequential_access=false 516size=32768 517system=system 518tags=system.cpu0.icache.tags 519tgts_per_mshr=20 520write_buffers=8 521cpu_side=system.cpu0.icache_port 522mem_side=system.toL2Bus.slave[0] 523 524[system.cpu0.icache.tags] 525type=LRU 526assoc=1 527block_size=64 528clk_domain=system.cpu_clk_domain 529eventq_index=0 530hit_latency=2 531sequential_access=false 532size=32768 533 534[system.cpu0.interrupts] 535type=SparcInterrupts 536eventq_index=0 537 538[system.cpu0.isa] 539type=SparcISA 540eventq_index=0 541 542[system.cpu0.itb] 543type=SparcTLB 544eventq_index=0 545size=64 546 547[system.cpu0.tracer] 548type=ExeTracer 549eventq_index=0 550 551[system.cpu0.workload] 552type=LiveProcess 553cmd=test_atomic 4 554cwd= 555drivers= 556egid=100 557env= 558errout=cerr 559euid=100 560eventq_index=0 561executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic 562gid=100 563input=cin 564kvmInSE=false 565max_stack_size=67108864 566output=cout 567pid=100 568ppid=99 569simpoint=0 570system=system 571uid=100 572useArchPT=false 573 574[system.cpu1] 575type=DerivO3CPU 576children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 577LFSTSize=1024 578LQEntries=32 579LSQCheckLoads=true 580LSQDepCheckShift=4 581SQEntries=32 582SSITSize=1024 583activity=0 584backComSize=5 585branchPred=system.cpu1.branchPred 586cachePorts=200 587checker=Null 588clk_domain=system.cpu_clk_domain 589commitToDecodeDelay=1 590commitToFetchDelay=1 591commitToIEWDelay=1 592commitToRenameDelay=1 593commitWidth=8 594cpu_id=1 595decodeToFetchDelay=1 596decodeToRenameDelay=1 597decodeWidth=8 598dispatchWidth=8 599do_checkpoint_insts=true 600do_quiesce=true 601do_statistics_insts=true 602dtb=system.cpu1.dtb 603eventq_index=0 604fetchBufferSize=64 605fetchQueueSize=32 606fetchToDecodeDelay=1 607fetchTrapLatency=1 608fetchWidth=8 609forwardComSize=5 610fuPool=system.cpu1.fuPool 611function_trace=false 612function_trace_start=0 613iewToCommitDelay=1 614iewToDecodeDelay=1 615iewToFetchDelay=1 616iewToRenameDelay=1 617interrupts=system.cpu1.interrupts 618isa=system.cpu1.isa 619issueToExecuteDelay=1 620issueWidth=8 621itb=system.cpu1.itb 622max_insts_all_threads=0 623max_insts_any_thread=0 624max_loads_all_threads=0 625max_loads_any_thread=0 626needsTSO=false 627numIQEntries=64 628numPhysCCRegs=0 629numPhysFloatRegs=256 630numPhysIntRegs=256 631numROBEntries=192 632numRobs=1 633numThreads=1 634profile=0 635progress_interval=0 636renameToDecodeDelay=1 637renameToFetchDelay=1 638renameToIEWDelay=2 639renameToROBDelay=1 640renameWidth=8 641simpoint_start_insts= 642smtCommitPolicy=RoundRobin 643smtFetchPolicy=SingleThread 644smtIQPolicy=Partitioned 645smtIQThreshold=100 646smtLSQPolicy=Partitioned 647smtLSQThreshold=100 648smtNumFetchingThreads=1 649smtROBPolicy=Partitioned 650smtROBThreshold=100 651socket_id=0 652squashWidth=8 653store_set_clear_period=250000 654switched_out=false 655system=system 656tracer=system.cpu1.tracer 657trapLatency=13 658wbWidth=8 659workload=system.cpu0.workload 660dcache_port=system.cpu1.dcache.cpu_side 661icache_port=system.cpu1.icache.cpu_side 662 663[system.cpu1.branchPred] 664type=TournamentBP 665BTBEntries=4096 666BTBTagSize=16 667RASSize=16 668choiceCtrBits=2 669choicePredictorSize=8192 670eventq_index=0 671globalCtrBits=2 672globalPredictorSize=8192 673instShiftAmt=2 674localCtrBits=2 675localHistoryTableSize=2048 676localPredictorSize=2048 677numThreads=1 678 679[system.cpu1.dcache] 680type=Cache 681children=tags 682addr_ranges=0:18446744073709551615 683assoc=4 684clk_domain=system.cpu_clk_domain 685demand_mshr_reserve=1 686eventq_index=0 687forward_snoops=true 688hit_latency=2 689is_read_only=false 690max_miss_count=0 691mshrs=4 692prefetch_on_access=false 693prefetcher=Null 694response_latency=2 695sequential_access=false 696size=32768 697system=system 698tags=system.cpu1.dcache.tags 699tgts_per_mshr=20 700write_buffers=8 701cpu_side=system.cpu1.dcache_port 702mem_side=system.toL2Bus.slave[3] 703 704[system.cpu1.dcache.tags] 705type=LRU 706assoc=4 707block_size=64 708clk_domain=system.cpu_clk_domain 709eventq_index=0 710hit_latency=2 711sequential_access=false 712size=32768 713 714[system.cpu1.dtb] 715type=SparcTLB 716eventq_index=0 717size=64 718 719[system.cpu1.fuPool] 720type=FUPool 721children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 722FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 723eventq_index=0 724 725[system.cpu1.fuPool.FUList0] 726type=FUDesc 727children=opList 728count=6 729eventq_index=0 730opList=system.cpu1.fuPool.FUList0.opList 731 732[system.cpu1.fuPool.FUList0.opList] 733type=OpDesc 734eventq_index=0 735opClass=IntAlu 736opLat=1 737pipelined=true 738 739[system.cpu1.fuPool.FUList1] 740type=FUDesc 741children=opList0 opList1 742count=2 743eventq_index=0 744opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 745 746[system.cpu1.fuPool.FUList1.opList0] 747type=OpDesc 748eventq_index=0 749opClass=IntMult 750opLat=3 751pipelined=true 752 753[system.cpu1.fuPool.FUList1.opList1] 754type=OpDesc 755eventq_index=0 756opClass=IntDiv 757opLat=20 758pipelined=false 759 760[system.cpu1.fuPool.FUList2] 761type=FUDesc 762children=opList0 opList1 opList2 763count=4 764eventq_index=0 765opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 766 767[system.cpu1.fuPool.FUList2.opList0] 768type=OpDesc 769eventq_index=0 770opClass=FloatAdd 771opLat=2 772pipelined=true 773 774[system.cpu1.fuPool.FUList2.opList1] 775type=OpDesc 776eventq_index=0 777opClass=FloatCmp 778opLat=2 779pipelined=true 780 781[system.cpu1.fuPool.FUList2.opList2] 782type=OpDesc 783eventq_index=0 784opClass=FloatCvt 785opLat=2 786pipelined=true 787 788[system.cpu1.fuPool.FUList3] 789type=FUDesc 790children=opList0 opList1 opList2 791count=2 792eventq_index=0 793opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 794 795[system.cpu1.fuPool.FUList3.opList0] 796type=OpDesc 797eventq_index=0 798opClass=FloatMult 799opLat=4 800pipelined=true 801 802[system.cpu1.fuPool.FUList3.opList1] 803type=OpDesc 804eventq_index=0 805opClass=FloatDiv 806opLat=12 807pipelined=false 808 809[system.cpu1.fuPool.FUList3.opList2] 810type=OpDesc 811eventq_index=0 812opClass=FloatSqrt 813opLat=24 814pipelined=false 815 816[system.cpu1.fuPool.FUList4] 817type=FUDesc 818children=opList 819count=0 820eventq_index=0 821opList=system.cpu1.fuPool.FUList4.opList 822 823[system.cpu1.fuPool.FUList4.opList] 824type=OpDesc 825eventq_index=0 826opClass=MemRead 827opLat=1 828pipelined=true 829 830[system.cpu1.fuPool.FUList5] 831type=FUDesc 832children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 833count=4 834eventq_index=0 835opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 836 837[system.cpu1.fuPool.FUList5.opList00] 838type=OpDesc 839eventq_index=0 840opClass=SimdAdd 841opLat=1 842pipelined=true 843 844[system.cpu1.fuPool.FUList5.opList01] 845type=OpDesc 846eventq_index=0 847opClass=SimdAddAcc 848opLat=1 849pipelined=true 850 851[system.cpu1.fuPool.FUList5.opList02] 852type=OpDesc 853eventq_index=0 854opClass=SimdAlu 855opLat=1 856pipelined=true 857 858[system.cpu1.fuPool.FUList5.opList03] 859type=OpDesc 860eventq_index=0 861opClass=SimdCmp 862opLat=1 863pipelined=true 864 865[system.cpu1.fuPool.FUList5.opList04] 866type=OpDesc 867eventq_index=0 868opClass=SimdCvt 869opLat=1 870pipelined=true 871 872[system.cpu1.fuPool.FUList5.opList05] 873type=OpDesc 874eventq_index=0 875opClass=SimdMisc 876opLat=1 877pipelined=true 878 879[system.cpu1.fuPool.FUList5.opList06] 880type=OpDesc 881eventq_index=0 882opClass=SimdMult 883opLat=1 884pipelined=true 885 886[system.cpu1.fuPool.FUList5.opList07] 887type=OpDesc 888eventq_index=0 889opClass=SimdMultAcc 890opLat=1 891pipelined=true 892 893[system.cpu1.fuPool.FUList5.opList08] 894type=OpDesc 895eventq_index=0 896opClass=SimdShift 897opLat=1 898pipelined=true 899 900[system.cpu1.fuPool.FUList5.opList09] 901type=OpDesc 902eventq_index=0 903opClass=SimdShiftAcc 904opLat=1 905pipelined=true 906 907[system.cpu1.fuPool.FUList5.opList10] 908type=OpDesc 909eventq_index=0 910opClass=SimdSqrt 911opLat=1 912pipelined=true 913 914[system.cpu1.fuPool.FUList5.opList11] 915type=OpDesc 916eventq_index=0 917opClass=SimdFloatAdd 918opLat=1 919pipelined=true 920 921[system.cpu1.fuPool.FUList5.opList12] 922type=OpDesc 923eventq_index=0 924opClass=SimdFloatAlu 925opLat=1 926pipelined=true 927 928[system.cpu1.fuPool.FUList5.opList13] 929type=OpDesc 930eventq_index=0 931opClass=SimdFloatCmp 932opLat=1 933pipelined=true 934 935[system.cpu1.fuPool.FUList5.opList14] 936type=OpDesc 937eventq_index=0 938opClass=SimdFloatCvt 939opLat=1 940pipelined=true 941 942[system.cpu1.fuPool.FUList5.opList15] 943type=OpDesc 944eventq_index=0 945opClass=SimdFloatDiv 946opLat=1 947pipelined=true 948 949[system.cpu1.fuPool.FUList5.opList16] 950type=OpDesc 951eventq_index=0 952opClass=SimdFloatMisc 953opLat=1 954pipelined=true 955 956[system.cpu1.fuPool.FUList5.opList17] 957type=OpDesc 958eventq_index=0 959opClass=SimdFloatMult 960opLat=1 961pipelined=true 962 963[system.cpu1.fuPool.FUList5.opList18] 964type=OpDesc 965eventq_index=0 966opClass=SimdFloatMultAcc 967opLat=1 968pipelined=true 969 970[system.cpu1.fuPool.FUList5.opList19] 971type=OpDesc 972eventq_index=0 973opClass=SimdFloatSqrt 974opLat=1 975pipelined=true 976 977[system.cpu1.fuPool.FUList6] 978type=FUDesc 979children=opList 980count=0 981eventq_index=0 982opList=system.cpu1.fuPool.FUList6.opList 983 984[system.cpu1.fuPool.FUList6.opList] 985type=OpDesc 986eventq_index=0 987opClass=MemWrite 988opLat=1 989pipelined=true 990 991[system.cpu1.fuPool.FUList7] 992type=FUDesc 993children=opList0 opList1 994count=4 995eventq_index=0 996opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 997 998[system.cpu1.fuPool.FUList7.opList0] 999type=OpDesc 1000eventq_index=0 1001opClass=MemRead 1002opLat=1 1003pipelined=true 1004 1005[system.cpu1.fuPool.FUList7.opList1] 1006type=OpDesc 1007eventq_index=0 1008opClass=MemWrite 1009opLat=1 1010pipelined=true 1011 1012[system.cpu1.fuPool.FUList8] 1013type=FUDesc 1014children=opList 1015count=1 1016eventq_index=0 1017opList=system.cpu1.fuPool.FUList8.opList 1018 1019[system.cpu1.fuPool.FUList8.opList] 1020type=OpDesc 1021eventq_index=0 1022opClass=IprAccess 1023opLat=3 1024pipelined=false 1025 1026[system.cpu1.icache] 1027type=Cache 1028children=tags 1029addr_ranges=0:18446744073709551615 1030assoc=1 1031clk_domain=system.cpu_clk_domain 1032demand_mshr_reserve=1 1033eventq_index=0 1034forward_snoops=true 1035hit_latency=2 1036is_read_only=true 1037max_miss_count=0 1038mshrs=4 1039prefetch_on_access=false 1040prefetcher=Null 1041response_latency=2 1042sequential_access=false 1043size=32768 1044system=system 1045tags=system.cpu1.icache.tags 1046tgts_per_mshr=20 1047write_buffers=8 1048cpu_side=system.cpu1.icache_port 1049mem_side=system.toL2Bus.slave[2] 1050 1051[system.cpu1.icache.tags] 1052type=LRU 1053assoc=1 1054block_size=64 1055clk_domain=system.cpu_clk_domain 1056eventq_index=0 1057hit_latency=2 1058sequential_access=false 1059size=32768 1060 1061[system.cpu1.interrupts] 1062type=SparcInterrupts 1063eventq_index=0 1064 1065[system.cpu1.isa] 1066type=SparcISA 1067eventq_index=0 1068 1069[system.cpu1.itb] 1070type=SparcTLB 1071eventq_index=0 1072size=64 1073 1074[system.cpu1.tracer] 1075type=ExeTracer 1076eventq_index=0 1077 1078[system.cpu2] 1079type=DerivO3CPU 1080children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1081LFSTSize=1024 1082LQEntries=32 1083LSQCheckLoads=true 1084LSQDepCheckShift=4 1085SQEntries=32 1086SSITSize=1024 1087activity=0 1088backComSize=5 1089branchPred=system.cpu2.branchPred 1090cachePorts=200 1091checker=Null 1092clk_domain=system.cpu_clk_domain 1093commitToDecodeDelay=1 1094commitToFetchDelay=1 1095commitToIEWDelay=1 1096commitToRenameDelay=1 1097commitWidth=8 1098cpu_id=2 1099decodeToFetchDelay=1 1100decodeToRenameDelay=1 1101decodeWidth=8 1102dispatchWidth=8 1103do_checkpoint_insts=true 1104do_quiesce=true 1105do_statistics_insts=true 1106dtb=system.cpu2.dtb 1107eventq_index=0 1108fetchBufferSize=64 1109fetchQueueSize=32 1110fetchToDecodeDelay=1 1111fetchTrapLatency=1 1112fetchWidth=8 1113forwardComSize=5 1114fuPool=system.cpu2.fuPool 1115function_trace=false 1116function_trace_start=0 1117iewToCommitDelay=1 1118iewToDecodeDelay=1 1119iewToFetchDelay=1 1120iewToRenameDelay=1 1121interrupts=system.cpu2.interrupts 1122isa=system.cpu2.isa 1123issueToExecuteDelay=1 1124issueWidth=8 1125itb=system.cpu2.itb 1126max_insts_all_threads=0 1127max_insts_any_thread=0 1128max_loads_all_threads=0 1129max_loads_any_thread=0 1130needsTSO=false 1131numIQEntries=64 1132numPhysCCRegs=0 1133numPhysFloatRegs=256 1134numPhysIntRegs=256 1135numROBEntries=192 1136numRobs=1 1137numThreads=1 1138profile=0 1139progress_interval=0 1140renameToDecodeDelay=1 1141renameToFetchDelay=1 1142renameToIEWDelay=2 1143renameToROBDelay=1 1144renameWidth=8 1145simpoint_start_insts= 1146smtCommitPolicy=RoundRobin 1147smtFetchPolicy=SingleThread 1148smtIQPolicy=Partitioned 1149smtIQThreshold=100 1150smtLSQPolicy=Partitioned 1151smtLSQThreshold=100 1152smtNumFetchingThreads=1 1153smtROBPolicy=Partitioned 1154smtROBThreshold=100 1155socket_id=0 1156squashWidth=8 1157store_set_clear_period=250000 1158switched_out=false 1159system=system 1160tracer=system.cpu2.tracer 1161trapLatency=13 1162wbWidth=8 1163workload=system.cpu0.workload 1164dcache_port=system.cpu2.dcache.cpu_side 1165icache_port=system.cpu2.icache.cpu_side 1166 1167[system.cpu2.branchPred] 1168type=TournamentBP 1169BTBEntries=4096 1170BTBTagSize=16 1171RASSize=16 1172choiceCtrBits=2 1173choicePredictorSize=8192 1174eventq_index=0 1175globalCtrBits=2 1176globalPredictorSize=8192 1177instShiftAmt=2 1178localCtrBits=2 1179localHistoryTableSize=2048 1180localPredictorSize=2048 1181numThreads=1 1182 1183[system.cpu2.dcache] 1184type=Cache 1185children=tags 1186addr_ranges=0:18446744073709551615 1187assoc=4 1188clk_domain=system.cpu_clk_domain 1189demand_mshr_reserve=1 1190eventq_index=0 1191forward_snoops=true 1192hit_latency=2 1193is_read_only=false 1194max_miss_count=0 1195mshrs=4 1196prefetch_on_access=false 1197prefetcher=Null 1198response_latency=2 1199sequential_access=false 1200size=32768 1201system=system 1202tags=system.cpu2.dcache.tags 1203tgts_per_mshr=20 1204write_buffers=8 1205cpu_side=system.cpu2.dcache_port 1206mem_side=system.toL2Bus.slave[5] 1207 1208[system.cpu2.dcache.tags] 1209type=LRU 1210assoc=4 1211block_size=64 1212clk_domain=system.cpu_clk_domain 1213eventq_index=0 1214hit_latency=2 1215sequential_access=false 1216size=32768 1217 1218[system.cpu2.dtb] 1219type=SparcTLB 1220eventq_index=0 1221size=64 1222 1223[system.cpu2.fuPool] 1224type=FUPool 1225children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1226FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1227eventq_index=0 1228 1229[system.cpu2.fuPool.FUList0] 1230type=FUDesc 1231children=opList 1232count=6 1233eventq_index=0 1234opList=system.cpu2.fuPool.FUList0.opList 1235 1236[system.cpu2.fuPool.FUList0.opList] 1237type=OpDesc 1238eventq_index=0 1239opClass=IntAlu 1240opLat=1 1241pipelined=true 1242 1243[system.cpu2.fuPool.FUList1] 1244type=FUDesc 1245children=opList0 opList1 1246count=2 1247eventq_index=0 1248opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1249 1250[system.cpu2.fuPool.FUList1.opList0] 1251type=OpDesc 1252eventq_index=0 1253opClass=IntMult 1254opLat=3 1255pipelined=true 1256 1257[system.cpu2.fuPool.FUList1.opList1] 1258type=OpDesc 1259eventq_index=0 1260opClass=IntDiv 1261opLat=20 1262pipelined=false 1263 1264[system.cpu2.fuPool.FUList2] 1265type=FUDesc 1266children=opList0 opList1 opList2 1267count=4 1268eventq_index=0 1269opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1270 1271[system.cpu2.fuPool.FUList2.opList0] 1272type=OpDesc 1273eventq_index=0 1274opClass=FloatAdd 1275opLat=2 1276pipelined=true 1277 1278[system.cpu2.fuPool.FUList2.opList1] 1279type=OpDesc 1280eventq_index=0 1281opClass=FloatCmp 1282opLat=2 1283pipelined=true 1284 1285[system.cpu2.fuPool.FUList2.opList2] 1286type=OpDesc 1287eventq_index=0 1288opClass=FloatCvt 1289opLat=2 1290pipelined=true 1291 1292[system.cpu2.fuPool.FUList3] 1293type=FUDesc 1294children=opList0 opList1 opList2 1295count=2 1296eventq_index=0 1297opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1298 1299[system.cpu2.fuPool.FUList3.opList0] 1300type=OpDesc 1301eventq_index=0 1302opClass=FloatMult 1303opLat=4 1304pipelined=true 1305 1306[system.cpu2.fuPool.FUList3.opList1] 1307type=OpDesc 1308eventq_index=0 1309opClass=FloatDiv 1310opLat=12 1311pipelined=false 1312 1313[system.cpu2.fuPool.FUList3.opList2] 1314type=OpDesc 1315eventq_index=0 1316opClass=FloatSqrt 1317opLat=24 1318pipelined=false 1319 1320[system.cpu2.fuPool.FUList4] 1321type=FUDesc 1322children=opList 1323count=0 1324eventq_index=0 1325opList=system.cpu2.fuPool.FUList4.opList 1326 1327[system.cpu2.fuPool.FUList4.opList] 1328type=OpDesc 1329eventq_index=0 1330opClass=MemRead 1331opLat=1 1332pipelined=true 1333 1334[system.cpu2.fuPool.FUList5] 1335type=FUDesc 1336children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1337count=4 1338eventq_index=0 1339opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1340 1341[system.cpu2.fuPool.FUList5.opList00] 1342type=OpDesc 1343eventq_index=0 1344opClass=SimdAdd 1345opLat=1 1346pipelined=true 1347 1348[system.cpu2.fuPool.FUList5.opList01] 1349type=OpDesc 1350eventq_index=0 1351opClass=SimdAddAcc 1352opLat=1 1353pipelined=true 1354 1355[system.cpu2.fuPool.FUList5.opList02] 1356type=OpDesc 1357eventq_index=0 1358opClass=SimdAlu 1359opLat=1 1360pipelined=true 1361 1362[system.cpu2.fuPool.FUList5.opList03] 1363type=OpDesc 1364eventq_index=0 1365opClass=SimdCmp 1366opLat=1 1367pipelined=true 1368 1369[system.cpu2.fuPool.FUList5.opList04] 1370type=OpDesc 1371eventq_index=0 1372opClass=SimdCvt 1373opLat=1 1374pipelined=true 1375 1376[system.cpu2.fuPool.FUList5.opList05] 1377type=OpDesc 1378eventq_index=0 1379opClass=SimdMisc 1380opLat=1 1381pipelined=true 1382 1383[system.cpu2.fuPool.FUList5.opList06] 1384type=OpDesc 1385eventq_index=0 1386opClass=SimdMult 1387opLat=1 1388pipelined=true 1389 1390[system.cpu2.fuPool.FUList5.opList07] 1391type=OpDesc 1392eventq_index=0 1393opClass=SimdMultAcc 1394opLat=1 1395pipelined=true 1396 1397[system.cpu2.fuPool.FUList5.opList08] 1398type=OpDesc 1399eventq_index=0 1400opClass=SimdShift 1401opLat=1 1402pipelined=true 1403 1404[system.cpu2.fuPool.FUList5.opList09] 1405type=OpDesc 1406eventq_index=0 1407opClass=SimdShiftAcc 1408opLat=1 1409pipelined=true 1410 1411[system.cpu2.fuPool.FUList5.opList10] 1412type=OpDesc 1413eventq_index=0 1414opClass=SimdSqrt 1415opLat=1 1416pipelined=true 1417 1418[system.cpu2.fuPool.FUList5.opList11] 1419type=OpDesc 1420eventq_index=0 1421opClass=SimdFloatAdd 1422opLat=1 1423pipelined=true 1424 1425[system.cpu2.fuPool.FUList5.opList12] 1426type=OpDesc 1427eventq_index=0 1428opClass=SimdFloatAlu 1429opLat=1 1430pipelined=true 1431 1432[system.cpu2.fuPool.FUList5.opList13] 1433type=OpDesc 1434eventq_index=0 1435opClass=SimdFloatCmp 1436opLat=1 1437pipelined=true 1438 1439[system.cpu2.fuPool.FUList5.opList14] 1440type=OpDesc 1441eventq_index=0 1442opClass=SimdFloatCvt 1443opLat=1 1444pipelined=true 1445 1446[system.cpu2.fuPool.FUList5.opList15] 1447type=OpDesc 1448eventq_index=0 1449opClass=SimdFloatDiv 1450opLat=1 1451pipelined=true 1452 1453[system.cpu2.fuPool.FUList5.opList16] 1454type=OpDesc 1455eventq_index=0 1456opClass=SimdFloatMisc 1457opLat=1 1458pipelined=true 1459 1460[system.cpu2.fuPool.FUList5.opList17] 1461type=OpDesc 1462eventq_index=0 1463opClass=SimdFloatMult 1464opLat=1 1465pipelined=true 1466 1467[system.cpu2.fuPool.FUList5.opList18] 1468type=OpDesc 1469eventq_index=0 1470opClass=SimdFloatMultAcc 1471opLat=1 1472pipelined=true 1473 1474[system.cpu2.fuPool.FUList5.opList19] 1475type=OpDesc 1476eventq_index=0 1477opClass=SimdFloatSqrt 1478opLat=1 1479pipelined=true 1480 1481[system.cpu2.fuPool.FUList6] 1482type=FUDesc 1483children=opList 1484count=0 1485eventq_index=0 1486opList=system.cpu2.fuPool.FUList6.opList 1487 1488[system.cpu2.fuPool.FUList6.opList] 1489type=OpDesc 1490eventq_index=0 1491opClass=MemWrite 1492opLat=1 1493pipelined=true 1494 1495[system.cpu2.fuPool.FUList7] 1496type=FUDesc 1497children=opList0 opList1 1498count=4 1499eventq_index=0 1500opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1501 1502[system.cpu2.fuPool.FUList7.opList0] 1503type=OpDesc 1504eventq_index=0 1505opClass=MemRead 1506opLat=1 1507pipelined=true 1508 1509[system.cpu2.fuPool.FUList7.opList1] 1510type=OpDesc 1511eventq_index=0 1512opClass=MemWrite 1513opLat=1 1514pipelined=true 1515 1516[system.cpu2.fuPool.FUList8] 1517type=FUDesc 1518children=opList 1519count=1 1520eventq_index=0 1521opList=system.cpu2.fuPool.FUList8.opList 1522 1523[system.cpu2.fuPool.FUList8.opList] 1524type=OpDesc 1525eventq_index=0 1526opClass=IprAccess 1527opLat=3 1528pipelined=false 1529 1530[system.cpu2.icache] 1531type=Cache 1532children=tags 1533addr_ranges=0:18446744073709551615 1534assoc=1 1535clk_domain=system.cpu_clk_domain 1536demand_mshr_reserve=1 1537eventq_index=0 1538forward_snoops=true 1539hit_latency=2 1540is_read_only=true 1541max_miss_count=0 1542mshrs=4 1543prefetch_on_access=false 1544prefetcher=Null 1545response_latency=2 1546sequential_access=false 1547size=32768 1548system=system 1549tags=system.cpu2.icache.tags 1550tgts_per_mshr=20 1551write_buffers=8 1552cpu_side=system.cpu2.icache_port 1553mem_side=system.toL2Bus.slave[4] 1554 1555[system.cpu2.icache.tags] 1556type=LRU 1557assoc=1 1558block_size=64 1559clk_domain=system.cpu_clk_domain 1560eventq_index=0 1561hit_latency=2 1562sequential_access=false 1563size=32768 1564 1565[system.cpu2.interrupts] 1566type=SparcInterrupts 1567eventq_index=0 1568 1569[system.cpu2.isa] 1570type=SparcISA 1571eventq_index=0 1572 1573[system.cpu2.itb] 1574type=SparcTLB 1575eventq_index=0 1576size=64 1577 1578[system.cpu2.tracer] 1579type=ExeTracer 1580eventq_index=0 1581 1582[system.cpu3] 1583type=DerivO3CPU 1584children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1585LFSTSize=1024 1586LQEntries=32 1587LSQCheckLoads=true 1588LSQDepCheckShift=4 1589SQEntries=32 1590SSITSize=1024 1591activity=0 1592backComSize=5 1593branchPred=system.cpu3.branchPred 1594cachePorts=200 1595checker=Null 1596clk_domain=system.cpu_clk_domain 1597commitToDecodeDelay=1 1598commitToFetchDelay=1 1599commitToIEWDelay=1 1600commitToRenameDelay=1 1601commitWidth=8 1602cpu_id=3 1603decodeToFetchDelay=1 1604decodeToRenameDelay=1 1605decodeWidth=8 1606dispatchWidth=8 1607do_checkpoint_insts=true 1608do_quiesce=true 1609do_statistics_insts=true 1610dtb=system.cpu3.dtb 1611eventq_index=0 1612fetchBufferSize=64 1613fetchQueueSize=32 1614fetchToDecodeDelay=1 1615fetchTrapLatency=1 1616fetchWidth=8 1617forwardComSize=5 1618fuPool=system.cpu3.fuPool 1619function_trace=false 1620function_trace_start=0 1621iewToCommitDelay=1 1622iewToDecodeDelay=1 1623iewToFetchDelay=1 1624iewToRenameDelay=1 1625interrupts=system.cpu3.interrupts 1626isa=system.cpu3.isa 1627issueToExecuteDelay=1 1628issueWidth=8 1629itb=system.cpu3.itb 1630max_insts_all_threads=0 1631max_insts_any_thread=0 1632max_loads_all_threads=0 1633max_loads_any_thread=0 1634needsTSO=false 1635numIQEntries=64 1636numPhysCCRegs=0 1637numPhysFloatRegs=256 1638numPhysIntRegs=256 1639numROBEntries=192 1640numRobs=1 1641numThreads=1 1642profile=0 1643progress_interval=0 1644renameToDecodeDelay=1 1645renameToFetchDelay=1 1646renameToIEWDelay=2 1647renameToROBDelay=1 1648renameWidth=8 1649simpoint_start_insts= 1650smtCommitPolicy=RoundRobin 1651smtFetchPolicy=SingleThread 1652smtIQPolicy=Partitioned 1653smtIQThreshold=100 1654smtLSQPolicy=Partitioned 1655smtLSQThreshold=100 1656smtNumFetchingThreads=1 1657smtROBPolicy=Partitioned 1658smtROBThreshold=100 1659socket_id=0 1660squashWidth=8 1661store_set_clear_period=250000 1662switched_out=false 1663system=system 1664tracer=system.cpu3.tracer 1665trapLatency=13 1666wbWidth=8 1667workload=system.cpu0.workload 1668dcache_port=system.cpu3.dcache.cpu_side 1669icache_port=system.cpu3.icache.cpu_side 1670 1671[system.cpu3.branchPred] 1672type=TournamentBP 1673BTBEntries=4096 1674BTBTagSize=16 1675RASSize=16 1676choiceCtrBits=2 1677choicePredictorSize=8192 1678eventq_index=0 1679globalCtrBits=2 1680globalPredictorSize=8192 1681instShiftAmt=2 1682localCtrBits=2 1683localHistoryTableSize=2048 1684localPredictorSize=2048 1685numThreads=1 1686 1687[system.cpu3.dcache] 1688type=Cache 1689children=tags 1690addr_ranges=0:18446744073709551615 1691assoc=4 1692clk_domain=system.cpu_clk_domain 1693demand_mshr_reserve=1 1694eventq_index=0 1695forward_snoops=true 1696hit_latency=2 1697is_read_only=false 1698max_miss_count=0 1699mshrs=4 1700prefetch_on_access=false 1701prefetcher=Null 1702response_latency=2 1703sequential_access=false 1704size=32768 1705system=system 1706tags=system.cpu3.dcache.tags 1707tgts_per_mshr=20 1708write_buffers=8 1709cpu_side=system.cpu3.dcache_port 1710mem_side=system.toL2Bus.slave[7] 1711 1712[system.cpu3.dcache.tags] 1713type=LRU 1714assoc=4 1715block_size=64 1716clk_domain=system.cpu_clk_domain 1717eventq_index=0 1718hit_latency=2 1719sequential_access=false 1720size=32768 1721 1722[system.cpu3.dtb] 1723type=SparcTLB 1724eventq_index=0 1725size=64 1726 1727[system.cpu3.fuPool] 1728type=FUPool 1729children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1730FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1731eventq_index=0 1732 1733[system.cpu3.fuPool.FUList0] 1734type=FUDesc 1735children=opList 1736count=6 1737eventq_index=0 1738opList=system.cpu3.fuPool.FUList0.opList 1739 1740[system.cpu3.fuPool.FUList0.opList] 1741type=OpDesc 1742eventq_index=0 1743opClass=IntAlu 1744opLat=1 1745pipelined=true 1746 1747[system.cpu3.fuPool.FUList1] 1748type=FUDesc 1749children=opList0 opList1 1750count=2 1751eventq_index=0 1752opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1753 1754[system.cpu3.fuPool.FUList1.opList0] 1755type=OpDesc 1756eventq_index=0 1757opClass=IntMult 1758opLat=3 1759pipelined=true 1760 1761[system.cpu3.fuPool.FUList1.opList1] 1762type=OpDesc 1763eventq_index=0 1764opClass=IntDiv 1765opLat=20 1766pipelined=false 1767 1768[system.cpu3.fuPool.FUList2] 1769type=FUDesc 1770children=opList0 opList1 opList2 1771count=4 1772eventq_index=0 1773opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1774 1775[system.cpu3.fuPool.FUList2.opList0] 1776type=OpDesc 1777eventq_index=0 1778opClass=FloatAdd 1779opLat=2 1780pipelined=true 1781 1782[system.cpu3.fuPool.FUList2.opList1] 1783type=OpDesc 1784eventq_index=0 1785opClass=FloatCmp 1786opLat=2 1787pipelined=true 1788 1789[system.cpu3.fuPool.FUList2.opList2] 1790type=OpDesc 1791eventq_index=0 1792opClass=FloatCvt 1793opLat=2 1794pipelined=true 1795 1796[system.cpu3.fuPool.FUList3] 1797type=FUDesc 1798children=opList0 opList1 opList2 1799count=2 1800eventq_index=0 1801opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1802 1803[system.cpu3.fuPool.FUList3.opList0] 1804type=OpDesc 1805eventq_index=0 1806opClass=FloatMult 1807opLat=4 1808pipelined=true 1809 1810[system.cpu3.fuPool.FUList3.opList1] 1811type=OpDesc 1812eventq_index=0 1813opClass=FloatDiv 1814opLat=12 1815pipelined=false 1816 1817[system.cpu3.fuPool.FUList3.opList2] 1818type=OpDesc 1819eventq_index=0 1820opClass=FloatSqrt 1821opLat=24 1822pipelined=false 1823 1824[system.cpu3.fuPool.FUList4] 1825type=FUDesc 1826children=opList 1827count=0 1828eventq_index=0 1829opList=system.cpu3.fuPool.FUList4.opList 1830 1831[system.cpu3.fuPool.FUList4.opList] 1832type=OpDesc 1833eventq_index=0 1834opClass=MemRead 1835opLat=1 1836pipelined=true 1837 1838[system.cpu3.fuPool.FUList5] 1839type=FUDesc 1840children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1841count=4 1842eventq_index=0 1843opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1844 1845[system.cpu3.fuPool.FUList5.opList00] 1846type=OpDesc 1847eventq_index=0 1848opClass=SimdAdd 1849opLat=1 1850pipelined=true 1851 1852[system.cpu3.fuPool.FUList5.opList01] 1853type=OpDesc 1854eventq_index=0 1855opClass=SimdAddAcc 1856opLat=1 1857pipelined=true 1858 1859[system.cpu3.fuPool.FUList5.opList02] 1860type=OpDesc 1861eventq_index=0 1862opClass=SimdAlu 1863opLat=1 1864pipelined=true 1865 1866[system.cpu3.fuPool.FUList5.opList03] 1867type=OpDesc 1868eventq_index=0 1869opClass=SimdCmp 1870opLat=1 1871pipelined=true 1872 1873[system.cpu3.fuPool.FUList5.opList04] 1874type=OpDesc 1875eventq_index=0 1876opClass=SimdCvt 1877opLat=1 1878pipelined=true 1879 1880[system.cpu3.fuPool.FUList5.opList05] 1881type=OpDesc 1882eventq_index=0 1883opClass=SimdMisc 1884opLat=1 1885pipelined=true 1886 1887[system.cpu3.fuPool.FUList5.opList06] 1888type=OpDesc 1889eventq_index=0 1890opClass=SimdMult 1891opLat=1 1892pipelined=true 1893 1894[system.cpu3.fuPool.FUList5.opList07] 1895type=OpDesc 1896eventq_index=0 1897opClass=SimdMultAcc 1898opLat=1 1899pipelined=true 1900 1901[system.cpu3.fuPool.FUList5.opList08] 1902type=OpDesc 1903eventq_index=0 1904opClass=SimdShift 1905opLat=1 1906pipelined=true 1907 1908[system.cpu3.fuPool.FUList5.opList09] 1909type=OpDesc 1910eventq_index=0 1911opClass=SimdShiftAcc 1912opLat=1 1913pipelined=true 1914 1915[system.cpu3.fuPool.FUList5.opList10] 1916type=OpDesc 1917eventq_index=0 1918opClass=SimdSqrt 1919opLat=1 1920pipelined=true 1921 1922[system.cpu3.fuPool.FUList5.opList11] 1923type=OpDesc 1924eventq_index=0 1925opClass=SimdFloatAdd 1926opLat=1 1927pipelined=true 1928 1929[system.cpu3.fuPool.FUList5.opList12] 1930type=OpDesc 1931eventq_index=0 1932opClass=SimdFloatAlu 1933opLat=1 1934pipelined=true 1935 1936[system.cpu3.fuPool.FUList5.opList13] 1937type=OpDesc 1938eventq_index=0 1939opClass=SimdFloatCmp 1940opLat=1 1941pipelined=true 1942 1943[system.cpu3.fuPool.FUList5.opList14] 1944type=OpDesc 1945eventq_index=0 1946opClass=SimdFloatCvt 1947opLat=1 1948pipelined=true 1949 1950[system.cpu3.fuPool.FUList5.opList15] 1951type=OpDesc 1952eventq_index=0 1953opClass=SimdFloatDiv 1954opLat=1 1955pipelined=true 1956 1957[system.cpu3.fuPool.FUList5.opList16] 1958type=OpDesc 1959eventq_index=0 1960opClass=SimdFloatMisc 1961opLat=1 1962pipelined=true 1963 1964[system.cpu3.fuPool.FUList5.opList17] 1965type=OpDesc 1966eventq_index=0 1967opClass=SimdFloatMult 1968opLat=1 1969pipelined=true 1970 1971[system.cpu3.fuPool.FUList5.opList18] 1972type=OpDesc 1973eventq_index=0 1974opClass=SimdFloatMultAcc 1975opLat=1 1976pipelined=true 1977 1978[system.cpu3.fuPool.FUList5.opList19] 1979type=OpDesc 1980eventq_index=0 1981opClass=SimdFloatSqrt 1982opLat=1 1983pipelined=true 1984 1985[system.cpu3.fuPool.FUList6] 1986type=FUDesc 1987children=opList 1988count=0 1989eventq_index=0 1990opList=system.cpu3.fuPool.FUList6.opList 1991 1992[system.cpu3.fuPool.FUList6.opList] 1993type=OpDesc 1994eventq_index=0 1995opClass=MemWrite 1996opLat=1 1997pipelined=true 1998 1999[system.cpu3.fuPool.FUList7] 2000type=FUDesc 2001children=opList0 opList1 2002count=4 2003eventq_index=0 2004opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 2005 2006[system.cpu3.fuPool.FUList7.opList0] 2007type=OpDesc 2008eventq_index=0 2009opClass=MemRead 2010opLat=1 2011pipelined=true 2012 2013[system.cpu3.fuPool.FUList7.opList1] 2014type=OpDesc 2015eventq_index=0 2016opClass=MemWrite 2017opLat=1 2018pipelined=true 2019 2020[system.cpu3.fuPool.FUList8] 2021type=FUDesc 2022children=opList 2023count=1 2024eventq_index=0 2025opList=system.cpu3.fuPool.FUList8.opList 2026 2027[system.cpu3.fuPool.FUList8.opList] 2028type=OpDesc 2029eventq_index=0 2030opClass=IprAccess 2031opLat=3 2032pipelined=false 2033 2034[system.cpu3.icache] 2035type=Cache 2036children=tags 2037addr_ranges=0:18446744073709551615 2038assoc=1 2039clk_domain=system.cpu_clk_domain 2040demand_mshr_reserve=1 2041eventq_index=0 2042forward_snoops=true 2043hit_latency=2 2044is_read_only=true 2045max_miss_count=0 2046mshrs=4 2047prefetch_on_access=false 2048prefetcher=Null 2049response_latency=2 2050sequential_access=false 2051size=32768 2052system=system 2053tags=system.cpu3.icache.tags 2054tgts_per_mshr=20 2055write_buffers=8 2056cpu_side=system.cpu3.icache_port 2057mem_side=system.toL2Bus.slave[6] 2058 2059[system.cpu3.icache.tags] 2060type=LRU 2061assoc=1 2062block_size=64 2063clk_domain=system.cpu_clk_domain 2064eventq_index=0 2065hit_latency=2 2066sequential_access=false 2067size=32768 2068 2069[system.cpu3.interrupts] 2070type=SparcInterrupts 2071eventq_index=0 2072 2073[system.cpu3.isa] 2074type=SparcISA 2075eventq_index=0 2076 2077[system.cpu3.itb] 2078type=SparcTLB 2079eventq_index=0 2080size=64 2081 2082[system.cpu3.tracer] 2083type=ExeTracer 2084eventq_index=0 2085 2086[system.cpu_clk_domain] 2087type=SrcClockDomain 2088clock=500 2089domain_id=-1 2090eventq_index=0 2091init_perf_level=0 2092voltage_domain=system.voltage_domain 2093 2094[system.dvfs_handler] 2095type=DVFSHandler 2096domains= 2097enable=false 2098eventq_index=0 2099sys_clk_domain=system.clk_domain 2100transition_latency=100000000 2101 2102[system.l2c] 2103type=Cache 2104children=tags 2105addr_ranges=0:18446744073709551615 2106assoc=8 2107clk_domain=system.cpu_clk_domain 2108demand_mshr_reserve=1 2109eventq_index=0 2110forward_snoops=true 2111hit_latency=20 2112is_read_only=false 2113max_miss_count=0 2114mshrs=20 2115prefetch_on_access=false 2116prefetcher=Null 2117response_latency=20 2118sequential_access=false 2119size=4194304 2120system=system 2121tags=system.l2c.tags 2122tgts_per_mshr=12 2123write_buffers=8 2124cpu_side=system.toL2Bus.master[0] 2125mem_side=system.membus.slave[1] 2126 2127[system.l2c.tags] 2128type=LRU 2129assoc=8 2130block_size=64 2131clk_domain=system.cpu_clk_domain 2132eventq_index=0 2133hit_latency=20 2134sequential_access=false 2135size=4194304 2136 2137[system.membus] 2138type=CoherentXBar 2139clk_domain=system.clk_domain 2140eventq_index=0 2141forward_latency=4 2142frontend_latency=3 2143response_latency=2 2144snoop_filter=Null 2145snoop_response_latency=4 2146system=system 2147use_default_range=false 2148width=16 2149master=system.physmem.port 2150slave=system.system_port system.l2c.mem_side 2151 2152[system.physmem] 2153type=DRAMCtrl 2154IDD0=0.075000 2155IDD02=0.000000 2156IDD2N=0.050000 2157IDD2N2=0.000000 2158IDD2P0=0.000000 2159IDD2P02=0.000000 2160IDD2P1=0.000000 2161IDD2P12=0.000000 2162IDD3N=0.057000 2163IDD3N2=0.000000 2164IDD3P0=0.000000 2165IDD3P02=0.000000 2166IDD3P1=0.000000 2167IDD3P12=0.000000 2168IDD4R=0.187000 2169IDD4R2=0.000000 2170IDD4W=0.165000 2171IDD4W2=0.000000 2172IDD5=0.220000 2173IDD52=0.000000 2174IDD6=0.000000 2175IDD62=0.000000 2176VDD=1.500000 2177VDD2=0.000000 2178activation_limit=4 2179addr_mapping=RoRaBaCoCh 2180bank_groups_per_rank=0 2181banks_per_rank=8 2182burst_length=8 2183channels=1 2184clk_domain=system.clk_domain 2185conf_table_reported=true 2186device_bus_width=8 2187device_rowbuffer_size=1024 2188device_size=536870912 2189devices_per_rank=8 2190dll=true 2191eventq_index=0 2192in_addr_map=true 2193max_accesses_per_row=16 2194mem_sched_policy=frfcfs 2195min_writes_per_switch=16 2196null=false 2197page_policy=open_adaptive 2198range=0:134217727 2199ranks_per_channel=2 2200read_buffer_size=32 2201static_backend_latency=10000 2202static_frontend_latency=10000 2203tBURST=5000 2204tCCD_L=0 2205tCK=1250 2206tCL=13750 2207tCS=2500 2208tRAS=35000 2209tRCD=13750 2210tREFI=7800000 2211tRFC=260000 2212tRP=13750 2213tRRD=6000 2214tRRD_L=0 2215tRTP=7500 2216tRTW=2500 2217tWR=15000 2218tWTR=7500 2219tXAW=30000 2220tXP=0 2221tXPDLL=0 2222tXS=0 2223tXSDLL=0 2224write_buffer_size=64 2225write_high_thresh_perc=85 2226write_low_thresh_perc=50 2227port=system.membus.master[0] 2228 2229[system.toL2Bus] 2230type=CoherentXBar 2231clk_domain=system.cpu_clk_domain 2232eventq_index=0 2233forward_latency=0 2234frontend_latency=1 2235response_latency=1 2236snoop_filter=Null 2237snoop_response_latency=1 2238system=system 2239use_default_range=false 2240width=32 2241master=system.l2c.cpu_side 2242slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2243 2244[system.voltage_domain] 2245type=VoltageDomain 2246eventq_index=0 2247voltage=1.000000 2248 2249