config.ini revision 10798
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu0] 48type=DerivO3CPU 49children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu0.branchPred 59cachePorts=200 60checker=Null 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dtb=system.cpu0.dtb 76eventq_index=0 77fetchBufferSize=64 78fetchQueueSize=32 79fetchToDecodeDelay=1 80fetchTrapLatency=1 81fetchWidth=8 82forwardComSize=5 83fuPool=system.cpu0.fuPool 84function_trace=false 85function_trace_start=0 86iewToCommitDelay=1 87iewToDecodeDelay=1 88iewToFetchDelay=1 89iewToRenameDelay=1 90interrupts=system.cpu0.interrupts 91isa=system.cpu0.isa 92issueToExecuteDelay=1 93issueWidth=8 94itb=system.cpu0.itb 95max_insts_all_threads=0 96max_insts_any_thread=0 97max_loads_all_threads=0 98max_loads_any_thread=0 99needsTSO=false 100numIQEntries=64 101numPhysCCRegs=0 102numPhysFloatRegs=256 103numPhysIntRegs=256 104numROBEntries=192 105numRobs=1 106numThreads=1 107profile=0 108progress_interval=0 109renameToDecodeDelay=1 110renameToFetchDelay=1 111renameToIEWDelay=2 112renameToROBDelay=1 113renameWidth=8 114simpoint_start_insts= 115smtCommitPolicy=RoundRobin 116smtFetchPolicy=SingleThread 117smtIQPolicy=Partitioned 118smtIQThreshold=100 119smtLSQPolicy=Partitioned 120smtLSQThreshold=100 121smtNumFetchingThreads=1 122smtROBPolicy=Partitioned 123smtROBThreshold=100 124socket_id=0 125squashWidth=8 126store_set_clear_period=250000 127switched_out=false 128system=system 129tracer=system.cpu0.tracer 130trapLatency=13 131wbWidth=8 132workload=system.cpu0.workload 133dcache_port=system.cpu0.dcache.cpu_side 134icache_port=system.cpu0.icache.cpu_side 135 136[system.cpu0.branchPred] 137type=TournamentBP 138BTBEntries=4096 139BTBTagSize=16 140RASSize=16 141choiceCtrBits=2 142choicePredictorSize=8192 143eventq_index=0 144globalCtrBits=2 145globalPredictorSize=8192 146instShiftAmt=2 147localCtrBits=2 148localHistoryTableSize=2048 149localPredictorSize=2048 150numThreads=1 151 152[system.cpu0.dcache] 153type=BaseCache 154children=tags 155addr_ranges=0:18446744073709551615 156assoc=4 157clk_domain=system.cpu_clk_domain 158demand_mshr_reserve=1 159eventq_index=0 160forward_snoops=true 161hit_latency=2 162is_top_level=true 163max_miss_count=0 164mshrs=4 165prefetch_on_access=false 166prefetcher=Null 167response_latency=2 168sequential_access=false 169size=32768 170system=system 171tags=system.cpu0.dcache.tags 172tgts_per_mshr=20 173two_queue=false 174write_buffers=8 175cpu_side=system.cpu0.dcache_port 176mem_side=system.toL2Bus.slave[1] 177 178[system.cpu0.dcache.tags] 179type=LRU 180assoc=4 181block_size=64 182clk_domain=system.cpu_clk_domain 183eventq_index=0 184hit_latency=2 185sequential_access=false 186size=32768 187 188[system.cpu0.dtb] 189type=SparcTLB 190eventq_index=0 191size=64 192 193[system.cpu0.fuPool] 194type=FUPool 195children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 196FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 197eventq_index=0 198 199[system.cpu0.fuPool.FUList0] 200type=FUDesc 201children=opList 202count=6 203eventq_index=0 204opList=system.cpu0.fuPool.FUList0.opList 205 206[system.cpu0.fuPool.FUList0.opList] 207type=OpDesc 208eventq_index=0 209issueLat=1 210opClass=IntAlu 211opLat=1 212 213[system.cpu0.fuPool.FUList1] 214type=FUDesc 215children=opList0 opList1 216count=2 217eventq_index=0 218opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 219 220[system.cpu0.fuPool.FUList1.opList0] 221type=OpDesc 222eventq_index=0 223issueLat=1 224opClass=IntMult 225opLat=3 226 227[system.cpu0.fuPool.FUList1.opList1] 228type=OpDesc 229eventq_index=0 230issueLat=19 231opClass=IntDiv 232opLat=20 233 234[system.cpu0.fuPool.FUList2] 235type=FUDesc 236children=opList0 opList1 opList2 237count=4 238eventq_index=0 239opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 240 241[system.cpu0.fuPool.FUList2.opList0] 242type=OpDesc 243eventq_index=0 244issueLat=1 245opClass=FloatAdd 246opLat=2 247 248[system.cpu0.fuPool.FUList2.opList1] 249type=OpDesc 250eventq_index=0 251issueLat=1 252opClass=FloatCmp 253opLat=2 254 255[system.cpu0.fuPool.FUList2.opList2] 256type=OpDesc 257eventq_index=0 258issueLat=1 259opClass=FloatCvt 260opLat=2 261 262[system.cpu0.fuPool.FUList3] 263type=FUDesc 264children=opList0 opList1 opList2 265count=2 266eventq_index=0 267opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 268 269[system.cpu0.fuPool.FUList3.opList0] 270type=OpDesc 271eventq_index=0 272issueLat=1 273opClass=FloatMult 274opLat=4 275 276[system.cpu0.fuPool.FUList3.opList1] 277type=OpDesc 278eventq_index=0 279issueLat=12 280opClass=FloatDiv 281opLat=12 282 283[system.cpu0.fuPool.FUList3.opList2] 284type=OpDesc 285eventq_index=0 286issueLat=24 287opClass=FloatSqrt 288opLat=24 289 290[system.cpu0.fuPool.FUList4] 291type=FUDesc 292children=opList 293count=0 294eventq_index=0 295opList=system.cpu0.fuPool.FUList4.opList 296 297[system.cpu0.fuPool.FUList4.opList] 298type=OpDesc 299eventq_index=0 300issueLat=1 301opClass=MemRead 302opLat=1 303 304[system.cpu0.fuPool.FUList5] 305type=FUDesc 306children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 307count=4 308eventq_index=0 309opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 310 311[system.cpu0.fuPool.FUList5.opList00] 312type=OpDesc 313eventq_index=0 314issueLat=1 315opClass=SimdAdd 316opLat=1 317 318[system.cpu0.fuPool.FUList5.opList01] 319type=OpDesc 320eventq_index=0 321issueLat=1 322opClass=SimdAddAcc 323opLat=1 324 325[system.cpu0.fuPool.FUList5.opList02] 326type=OpDesc 327eventq_index=0 328issueLat=1 329opClass=SimdAlu 330opLat=1 331 332[system.cpu0.fuPool.FUList5.opList03] 333type=OpDesc 334eventq_index=0 335issueLat=1 336opClass=SimdCmp 337opLat=1 338 339[system.cpu0.fuPool.FUList5.opList04] 340type=OpDesc 341eventq_index=0 342issueLat=1 343opClass=SimdCvt 344opLat=1 345 346[system.cpu0.fuPool.FUList5.opList05] 347type=OpDesc 348eventq_index=0 349issueLat=1 350opClass=SimdMisc 351opLat=1 352 353[system.cpu0.fuPool.FUList5.opList06] 354type=OpDesc 355eventq_index=0 356issueLat=1 357opClass=SimdMult 358opLat=1 359 360[system.cpu0.fuPool.FUList5.opList07] 361type=OpDesc 362eventq_index=0 363issueLat=1 364opClass=SimdMultAcc 365opLat=1 366 367[system.cpu0.fuPool.FUList5.opList08] 368type=OpDesc 369eventq_index=0 370issueLat=1 371opClass=SimdShift 372opLat=1 373 374[system.cpu0.fuPool.FUList5.opList09] 375type=OpDesc 376eventq_index=0 377issueLat=1 378opClass=SimdShiftAcc 379opLat=1 380 381[system.cpu0.fuPool.FUList5.opList10] 382type=OpDesc 383eventq_index=0 384issueLat=1 385opClass=SimdSqrt 386opLat=1 387 388[system.cpu0.fuPool.FUList5.opList11] 389type=OpDesc 390eventq_index=0 391issueLat=1 392opClass=SimdFloatAdd 393opLat=1 394 395[system.cpu0.fuPool.FUList5.opList12] 396type=OpDesc 397eventq_index=0 398issueLat=1 399opClass=SimdFloatAlu 400opLat=1 401 402[system.cpu0.fuPool.FUList5.opList13] 403type=OpDesc 404eventq_index=0 405issueLat=1 406opClass=SimdFloatCmp 407opLat=1 408 409[system.cpu0.fuPool.FUList5.opList14] 410type=OpDesc 411eventq_index=0 412issueLat=1 413opClass=SimdFloatCvt 414opLat=1 415 416[system.cpu0.fuPool.FUList5.opList15] 417type=OpDesc 418eventq_index=0 419issueLat=1 420opClass=SimdFloatDiv 421opLat=1 422 423[system.cpu0.fuPool.FUList5.opList16] 424type=OpDesc 425eventq_index=0 426issueLat=1 427opClass=SimdFloatMisc 428opLat=1 429 430[system.cpu0.fuPool.FUList5.opList17] 431type=OpDesc 432eventq_index=0 433issueLat=1 434opClass=SimdFloatMult 435opLat=1 436 437[system.cpu0.fuPool.FUList5.opList18] 438type=OpDesc 439eventq_index=0 440issueLat=1 441opClass=SimdFloatMultAcc 442opLat=1 443 444[system.cpu0.fuPool.FUList5.opList19] 445type=OpDesc 446eventq_index=0 447issueLat=1 448opClass=SimdFloatSqrt 449opLat=1 450 451[system.cpu0.fuPool.FUList6] 452type=FUDesc 453children=opList 454count=0 455eventq_index=0 456opList=system.cpu0.fuPool.FUList6.opList 457 458[system.cpu0.fuPool.FUList6.opList] 459type=OpDesc 460eventq_index=0 461issueLat=1 462opClass=MemWrite 463opLat=1 464 465[system.cpu0.fuPool.FUList7] 466type=FUDesc 467children=opList0 opList1 468count=4 469eventq_index=0 470opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 471 472[system.cpu0.fuPool.FUList7.opList0] 473type=OpDesc 474eventq_index=0 475issueLat=1 476opClass=MemRead 477opLat=1 478 479[system.cpu0.fuPool.FUList7.opList1] 480type=OpDesc 481eventq_index=0 482issueLat=1 483opClass=MemWrite 484opLat=1 485 486[system.cpu0.fuPool.FUList8] 487type=FUDesc 488children=opList 489count=1 490eventq_index=0 491opList=system.cpu0.fuPool.FUList8.opList 492 493[system.cpu0.fuPool.FUList8.opList] 494type=OpDesc 495eventq_index=0 496issueLat=3 497opClass=IprAccess 498opLat=3 499 500[system.cpu0.icache] 501type=BaseCache 502children=tags 503addr_ranges=0:18446744073709551615 504assoc=1 505clk_domain=system.cpu_clk_domain 506demand_mshr_reserve=1 507eventq_index=0 508forward_snoops=true 509hit_latency=2 510is_top_level=true 511max_miss_count=0 512mshrs=4 513prefetch_on_access=false 514prefetcher=Null 515response_latency=2 516sequential_access=false 517size=32768 518system=system 519tags=system.cpu0.icache.tags 520tgts_per_mshr=20 521two_queue=false 522write_buffers=8 523cpu_side=system.cpu0.icache_port 524mem_side=system.toL2Bus.slave[0] 525 526[system.cpu0.icache.tags] 527type=LRU 528assoc=1 529block_size=64 530clk_domain=system.cpu_clk_domain 531eventq_index=0 532hit_latency=2 533sequential_access=false 534size=32768 535 536[system.cpu0.interrupts] 537type=SparcInterrupts 538eventq_index=0 539 540[system.cpu0.isa] 541type=SparcISA 542eventq_index=0 543 544[system.cpu0.itb] 545type=SparcTLB 546eventq_index=0 547size=64 548 549[system.cpu0.tracer] 550type=ExeTracer 551eventq_index=0 552 553[system.cpu0.workload] 554type=LiveProcess 555cmd=test_atomic 4 556cwd= 557drivers= 558egid=100 559env= 560errout=cerr 561euid=100 562eventq_index=0 563executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic 564gid=100 565input=cin 566kvmInSE=false 567max_stack_size=67108864 568output=cout 569pid=100 570ppid=99 571simpoint=0 572system=system 573uid=100 574useArchPT=false 575 576[system.cpu1] 577type=DerivO3CPU 578children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 579LFSTSize=1024 580LQEntries=32 581LSQCheckLoads=true 582LSQDepCheckShift=4 583SQEntries=32 584SSITSize=1024 585activity=0 586backComSize=5 587branchPred=system.cpu1.branchPred 588cachePorts=200 589checker=Null 590clk_domain=system.cpu_clk_domain 591commitToDecodeDelay=1 592commitToFetchDelay=1 593commitToIEWDelay=1 594commitToRenameDelay=1 595commitWidth=8 596cpu_id=1 597decodeToFetchDelay=1 598decodeToRenameDelay=1 599decodeWidth=8 600dispatchWidth=8 601do_checkpoint_insts=true 602do_quiesce=true 603do_statistics_insts=true 604dtb=system.cpu1.dtb 605eventq_index=0 606fetchBufferSize=64 607fetchQueueSize=32 608fetchToDecodeDelay=1 609fetchTrapLatency=1 610fetchWidth=8 611forwardComSize=5 612fuPool=system.cpu1.fuPool 613function_trace=false 614function_trace_start=0 615iewToCommitDelay=1 616iewToDecodeDelay=1 617iewToFetchDelay=1 618iewToRenameDelay=1 619interrupts=system.cpu1.interrupts 620isa=system.cpu1.isa 621issueToExecuteDelay=1 622issueWidth=8 623itb=system.cpu1.itb 624max_insts_all_threads=0 625max_insts_any_thread=0 626max_loads_all_threads=0 627max_loads_any_thread=0 628needsTSO=false 629numIQEntries=64 630numPhysCCRegs=0 631numPhysFloatRegs=256 632numPhysIntRegs=256 633numROBEntries=192 634numRobs=1 635numThreads=1 636profile=0 637progress_interval=0 638renameToDecodeDelay=1 639renameToFetchDelay=1 640renameToIEWDelay=2 641renameToROBDelay=1 642renameWidth=8 643simpoint_start_insts= 644smtCommitPolicy=RoundRobin 645smtFetchPolicy=SingleThread 646smtIQPolicy=Partitioned 647smtIQThreshold=100 648smtLSQPolicy=Partitioned 649smtLSQThreshold=100 650smtNumFetchingThreads=1 651smtROBPolicy=Partitioned 652smtROBThreshold=100 653socket_id=0 654squashWidth=8 655store_set_clear_period=250000 656switched_out=false 657system=system 658tracer=system.cpu1.tracer 659trapLatency=13 660wbWidth=8 661workload=system.cpu0.workload 662dcache_port=system.cpu1.dcache.cpu_side 663icache_port=system.cpu1.icache.cpu_side 664 665[system.cpu1.branchPred] 666type=TournamentBP 667BTBEntries=4096 668BTBTagSize=16 669RASSize=16 670choiceCtrBits=2 671choicePredictorSize=8192 672eventq_index=0 673globalCtrBits=2 674globalPredictorSize=8192 675instShiftAmt=2 676localCtrBits=2 677localHistoryTableSize=2048 678localPredictorSize=2048 679numThreads=1 680 681[system.cpu1.dcache] 682type=BaseCache 683children=tags 684addr_ranges=0:18446744073709551615 685assoc=4 686clk_domain=system.cpu_clk_domain 687demand_mshr_reserve=1 688eventq_index=0 689forward_snoops=true 690hit_latency=2 691is_top_level=true 692max_miss_count=0 693mshrs=4 694prefetch_on_access=false 695prefetcher=Null 696response_latency=2 697sequential_access=false 698size=32768 699system=system 700tags=system.cpu1.dcache.tags 701tgts_per_mshr=20 702two_queue=false 703write_buffers=8 704cpu_side=system.cpu1.dcache_port 705mem_side=system.toL2Bus.slave[3] 706 707[system.cpu1.dcache.tags] 708type=LRU 709assoc=4 710block_size=64 711clk_domain=system.cpu_clk_domain 712eventq_index=0 713hit_latency=2 714sequential_access=false 715size=32768 716 717[system.cpu1.dtb] 718type=SparcTLB 719eventq_index=0 720size=64 721 722[system.cpu1.fuPool] 723type=FUPool 724children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 725FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 726eventq_index=0 727 728[system.cpu1.fuPool.FUList0] 729type=FUDesc 730children=opList 731count=6 732eventq_index=0 733opList=system.cpu1.fuPool.FUList0.opList 734 735[system.cpu1.fuPool.FUList0.opList] 736type=OpDesc 737eventq_index=0 738issueLat=1 739opClass=IntAlu 740opLat=1 741 742[system.cpu1.fuPool.FUList1] 743type=FUDesc 744children=opList0 opList1 745count=2 746eventq_index=0 747opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 748 749[system.cpu1.fuPool.FUList1.opList0] 750type=OpDesc 751eventq_index=0 752issueLat=1 753opClass=IntMult 754opLat=3 755 756[system.cpu1.fuPool.FUList1.opList1] 757type=OpDesc 758eventq_index=0 759issueLat=19 760opClass=IntDiv 761opLat=20 762 763[system.cpu1.fuPool.FUList2] 764type=FUDesc 765children=opList0 opList1 opList2 766count=4 767eventq_index=0 768opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 769 770[system.cpu1.fuPool.FUList2.opList0] 771type=OpDesc 772eventq_index=0 773issueLat=1 774opClass=FloatAdd 775opLat=2 776 777[system.cpu1.fuPool.FUList2.opList1] 778type=OpDesc 779eventq_index=0 780issueLat=1 781opClass=FloatCmp 782opLat=2 783 784[system.cpu1.fuPool.FUList2.opList2] 785type=OpDesc 786eventq_index=0 787issueLat=1 788opClass=FloatCvt 789opLat=2 790 791[system.cpu1.fuPool.FUList3] 792type=FUDesc 793children=opList0 opList1 opList2 794count=2 795eventq_index=0 796opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 797 798[system.cpu1.fuPool.FUList3.opList0] 799type=OpDesc 800eventq_index=0 801issueLat=1 802opClass=FloatMult 803opLat=4 804 805[system.cpu1.fuPool.FUList3.opList1] 806type=OpDesc 807eventq_index=0 808issueLat=12 809opClass=FloatDiv 810opLat=12 811 812[system.cpu1.fuPool.FUList3.opList2] 813type=OpDesc 814eventq_index=0 815issueLat=24 816opClass=FloatSqrt 817opLat=24 818 819[system.cpu1.fuPool.FUList4] 820type=FUDesc 821children=opList 822count=0 823eventq_index=0 824opList=system.cpu1.fuPool.FUList4.opList 825 826[system.cpu1.fuPool.FUList4.opList] 827type=OpDesc 828eventq_index=0 829issueLat=1 830opClass=MemRead 831opLat=1 832 833[system.cpu1.fuPool.FUList5] 834type=FUDesc 835children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 836count=4 837eventq_index=0 838opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 839 840[system.cpu1.fuPool.FUList5.opList00] 841type=OpDesc 842eventq_index=0 843issueLat=1 844opClass=SimdAdd 845opLat=1 846 847[system.cpu1.fuPool.FUList5.opList01] 848type=OpDesc 849eventq_index=0 850issueLat=1 851opClass=SimdAddAcc 852opLat=1 853 854[system.cpu1.fuPool.FUList5.opList02] 855type=OpDesc 856eventq_index=0 857issueLat=1 858opClass=SimdAlu 859opLat=1 860 861[system.cpu1.fuPool.FUList5.opList03] 862type=OpDesc 863eventq_index=0 864issueLat=1 865opClass=SimdCmp 866opLat=1 867 868[system.cpu1.fuPool.FUList5.opList04] 869type=OpDesc 870eventq_index=0 871issueLat=1 872opClass=SimdCvt 873opLat=1 874 875[system.cpu1.fuPool.FUList5.opList05] 876type=OpDesc 877eventq_index=0 878issueLat=1 879opClass=SimdMisc 880opLat=1 881 882[system.cpu1.fuPool.FUList5.opList06] 883type=OpDesc 884eventq_index=0 885issueLat=1 886opClass=SimdMult 887opLat=1 888 889[system.cpu1.fuPool.FUList5.opList07] 890type=OpDesc 891eventq_index=0 892issueLat=1 893opClass=SimdMultAcc 894opLat=1 895 896[system.cpu1.fuPool.FUList5.opList08] 897type=OpDesc 898eventq_index=0 899issueLat=1 900opClass=SimdShift 901opLat=1 902 903[system.cpu1.fuPool.FUList5.opList09] 904type=OpDesc 905eventq_index=0 906issueLat=1 907opClass=SimdShiftAcc 908opLat=1 909 910[system.cpu1.fuPool.FUList5.opList10] 911type=OpDesc 912eventq_index=0 913issueLat=1 914opClass=SimdSqrt 915opLat=1 916 917[system.cpu1.fuPool.FUList5.opList11] 918type=OpDesc 919eventq_index=0 920issueLat=1 921opClass=SimdFloatAdd 922opLat=1 923 924[system.cpu1.fuPool.FUList5.opList12] 925type=OpDesc 926eventq_index=0 927issueLat=1 928opClass=SimdFloatAlu 929opLat=1 930 931[system.cpu1.fuPool.FUList5.opList13] 932type=OpDesc 933eventq_index=0 934issueLat=1 935opClass=SimdFloatCmp 936opLat=1 937 938[system.cpu1.fuPool.FUList5.opList14] 939type=OpDesc 940eventq_index=0 941issueLat=1 942opClass=SimdFloatCvt 943opLat=1 944 945[system.cpu1.fuPool.FUList5.opList15] 946type=OpDesc 947eventq_index=0 948issueLat=1 949opClass=SimdFloatDiv 950opLat=1 951 952[system.cpu1.fuPool.FUList5.opList16] 953type=OpDesc 954eventq_index=0 955issueLat=1 956opClass=SimdFloatMisc 957opLat=1 958 959[system.cpu1.fuPool.FUList5.opList17] 960type=OpDesc 961eventq_index=0 962issueLat=1 963opClass=SimdFloatMult 964opLat=1 965 966[system.cpu1.fuPool.FUList5.opList18] 967type=OpDesc 968eventq_index=0 969issueLat=1 970opClass=SimdFloatMultAcc 971opLat=1 972 973[system.cpu1.fuPool.FUList5.opList19] 974type=OpDesc 975eventq_index=0 976issueLat=1 977opClass=SimdFloatSqrt 978opLat=1 979 980[system.cpu1.fuPool.FUList6] 981type=FUDesc 982children=opList 983count=0 984eventq_index=0 985opList=system.cpu1.fuPool.FUList6.opList 986 987[system.cpu1.fuPool.FUList6.opList] 988type=OpDesc 989eventq_index=0 990issueLat=1 991opClass=MemWrite 992opLat=1 993 994[system.cpu1.fuPool.FUList7] 995type=FUDesc 996children=opList0 opList1 997count=4 998eventq_index=0 999opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 1000 1001[system.cpu1.fuPool.FUList7.opList0] 1002type=OpDesc 1003eventq_index=0 1004issueLat=1 1005opClass=MemRead 1006opLat=1 1007 1008[system.cpu1.fuPool.FUList7.opList1] 1009type=OpDesc 1010eventq_index=0 1011issueLat=1 1012opClass=MemWrite 1013opLat=1 1014 1015[system.cpu1.fuPool.FUList8] 1016type=FUDesc 1017children=opList 1018count=1 1019eventq_index=0 1020opList=system.cpu1.fuPool.FUList8.opList 1021 1022[system.cpu1.fuPool.FUList8.opList] 1023type=OpDesc 1024eventq_index=0 1025issueLat=3 1026opClass=IprAccess 1027opLat=3 1028 1029[system.cpu1.icache] 1030type=BaseCache 1031children=tags 1032addr_ranges=0:18446744073709551615 1033assoc=1 1034clk_domain=system.cpu_clk_domain 1035demand_mshr_reserve=1 1036eventq_index=0 1037forward_snoops=true 1038hit_latency=2 1039is_top_level=true 1040max_miss_count=0 1041mshrs=4 1042prefetch_on_access=false 1043prefetcher=Null 1044response_latency=2 1045sequential_access=false 1046size=32768 1047system=system 1048tags=system.cpu1.icache.tags 1049tgts_per_mshr=20 1050two_queue=false 1051write_buffers=8 1052cpu_side=system.cpu1.icache_port 1053mem_side=system.toL2Bus.slave[2] 1054 1055[system.cpu1.icache.tags] 1056type=LRU 1057assoc=1 1058block_size=64 1059clk_domain=system.cpu_clk_domain 1060eventq_index=0 1061hit_latency=2 1062sequential_access=false 1063size=32768 1064 1065[system.cpu1.interrupts] 1066type=SparcInterrupts 1067eventq_index=0 1068 1069[system.cpu1.isa] 1070type=SparcISA 1071eventq_index=0 1072 1073[system.cpu1.itb] 1074type=SparcTLB 1075eventq_index=0 1076size=64 1077 1078[system.cpu1.tracer] 1079type=ExeTracer 1080eventq_index=0 1081 1082[system.cpu2] 1083type=DerivO3CPU 1084children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1085LFSTSize=1024 1086LQEntries=32 1087LSQCheckLoads=true 1088LSQDepCheckShift=4 1089SQEntries=32 1090SSITSize=1024 1091activity=0 1092backComSize=5 1093branchPred=system.cpu2.branchPred 1094cachePorts=200 1095checker=Null 1096clk_domain=system.cpu_clk_domain 1097commitToDecodeDelay=1 1098commitToFetchDelay=1 1099commitToIEWDelay=1 1100commitToRenameDelay=1 1101commitWidth=8 1102cpu_id=2 1103decodeToFetchDelay=1 1104decodeToRenameDelay=1 1105decodeWidth=8 1106dispatchWidth=8 1107do_checkpoint_insts=true 1108do_quiesce=true 1109do_statistics_insts=true 1110dtb=system.cpu2.dtb 1111eventq_index=0 1112fetchBufferSize=64 1113fetchQueueSize=32 1114fetchToDecodeDelay=1 1115fetchTrapLatency=1 1116fetchWidth=8 1117forwardComSize=5 1118fuPool=system.cpu2.fuPool 1119function_trace=false 1120function_trace_start=0 1121iewToCommitDelay=1 1122iewToDecodeDelay=1 1123iewToFetchDelay=1 1124iewToRenameDelay=1 1125interrupts=system.cpu2.interrupts 1126isa=system.cpu2.isa 1127issueToExecuteDelay=1 1128issueWidth=8 1129itb=system.cpu2.itb 1130max_insts_all_threads=0 1131max_insts_any_thread=0 1132max_loads_all_threads=0 1133max_loads_any_thread=0 1134needsTSO=false 1135numIQEntries=64 1136numPhysCCRegs=0 1137numPhysFloatRegs=256 1138numPhysIntRegs=256 1139numROBEntries=192 1140numRobs=1 1141numThreads=1 1142profile=0 1143progress_interval=0 1144renameToDecodeDelay=1 1145renameToFetchDelay=1 1146renameToIEWDelay=2 1147renameToROBDelay=1 1148renameWidth=8 1149simpoint_start_insts= 1150smtCommitPolicy=RoundRobin 1151smtFetchPolicy=SingleThread 1152smtIQPolicy=Partitioned 1153smtIQThreshold=100 1154smtLSQPolicy=Partitioned 1155smtLSQThreshold=100 1156smtNumFetchingThreads=1 1157smtROBPolicy=Partitioned 1158smtROBThreshold=100 1159socket_id=0 1160squashWidth=8 1161store_set_clear_period=250000 1162switched_out=false 1163system=system 1164tracer=system.cpu2.tracer 1165trapLatency=13 1166wbWidth=8 1167workload=system.cpu0.workload 1168dcache_port=system.cpu2.dcache.cpu_side 1169icache_port=system.cpu2.icache.cpu_side 1170 1171[system.cpu2.branchPred] 1172type=TournamentBP 1173BTBEntries=4096 1174BTBTagSize=16 1175RASSize=16 1176choiceCtrBits=2 1177choicePredictorSize=8192 1178eventq_index=0 1179globalCtrBits=2 1180globalPredictorSize=8192 1181instShiftAmt=2 1182localCtrBits=2 1183localHistoryTableSize=2048 1184localPredictorSize=2048 1185numThreads=1 1186 1187[system.cpu2.dcache] 1188type=BaseCache 1189children=tags 1190addr_ranges=0:18446744073709551615 1191assoc=4 1192clk_domain=system.cpu_clk_domain 1193demand_mshr_reserve=1 1194eventq_index=0 1195forward_snoops=true 1196hit_latency=2 1197is_top_level=true 1198max_miss_count=0 1199mshrs=4 1200prefetch_on_access=false 1201prefetcher=Null 1202response_latency=2 1203sequential_access=false 1204size=32768 1205system=system 1206tags=system.cpu2.dcache.tags 1207tgts_per_mshr=20 1208two_queue=false 1209write_buffers=8 1210cpu_side=system.cpu2.dcache_port 1211mem_side=system.toL2Bus.slave[5] 1212 1213[system.cpu2.dcache.tags] 1214type=LRU 1215assoc=4 1216block_size=64 1217clk_domain=system.cpu_clk_domain 1218eventq_index=0 1219hit_latency=2 1220sequential_access=false 1221size=32768 1222 1223[system.cpu2.dtb] 1224type=SparcTLB 1225eventq_index=0 1226size=64 1227 1228[system.cpu2.fuPool] 1229type=FUPool 1230children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1231FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1232eventq_index=0 1233 1234[system.cpu2.fuPool.FUList0] 1235type=FUDesc 1236children=opList 1237count=6 1238eventq_index=0 1239opList=system.cpu2.fuPool.FUList0.opList 1240 1241[system.cpu2.fuPool.FUList0.opList] 1242type=OpDesc 1243eventq_index=0 1244issueLat=1 1245opClass=IntAlu 1246opLat=1 1247 1248[system.cpu2.fuPool.FUList1] 1249type=FUDesc 1250children=opList0 opList1 1251count=2 1252eventq_index=0 1253opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1254 1255[system.cpu2.fuPool.FUList1.opList0] 1256type=OpDesc 1257eventq_index=0 1258issueLat=1 1259opClass=IntMult 1260opLat=3 1261 1262[system.cpu2.fuPool.FUList1.opList1] 1263type=OpDesc 1264eventq_index=0 1265issueLat=19 1266opClass=IntDiv 1267opLat=20 1268 1269[system.cpu2.fuPool.FUList2] 1270type=FUDesc 1271children=opList0 opList1 opList2 1272count=4 1273eventq_index=0 1274opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1275 1276[system.cpu2.fuPool.FUList2.opList0] 1277type=OpDesc 1278eventq_index=0 1279issueLat=1 1280opClass=FloatAdd 1281opLat=2 1282 1283[system.cpu2.fuPool.FUList2.opList1] 1284type=OpDesc 1285eventq_index=0 1286issueLat=1 1287opClass=FloatCmp 1288opLat=2 1289 1290[system.cpu2.fuPool.FUList2.opList2] 1291type=OpDesc 1292eventq_index=0 1293issueLat=1 1294opClass=FloatCvt 1295opLat=2 1296 1297[system.cpu2.fuPool.FUList3] 1298type=FUDesc 1299children=opList0 opList1 opList2 1300count=2 1301eventq_index=0 1302opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1303 1304[system.cpu2.fuPool.FUList3.opList0] 1305type=OpDesc 1306eventq_index=0 1307issueLat=1 1308opClass=FloatMult 1309opLat=4 1310 1311[system.cpu2.fuPool.FUList3.opList1] 1312type=OpDesc 1313eventq_index=0 1314issueLat=12 1315opClass=FloatDiv 1316opLat=12 1317 1318[system.cpu2.fuPool.FUList3.opList2] 1319type=OpDesc 1320eventq_index=0 1321issueLat=24 1322opClass=FloatSqrt 1323opLat=24 1324 1325[system.cpu2.fuPool.FUList4] 1326type=FUDesc 1327children=opList 1328count=0 1329eventq_index=0 1330opList=system.cpu2.fuPool.FUList4.opList 1331 1332[system.cpu2.fuPool.FUList4.opList] 1333type=OpDesc 1334eventq_index=0 1335issueLat=1 1336opClass=MemRead 1337opLat=1 1338 1339[system.cpu2.fuPool.FUList5] 1340type=FUDesc 1341children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1342count=4 1343eventq_index=0 1344opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1345 1346[system.cpu2.fuPool.FUList5.opList00] 1347type=OpDesc 1348eventq_index=0 1349issueLat=1 1350opClass=SimdAdd 1351opLat=1 1352 1353[system.cpu2.fuPool.FUList5.opList01] 1354type=OpDesc 1355eventq_index=0 1356issueLat=1 1357opClass=SimdAddAcc 1358opLat=1 1359 1360[system.cpu2.fuPool.FUList5.opList02] 1361type=OpDesc 1362eventq_index=0 1363issueLat=1 1364opClass=SimdAlu 1365opLat=1 1366 1367[system.cpu2.fuPool.FUList5.opList03] 1368type=OpDesc 1369eventq_index=0 1370issueLat=1 1371opClass=SimdCmp 1372opLat=1 1373 1374[system.cpu2.fuPool.FUList5.opList04] 1375type=OpDesc 1376eventq_index=0 1377issueLat=1 1378opClass=SimdCvt 1379opLat=1 1380 1381[system.cpu2.fuPool.FUList5.opList05] 1382type=OpDesc 1383eventq_index=0 1384issueLat=1 1385opClass=SimdMisc 1386opLat=1 1387 1388[system.cpu2.fuPool.FUList5.opList06] 1389type=OpDesc 1390eventq_index=0 1391issueLat=1 1392opClass=SimdMult 1393opLat=1 1394 1395[system.cpu2.fuPool.FUList5.opList07] 1396type=OpDesc 1397eventq_index=0 1398issueLat=1 1399opClass=SimdMultAcc 1400opLat=1 1401 1402[system.cpu2.fuPool.FUList5.opList08] 1403type=OpDesc 1404eventq_index=0 1405issueLat=1 1406opClass=SimdShift 1407opLat=1 1408 1409[system.cpu2.fuPool.FUList5.opList09] 1410type=OpDesc 1411eventq_index=0 1412issueLat=1 1413opClass=SimdShiftAcc 1414opLat=1 1415 1416[system.cpu2.fuPool.FUList5.opList10] 1417type=OpDesc 1418eventq_index=0 1419issueLat=1 1420opClass=SimdSqrt 1421opLat=1 1422 1423[system.cpu2.fuPool.FUList5.opList11] 1424type=OpDesc 1425eventq_index=0 1426issueLat=1 1427opClass=SimdFloatAdd 1428opLat=1 1429 1430[system.cpu2.fuPool.FUList5.opList12] 1431type=OpDesc 1432eventq_index=0 1433issueLat=1 1434opClass=SimdFloatAlu 1435opLat=1 1436 1437[system.cpu2.fuPool.FUList5.opList13] 1438type=OpDesc 1439eventq_index=0 1440issueLat=1 1441opClass=SimdFloatCmp 1442opLat=1 1443 1444[system.cpu2.fuPool.FUList5.opList14] 1445type=OpDesc 1446eventq_index=0 1447issueLat=1 1448opClass=SimdFloatCvt 1449opLat=1 1450 1451[system.cpu2.fuPool.FUList5.opList15] 1452type=OpDesc 1453eventq_index=0 1454issueLat=1 1455opClass=SimdFloatDiv 1456opLat=1 1457 1458[system.cpu2.fuPool.FUList5.opList16] 1459type=OpDesc 1460eventq_index=0 1461issueLat=1 1462opClass=SimdFloatMisc 1463opLat=1 1464 1465[system.cpu2.fuPool.FUList5.opList17] 1466type=OpDesc 1467eventq_index=0 1468issueLat=1 1469opClass=SimdFloatMult 1470opLat=1 1471 1472[system.cpu2.fuPool.FUList5.opList18] 1473type=OpDesc 1474eventq_index=0 1475issueLat=1 1476opClass=SimdFloatMultAcc 1477opLat=1 1478 1479[system.cpu2.fuPool.FUList5.opList19] 1480type=OpDesc 1481eventq_index=0 1482issueLat=1 1483opClass=SimdFloatSqrt 1484opLat=1 1485 1486[system.cpu2.fuPool.FUList6] 1487type=FUDesc 1488children=opList 1489count=0 1490eventq_index=0 1491opList=system.cpu2.fuPool.FUList6.opList 1492 1493[system.cpu2.fuPool.FUList6.opList] 1494type=OpDesc 1495eventq_index=0 1496issueLat=1 1497opClass=MemWrite 1498opLat=1 1499 1500[system.cpu2.fuPool.FUList7] 1501type=FUDesc 1502children=opList0 opList1 1503count=4 1504eventq_index=0 1505opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1506 1507[system.cpu2.fuPool.FUList7.opList0] 1508type=OpDesc 1509eventq_index=0 1510issueLat=1 1511opClass=MemRead 1512opLat=1 1513 1514[system.cpu2.fuPool.FUList7.opList1] 1515type=OpDesc 1516eventq_index=0 1517issueLat=1 1518opClass=MemWrite 1519opLat=1 1520 1521[system.cpu2.fuPool.FUList8] 1522type=FUDesc 1523children=opList 1524count=1 1525eventq_index=0 1526opList=system.cpu2.fuPool.FUList8.opList 1527 1528[system.cpu2.fuPool.FUList8.opList] 1529type=OpDesc 1530eventq_index=0 1531issueLat=3 1532opClass=IprAccess 1533opLat=3 1534 1535[system.cpu2.icache] 1536type=BaseCache 1537children=tags 1538addr_ranges=0:18446744073709551615 1539assoc=1 1540clk_domain=system.cpu_clk_domain 1541demand_mshr_reserve=1 1542eventq_index=0 1543forward_snoops=true 1544hit_latency=2 1545is_top_level=true 1546max_miss_count=0 1547mshrs=4 1548prefetch_on_access=false 1549prefetcher=Null 1550response_latency=2 1551sequential_access=false 1552size=32768 1553system=system 1554tags=system.cpu2.icache.tags 1555tgts_per_mshr=20 1556two_queue=false 1557write_buffers=8 1558cpu_side=system.cpu2.icache_port 1559mem_side=system.toL2Bus.slave[4] 1560 1561[system.cpu2.icache.tags] 1562type=LRU 1563assoc=1 1564block_size=64 1565clk_domain=system.cpu_clk_domain 1566eventq_index=0 1567hit_latency=2 1568sequential_access=false 1569size=32768 1570 1571[system.cpu2.interrupts] 1572type=SparcInterrupts 1573eventq_index=0 1574 1575[system.cpu2.isa] 1576type=SparcISA 1577eventq_index=0 1578 1579[system.cpu2.itb] 1580type=SparcTLB 1581eventq_index=0 1582size=64 1583 1584[system.cpu2.tracer] 1585type=ExeTracer 1586eventq_index=0 1587 1588[system.cpu3] 1589type=DerivO3CPU 1590children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1591LFSTSize=1024 1592LQEntries=32 1593LSQCheckLoads=true 1594LSQDepCheckShift=4 1595SQEntries=32 1596SSITSize=1024 1597activity=0 1598backComSize=5 1599branchPred=system.cpu3.branchPred 1600cachePorts=200 1601checker=Null 1602clk_domain=system.cpu_clk_domain 1603commitToDecodeDelay=1 1604commitToFetchDelay=1 1605commitToIEWDelay=1 1606commitToRenameDelay=1 1607commitWidth=8 1608cpu_id=3 1609decodeToFetchDelay=1 1610decodeToRenameDelay=1 1611decodeWidth=8 1612dispatchWidth=8 1613do_checkpoint_insts=true 1614do_quiesce=true 1615do_statistics_insts=true 1616dtb=system.cpu3.dtb 1617eventq_index=0 1618fetchBufferSize=64 1619fetchQueueSize=32 1620fetchToDecodeDelay=1 1621fetchTrapLatency=1 1622fetchWidth=8 1623forwardComSize=5 1624fuPool=system.cpu3.fuPool 1625function_trace=false 1626function_trace_start=0 1627iewToCommitDelay=1 1628iewToDecodeDelay=1 1629iewToFetchDelay=1 1630iewToRenameDelay=1 1631interrupts=system.cpu3.interrupts 1632isa=system.cpu3.isa 1633issueToExecuteDelay=1 1634issueWidth=8 1635itb=system.cpu3.itb 1636max_insts_all_threads=0 1637max_insts_any_thread=0 1638max_loads_all_threads=0 1639max_loads_any_thread=0 1640needsTSO=false 1641numIQEntries=64 1642numPhysCCRegs=0 1643numPhysFloatRegs=256 1644numPhysIntRegs=256 1645numROBEntries=192 1646numRobs=1 1647numThreads=1 1648profile=0 1649progress_interval=0 1650renameToDecodeDelay=1 1651renameToFetchDelay=1 1652renameToIEWDelay=2 1653renameToROBDelay=1 1654renameWidth=8 1655simpoint_start_insts= 1656smtCommitPolicy=RoundRobin 1657smtFetchPolicy=SingleThread 1658smtIQPolicy=Partitioned 1659smtIQThreshold=100 1660smtLSQPolicy=Partitioned 1661smtLSQThreshold=100 1662smtNumFetchingThreads=1 1663smtROBPolicy=Partitioned 1664smtROBThreshold=100 1665socket_id=0 1666squashWidth=8 1667store_set_clear_period=250000 1668switched_out=false 1669system=system 1670tracer=system.cpu3.tracer 1671trapLatency=13 1672wbWidth=8 1673workload=system.cpu0.workload 1674dcache_port=system.cpu3.dcache.cpu_side 1675icache_port=system.cpu3.icache.cpu_side 1676 1677[system.cpu3.branchPred] 1678type=TournamentBP 1679BTBEntries=4096 1680BTBTagSize=16 1681RASSize=16 1682choiceCtrBits=2 1683choicePredictorSize=8192 1684eventq_index=0 1685globalCtrBits=2 1686globalPredictorSize=8192 1687instShiftAmt=2 1688localCtrBits=2 1689localHistoryTableSize=2048 1690localPredictorSize=2048 1691numThreads=1 1692 1693[system.cpu3.dcache] 1694type=BaseCache 1695children=tags 1696addr_ranges=0:18446744073709551615 1697assoc=4 1698clk_domain=system.cpu_clk_domain 1699demand_mshr_reserve=1 1700eventq_index=0 1701forward_snoops=true 1702hit_latency=2 1703is_top_level=true 1704max_miss_count=0 1705mshrs=4 1706prefetch_on_access=false 1707prefetcher=Null 1708response_latency=2 1709sequential_access=false 1710size=32768 1711system=system 1712tags=system.cpu3.dcache.tags 1713tgts_per_mshr=20 1714two_queue=false 1715write_buffers=8 1716cpu_side=system.cpu3.dcache_port 1717mem_side=system.toL2Bus.slave[7] 1718 1719[system.cpu3.dcache.tags] 1720type=LRU 1721assoc=4 1722block_size=64 1723clk_domain=system.cpu_clk_domain 1724eventq_index=0 1725hit_latency=2 1726sequential_access=false 1727size=32768 1728 1729[system.cpu3.dtb] 1730type=SparcTLB 1731eventq_index=0 1732size=64 1733 1734[system.cpu3.fuPool] 1735type=FUPool 1736children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1737FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1738eventq_index=0 1739 1740[system.cpu3.fuPool.FUList0] 1741type=FUDesc 1742children=opList 1743count=6 1744eventq_index=0 1745opList=system.cpu3.fuPool.FUList0.opList 1746 1747[system.cpu3.fuPool.FUList0.opList] 1748type=OpDesc 1749eventq_index=0 1750issueLat=1 1751opClass=IntAlu 1752opLat=1 1753 1754[system.cpu3.fuPool.FUList1] 1755type=FUDesc 1756children=opList0 opList1 1757count=2 1758eventq_index=0 1759opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1760 1761[system.cpu3.fuPool.FUList1.opList0] 1762type=OpDesc 1763eventq_index=0 1764issueLat=1 1765opClass=IntMult 1766opLat=3 1767 1768[system.cpu3.fuPool.FUList1.opList1] 1769type=OpDesc 1770eventq_index=0 1771issueLat=19 1772opClass=IntDiv 1773opLat=20 1774 1775[system.cpu3.fuPool.FUList2] 1776type=FUDesc 1777children=opList0 opList1 opList2 1778count=4 1779eventq_index=0 1780opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1781 1782[system.cpu3.fuPool.FUList2.opList0] 1783type=OpDesc 1784eventq_index=0 1785issueLat=1 1786opClass=FloatAdd 1787opLat=2 1788 1789[system.cpu3.fuPool.FUList2.opList1] 1790type=OpDesc 1791eventq_index=0 1792issueLat=1 1793opClass=FloatCmp 1794opLat=2 1795 1796[system.cpu3.fuPool.FUList2.opList2] 1797type=OpDesc 1798eventq_index=0 1799issueLat=1 1800opClass=FloatCvt 1801opLat=2 1802 1803[system.cpu3.fuPool.FUList3] 1804type=FUDesc 1805children=opList0 opList1 opList2 1806count=2 1807eventq_index=0 1808opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1809 1810[system.cpu3.fuPool.FUList3.opList0] 1811type=OpDesc 1812eventq_index=0 1813issueLat=1 1814opClass=FloatMult 1815opLat=4 1816 1817[system.cpu3.fuPool.FUList3.opList1] 1818type=OpDesc 1819eventq_index=0 1820issueLat=12 1821opClass=FloatDiv 1822opLat=12 1823 1824[system.cpu3.fuPool.FUList3.opList2] 1825type=OpDesc 1826eventq_index=0 1827issueLat=24 1828opClass=FloatSqrt 1829opLat=24 1830 1831[system.cpu3.fuPool.FUList4] 1832type=FUDesc 1833children=opList 1834count=0 1835eventq_index=0 1836opList=system.cpu3.fuPool.FUList4.opList 1837 1838[system.cpu3.fuPool.FUList4.opList] 1839type=OpDesc 1840eventq_index=0 1841issueLat=1 1842opClass=MemRead 1843opLat=1 1844 1845[system.cpu3.fuPool.FUList5] 1846type=FUDesc 1847children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1848count=4 1849eventq_index=0 1850opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1851 1852[system.cpu3.fuPool.FUList5.opList00] 1853type=OpDesc 1854eventq_index=0 1855issueLat=1 1856opClass=SimdAdd 1857opLat=1 1858 1859[system.cpu3.fuPool.FUList5.opList01] 1860type=OpDesc 1861eventq_index=0 1862issueLat=1 1863opClass=SimdAddAcc 1864opLat=1 1865 1866[system.cpu3.fuPool.FUList5.opList02] 1867type=OpDesc 1868eventq_index=0 1869issueLat=1 1870opClass=SimdAlu 1871opLat=1 1872 1873[system.cpu3.fuPool.FUList5.opList03] 1874type=OpDesc 1875eventq_index=0 1876issueLat=1 1877opClass=SimdCmp 1878opLat=1 1879 1880[system.cpu3.fuPool.FUList5.opList04] 1881type=OpDesc 1882eventq_index=0 1883issueLat=1 1884opClass=SimdCvt 1885opLat=1 1886 1887[system.cpu3.fuPool.FUList5.opList05] 1888type=OpDesc 1889eventq_index=0 1890issueLat=1 1891opClass=SimdMisc 1892opLat=1 1893 1894[system.cpu3.fuPool.FUList5.opList06] 1895type=OpDesc 1896eventq_index=0 1897issueLat=1 1898opClass=SimdMult 1899opLat=1 1900 1901[system.cpu3.fuPool.FUList5.opList07] 1902type=OpDesc 1903eventq_index=0 1904issueLat=1 1905opClass=SimdMultAcc 1906opLat=1 1907 1908[system.cpu3.fuPool.FUList5.opList08] 1909type=OpDesc 1910eventq_index=0 1911issueLat=1 1912opClass=SimdShift 1913opLat=1 1914 1915[system.cpu3.fuPool.FUList5.opList09] 1916type=OpDesc 1917eventq_index=0 1918issueLat=1 1919opClass=SimdShiftAcc 1920opLat=1 1921 1922[system.cpu3.fuPool.FUList5.opList10] 1923type=OpDesc 1924eventq_index=0 1925issueLat=1 1926opClass=SimdSqrt 1927opLat=1 1928 1929[system.cpu3.fuPool.FUList5.opList11] 1930type=OpDesc 1931eventq_index=0 1932issueLat=1 1933opClass=SimdFloatAdd 1934opLat=1 1935 1936[system.cpu3.fuPool.FUList5.opList12] 1937type=OpDesc 1938eventq_index=0 1939issueLat=1 1940opClass=SimdFloatAlu 1941opLat=1 1942 1943[system.cpu3.fuPool.FUList5.opList13] 1944type=OpDesc 1945eventq_index=0 1946issueLat=1 1947opClass=SimdFloatCmp 1948opLat=1 1949 1950[system.cpu3.fuPool.FUList5.opList14] 1951type=OpDesc 1952eventq_index=0 1953issueLat=1 1954opClass=SimdFloatCvt 1955opLat=1 1956 1957[system.cpu3.fuPool.FUList5.opList15] 1958type=OpDesc 1959eventq_index=0 1960issueLat=1 1961opClass=SimdFloatDiv 1962opLat=1 1963 1964[system.cpu3.fuPool.FUList5.opList16] 1965type=OpDesc 1966eventq_index=0 1967issueLat=1 1968opClass=SimdFloatMisc 1969opLat=1 1970 1971[system.cpu3.fuPool.FUList5.opList17] 1972type=OpDesc 1973eventq_index=0 1974issueLat=1 1975opClass=SimdFloatMult 1976opLat=1 1977 1978[system.cpu3.fuPool.FUList5.opList18] 1979type=OpDesc 1980eventq_index=0 1981issueLat=1 1982opClass=SimdFloatMultAcc 1983opLat=1 1984 1985[system.cpu3.fuPool.FUList5.opList19] 1986type=OpDesc 1987eventq_index=0 1988issueLat=1 1989opClass=SimdFloatSqrt 1990opLat=1 1991 1992[system.cpu3.fuPool.FUList6] 1993type=FUDesc 1994children=opList 1995count=0 1996eventq_index=0 1997opList=system.cpu3.fuPool.FUList6.opList 1998 1999[system.cpu3.fuPool.FUList6.opList] 2000type=OpDesc 2001eventq_index=0 2002issueLat=1 2003opClass=MemWrite 2004opLat=1 2005 2006[system.cpu3.fuPool.FUList7] 2007type=FUDesc 2008children=opList0 opList1 2009count=4 2010eventq_index=0 2011opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 2012 2013[system.cpu3.fuPool.FUList7.opList0] 2014type=OpDesc 2015eventq_index=0 2016issueLat=1 2017opClass=MemRead 2018opLat=1 2019 2020[system.cpu3.fuPool.FUList7.opList1] 2021type=OpDesc 2022eventq_index=0 2023issueLat=1 2024opClass=MemWrite 2025opLat=1 2026 2027[system.cpu3.fuPool.FUList8] 2028type=FUDesc 2029children=opList 2030count=1 2031eventq_index=0 2032opList=system.cpu3.fuPool.FUList8.opList 2033 2034[system.cpu3.fuPool.FUList8.opList] 2035type=OpDesc 2036eventq_index=0 2037issueLat=3 2038opClass=IprAccess 2039opLat=3 2040 2041[system.cpu3.icache] 2042type=BaseCache 2043children=tags 2044addr_ranges=0:18446744073709551615 2045assoc=1 2046clk_domain=system.cpu_clk_domain 2047demand_mshr_reserve=1 2048eventq_index=0 2049forward_snoops=true 2050hit_latency=2 2051is_top_level=true 2052max_miss_count=0 2053mshrs=4 2054prefetch_on_access=false 2055prefetcher=Null 2056response_latency=2 2057sequential_access=false 2058size=32768 2059system=system 2060tags=system.cpu3.icache.tags 2061tgts_per_mshr=20 2062two_queue=false 2063write_buffers=8 2064cpu_side=system.cpu3.icache_port 2065mem_side=system.toL2Bus.slave[6] 2066 2067[system.cpu3.icache.tags] 2068type=LRU 2069assoc=1 2070block_size=64 2071clk_domain=system.cpu_clk_domain 2072eventq_index=0 2073hit_latency=2 2074sequential_access=false 2075size=32768 2076 2077[system.cpu3.interrupts] 2078type=SparcInterrupts 2079eventq_index=0 2080 2081[system.cpu3.isa] 2082type=SparcISA 2083eventq_index=0 2084 2085[system.cpu3.itb] 2086type=SparcTLB 2087eventq_index=0 2088size=64 2089 2090[system.cpu3.tracer] 2091type=ExeTracer 2092eventq_index=0 2093 2094[system.cpu_clk_domain] 2095type=SrcClockDomain 2096clock=500 2097domain_id=-1 2098eventq_index=0 2099init_perf_level=0 2100voltage_domain=system.voltage_domain 2101 2102[system.dvfs_handler] 2103type=DVFSHandler 2104domains= 2105enable=false 2106eventq_index=0 2107sys_clk_domain=system.clk_domain 2108transition_latency=100000000 2109 2110[system.l2c] 2111type=BaseCache 2112children=tags 2113addr_ranges=0:18446744073709551615 2114assoc=8 2115clk_domain=system.cpu_clk_domain 2116demand_mshr_reserve=1 2117eventq_index=0 2118forward_snoops=true 2119hit_latency=20 2120is_top_level=false 2121max_miss_count=0 2122mshrs=20 2123prefetch_on_access=false 2124prefetcher=Null 2125response_latency=20 2126sequential_access=false 2127size=4194304 2128system=system 2129tags=system.l2c.tags 2130tgts_per_mshr=12 2131two_queue=false 2132write_buffers=8 2133cpu_side=system.toL2Bus.master[0] 2134mem_side=system.membus.slave[1] 2135 2136[system.l2c.tags] 2137type=LRU 2138assoc=8 2139block_size=64 2140clk_domain=system.cpu_clk_domain 2141eventq_index=0 2142hit_latency=20 2143sequential_access=false 2144size=4194304 2145 2146[system.membus] 2147type=CoherentXBar 2148clk_domain=system.clk_domain 2149eventq_index=0 2150forward_latency=4 2151frontend_latency=3 2152response_latency=2 2153snoop_filter=Null 2154snoop_response_latency=4 2155system=system 2156use_default_range=false 2157width=16 2158master=system.physmem.port 2159slave=system.system_port system.l2c.mem_side 2160 2161[system.physmem] 2162type=DRAMCtrl 2163IDD0=0.075000 2164IDD02=0.000000 2165IDD2N=0.050000 2166IDD2N2=0.000000 2167IDD2P0=0.000000 2168IDD2P02=0.000000 2169IDD2P1=0.000000 2170IDD2P12=0.000000 2171IDD3N=0.057000 2172IDD3N2=0.000000 2173IDD3P0=0.000000 2174IDD3P02=0.000000 2175IDD3P1=0.000000 2176IDD3P12=0.000000 2177IDD4R=0.187000 2178IDD4R2=0.000000 2179IDD4W=0.165000 2180IDD4W2=0.000000 2181IDD5=0.220000 2182IDD52=0.000000 2183IDD6=0.000000 2184IDD62=0.000000 2185VDD=1.500000 2186VDD2=0.000000 2187activation_limit=4 2188addr_mapping=RoRaBaCoCh 2189bank_groups_per_rank=0 2190banks_per_rank=8 2191burst_length=8 2192channels=1 2193clk_domain=system.clk_domain 2194conf_table_reported=true 2195device_bus_width=8 2196device_rowbuffer_size=1024 2197device_size=536870912 2198devices_per_rank=8 2199dll=true 2200eventq_index=0 2201in_addr_map=true 2202max_accesses_per_row=16 2203mem_sched_policy=frfcfs 2204min_writes_per_switch=16 2205null=false 2206page_policy=open_adaptive 2207range=0:134217727 2208ranks_per_channel=2 2209read_buffer_size=32 2210static_backend_latency=10000 2211static_frontend_latency=10000 2212tBURST=5000 2213tCCD_L=0 2214tCK=1250 2215tCL=13750 2216tCS=2500 2217tRAS=35000 2218tRCD=13750 2219tREFI=7800000 2220tRFC=260000 2221tRP=13750 2222tRRD=6000 2223tRRD_L=0 2224tRTP=7500 2225tRTW=2500 2226tWR=15000 2227tWTR=7500 2228tXAW=30000 2229tXP=0 2230tXPDLL=0 2231tXS=0 2232tXSDLL=0 2233write_buffer_size=64 2234write_high_thresh_perc=85 2235write_low_thresh_perc=50 2236port=system.membus.master[0] 2237 2238[system.toL2Bus] 2239type=CoherentXBar 2240clk_domain=system.cpu_clk_domain 2241eventq_index=0 2242forward_latency=0 2243frontend_latency=1 2244response_latency=1 2245snoop_filter=Null 2246snoop_response_latency=1 2247system=system 2248use_default_range=false 2249width=32 2250master=system.l2c.cpu_side 2251slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2252 2253[system.voltage_domain] 2254type=VoltageDomain 2255eventq_index=0 2256voltage=1.000000 2257 2258