config.ini revision 10736
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu0] 48type=DerivO3CPU 49children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu0.branchPred 59cachePorts=200 60checker=Null 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dtb=system.cpu0.dtb 76eventq_index=0 77fetchBufferSize=64 78fetchQueueSize=32 79fetchToDecodeDelay=1 80fetchTrapLatency=1 81fetchWidth=8 82forwardComSize=5 83fuPool=system.cpu0.fuPool 84function_trace=false 85function_trace_start=0 86iewToCommitDelay=1 87iewToDecodeDelay=1 88iewToFetchDelay=1 89iewToRenameDelay=1 90interrupts=system.cpu0.interrupts 91isa=system.cpu0.isa 92issueToExecuteDelay=1 93issueWidth=8 94itb=system.cpu0.itb 95max_insts_all_threads=0 96max_insts_any_thread=0 97max_loads_all_threads=0 98max_loads_any_thread=0 99needsTSO=false 100numIQEntries=64 101numPhysCCRegs=0 102numPhysFloatRegs=256 103numPhysIntRegs=256 104numROBEntries=192 105numRobs=1 106numThreads=1 107profile=0 108progress_interval=0 109renameToDecodeDelay=1 110renameToFetchDelay=1 111renameToIEWDelay=2 112renameToROBDelay=1 113renameWidth=8 114simpoint_start_insts= 115smtCommitPolicy=RoundRobin 116smtFetchPolicy=SingleThread 117smtIQPolicy=Partitioned 118smtIQThreshold=100 119smtLSQPolicy=Partitioned 120smtLSQThreshold=100 121smtNumFetchingThreads=1 122smtROBPolicy=Partitioned 123smtROBThreshold=100 124socket_id=0 125squashWidth=8 126store_set_clear_period=250000 127switched_out=false 128system=system 129tracer=system.cpu0.tracer 130trapLatency=13 131wbWidth=8 132workload=system.cpu0.workload 133dcache_port=system.cpu0.dcache.cpu_side 134icache_port=system.cpu0.icache.cpu_side 135 136[system.cpu0.branchPred] 137type=BranchPredictor 138BTBEntries=4096 139BTBTagSize=16 140RASSize=16 141choiceCtrBits=2 142choicePredictorSize=8192 143eventq_index=0 144globalCtrBits=2 145globalPredictorSize=8192 146instShiftAmt=2 147localCtrBits=2 148localHistoryTableSize=2048 149localPredictorSize=2048 150numThreads=1 151predType=tournament 152 153[system.cpu0.dcache] 154type=BaseCache 155children=tags 156addr_ranges=0:18446744073709551615 157assoc=4 158clk_domain=system.cpu_clk_domain 159demand_mshr_reserve=1 160eventq_index=0 161forward_snoops=true 162hit_latency=2 163is_top_level=true 164max_miss_count=0 165mshrs=4 166prefetch_on_access=false 167prefetcher=Null 168response_latency=2 169sequential_access=false 170size=32768 171system=system 172tags=system.cpu0.dcache.tags 173tgts_per_mshr=20 174two_queue=false 175write_buffers=8 176cpu_side=system.cpu0.dcache_port 177mem_side=system.toL2Bus.slave[1] 178 179[system.cpu0.dcache.tags] 180type=LRU 181assoc=4 182block_size=64 183clk_domain=system.cpu_clk_domain 184eventq_index=0 185hit_latency=2 186sequential_access=false 187size=32768 188 189[system.cpu0.dtb] 190type=SparcTLB 191eventq_index=0 192size=64 193 194[system.cpu0.fuPool] 195type=FUPool 196children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 197FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 198eventq_index=0 199 200[system.cpu0.fuPool.FUList0] 201type=FUDesc 202children=opList 203count=6 204eventq_index=0 205opList=system.cpu0.fuPool.FUList0.opList 206 207[system.cpu0.fuPool.FUList0.opList] 208type=OpDesc 209eventq_index=0 210issueLat=1 211opClass=IntAlu 212opLat=1 213 214[system.cpu0.fuPool.FUList1] 215type=FUDesc 216children=opList0 opList1 217count=2 218eventq_index=0 219opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 220 221[system.cpu0.fuPool.FUList1.opList0] 222type=OpDesc 223eventq_index=0 224issueLat=1 225opClass=IntMult 226opLat=3 227 228[system.cpu0.fuPool.FUList1.opList1] 229type=OpDesc 230eventq_index=0 231issueLat=19 232opClass=IntDiv 233opLat=20 234 235[system.cpu0.fuPool.FUList2] 236type=FUDesc 237children=opList0 opList1 opList2 238count=4 239eventq_index=0 240opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 241 242[system.cpu0.fuPool.FUList2.opList0] 243type=OpDesc 244eventq_index=0 245issueLat=1 246opClass=FloatAdd 247opLat=2 248 249[system.cpu0.fuPool.FUList2.opList1] 250type=OpDesc 251eventq_index=0 252issueLat=1 253opClass=FloatCmp 254opLat=2 255 256[system.cpu0.fuPool.FUList2.opList2] 257type=OpDesc 258eventq_index=0 259issueLat=1 260opClass=FloatCvt 261opLat=2 262 263[system.cpu0.fuPool.FUList3] 264type=FUDesc 265children=opList0 opList1 opList2 266count=2 267eventq_index=0 268opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 269 270[system.cpu0.fuPool.FUList3.opList0] 271type=OpDesc 272eventq_index=0 273issueLat=1 274opClass=FloatMult 275opLat=4 276 277[system.cpu0.fuPool.FUList3.opList1] 278type=OpDesc 279eventq_index=0 280issueLat=12 281opClass=FloatDiv 282opLat=12 283 284[system.cpu0.fuPool.FUList3.opList2] 285type=OpDesc 286eventq_index=0 287issueLat=24 288opClass=FloatSqrt 289opLat=24 290 291[system.cpu0.fuPool.FUList4] 292type=FUDesc 293children=opList 294count=0 295eventq_index=0 296opList=system.cpu0.fuPool.FUList4.opList 297 298[system.cpu0.fuPool.FUList4.opList] 299type=OpDesc 300eventq_index=0 301issueLat=1 302opClass=MemRead 303opLat=1 304 305[system.cpu0.fuPool.FUList5] 306type=FUDesc 307children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 308count=4 309eventq_index=0 310opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 311 312[system.cpu0.fuPool.FUList5.opList00] 313type=OpDesc 314eventq_index=0 315issueLat=1 316opClass=SimdAdd 317opLat=1 318 319[system.cpu0.fuPool.FUList5.opList01] 320type=OpDesc 321eventq_index=0 322issueLat=1 323opClass=SimdAddAcc 324opLat=1 325 326[system.cpu0.fuPool.FUList5.opList02] 327type=OpDesc 328eventq_index=0 329issueLat=1 330opClass=SimdAlu 331opLat=1 332 333[system.cpu0.fuPool.FUList5.opList03] 334type=OpDesc 335eventq_index=0 336issueLat=1 337opClass=SimdCmp 338opLat=1 339 340[system.cpu0.fuPool.FUList5.opList04] 341type=OpDesc 342eventq_index=0 343issueLat=1 344opClass=SimdCvt 345opLat=1 346 347[system.cpu0.fuPool.FUList5.opList05] 348type=OpDesc 349eventq_index=0 350issueLat=1 351opClass=SimdMisc 352opLat=1 353 354[system.cpu0.fuPool.FUList5.opList06] 355type=OpDesc 356eventq_index=0 357issueLat=1 358opClass=SimdMult 359opLat=1 360 361[system.cpu0.fuPool.FUList5.opList07] 362type=OpDesc 363eventq_index=0 364issueLat=1 365opClass=SimdMultAcc 366opLat=1 367 368[system.cpu0.fuPool.FUList5.opList08] 369type=OpDesc 370eventq_index=0 371issueLat=1 372opClass=SimdShift 373opLat=1 374 375[system.cpu0.fuPool.FUList5.opList09] 376type=OpDesc 377eventq_index=0 378issueLat=1 379opClass=SimdShiftAcc 380opLat=1 381 382[system.cpu0.fuPool.FUList5.opList10] 383type=OpDesc 384eventq_index=0 385issueLat=1 386opClass=SimdSqrt 387opLat=1 388 389[system.cpu0.fuPool.FUList5.opList11] 390type=OpDesc 391eventq_index=0 392issueLat=1 393opClass=SimdFloatAdd 394opLat=1 395 396[system.cpu0.fuPool.FUList5.opList12] 397type=OpDesc 398eventq_index=0 399issueLat=1 400opClass=SimdFloatAlu 401opLat=1 402 403[system.cpu0.fuPool.FUList5.opList13] 404type=OpDesc 405eventq_index=0 406issueLat=1 407opClass=SimdFloatCmp 408opLat=1 409 410[system.cpu0.fuPool.FUList5.opList14] 411type=OpDesc 412eventq_index=0 413issueLat=1 414opClass=SimdFloatCvt 415opLat=1 416 417[system.cpu0.fuPool.FUList5.opList15] 418type=OpDesc 419eventq_index=0 420issueLat=1 421opClass=SimdFloatDiv 422opLat=1 423 424[system.cpu0.fuPool.FUList5.opList16] 425type=OpDesc 426eventq_index=0 427issueLat=1 428opClass=SimdFloatMisc 429opLat=1 430 431[system.cpu0.fuPool.FUList5.opList17] 432type=OpDesc 433eventq_index=0 434issueLat=1 435opClass=SimdFloatMult 436opLat=1 437 438[system.cpu0.fuPool.FUList5.opList18] 439type=OpDesc 440eventq_index=0 441issueLat=1 442opClass=SimdFloatMultAcc 443opLat=1 444 445[system.cpu0.fuPool.FUList5.opList19] 446type=OpDesc 447eventq_index=0 448issueLat=1 449opClass=SimdFloatSqrt 450opLat=1 451 452[system.cpu0.fuPool.FUList6] 453type=FUDesc 454children=opList 455count=0 456eventq_index=0 457opList=system.cpu0.fuPool.FUList6.opList 458 459[system.cpu0.fuPool.FUList6.opList] 460type=OpDesc 461eventq_index=0 462issueLat=1 463opClass=MemWrite 464opLat=1 465 466[system.cpu0.fuPool.FUList7] 467type=FUDesc 468children=opList0 opList1 469count=4 470eventq_index=0 471opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 472 473[system.cpu0.fuPool.FUList7.opList0] 474type=OpDesc 475eventq_index=0 476issueLat=1 477opClass=MemRead 478opLat=1 479 480[system.cpu0.fuPool.FUList7.opList1] 481type=OpDesc 482eventq_index=0 483issueLat=1 484opClass=MemWrite 485opLat=1 486 487[system.cpu0.fuPool.FUList8] 488type=FUDesc 489children=opList 490count=1 491eventq_index=0 492opList=system.cpu0.fuPool.FUList8.opList 493 494[system.cpu0.fuPool.FUList8.opList] 495type=OpDesc 496eventq_index=0 497issueLat=3 498opClass=IprAccess 499opLat=3 500 501[system.cpu0.icache] 502type=BaseCache 503children=tags 504addr_ranges=0:18446744073709551615 505assoc=1 506clk_domain=system.cpu_clk_domain 507demand_mshr_reserve=1 508eventq_index=0 509forward_snoops=true 510hit_latency=2 511is_top_level=true 512max_miss_count=0 513mshrs=4 514prefetch_on_access=false 515prefetcher=Null 516response_latency=2 517sequential_access=false 518size=32768 519system=system 520tags=system.cpu0.icache.tags 521tgts_per_mshr=20 522two_queue=false 523write_buffers=8 524cpu_side=system.cpu0.icache_port 525mem_side=system.toL2Bus.slave[0] 526 527[system.cpu0.icache.tags] 528type=LRU 529assoc=1 530block_size=64 531clk_domain=system.cpu_clk_domain 532eventq_index=0 533hit_latency=2 534sequential_access=false 535size=32768 536 537[system.cpu0.interrupts] 538type=SparcInterrupts 539eventq_index=0 540 541[system.cpu0.isa] 542type=SparcISA 543eventq_index=0 544 545[system.cpu0.itb] 546type=SparcTLB 547eventq_index=0 548size=64 549 550[system.cpu0.tracer] 551type=ExeTracer 552eventq_index=0 553 554[system.cpu0.workload] 555type=LiveProcess 556cmd=test_atomic 4 557cwd= 558drivers= 559egid=100 560env= 561errout=cerr 562euid=100 563eventq_index=0 564executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic 565gid=100 566input=cin 567kvmInSE=false 568max_stack_size=67108864 569output=cout 570pid=100 571ppid=99 572simpoint=0 573system=system 574uid=100 575useArchPT=false 576 577[system.cpu1] 578type=DerivO3CPU 579children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 580LFSTSize=1024 581LQEntries=32 582LSQCheckLoads=true 583LSQDepCheckShift=4 584SQEntries=32 585SSITSize=1024 586activity=0 587backComSize=5 588branchPred=system.cpu1.branchPred 589cachePorts=200 590checker=Null 591clk_domain=system.cpu_clk_domain 592commitToDecodeDelay=1 593commitToFetchDelay=1 594commitToIEWDelay=1 595commitToRenameDelay=1 596commitWidth=8 597cpu_id=1 598decodeToFetchDelay=1 599decodeToRenameDelay=1 600decodeWidth=8 601dispatchWidth=8 602do_checkpoint_insts=true 603do_quiesce=true 604do_statistics_insts=true 605dtb=system.cpu1.dtb 606eventq_index=0 607fetchBufferSize=64 608fetchQueueSize=32 609fetchToDecodeDelay=1 610fetchTrapLatency=1 611fetchWidth=8 612forwardComSize=5 613fuPool=system.cpu1.fuPool 614function_trace=false 615function_trace_start=0 616iewToCommitDelay=1 617iewToDecodeDelay=1 618iewToFetchDelay=1 619iewToRenameDelay=1 620interrupts=system.cpu1.interrupts 621isa=system.cpu1.isa 622issueToExecuteDelay=1 623issueWidth=8 624itb=system.cpu1.itb 625max_insts_all_threads=0 626max_insts_any_thread=0 627max_loads_all_threads=0 628max_loads_any_thread=0 629needsTSO=false 630numIQEntries=64 631numPhysCCRegs=0 632numPhysFloatRegs=256 633numPhysIntRegs=256 634numROBEntries=192 635numRobs=1 636numThreads=1 637profile=0 638progress_interval=0 639renameToDecodeDelay=1 640renameToFetchDelay=1 641renameToIEWDelay=2 642renameToROBDelay=1 643renameWidth=8 644simpoint_start_insts= 645smtCommitPolicy=RoundRobin 646smtFetchPolicy=SingleThread 647smtIQPolicy=Partitioned 648smtIQThreshold=100 649smtLSQPolicy=Partitioned 650smtLSQThreshold=100 651smtNumFetchingThreads=1 652smtROBPolicy=Partitioned 653smtROBThreshold=100 654socket_id=0 655squashWidth=8 656store_set_clear_period=250000 657switched_out=false 658system=system 659tracer=system.cpu1.tracer 660trapLatency=13 661wbWidth=8 662workload=system.cpu0.workload 663dcache_port=system.cpu1.dcache.cpu_side 664icache_port=system.cpu1.icache.cpu_side 665 666[system.cpu1.branchPred] 667type=BranchPredictor 668BTBEntries=4096 669BTBTagSize=16 670RASSize=16 671choiceCtrBits=2 672choicePredictorSize=8192 673eventq_index=0 674globalCtrBits=2 675globalPredictorSize=8192 676instShiftAmt=2 677localCtrBits=2 678localHistoryTableSize=2048 679localPredictorSize=2048 680numThreads=1 681predType=tournament 682 683[system.cpu1.dcache] 684type=BaseCache 685children=tags 686addr_ranges=0:18446744073709551615 687assoc=4 688clk_domain=system.cpu_clk_domain 689demand_mshr_reserve=1 690eventq_index=0 691forward_snoops=true 692hit_latency=2 693is_top_level=true 694max_miss_count=0 695mshrs=4 696prefetch_on_access=false 697prefetcher=Null 698response_latency=2 699sequential_access=false 700size=32768 701system=system 702tags=system.cpu1.dcache.tags 703tgts_per_mshr=20 704two_queue=false 705write_buffers=8 706cpu_side=system.cpu1.dcache_port 707mem_side=system.toL2Bus.slave[3] 708 709[system.cpu1.dcache.tags] 710type=LRU 711assoc=4 712block_size=64 713clk_domain=system.cpu_clk_domain 714eventq_index=0 715hit_latency=2 716sequential_access=false 717size=32768 718 719[system.cpu1.dtb] 720type=SparcTLB 721eventq_index=0 722size=64 723 724[system.cpu1.fuPool] 725type=FUPool 726children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 727FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 728eventq_index=0 729 730[system.cpu1.fuPool.FUList0] 731type=FUDesc 732children=opList 733count=6 734eventq_index=0 735opList=system.cpu1.fuPool.FUList0.opList 736 737[system.cpu1.fuPool.FUList0.opList] 738type=OpDesc 739eventq_index=0 740issueLat=1 741opClass=IntAlu 742opLat=1 743 744[system.cpu1.fuPool.FUList1] 745type=FUDesc 746children=opList0 opList1 747count=2 748eventq_index=0 749opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 750 751[system.cpu1.fuPool.FUList1.opList0] 752type=OpDesc 753eventq_index=0 754issueLat=1 755opClass=IntMult 756opLat=3 757 758[system.cpu1.fuPool.FUList1.opList1] 759type=OpDesc 760eventq_index=0 761issueLat=19 762opClass=IntDiv 763opLat=20 764 765[system.cpu1.fuPool.FUList2] 766type=FUDesc 767children=opList0 opList1 opList2 768count=4 769eventq_index=0 770opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 771 772[system.cpu1.fuPool.FUList2.opList0] 773type=OpDesc 774eventq_index=0 775issueLat=1 776opClass=FloatAdd 777opLat=2 778 779[system.cpu1.fuPool.FUList2.opList1] 780type=OpDesc 781eventq_index=0 782issueLat=1 783opClass=FloatCmp 784opLat=2 785 786[system.cpu1.fuPool.FUList2.opList2] 787type=OpDesc 788eventq_index=0 789issueLat=1 790opClass=FloatCvt 791opLat=2 792 793[system.cpu1.fuPool.FUList3] 794type=FUDesc 795children=opList0 opList1 opList2 796count=2 797eventq_index=0 798opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 799 800[system.cpu1.fuPool.FUList3.opList0] 801type=OpDesc 802eventq_index=0 803issueLat=1 804opClass=FloatMult 805opLat=4 806 807[system.cpu1.fuPool.FUList3.opList1] 808type=OpDesc 809eventq_index=0 810issueLat=12 811opClass=FloatDiv 812opLat=12 813 814[system.cpu1.fuPool.FUList3.opList2] 815type=OpDesc 816eventq_index=0 817issueLat=24 818opClass=FloatSqrt 819opLat=24 820 821[system.cpu1.fuPool.FUList4] 822type=FUDesc 823children=opList 824count=0 825eventq_index=0 826opList=system.cpu1.fuPool.FUList4.opList 827 828[system.cpu1.fuPool.FUList4.opList] 829type=OpDesc 830eventq_index=0 831issueLat=1 832opClass=MemRead 833opLat=1 834 835[system.cpu1.fuPool.FUList5] 836type=FUDesc 837children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 838count=4 839eventq_index=0 840opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 841 842[system.cpu1.fuPool.FUList5.opList00] 843type=OpDesc 844eventq_index=0 845issueLat=1 846opClass=SimdAdd 847opLat=1 848 849[system.cpu1.fuPool.FUList5.opList01] 850type=OpDesc 851eventq_index=0 852issueLat=1 853opClass=SimdAddAcc 854opLat=1 855 856[system.cpu1.fuPool.FUList5.opList02] 857type=OpDesc 858eventq_index=0 859issueLat=1 860opClass=SimdAlu 861opLat=1 862 863[system.cpu1.fuPool.FUList5.opList03] 864type=OpDesc 865eventq_index=0 866issueLat=1 867opClass=SimdCmp 868opLat=1 869 870[system.cpu1.fuPool.FUList5.opList04] 871type=OpDesc 872eventq_index=0 873issueLat=1 874opClass=SimdCvt 875opLat=1 876 877[system.cpu1.fuPool.FUList5.opList05] 878type=OpDesc 879eventq_index=0 880issueLat=1 881opClass=SimdMisc 882opLat=1 883 884[system.cpu1.fuPool.FUList5.opList06] 885type=OpDesc 886eventq_index=0 887issueLat=1 888opClass=SimdMult 889opLat=1 890 891[system.cpu1.fuPool.FUList5.opList07] 892type=OpDesc 893eventq_index=0 894issueLat=1 895opClass=SimdMultAcc 896opLat=1 897 898[system.cpu1.fuPool.FUList5.opList08] 899type=OpDesc 900eventq_index=0 901issueLat=1 902opClass=SimdShift 903opLat=1 904 905[system.cpu1.fuPool.FUList5.opList09] 906type=OpDesc 907eventq_index=0 908issueLat=1 909opClass=SimdShiftAcc 910opLat=1 911 912[system.cpu1.fuPool.FUList5.opList10] 913type=OpDesc 914eventq_index=0 915issueLat=1 916opClass=SimdSqrt 917opLat=1 918 919[system.cpu1.fuPool.FUList5.opList11] 920type=OpDesc 921eventq_index=0 922issueLat=1 923opClass=SimdFloatAdd 924opLat=1 925 926[system.cpu1.fuPool.FUList5.opList12] 927type=OpDesc 928eventq_index=0 929issueLat=1 930opClass=SimdFloatAlu 931opLat=1 932 933[system.cpu1.fuPool.FUList5.opList13] 934type=OpDesc 935eventq_index=0 936issueLat=1 937opClass=SimdFloatCmp 938opLat=1 939 940[system.cpu1.fuPool.FUList5.opList14] 941type=OpDesc 942eventq_index=0 943issueLat=1 944opClass=SimdFloatCvt 945opLat=1 946 947[system.cpu1.fuPool.FUList5.opList15] 948type=OpDesc 949eventq_index=0 950issueLat=1 951opClass=SimdFloatDiv 952opLat=1 953 954[system.cpu1.fuPool.FUList5.opList16] 955type=OpDesc 956eventq_index=0 957issueLat=1 958opClass=SimdFloatMisc 959opLat=1 960 961[system.cpu1.fuPool.FUList5.opList17] 962type=OpDesc 963eventq_index=0 964issueLat=1 965opClass=SimdFloatMult 966opLat=1 967 968[system.cpu1.fuPool.FUList5.opList18] 969type=OpDesc 970eventq_index=0 971issueLat=1 972opClass=SimdFloatMultAcc 973opLat=1 974 975[system.cpu1.fuPool.FUList5.opList19] 976type=OpDesc 977eventq_index=0 978issueLat=1 979opClass=SimdFloatSqrt 980opLat=1 981 982[system.cpu1.fuPool.FUList6] 983type=FUDesc 984children=opList 985count=0 986eventq_index=0 987opList=system.cpu1.fuPool.FUList6.opList 988 989[system.cpu1.fuPool.FUList6.opList] 990type=OpDesc 991eventq_index=0 992issueLat=1 993opClass=MemWrite 994opLat=1 995 996[system.cpu1.fuPool.FUList7] 997type=FUDesc 998children=opList0 opList1 999count=4 1000eventq_index=0 1001opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 1002 1003[system.cpu1.fuPool.FUList7.opList0] 1004type=OpDesc 1005eventq_index=0 1006issueLat=1 1007opClass=MemRead 1008opLat=1 1009 1010[system.cpu1.fuPool.FUList7.opList1] 1011type=OpDesc 1012eventq_index=0 1013issueLat=1 1014opClass=MemWrite 1015opLat=1 1016 1017[system.cpu1.fuPool.FUList8] 1018type=FUDesc 1019children=opList 1020count=1 1021eventq_index=0 1022opList=system.cpu1.fuPool.FUList8.opList 1023 1024[system.cpu1.fuPool.FUList8.opList] 1025type=OpDesc 1026eventq_index=0 1027issueLat=3 1028opClass=IprAccess 1029opLat=3 1030 1031[system.cpu1.icache] 1032type=BaseCache 1033children=tags 1034addr_ranges=0:18446744073709551615 1035assoc=1 1036clk_domain=system.cpu_clk_domain 1037demand_mshr_reserve=1 1038eventq_index=0 1039forward_snoops=true 1040hit_latency=2 1041is_top_level=true 1042max_miss_count=0 1043mshrs=4 1044prefetch_on_access=false 1045prefetcher=Null 1046response_latency=2 1047sequential_access=false 1048size=32768 1049system=system 1050tags=system.cpu1.icache.tags 1051tgts_per_mshr=20 1052two_queue=false 1053write_buffers=8 1054cpu_side=system.cpu1.icache_port 1055mem_side=system.toL2Bus.slave[2] 1056 1057[system.cpu1.icache.tags] 1058type=LRU 1059assoc=1 1060block_size=64 1061clk_domain=system.cpu_clk_domain 1062eventq_index=0 1063hit_latency=2 1064sequential_access=false 1065size=32768 1066 1067[system.cpu1.interrupts] 1068type=SparcInterrupts 1069eventq_index=0 1070 1071[system.cpu1.isa] 1072type=SparcISA 1073eventq_index=0 1074 1075[system.cpu1.itb] 1076type=SparcTLB 1077eventq_index=0 1078size=64 1079 1080[system.cpu1.tracer] 1081type=ExeTracer 1082eventq_index=0 1083 1084[system.cpu2] 1085type=DerivO3CPU 1086children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1087LFSTSize=1024 1088LQEntries=32 1089LSQCheckLoads=true 1090LSQDepCheckShift=4 1091SQEntries=32 1092SSITSize=1024 1093activity=0 1094backComSize=5 1095branchPred=system.cpu2.branchPred 1096cachePorts=200 1097checker=Null 1098clk_domain=system.cpu_clk_domain 1099commitToDecodeDelay=1 1100commitToFetchDelay=1 1101commitToIEWDelay=1 1102commitToRenameDelay=1 1103commitWidth=8 1104cpu_id=2 1105decodeToFetchDelay=1 1106decodeToRenameDelay=1 1107decodeWidth=8 1108dispatchWidth=8 1109do_checkpoint_insts=true 1110do_quiesce=true 1111do_statistics_insts=true 1112dtb=system.cpu2.dtb 1113eventq_index=0 1114fetchBufferSize=64 1115fetchQueueSize=32 1116fetchToDecodeDelay=1 1117fetchTrapLatency=1 1118fetchWidth=8 1119forwardComSize=5 1120fuPool=system.cpu2.fuPool 1121function_trace=false 1122function_trace_start=0 1123iewToCommitDelay=1 1124iewToDecodeDelay=1 1125iewToFetchDelay=1 1126iewToRenameDelay=1 1127interrupts=system.cpu2.interrupts 1128isa=system.cpu2.isa 1129issueToExecuteDelay=1 1130issueWidth=8 1131itb=system.cpu2.itb 1132max_insts_all_threads=0 1133max_insts_any_thread=0 1134max_loads_all_threads=0 1135max_loads_any_thread=0 1136needsTSO=false 1137numIQEntries=64 1138numPhysCCRegs=0 1139numPhysFloatRegs=256 1140numPhysIntRegs=256 1141numROBEntries=192 1142numRobs=1 1143numThreads=1 1144profile=0 1145progress_interval=0 1146renameToDecodeDelay=1 1147renameToFetchDelay=1 1148renameToIEWDelay=2 1149renameToROBDelay=1 1150renameWidth=8 1151simpoint_start_insts= 1152smtCommitPolicy=RoundRobin 1153smtFetchPolicy=SingleThread 1154smtIQPolicy=Partitioned 1155smtIQThreshold=100 1156smtLSQPolicy=Partitioned 1157smtLSQThreshold=100 1158smtNumFetchingThreads=1 1159smtROBPolicy=Partitioned 1160smtROBThreshold=100 1161socket_id=0 1162squashWidth=8 1163store_set_clear_period=250000 1164switched_out=false 1165system=system 1166tracer=system.cpu2.tracer 1167trapLatency=13 1168wbWidth=8 1169workload=system.cpu0.workload 1170dcache_port=system.cpu2.dcache.cpu_side 1171icache_port=system.cpu2.icache.cpu_side 1172 1173[system.cpu2.branchPred] 1174type=BranchPredictor 1175BTBEntries=4096 1176BTBTagSize=16 1177RASSize=16 1178choiceCtrBits=2 1179choicePredictorSize=8192 1180eventq_index=0 1181globalCtrBits=2 1182globalPredictorSize=8192 1183instShiftAmt=2 1184localCtrBits=2 1185localHistoryTableSize=2048 1186localPredictorSize=2048 1187numThreads=1 1188predType=tournament 1189 1190[system.cpu2.dcache] 1191type=BaseCache 1192children=tags 1193addr_ranges=0:18446744073709551615 1194assoc=4 1195clk_domain=system.cpu_clk_domain 1196demand_mshr_reserve=1 1197eventq_index=0 1198forward_snoops=true 1199hit_latency=2 1200is_top_level=true 1201max_miss_count=0 1202mshrs=4 1203prefetch_on_access=false 1204prefetcher=Null 1205response_latency=2 1206sequential_access=false 1207size=32768 1208system=system 1209tags=system.cpu2.dcache.tags 1210tgts_per_mshr=20 1211two_queue=false 1212write_buffers=8 1213cpu_side=system.cpu2.dcache_port 1214mem_side=system.toL2Bus.slave[5] 1215 1216[system.cpu2.dcache.tags] 1217type=LRU 1218assoc=4 1219block_size=64 1220clk_domain=system.cpu_clk_domain 1221eventq_index=0 1222hit_latency=2 1223sequential_access=false 1224size=32768 1225 1226[system.cpu2.dtb] 1227type=SparcTLB 1228eventq_index=0 1229size=64 1230 1231[system.cpu2.fuPool] 1232type=FUPool 1233children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1234FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1235eventq_index=0 1236 1237[system.cpu2.fuPool.FUList0] 1238type=FUDesc 1239children=opList 1240count=6 1241eventq_index=0 1242opList=system.cpu2.fuPool.FUList0.opList 1243 1244[system.cpu2.fuPool.FUList0.opList] 1245type=OpDesc 1246eventq_index=0 1247issueLat=1 1248opClass=IntAlu 1249opLat=1 1250 1251[system.cpu2.fuPool.FUList1] 1252type=FUDesc 1253children=opList0 opList1 1254count=2 1255eventq_index=0 1256opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1257 1258[system.cpu2.fuPool.FUList1.opList0] 1259type=OpDesc 1260eventq_index=0 1261issueLat=1 1262opClass=IntMult 1263opLat=3 1264 1265[system.cpu2.fuPool.FUList1.opList1] 1266type=OpDesc 1267eventq_index=0 1268issueLat=19 1269opClass=IntDiv 1270opLat=20 1271 1272[system.cpu2.fuPool.FUList2] 1273type=FUDesc 1274children=opList0 opList1 opList2 1275count=4 1276eventq_index=0 1277opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1278 1279[system.cpu2.fuPool.FUList2.opList0] 1280type=OpDesc 1281eventq_index=0 1282issueLat=1 1283opClass=FloatAdd 1284opLat=2 1285 1286[system.cpu2.fuPool.FUList2.opList1] 1287type=OpDesc 1288eventq_index=0 1289issueLat=1 1290opClass=FloatCmp 1291opLat=2 1292 1293[system.cpu2.fuPool.FUList2.opList2] 1294type=OpDesc 1295eventq_index=0 1296issueLat=1 1297opClass=FloatCvt 1298opLat=2 1299 1300[system.cpu2.fuPool.FUList3] 1301type=FUDesc 1302children=opList0 opList1 opList2 1303count=2 1304eventq_index=0 1305opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1306 1307[system.cpu2.fuPool.FUList3.opList0] 1308type=OpDesc 1309eventq_index=0 1310issueLat=1 1311opClass=FloatMult 1312opLat=4 1313 1314[system.cpu2.fuPool.FUList3.opList1] 1315type=OpDesc 1316eventq_index=0 1317issueLat=12 1318opClass=FloatDiv 1319opLat=12 1320 1321[system.cpu2.fuPool.FUList3.opList2] 1322type=OpDesc 1323eventq_index=0 1324issueLat=24 1325opClass=FloatSqrt 1326opLat=24 1327 1328[system.cpu2.fuPool.FUList4] 1329type=FUDesc 1330children=opList 1331count=0 1332eventq_index=0 1333opList=system.cpu2.fuPool.FUList4.opList 1334 1335[system.cpu2.fuPool.FUList4.opList] 1336type=OpDesc 1337eventq_index=0 1338issueLat=1 1339opClass=MemRead 1340opLat=1 1341 1342[system.cpu2.fuPool.FUList5] 1343type=FUDesc 1344children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1345count=4 1346eventq_index=0 1347opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1348 1349[system.cpu2.fuPool.FUList5.opList00] 1350type=OpDesc 1351eventq_index=0 1352issueLat=1 1353opClass=SimdAdd 1354opLat=1 1355 1356[system.cpu2.fuPool.FUList5.opList01] 1357type=OpDesc 1358eventq_index=0 1359issueLat=1 1360opClass=SimdAddAcc 1361opLat=1 1362 1363[system.cpu2.fuPool.FUList5.opList02] 1364type=OpDesc 1365eventq_index=0 1366issueLat=1 1367opClass=SimdAlu 1368opLat=1 1369 1370[system.cpu2.fuPool.FUList5.opList03] 1371type=OpDesc 1372eventq_index=0 1373issueLat=1 1374opClass=SimdCmp 1375opLat=1 1376 1377[system.cpu2.fuPool.FUList5.opList04] 1378type=OpDesc 1379eventq_index=0 1380issueLat=1 1381opClass=SimdCvt 1382opLat=1 1383 1384[system.cpu2.fuPool.FUList5.opList05] 1385type=OpDesc 1386eventq_index=0 1387issueLat=1 1388opClass=SimdMisc 1389opLat=1 1390 1391[system.cpu2.fuPool.FUList5.opList06] 1392type=OpDesc 1393eventq_index=0 1394issueLat=1 1395opClass=SimdMult 1396opLat=1 1397 1398[system.cpu2.fuPool.FUList5.opList07] 1399type=OpDesc 1400eventq_index=0 1401issueLat=1 1402opClass=SimdMultAcc 1403opLat=1 1404 1405[system.cpu2.fuPool.FUList5.opList08] 1406type=OpDesc 1407eventq_index=0 1408issueLat=1 1409opClass=SimdShift 1410opLat=1 1411 1412[system.cpu2.fuPool.FUList5.opList09] 1413type=OpDesc 1414eventq_index=0 1415issueLat=1 1416opClass=SimdShiftAcc 1417opLat=1 1418 1419[system.cpu2.fuPool.FUList5.opList10] 1420type=OpDesc 1421eventq_index=0 1422issueLat=1 1423opClass=SimdSqrt 1424opLat=1 1425 1426[system.cpu2.fuPool.FUList5.opList11] 1427type=OpDesc 1428eventq_index=0 1429issueLat=1 1430opClass=SimdFloatAdd 1431opLat=1 1432 1433[system.cpu2.fuPool.FUList5.opList12] 1434type=OpDesc 1435eventq_index=0 1436issueLat=1 1437opClass=SimdFloatAlu 1438opLat=1 1439 1440[system.cpu2.fuPool.FUList5.opList13] 1441type=OpDesc 1442eventq_index=0 1443issueLat=1 1444opClass=SimdFloatCmp 1445opLat=1 1446 1447[system.cpu2.fuPool.FUList5.opList14] 1448type=OpDesc 1449eventq_index=0 1450issueLat=1 1451opClass=SimdFloatCvt 1452opLat=1 1453 1454[system.cpu2.fuPool.FUList5.opList15] 1455type=OpDesc 1456eventq_index=0 1457issueLat=1 1458opClass=SimdFloatDiv 1459opLat=1 1460 1461[system.cpu2.fuPool.FUList5.opList16] 1462type=OpDesc 1463eventq_index=0 1464issueLat=1 1465opClass=SimdFloatMisc 1466opLat=1 1467 1468[system.cpu2.fuPool.FUList5.opList17] 1469type=OpDesc 1470eventq_index=0 1471issueLat=1 1472opClass=SimdFloatMult 1473opLat=1 1474 1475[system.cpu2.fuPool.FUList5.opList18] 1476type=OpDesc 1477eventq_index=0 1478issueLat=1 1479opClass=SimdFloatMultAcc 1480opLat=1 1481 1482[system.cpu2.fuPool.FUList5.opList19] 1483type=OpDesc 1484eventq_index=0 1485issueLat=1 1486opClass=SimdFloatSqrt 1487opLat=1 1488 1489[system.cpu2.fuPool.FUList6] 1490type=FUDesc 1491children=opList 1492count=0 1493eventq_index=0 1494opList=system.cpu2.fuPool.FUList6.opList 1495 1496[system.cpu2.fuPool.FUList6.opList] 1497type=OpDesc 1498eventq_index=0 1499issueLat=1 1500opClass=MemWrite 1501opLat=1 1502 1503[system.cpu2.fuPool.FUList7] 1504type=FUDesc 1505children=opList0 opList1 1506count=4 1507eventq_index=0 1508opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1509 1510[system.cpu2.fuPool.FUList7.opList0] 1511type=OpDesc 1512eventq_index=0 1513issueLat=1 1514opClass=MemRead 1515opLat=1 1516 1517[system.cpu2.fuPool.FUList7.opList1] 1518type=OpDesc 1519eventq_index=0 1520issueLat=1 1521opClass=MemWrite 1522opLat=1 1523 1524[system.cpu2.fuPool.FUList8] 1525type=FUDesc 1526children=opList 1527count=1 1528eventq_index=0 1529opList=system.cpu2.fuPool.FUList8.opList 1530 1531[system.cpu2.fuPool.FUList8.opList] 1532type=OpDesc 1533eventq_index=0 1534issueLat=3 1535opClass=IprAccess 1536opLat=3 1537 1538[system.cpu2.icache] 1539type=BaseCache 1540children=tags 1541addr_ranges=0:18446744073709551615 1542assoc=1 1543clk_domain=system.cpu_clk_domain 1544demand_mshr_reserve=1 1545eventq_index=0 1546forward_snoops=true 1547hit_latency=2 1548is_top_level=true 1549max_miss_count=0 1550mshrs=4 1551prefetch_on_access=false 1552prefetcher=Null 1553response_latency=2 1554sequential_access=false 1555size=32768 1556system=system 1557tags=system.cpu2.icache.tags 1558tgts_per_mshr=20 1559two_queue=false 1560write_buffers=8 1561cpu_side=system.cpu2.icache_port 1562mem_side=system.toL2Bus.slave[4] 1563 1564[system.cpu2.icache.tags] 1565type=LRU 1566assoc=1 1567block_size=64 1568clk_domain=system.cpu_clk_domain 1569eventq_index=0 1570hit_latency=2 1571sequential_access=false 1572size=32768 1573 1574[system.cpu2.interrupts] 1575type=SparcInterrupts 1576eventq_index=0 1577 1578[system.cpu2.isa] 1579type=SparcISA 1580eventq_index=0 1581 1582[system.cpu2.itb] 1583type=SparcTLB 1584eventq_index=0 1585size=64 1586 1587[system.cpu2.tracer] 1588type=ExeTracer 1589eventq_index=0 1590 1591[system.cpu3] 1592type=DerivO3CPU 1593children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1594LFSTSize=1024 1595LQEntries=32 1596LSQCheckLoads=true 1597LSQDepCheckShift=4 1598SQEntries=32 1599SSITSize=1024 1600activity=0 1601backComSize=5 1602branchPred=system.cpu3.branchPred 1603cachePorts=200 1604checker=Null 1605clk_domain=system.cpu_clk_domain 1606commitToDecodeDelay=1 1607commitToFetchDelay=1 1608commitToIEWDelay=1 1609commitToRenameDelay=1 1610commitWidth=8 1611cpu_id=3 1612decodeToFetchDelay=1 1613decodeToRenameDelay=1 1614decodeWidth=8 1615dispatchWidth=8 1616do_checkpoint_insts=true 1617do_quiesce=true 1618do_statistics_insts=true 1619dtb=system.cpu3.dtb 1620eventq_index=0 1621fetchBufferSize=64 1622fetchQueueSize=32 1623fetchToDecodeDelay=1 1624fetchTrapLatency=1 1625fetchWidth=8 1626forwardComSize=5 1627fuPool=system.cpu3.fuPool 1628function_trace=false 1629function_trace_start=0 1630iewToCommitDelay=1 1631iewToDecodeDelay=1 1632iewToFetchDelay=1 1633iewToRenameDelay=1 1634interrupts=system.cpu3.interrupts 1635isa=system.cpu3.isa 1636issueToExecuteDelay=1 1637issueWidth=8 1638itb=system.cpu3.itb 1639max_insts_all_threads=0 1640max_insts_any_thread=0 1641max_loads_all_threads=0 1642max_loads_any_thread=0 1643needsTSO=false 1644numIQEntries=64 1645numPhysCCRegs=0 1646numPhysFloatRegs=256 1647numPhysIntRegs=256 1648numROBEntries=192 1649numRobs=1 1650numThreads=1 1651profile=0 1652progress_interval=0 1653renameToDecodeDelay=1 1654renameToFetchDelay=1 1655renameToIEWDelay=2 1656renameToROBDelay=1 1657renameWidth=8 1658simpoint_start_insts= 1659smtCommitPolicy=RoundRobin 1660smtFetchPolicy=SingleThread 1661smtIQPolicy=Partitioned 1662smtIQThreshold=100 1663smtLSQPolicy=Partitioned 1664smtLSQThreshold=100 1665smtNumFetchingThreads=1 1666smtROBPolicy=Partitioned 1667smtROBThreshold=100 1668socket_id=0 1669squashWidth=8 1670store_set_clear_period=250000 1671switched_out=false 1672system=system 1673tracer=system.cpu3.tracer 1674trapLatency=13 1675wbWidth=8 1676workload=system.cpu0.workload 1677dcache_port=system.cpu3.dcache.cpu_side 1678icache_port=system.cpu3.icache.cpu_side 1679 1680[system.cpu3.branchPred] 1681type=BranchPredictor 1682BTBEntries=4096 1683BTBTagSize=16 1684RASSize=16 1685choiceCtrBits=2 1686choicePredictorSize=8192 1687eventq_index=0 1688globalCtrBits=2 1689globalPredictorSize=8192 1690instShiftAmt=2 1691localCtrBits=2 1692localHistoryTableSize=2048 1693localPredictorSize=2048 1694numThreads=1 1695predType=tournament 1696 1697[system.cpu3.dcache] 1698type=BaseCache 1699children=tags 1700addr_ranges=0:18446744073709551615 1701assoc=4 1702clk_domain=system.cpu_clk_domain 1703demand_mshr_reserve=1 1704eventq_index=0 1705forward_snoops=true 1706hit_latency=2 1707is_top_level=true 1708max_miss_count=0 1709mshrs=4 1710prefetch_on_access=false 1711prefetcher=Null 1712response_latency=2 1713sequential_access=false 1714size=32768 1715system=system 1716tags=system.cpu3.dcache.tags 1717tgts_per_mshr=20 1718two_queue=false 1719write_buffers=8 1720cpu_side=system.cpu3.dcache_port 1721mem_side=system.toL2Bus.slave[7] 1722 1723[system.cpu3.dcache.tags] 1724type=LRU 1725assoc=4 1726block_size=64 1727clk_domain=system.cpu_clk_domain 1728eventq_index=0 1729hit_latency=2 1730sequential_access=false 1731size=32768 1732 1733[system.cpu3.dtb] 1734type=SparcTLB 1735eventq_index=0 1736size=64 1737 1738[system.cpu3.fuPool] 1739type=FUPool 1740children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1741FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1742eventq_index=0 1743 1744[system.cpu3.fuPool.FUList0] 1745type=FUDesc 1746children=opList 1747count=6 1748eventq_index=0 1749opList=system.cpu3.fuPool.FUList0.opList 1750 1751[system.cpu3.fuPool.FUList0.opList] 1752type=OpDesc 1753eventq_index=0 1754issueLat=1 1755opClass=IntAlu 1756opLat=1 1757 1758[system.cpu3.fuPool.FUList1] 1759type=FUDesc 1760children=opList0 opList1 1761count=2 1762eventq_index=0 1763opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1764 1765[system.cpu3.fuPool.FUList1.opList0] 1766type=OpDesc 1767eventq_index=0 1768issueLat=1 1769opClass=IntMult 1770opLat=3 1771 1772[system.cpu3.fuPool.FUList1.opList1] 1773type=OpDesc 1774eventq_index=0 1775issueLat=19 1776opClass=IntDiv 1777opLat=20 1778 1779[system.cpu3.fuPool.FUList2] 1780type=FUDesc 1781children=opList0 opList1 opList2 1782count=4 1783eventq_index=0 1784opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1785 1786[system.cpu3.fuPool.FUList2.opList0] 1787type=OpDesc 1788eventq_index=0 1789issueLat=1 1790opClass=FloatAdd 1791opLat=2 1792 1793[system.cpu3.fuPool.FUList2.opList1] 1794type=OpDesc 1795eventq_index=0 1796issueLat=1 1797opClass=FloatCmp 1798opLat=2 1799 1800[system.cpu3.fuPool.FUList2.opList2] 1801type=OpDesc 1802eventq_index=0 1803issueLat=1 1804opClass=FloatCvt 1805opLat=2 1806 1807[system.cpu3.fuPool.FUList3] 1808type=FUDesc 1809children=opList0 opList1 opList2 1810count=2 1811eventq_index=0 1812opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1813 1814[system.cpu3.fuPool.FUList3.opList0] 1815type=OpDesc 1816eventq_index=0 1817issueLat=1 1818opClass=FloatMult 1819opLat=4 1820 1821[system.cpu3.fuPool.FUList3.opList1] 1822type=OpDesc 1823eventq_index=0 1824issueLat=12 1825opClass=FloatDiv 1826opLat=12 1827 1828[system.cpu3.fuPool.FUList3.opList2] 1829type=OpDesc 1830eventq_index=0 1831issueLat=24 1832opClass=FloatSqrt 1833opLat=24 1834 1835[system.cpu3.fuPool.FUList4] 1836type=FUDesc 1837children=opList 1838count=0 1839eventq_index=0 1840opList=system.cpu3.fuPool.FUList4.opList 1841 1842[system.cpu3.fuPool.FUList4.opList] 1843type=OpDesc 1844eventq_index=0 1845issueLat=1 1846opClass=MemRead 1847opLat=1 1848 1849[system.cpu3.fuPool.FUList5] 1850type=FUDesc 1851children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1852count=4 1853eventq_index=0 1854opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1855 1856[system.cpu3.fuPool.FUList5.opList00] 1857type=OpDesc 1858eventq_index=0 1859issueLat=1 1860opClass=SimdAdd 1861opLat=1 1862 1863[system.cpu3.fuPool.FUList5.opList01] 1864type=OpDesc 1865eventq_index=0 1866issueLat=1 1867opClass=SimdAddAcc 1868opLat=1 1869 1870[system.cpu3.fuPool.FUList5.opList02] 1871type=OpDesc 1872eventq_index=0 1873issueLat=1 1874opClass=SimdAlu 1875opLat=1 1876 1877[system.cpu3.fuPool.FUList5.opList03] 1878type=OpDesc 1879eventq_index=0 1880issueLat=1 1881opClass=SimdCmp 1882opLat=1 1883 1884[system.cpu3.fuPool.FUList5.opList04] 1885type=OpDesc 1886eventq_index=0 1887issueLat=1 1888opClass=SimdCvt 1889opLat=1 1890 1891[system.cpu3.fuPool.FUList5.opList05] 1892type=OpDesc 1893eventq_index=0 1894issueLat=1 1895opClass=SimdMisc 1896opLat=1 1897 1898[system.cpu3.fuPool.FUList5.opList06] 1899type=OpDesc 1900eventq_index=0 1901issueLat=1 1902opClass=SimdMult 1903opLat=1 1904 1905[system.cpu3.fuPool.FUList5.opList07] 1906type=OpDesc 1907eventq_index=0 1908issueLat=1 1909opClass=SimdMultAcc 1910opLat=1 1911 1912[system.cpu3.fuPool.FUList5.opList08] 1913type=OpDesc 1914eventq_index=0 1915issueLat=1 1916opClass=SimdShift 1917opLat=1 1918 1919[system.cpu3.fuPool.FUList5.opList09] 1920type=OpDesc 1921eventq_index=0 1922issueLat=1 1923opClass=SimdShiftAcc 1924opLat=1 1925 1926[system.cpu3.fuPool.FUList5.opList10] 1927type=OpDesc 1928eventq_index=0 1929issueLat=1 1930opClass=SimdSqrt 1931opLat=1 1932 1933[system.cpu3.fuPool.FUList5.opList11] 1934type=OpDesc 1935eventq_index=0 1936issueLat=1 1937opClass=SimdFloatAdd 1938opLat=1 1939 1940[system.cpu3.fuPool.FUList5.opList12] 1941type=OpDesc 1942eventq_index=0 1943issueLat=1 1944opClass=SimdFloatAlu 1945opLat=1 1946 1947[system.cpu3.fuPool.FUList5.opList13] 1948type=OpDesc 1949eventq_index=0 1950issueLat=1 1951opClass=SimdFloatCmp 1952opLat=1 1953 1954[system.cpu3.fuPool.FUList5.opList14] 1955type=OpDesc 1956eventq_index=0 1957issueLat=1 1958opClass=SimdFloatCvt 1959opLat=1 1960 1961[system.cpu3.fuPool.FUList5.opList15] 1962type=OpDesc 1963eventq_index=0 1964issueLat=1 1965opClass=SimdFloatDiv 1966opLat=1 1967 1968[system.cpu3.fuPool.FUList5.opList16] 1969type=OpDesc 1970eventq_index=0 1971issueLat=1 1972opClass=SimdFloatMisc 1973opLat=1 1974 1975[system.cpu3.fuPool.FUList5.opList17] 1976type=OpDesc 1977eventq_index=0 1978issueLat=1 1979opClass=SimdFloatMult 1980opLat=1 1981 1982[system.cpu3.fuPool.FUList5.opList18] 1983type=OpDesc 1984eventq_index=0 1985issueLat=1 1986opClass=SimdFloatMultAcc 1987opLat=1 1988 1989[system.cpu3.fuPool.FUList5.opList19] 1990type=OpDesc 1991eventq_index=0 1992issueLat=1 1993opClass=SimdFloatSqrt 1994opLat=1 1995 1996[system.cpu3.fuPool.FUList6] 1997type=FUDesc 1998children=opList 1999count=0 2000eventq_index=0 2001opList=system.cpu3.fuPool.FUList6.opList 2002 2003[system.cpu3.fuPool.FUList6.opList] 2004type=OpDesc 2005eventq_index=0 2006issueLat=1 2007opClass=MemWrite 2008opLat=1 2009 2010[system.cpu3.fuPool.FUList7] 2011type=FUDesc 2012children=opList0 opList1 2013count=4 2014eventq_index=0 2015opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 2016 2017[system.cpu3.fuPool.FUList7.opList0] 2018type=OpDesc 2019eventq_index=0 2020issueLat=1 2021opClass=MemRead 2022opLat=1 2023 2024[system.cpu3.fuPool.FUList7.opList1] 2025type=OpDesc 2026eventq_index=0 2027issueLat=1 2028opClass=MemWrite 2029opLat=1 2030 2031[system.cpu3.fuPool.FUList8] 2032type=FUDesc 2033children=opList 2034count=1 2035eventq_index=0 2036opList=system.cpu3.fuPool.FUList8.opList 2037 2038[system.cpu3.fuPool.FUList8.opList] 2039type=OpDesc 2040eventq_index=0 2041issueLat=3 2042opClass=IprAccess 2043opLat=3 2044 2045[system.cpu3.icache] 2046type=BaseCache 2047children=tags 2048addr_ranges=0:18446744073709551615 2049assoc=1 2050clk_domain=system.cpu_clk_domain 2051demand_mshr_reserve=1 2052eventq_index=0 2053forward_snoops=true 2054hit_latency=2 2055is_top_level=true 2056max_miss_count=0 2057mshrs=4 2058prefetch_on_access=false 2059prefetcher=Null 2060response_latency=2 2061sequential_access=false 2062size=32768 2063system=system 2064tags=system.cpu3.icache.tags 2065tgts_per_mshr=20 2066two_queue=false 2067write_buffers=8 2068cpu_side=system.cpu3.icache_port 2069mem_side=system.toL2Bus.slave[6] 2070 2071[system.cpu3.icache.tags] 2072type=LRU 2073assoc=1 2074block_size=64 2075clk_domain=system.cpu_clk_domain 2076eventq_index=0 2077hit_latency=2 2078sequential_access=false 2079size=32768 2080 2081[system.cpu3.interrupts] 2082type=SparcInterrupts 2083eventq_index=0 2084 2085[system.cpu3.isa] 2086type=SparcISA 2087eventq_index=0 2088 2089[system.cpu3.itb] 2090type=SparcTLB 2091eventq_index=0 2092size=64 2093 2094[system.cpu3.tracer] 2095type=ExeTracer 2096eventq_index=0 2097 2098[system.cpu_clk_domain] 2099type=SrcClockDomain 2100clock=500 2101domain_id=-1 2102eventq_index=0 2103init_perf_level=0 2104voltage_domain=system.voltage_domain 2105 2106[system.dvfs_handler] 2107type=DVFSHandler 2108domains= 2109enable=false 2110eventq_index=0 2111sys_clk_domain=system.clk_domain 2112transition_latency=100000000 2113 2114[system.l2c] 2115type=BaseCache 2116children=tags 2117addr_ranges=0:18446744073709551615 2118assoc=8 2119clk_domain=system.cpu_clk_domain 2120demand_mshr_reserve=1 2121eventq_index=0 2122forward_snoops=true 2123hit_latency=20 2124is_top_level=false 2125max_miss_count=0 2126mshrs=20 2127prefetch_on_access=false 2128prefetcher=Null 2129response_latency=20 2130sequential_access=false 2131size=4194304 2132system=system 2133tags=system.l2c.tags 2134tgts_per_mshr=12 2135two_queue=false 2136write_buffers=8 2137cpu_side=system.toL2Bus.master[0] 2138mem_side=system.membus.slave[1] 2139 2140[system.l2c.tags] 2141type=LRU 2142assoc=8 2143block_size=64 2144clk_domain=system.cpu_clk_domain 2145eventq_index=0 2146hit_latency=20 2147sequential_access=false 2148size=4194304 2149 2150[system.membus] 2151type=CoherentXBar 2152clk_domain=system.clk_domain 2153eventq_index=0 2154forward_latency=4 2155frontend_latency=3 2156response_latency=2 2157snoop_filter=Null 2158snoop_response_latency=4 2159system=system 2160use_default_range=false 2161width=16 2162master=system.physmem.port 2163slave=system.system_port system.l2c.mem_side 2164 2165[system.physmem] 2166type=DRAMCtrl 2167IDD0=0.075000 2168IDD02=0.000000 2169IDD2N=0.050000 2170IDD2N2=0.000000 2171IDD2P0=0.000000 2172IDD2P02=0.000000 2173IDD2P1=0.000000 2174IDD2P12=0.000000 2175IDD3N=0.057000 2176IDD3N2=0.000000 2177IDD3P0=0.000000 2178IDD3P02=0.000000 2179IDD3P1=0.000000 2180IDD3P12=0.000000 2181IDD4R=0.187000 2182IDD4R2=0.000000 2183IDD4W=0.165000 2184IDD4W2=0.000000 2185IDD5=0.220000 2186IDD52=0.000000 2187IDD6=0.000000 2188IDD62=0.000000 2189VDD=1.500000 2190VDD2=0.000000 2191activation_limit=4 2192addr_mapping=RoRaBaCoCh 2193bank_groups_per_rank=0 2194banks_per_rank=8 2195burst_length=8 2196channels=1 2197clk_domain=system.clk_domain 2198conf_table_reported=true 2199device_bus_width=8 2200device_rowbuffer_size=1024 2201device_size=536870912 2202devices_per_rank=8 2203dll=true 2204eventq_index=0 2205in_addr_map=true 2206max_accesses_per_row=16 2207mem_sched_policy=frfcfs 2208min_writes_per_switch=16 2209null=false 2210page_policy=open_adaptive 2211range=0:134217727 2212ranks_per_channel=2 2213read_buffer_size=32 2214static_backend_latency=10000 2215static_frontend_latency=10000 2216tBURST=5000 2217tCCD_L=0 2218tCK=1250 2219tCL=13750 2220tCS=2500 2221tRAS=35000 2222tRCD=13750 2223tREFI=7800000 2224tRFC=260000 2225tRP=13750 2226tRRD=6000 2227tRRD_L=0 2228tRTP=7500 2229tRTW=2500 2230tWR=15000 2231tWTR=7500 2232tXAW=30000 2233tXP=0 2234tXPDLL=0 2235tXS=0 2236tXSDLL=0 2237write_buffer_size=64 2238write_high_thresh_perc=85 2239write_low_thresh_perc=50 2240port=system.membus.master[0] 2241 2242[system.toL2Bus] 2243type=CoherentXBar 2244clk_domain=system.cpu_clk_domain 2245eventq_index=0 2246forward_latency=0 2247frontend_latency=1 2248response_latency=1 2249snoop_filter=Null 2250snoop_response_latency=1 2251system=system 2252use_default_range=false 2253width=32 2254master=system.l2c.cpu_side 2255slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2256 2257[system.voltage_domain] 2258type=VoltageDomain 2259eventq_index=0 2260voltage=1.000000 2261 2262