config.ini revision 10451
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu0] 47type=DerivO3CPU 48children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 49LFSTSize=1024 50LQEntries=32 51LSQCheckLoads=true 52LSQDepCheckShift=4 53SQEntries=32 54SSITSize=1024 55activity=0 56backComSize=5 57branchPred=system.cpu0.branchPred 58cachePorts=200 59checker=Null 60clk_domain=system.cpu_clk_domain 61commitToDecodeDelay=1 62commitToFetchDelay=1 63commitToIEWDelay=1 64commitToRenameDelay=1 65commitWidth=8 66cpu_id=0 67decodeToFetchDelay=1 68decodeToRenameDelay=1 69decodeWidth=8 70dispatchWidth=8 71do_checkpoint_insts=true 72do_quiesce=true 73do_statistics_insts=true 74dtb=system.cpu0.dtb 75eventq_index=0 76fetchBufferSize=64 77fetchQueueSize=32 78fetchToDecodeDelay=1 79fetchTrapLatency=1 80fetchWidth=8 81forwardComSize=5 82fuPool=system.cpu0.fuPool 83function_trace=false 84function_trace_start=0 85iewToCommitDelay=1 86iewToDecodeDelay=1 87iewToFetchDelay=1 88iewToRenameDelay=1 89interrupts=system.cpu0.interrupts 90isa=system.cpu0.isa 91issueToExecuteDelay=1 92issueWidth=8 93itb=system.cpu0.itb 94max_insts_all_threads=0 95max_insts_any_thread=0 96max_loads_all_threads=0 97max_loads_any_thread=0 98needsTSO=false 99numIQEntries=64 100numPhysCCRegs=0 101numPhysFloatRegs=256 102numPhysIntRegs=256 103numROBEntries=192 104numRobs=1 105numThreads=1 106profile=0 107progress_interval=0 108renameToDecodeDelay=1 109renameToFetchDelay=1 110renameToIEWDelay=2 111renameToROBDelay=1 112renameWidth=8 113simpoint_start_insts= 114smtCommitPolicy=RoundRobin 115smtFetchPolicy=SingleThread 116smtIQPolicy=Partitioned 117smtIQThreshold=100 118smtLSQPolicy=Partitioned 119smtLSQThreshold=100 120smtNumFetchingThreads=1 121smtROBPolicy=Partitioned 122smtROBThreshold=100 123socket_id=0 124squashWidth=8 125store_set_clear_period=250000 126switched_out=false 127system=system 128tracer=system.cpu0.tracer 129trapLatency=13 130wbWidth=8 131workload=system.cpu0.workload 132dcache_port=system.cpu0.dcache.cpu_side 133icache_port=system.cpu0.icache.cpu_side 134 135[system.cpu0.branchPred] 136type=BranchPredictor 137BTBEntries=4096 138BTBTagSize=16 139RASSize=16 140choiceCtrBits=2 141choicePredictorSize=8192 142eventq_index=0 143globalCtrBits=2 144globalPredictorSize=8192 145instShiftAmt=2 146localCtrBits=2 147localHistoryTableSize=2048 148localPredictorSize=2048 149numThreads=1 150predType=tournament 151 152[system.cpu0.dcache] 153type=BaseCache 154children=tags 155addr_ranges=0:18446744073709551615 156assoc=4 157clk_domain=system.cpu_clk_domain 158eventq_index=0 159forward_snoops=true 160hit_latency=2 161is_top_level=true 162max_miss_count=0 163mshrs=4 164prefetch_on_access=false 165prefetcher=Null 166response_latency=2 167sequential_access=false 168size=32768 169system=system 170tags=system.cpu0.dcache.tags 171tgts_per_mshr=20 172two_queue=false 173write_buffers=8 174cpu_side=system.cpu0.dcache_port 175mem_side=system.toL2Bus.slave[1] 176 177[system.cpu0.dcache.tags] 178type=LRU 179assoc=4 180block_size=64 181clk_domain=system.cpu_clk_domain 182eventq_index=0 183hit_latency=2 184sequential_access=false 185size=32768 186 187[system.cpu0.dtb] 188type=SparcTLB 189eventq_index=0 190size=64 191 192[system.cpu0.fuPool] 193type=FUPool 194children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 195FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 196eventq_index=0 197 198[system.cpu0.fuPool.FUList0] 199type=FUDesc 200children=opList 201count=6 202eventq_index=0 203opList=system.cpu0.fuPool.FUList0.opList 204 205[system.cpu0.fuPool.FUList0.opList] 206type=OpDesc 207eventq_index=0 208issueLat=1 209opClass=IntAlu 210opLat=1 211 212[system.cpu0.fuPool.FUList1] 213type=FUDesc 214children=opList0 opList1 215count=2 216eventq_index=0 217opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 218 219[system.cpu0.fuPool.FUList1.opList0] 220type=OpDesc 221eventq_index=0 222issueLat=1 223opClass=IntMult 224opLat=3 225 226[system.cpu0.fuPool.FUList1.opList1] 227type=OpDesc 228eventq_index=0 229issueLat=19 230opClass=IntDiv 231opLat=20 232 233[system.cpu0.fuPool.FUList2] 234type=FUDesc 235children=opList0 opList1 opList2 236count=4 237eventq_index=0 238opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 239 240[system.cpu0.fuPool.FUList2.opList0] 241type=OpDesc 242eventq_index=0 243issueLat=1 244opClass=FloatAdd 245opLat=2 246 247[system.cpu0.fuPool.FUList2.opList1] 248type=OpDesc 249eventq_index=0 250issueLat=1 251opClass=FloatCmp 252opLat=2 253 254[system.cpu0.fuPool.FUList2.opList2] 255type=OpDesc 256eventq_index=0 257issueLat=1 258opClass=FloatCvt 259opLat=2 260 261[system.cpu0.fuPool.FUList3] 262type=FUDesc 263children=opList0 opList1 opList2 264count=2 265eventq_index=0 266opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 267 268[system.cpu0.fuPool.FUList3.opList0] 269type=OpDesc 270eventq_index=0 271issueLat=1 272opClass=FloatMult 273opLat=4 274 275[system.cpu0.fuPool.FUList3.opList1] 276type=OpDesc 277eventq_index=0 278issueLat=12 279opClass=FloatDiv 280opLat=12 281 282[system.cpu0.fuPool.FUList3.opList2] 283type=OpDesc 284eventq_index=0 285issueLat=24 286opClass=FloatSqrt 287opLat=24 288 289[system.cpu0.fuPool.FUList4] 290type=FUDesc 291children=opList 292count=0 293eventq_index=0 294opList=system.cpu0.fuPool.FUList4.opList 295 296[system.cpu0.fuPool.FUList4.opList] 297type=OpDesc 298eventq_index=0 299issueLat=1 300opClass=MemRead 301opLat=1 302 303[system.cpu0.fuPool.FUList5] 304type=FUDesc 305children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 306count=4 307eventq_index=0 308opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 309 310[system.cpu0.fuPool.FUList5.opList00] 311type=OpDesc 312eventq_index=0 313issueLat=1 314opClass=SimdAdd 315opLat=1 316 317[system.cpu0.fuPool.FUList5.opList01] 318type=OpDesc 319eventq_index=0 320issueLat=1 321opClass=SimdAddAcc 322opLat=1 323 324[system.cpu0.fuPool.FUList5.opList02] 325type=OpDesc 326eventq_index=0 327issueLat=1 328opClass=SimdAlu 329opLat=1 330 331[system.cpu0.fuPool.FUList5.opList03] 332type=OpDesc 333eventq_index=0 334issueLat=1 335opClass=SimdCmp 336opLat=1 337 338[system.cpu0.fuPool.FUList5.opList04] 339type=OpDesc 340eventq_index=0 341issueLat=1 342opClass=SimdCvt 343opLat=1 344 345[system.cpu0.fuPool.FUList5.opList05] 346type=OpDesc 347eventq_index=0 348issueLat=1 349opClass=SimdMisc 350opLat=1 351 352[system.cpu0.fuPool.FUList5.opList06] 353type=OpDesc 354eventq_index=0 355issueLat=1 356opClass=SimdMult 357opLat=1 358 359[system.cpu0.fuPool.FUList5.opList07] 360type=OpDesc 361eventq_index=0 362issueLat=1 363opClass=SimdMultAcc 364opLat=1 365 366[system.cpu0.fuPool.FUList5.opList08] 367type=OpDesc 368eventq_index=0 369issueLat=1 370opClass=SimdShift 371opLat=1 372 373[system.cpu0.fuPool.FUList5.opList09] 374type=OpDesc 375eventq_index=0 376issueLat=1 377opClass=SimdShiftAcc 378opLat=1 379 380[system.cpu0.fuPool.FUList5.opList10] 381type=OpDesc 382eventq_index=0 383issueLat=1 384opClass=SimdSqrt 385opLat=1 386 387[system.cpu0.fuPool.FUList5.opList11] 388type=OpDesc 389eventq_index=0 390issueLat=1 391opClass=SimdFloatAdd 392opLat=1 393 394[system.cpu0.fuPool.FUList5.opList12] 395type=OpDesc 396eventq_index=0 397issueLat=1 398opClass=SimdFloatAlu 399opLat=1 400 401[system.cpu0.fuPool.FUList5.opList13] 402type=OpDesc 403eventq_index=0 404issueLat=1 405opClass=SimdFloatCmp 406opLat=1 407 408[system.cpu0.fuPool.FUList5.opList14] 409type=OpDesc 410eventq_index=0 411issueLat=1 412opClass=SimdFloatCvt 413opLat=1 414 415[system.cpu0.fuPool.FUList5.opList15] 416type=OpDesc 417eventq_index=0 418issueLat=1 419opClass=SimdFloatDiv 420opLat=1 421 422[system.cpu0.fuPool.FUList5.opList16] 423type=OpDesc 424eventq_index=0 425issueLat=1 426opClass=SimdFloatMisc 427opLat=1 428 429[system.cpu0.fuPool.FUList5.opList17] 430type=OpDesc 431eventq_index=0 432issueLat=1 433opClass=SimdFloatMult 434opLat=1 435 436[system.cpu0.fuPool.FUList5.opList18] 437type=OpDesc 438eventq_index=0 439issueLat=1 440opClass=SimdFloatMultAcc 441opLat=1 442 443[system.cpu0.fuPool.FUList5.opList19] 444type=OpDesc 445eventq_index=0 446issueLat=1 447opClass=SimdFloatSqrt 448opLat=1 449 450[system.cpu0.fuPool.FUList6] 451type=FUDesc 452children=opList 453count=0 454eventq_index=0 455opList=system.cpu0.fuPool.FUList6.opList 456 457[system.cpu0.fuPool.FUList6.opList] 458type=OpDesc 459eventq_index=0 460issueLat=1 461opClass=MemWrite 462opLat=1 463 464[system.cpu0.fuPool.FUList7] 465type=FUDesc 466children=opList0 opList1 467count=4 468eventq_index=0 469opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 470 471[system.cpu0.fuPool.FUList7.opList0] 472type=OpDesc 473eventq_index=0 474issueLat=1 475opClass=MemRead 476opLat=1 477 478[system.cpu0.fuPool.FUList7.opList1] 479type=OpDesc 480eventq_index=0 481issueLat=1 482opClass=MemWrite 483opLat=1 484 485[system.cpu0.fuPool.FUList8] 486type=FUDesc 487children=opList 488count=1 489eventq_index=0 490opList=system.cpu0.fuPool.FUList8.opList 491 492[system.cpu0.fuPool.FUList8.opList] 493type=OpDesc 494eventq_index=0 495issueLat=3 496opClass=IprAccess 497opLat=3 498 499[system.cpu0.icache] 500type=BaseCache 501children=tags 502addr_ranges=0:18446744073709551615 503assoc=1 504clk_domain=system.cpu_clk_domain 505eventq_index=0 506forward_snoops=true 507hit_latency=2 508is_top_level=true 509max_miss_count=0 510mshrs=4 511prefetch_on_access=false 512prefetcher=Null 513response_latency=2 514sequential_access=false 515size=32768 516system=system 517tags=system.cpu0.icache.tags 518tgts_per_mshr=20 519two_queue=false 520write_buffers=8 521cpu_side=system.cpu0.icache_port 522mem_side=system.toL2Bus.slave[0] 523 524[system.cpu0.icache.tags] 525type=LRU 526assoc=1 527block_size=64 528clk_domain=system.cpu_clk_domain 529eventq_index=0 530hit_latency=2 531sequential_access=false 532size=32768 533 534[system.cpu0.interrupts] 535type=SparcInterrupts 536eventq_index=0 537 538[system.cpu0.isa] 539type=SparcISA 540eventq_index=0 541 542[system.cpu0.itb] 543type=SparcTLB 544eventq_index=0 545size=64 546 547[system.cpu0.tracer] 548type=ExeTracer 549eventq_index=0 550 551[system.cpu0.workload] 552type=LiveProcess 553cmd=test_atomic 4 554cwd= 555egid=100 556env= 557errout=cerr 558euid=100 559eventq_index=0 560executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic 561gid=100 562input=cin 563max_stack_size=67108864 564output=cout 565pid=100 566ppid=99 567simpoint=0 568system=system 569uid=100 570useArchPT=false 571 572[system.cpu1] 573type=DerivO3CPU 574children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 575LFSTSize=1024 576LQEntries=32 577LSQCheckLoads=true 578LSQDepCheckShift=4 579SQEntries=32 580SSITSize=1024 581activity=0 582backComSize=5 583branchPred=system.cpu1.branchPred 584cachePorts=200 585checker=Null 586clk_domain=system.cpu_clk_domain 587commitToDecodeDelay=1 588commitToFetchDelay=1 589commitToIEWDelay=1 590commitToRenameDelay=1 591commitWidth=8 592cpu_id=1 593decodeToFetchDelay=1 594decodeToRenameDelay=1 595decodeWidth=8 596dispatchWidth=8 597do_checkpoint_insts=true 598do_quiesce=true 599do_statistics_insts=true 600dtb=system.cpu1.dtb 601eventq_index=0 602fetchBufferSize=64 603fetchQueueSize=32 604fetchToDecodeDelay=1 605fetchTrapLatency=1 606fetchWidth=8 607forwardComSize=5 608fuPool=system.cpu1.fuPool 609function_trace=false 610function_trace_start=0 611iewToCommitDelay=1 612iewToDecodeDelay=1 613iewToFetchDelay=1 614iewToRenameDelay=1 615interrupts=system.cpu1.interrupts 616isa=system.cpu1.isa 617issueToExecuteDelay=1 618issueWidth=8 619itb=system.cpu1.itb 620max_insts_all_threads=0 621max_insts_any_thread=0 622max_loads_all_threads=0 623max_loads_any_thread=0 624needsTSO=false 625numIQEntries=64 626numPhysCCRegs=0 627numPhysFloatRegs=256 628numPhysIntRegs=256 629numROBEntries=192 630numRobs=1 631numThreads=1 632profile=0 633progress_interval=0 634renameToDecodeDelay=1 635renameToFetchDelay=1 636renameToIEWDelay=2 637renameToROBDelay=1 638renameWidth=8 639simpoint_start_insts= 640smtCommitPolicy=RoundRobin 641smtFetchPolicy=SingleThread 642smtIQPolicy=Partitioned 643smtIQThreshold=100 644smtLSQPolicy=Partitioned 645smtLSQThreshold=100 646smtNumFetchingThreads=1 647smtROBPolicy=Partitioned 648smtROBThreshold=100 649socket_id=0 650squashWidth=8 651store_set_clear_period=250000 652switched_out=false 653system=system 654tracer=system.cpu1.tracer 655trapLatency=13 656wbWidth=8 657workload=system.cpu0.workload 658dcache_port=system.cpu1.dcache.cpu_side 659icache_port=system.cpu1.icache.cpu_side 660 661[system.cpu1.branchPred] 662type=BranchPredictor 663BTBEntries=4096 664BTBTagSize=16 665RASSize=16 666choiceCtrBits=2 667choicePredictorSize=8192 668eventq_index=0 669globalCtrBits=2 670globalPredictorSize=8192 671instShiftAmt=2 672localCtrBits=2 673localHistoryTableSize=2048 674localPredictorSize=2048 675numThreads=1 676predType=tournament 677 678[system.cpu1.dcache] 679type=BaseCache 680children=tags 681addr_ranges=0:18446744073709551615 682assoc=4 683clk_domain=system.cpu_clk_domain 684eventq_index=0 685forward_snoops=true 686hit_latency=2 687is_top_level=true 688max_miss_count=0 689mshrs=4 690prefetch_on_access=false 691prefetcher=Null 692response_latency=2 693sequential_access=false 694size=32768 695system=system 696tags=system.cpu1.dcache.tags 697tgts_per_mshr=20 698two_queue=false 699write_buffers=8 700cpu_side=system.cpu1.dcache_port 701mem_side=system.toL2Bus.slave[3] 702 703[system.cpu1.dcache.tags] 704type=LRU 705assoc=4 706block_size=64 707clk_domain=system.cpu_clk_domain 708eventq_index=0 709hit_latency=2 710sequential_access=false 711size=32768 712 713[system.cpu1.dtb] 714type=SparcTLB 715eventq_index=0 716size=64 717 718[system.cpu1.fuPool] 719type=FUPool 720children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 721FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 722eventq_index=0 723 724[system.cpu1.fuPool.FUList0] 725type=FUDesc 726children=opList 727count=6 728eventq_index=0 729opList=system.cpu1.fuPool.FUList0.opList 730 731[system.cpu1.fuPool.FUList0.opList] 732type=OpDesc 733eventq_index=0 734issueLat=1 735opClass=IntAlu 736opLat=1 737 738[system.cpu1.fuPool.FUList1] 739type=FUDesc 740children=opList0 opList1 741count=2 742eventq_index=0 743opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 744 745[system.cpu1.fuPool.FUList1.opList0] 746type=OpDesc 747eventq_index=0 748issueLat=1 749opClass=IntMult 750opLat=3 751 752[system.cpu1.fuPool.FUList1.opList1] 753type=OpDesc 754eventq_index=0 755issueLat=19 756opClass=IntDiv 757opLat=20 758 759[system.cpu1.fuPool.FUList2] 760type=FUDesc 761children=opList0 opList1 opList2 762count=4 763eventq_index=0 764opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 765 766[system.cpu1.fuPool.FUList2.opList0] 767type=OpDesc 768eventq_index=0 769issueLat=1 770opClass=FloatAdd 771opLat=2 772 773[system.cpu1.fuPool.FUList2.opList1] 774type=OpDesc 775eventq_index=0 776issueLat=1 777opClass=FloatCmp 778opLat=2 779 780[system.cpu1.fuPool.FUList2.opList2] 781type=OpDesc 782eventq_index=0 783issueLat=1 784opClass=FloatCvt 785opLat=2 786 787[system.cpu1.fuPool.FUList3] 788type=FUDesc 789children=opList0 opList1 opList2 790count=2 791eventq_index=0 792opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 793 794[system.cpu1.fuPool.FUList3.opList0] 795type=OpDesc 796eventq_index=0 797issueLat=1 798opClass=FloatMult 799opLat=4 800 801[system.cpu1.fuPool.FUList3.opList1] 802type=OpDesc 803eventq_index=0 804issueLat=12 805opClass=FloatDiv 806opLat=12 807 808[system.cpu1.fuPool.FUList3.opList2] 809type=OpDesc 810eventq_index=0 811issueLat=24 812opClass=FloatSqrt 813opLat=24 814 815[system.cpu1.fuPool.FUList4] 816type=FUDesc 817children=opList 818count=0 819eventq_index=0 820opList=system.cpu1.fuPool.FUList4.opList 821 822[system.cpu1.fuPool.FUList4.opList] 823type=OpDesc 824eventq_index=0 825issueLat=1 826opClass=MemRead 827opLat=1 828 829[system.cpu1.fuPool.FUList5] 830type=FUDesc 831children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 832count=4 833eventq_index=0 834opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 835 836[system.cpu1.fuPool.FUList5.opList00] 837type=OpDesc 838eventq_index=0 839issueLat=1 840opClass=SimdAdd 841opLat=1 842 843[system.cpu1.fuPool.FUList5.opList01] 844type=OpDesc 845eventq_index=0 846issueLat=1 847opClass=SimdAddAcc 848opLat=1 849 850[system.cpu1.fuPool.FUList5.opList02] 851type=OpDesc 852eventq_index=0 853issueLat=1 854opClass=SimdAlu 855opLat=1 856 857[system.cpu1.fuPool.FUList5.opList03] 858type=OpDesc 859eventq_index=0 860issueLat=1 861opClass=SimdCmp 862opLat=1 863 864[system.cpu1.fuPool.FUList5.opList04] 865type=OpDesc 866eventq_index=0 867issueLat=1 868opClass=SimdCvt 869opLat=1 870 871[system.cpu1.fuPool.FUList5.opList05] 872type=OpDesc 873eventq_index=0 874issueLat=1 875opClass=SimdMisc 876opLat=1 877 878[system.cpu1.fuPool.FUList5.opList06] 879type=OpDesc 880eventq_index=0 881issueLat=1 882opClass=SimdMult 883opLat=1 884 885[system.cpu1.fuPool.FUList5.opList07] 886type=OpDesc 887eventq_index=0 888issueLat=1 889opClass=SimdMultAcc 890opLat=1 891 892[system.cpu1.fuPool.FUList5.opList08] 893type=OpDesc 894eventq_index=0 895issueLat=1 896opClass=SimdShift 897opLat=1 898 899[system.cpu1.fuPool.FUList5.opList09] 900type=OpDesc 901eventq_index=0 902issueLat=1 903opClass=SimdShiftAcc 904opLat=1 905 906[system.cpu1.fuPool.FUList5.opList10] 907type=OpDesc 908eventq_index=0 909issueLat=1 910opClass=SimdSqrt 911opLat=1 912 913[system.cpu1.fuPool.FUList5.opList11] 914type=OpDesc 915eventq_index=0 916issueLat=1 917opClass=SimdFloatAdd 918opLat=1 919 920[system.cpu1.fuPool.FUList5.opList12] 921type=OpDesc 922eventq_index=0 923issueLat=1 924opClass=SimdFloatAlu 925opLat=1 926 927[system.cpu1.fuPool.FUList5.opList13] 928type=OpDesc 929eventq_index=0 930issueLat=1 931opClass=SimdFloatCmp 932opLat=1 933 934[system.cpu1.fuPool.FUList5.opList14] 935type=OpDesc 936eventq_index=0 937issueLat=1 938opClass=SimdFloatCvt 939opLat=1 940 941[system.cpu1.fuPool.FUList5.opList15] 942type=OpDesc 943eventq_index=0 944issueLat=1 945opClass=SimdFloatDiv 946opLat=1 947 948[system.cpu1.fuPool.FUList5.opList16] 949type=OpDesc 950eventq_index=0 951issueLat=1 952opClass=SimdFloatMisc 953opLat=1 954 955[system.cpu1.fuPool.FUList5.opList17] 956type=OpDesc 957eventq_index=0 958issueLat=1 959opClass=SimdFloatMult 960opLat=1 961 962[system.cpu1.fuPool.FUList5.opList18] 963type=OpDesc 964eventq_index=0 965issueLat=1 966opClass=SimdFloatMultAcc 967opLat=1 968 969[system.cpu1.fuPool.FUList5.opList19] 970type=OpDesc 971eventq_index=0 972issueLat=1 973opClass=SimdFloatSqrt 974opLat=1 975 976[system.cpu1.fuPool.FUList6] 977type=FUDesc 978children=opList 979count=0 980eventq_index=0 981opList=system.cpu1.fuPool.FUList6.opList 982 983[system.cpu1.fuPool.FUList6.opList] 984type=OpDesc 985eventq_index=0 986issueLat=1 987opClass=MemWrite 988opLat=1 989 990[system.cpu1.fuPool.FUList7] 991type=FUDesc 992children=opList0 opList1 993count=4 994eventq_index=0 995opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 996 997[system.cpu1.fuPool.FUList7.opList0] 998type=OpDesc 999eventq_index=0 1000issueLat=1 1001opClass=MemRead 1002opLat=1 1003 1004[system.cpu1.fuPool.FUList7.opList1] 1005type=OpDesc 1006eventq_index=0 1007issueLat=1 1008opClass=MemWrite 1009opLat=1 1010 1011[system.cpu1.fuPool.FUList8] 1012type=FUDesc 1013children=opList 1014count=1 1015eventq_index=0 1016opList=system.cpu1.fuPool.FUList8.opList 1017 1018[system.cpu1.fuPool.FUList8.opList] 1019type=OpDesc 1020eventq_index=0 1021issueLat=3 1022opClass=IprAccess 1023opLat=3 1024 1025[system.cpu1.icache] 1026type=BaseCache 1027children=tags 1028addr_ranges=0:18446744073709551615 1029assoc=1 1030clk_domain=system.cpu_clk_domain 1031eventq_index=0 1032forward_snoops=true 1033hit_latency=2 1034is_top_level=true 1035max_miss_count=0 1036mshrs=4 1037prefetch_on_access=false 1038prefetcher=Null 1039response_latency=2 1040sequential_access=false 1041size=32768 1042system=system 1043tags=system.cpu1.icache.tags 1044tgts_per_mshr=20 1045two_queue=false 1046write_buffers=8 1047cpu_side=system.cpu1.icache_port 1048mem_side=system.toL2Bus.slave[2] 1049 1050[system.cpu1.icache.tags] 1051type=LRU 1052assoc=1 1053block_size=64 1054clk_domain=system.cpu_clk_domain 1055eventq_index=0 1056hit_latency=2 1057sequential_access=false 1058size=32768 1059 1060[system.cpu1.interrupts] 1061type=SparcInterrupts 1062eventq_index=0 1063 1064[system.cpu1.isa] 1065type=SparcISA 1066eventq_index=0 1067 1068[system.cpu1.itb] 1069type=SparcTLB 1070eventq_index=0 1071size=64 1072 1073[system.cpu1.tracer] 1074type=ExeTracer 1075eventq_index=0 1076 1077[system.cpu2] 1078type=DerivO3CPU 1079children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1080LFSTSize=1024 1081LQEntries=32 1082LSQCheckLoads=true 1083LSQDepCheckShift=4 1084SQEntries=32 1085SSITSize=1024 1086activity=0 1087backComSize=5 1088branchPred=system.cpu2.branchPred 1089cachePorts=200 1090checker=Null 1091clk_domain=system.cpu_clk_domain 1092commitToDecodeDelay=1 1093commitToFetchDelay=1 1094commitToIEWDelay=1 1095commitToRenameDelay=1 1096commitWidth=8 1097cpu_id=2 1098decodeToFetchDelay=1 1099decodeToRenameDelay=1 1100decodeWidth=8 1101dispatchWidth=8 1102do_checkpoint_insts=true 1103do_quiesce=true 1104do_statistics_insts=true 1105dtb=system.cpu2.dtb 1106eventq_index=0 1107fetchBufferSize=64 1108fetchQueueSize=32 1109fetchToDecodeDelay=1 1110fetchTrapLatency=1 1111fetchWidth=8 1112forwardComSize=5 1113fuPool=system.cpu2.fuPool 1114function_trace=false 1115function_trace_start=0 1116iewToCommitDelay=1 1117iewToDecodeDelay=1 1118iewToFetchDelay=1 1119iewToRenameDelay=1 1120interrupts=system.cpu2.interrupts 1121isa=system.cpu2.isa 1122issueToExecuteDelay=1 1123issueWidth=8 1124itb=system.cpu2.itb 1125max_insts_all_threads=0 1126max_insts_any_thread=0 1127max_loads_all_threads=0 1128max_loads_any_thread=0 1129needsTSO=false 1130numIQEntries=64 1131numPhysCCRegs=0 1132numPhysFloatRegs=256 1133numPhysIntRegs=256 1134numROBEntries=192 1135numRobs=1 1136numThreads=1 1137profile=0 1138progress_interval=0 1139renameToDecodeDelay=1 1140renameToFetchDelay=1 1141renameToIEWDelay=2 1142renameToROBDelay=1 1143renameWidth=8 1144simpoint_start_insts= 1145smtCommitPolicy=RoundRobin 1146smtFetchPolicy=SingleThread 1147smtIQPolicy=Partitioned 1148smtIQThreshold=100 1149smtLSQPolicy=Partitioned 1150smtLSQThreshold=100 1151smtNumFetchingThreads=1 1152smtROBPolicy=Partitioned 1153smtROBThreshold=100 1154socket_id=0 1155squashWidth=8 1156store_set_clear_period=250000 1157switched_out=false 1158system=system 1159tracer=system.cpu2.tracer 1160trapLatency=13 1161wbWidth=8 1162workload=system.cpu0.workload 1163dcache_port=system.cpu2.dcache.cpu_side 1164icache_port=system.cpu2.icache.cpu_side 1165 1166[system.cpu2.branchPred] 1167type=BranchPredictor 1168BTBEntries=4096 1169BTBTagSize=16 1170RASSize=16 1171choiceCtrBits=2 1172choicePredictorSize=8192 1173eventq_index=0 1174globalCtrBits=2 1175globalPredictorSize=8192 1176instShiftAmt=2 1177localCtrBits=2 1178localHistoryTableSize=2048 1179localPredictorSize=2048 1180numThreads=1 1181predType=tournament 1182 1183[system.cpu2.dcache] 1184type=BaseCache 1185children=tags 1186addr_ranges=0:18446744073709551615 1187assoc=4 1188clk_domain=system.cpu_clk_domain 1189eventq_index=0 1190forward_snoops=true 1191hit_latency=2 1192is_top_level=true 1193max_miss_count=0 1194mshrs=4 1195prefetch_on_access=false 1196prefetcher=Null 1197response_latency=2 1198sequential_access=false 1199size=32768 1200system=system 1201tags=system.cpu2.dcache.tags 1202tgts_per_mshr=20 1203two_queue=false 1204write_buffers=8 1205cpu_side=system.cpu2.dcache_port 1206mem_side=system.toL2Bus.slave[5] 1207 1208[system.cpu2.dcache.tags] 1209type=LRU 1210assoc=4 1211block_size=64 1212clk_domain=system.cpu_clk_domain 1213eventq_index=0 1214hit_latency=2 1215sequential_access=false 1216size=32768 1217 1218[system.cpu2.dtb] 1219type=SparcTLB 1220eventq_index=0 1221size=64 1222 1223[system.cpu2.fuPool] 1224type=FUPool 1225children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1226FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1227eventq_index=0 1228 1229[system.cpu2.fuPool.FUList0] 1230type=FUDesc 1231children=opList 1232count=6 1233eventq_index=0 1234opList=system.cpu2.fuPool.FUList0.opList 1235 1236[system.cpu2.fuPool.FUList0.opList] 1237type=OpDesc 1238eventq_index=0 1239issueLat=1 1240opClass=IntAlu 1241opLat=1 1242 1243[system.cpu2.fuPool.FUList1] 1244type=FUDesc 1245children=opList0 opList1 1246count=2 1247eventq_index=0 1248opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1249 1250[system.cpu2.fuPool.FUList1.opList0] 1251type=OpDesc 1252eventq_index=0 1253issueLat=1 1254opClass=IntMult 1255opLat=3 1256 1257[system.cpu2.fuPool.FUList1.opList1] 1258type=OpDesc 1259eventq_index=0 1260issueLat=19 1261opClass=IntDiv 1262opLat=20 1263 1264[system.cpu2.fuPool.FUList2] 1265type=FUDesc 1266children=opList0 opList1 opList2 1267count=4 1268eventq_index=0 1269opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1270 1271[system.cpu2.fuPool.FUList2.opList0] 1272type=OpDesc 1273eventq_index=0 1274issueLat=1 1275opClass=FloatAdd 1276opLat=2 1277 1278[system.cpu2.fuPool.FUList2.opList1] 1279type=OpDesc 1280eventq_index=0 1281issueLat=1 1282opClass=FloatCmp 1283opLat=2 1284 1285[system.cpu2.fuPool.FUList2.opList2] 1286type=OpDesc 1287eventq_index=0 1288issueLat=1 1289opClass=FloatCvt 1290opLat=2 1291 1292[system.cpu2.fuPool.FUList3] 1293type=FUDesc 1294children=opList0 opList1 opList2 1295count=2 1296eventq_index=0 1297opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1298 1299[system.cpu2.fuPool.FUList3.opList0] 1300type=OpDesc 1301eventq_index=0 1302issueLat=1 1303opClass=FloatMult 1304opLat=4 1305 1306[system.cpu2.fuPool.FUList3.opList1] 1307type=OpDesc 1308eventq_index=0 1309issueLat=12 1310opClass=FloatDiv 1311opLat=12 1312 1313[system.cpu2.fuPool.FUList3.opList2] 1314type=OpDesc 1315eventq_index=0 1316issueLat=24 1317opClass=FloatSqrt 1318opLat=24 1319 1320[system.cpu2.fuPool.FUList4] 1321type=FUDesc 1322children=opList 1323count=0 1324eventq_index=0 1325opList=system.cpu2.fuPool.FUList4.opList 1326 1327[system.cpu2.fuPool.FUList4.opList] 1328type=OpDesc 1329eventq_index=0 1330issueLat=1 1331opClass=MemRead 1332opLat=1 1333 1334[system.cpu2.fuPool.FUList5] 1335type=FUDesc 1336children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1337count=4 1338eventq_index=0 1339opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1340 1341[system.cpu2.fuPool.FUList5.opList00] 1342type=OpDesc 1343eventq_index=0 1344issueLat=1 1345opClass=SimdAdd 1346opLat=1 1347 1348[system.cpu2.fuPool.FUList5.opList01] 1349type=OpDesc 1350eventq_index=0 1351issueLat=1 1352opClass=SimdAddAcc 1353opLat=1 1354 1355[system.cpu2.fuPool.FUList5.opList02] 1356type=OpDesc 1357eventq_index=0 1358issueLat=1 1359opClass=SimdAlu 1360opLat=1 1361 1362[system.cpu2.fuPool.FUList5.opList03] 1363type=OpDesc 1364eventq_index=0 1365issueLat=1 1366opClass=SimdCmp 1367opLat=1 1368 1369[system.cpu2.fuPool.FUList5.opList04] 1370type=OpDesc 1371eventq_index=0 1372issueLat=1 1373opClass=SimdCvt 1374opLat=1 1375 1376[system.cpu2.fuPool.FUList5.opList05] 1377type=OpDesc 1378eventq_index=0 1379issueLat=1 1380opClass=SimdMisc 1381opLat=1 1382 1383[system.cpu2.fuPool.FUList5.opList06] 1384type=OpDesc 1385eventq_index=0 1386issueLat=1 1387opClass=SimdMult 1388opLat=1 1389 1390[system.cpu2.fuPool.FUList5.opList07] 1391type=OpDesc 1392eventq_index=0 1393issueLat=1 1394opClass=SimdMultAcc 1395opLat=1 1396 1397[system.cpu2.fuPool.FUList5.opList08] 1398type=OpDesc 1399eventq_index=0 1400issueLat=1 1401opClass=SimdShift 1402opLat=1 1403 1404[system.cpu2.fuPool.FUList5.opList09] 1405type=OpDesc 1406eventq_index=0 1407issueLat=1 1408opClass=SimdShiftAcc 1409opLat=1 1410 1411[system.cpu2.fuPool.FUList5.opList10] 1412type=OpDesc 1413eventq_index=0 1414issueLat=1 1415opClass=SimdSqrt 1416opLat=1 1417 1418[system.cpu2.fuPool.FUList5.opList11] 1419type=OpDesc 1420eventq_index=0 1421issueLat=1 1422opClass=SimdFloatAdd 1423opLat=1 1424 1425[system.cpu2.fuPool.FUList5.opList12] 1426type=OpDesc 1427eventq_index=0 1428issueLat=1 1429opClass=SimdFloatAlu 1430opLat=1 1431 1432[system.cpu2.fuPool.FUList5.opList13] 1433type=OpDesc 1434eventq_index=0 1435issueLat=1 1436opClass=SimdFloatCmp 1437opLat=1 1438 1439[system.cpu2.fuPool.FUList5.opList14] 1440type=OpDesc 1441eventq_index=0 1442issueLat=1 1443opClass=SimdFloatCvt 1444opLat=1 1445 1446[system.cpu2.fuPool.FUList5.opList15] 1447type=OpDesc 1448eventq_index=0 1449issueLat=1 1450opClass=SimdFloatDiv 1451opLat=1 1452 1453[system.cpu2.fuPool.FUList5.opList16] 1454type=OpDesc 1455eventq_index=0 1456issueLat=1 1457opClass=SimdFloatMisc 1458opLat=1 1459 1460[system.cpu2.fuPool.FUList5.opList17] 1461type=OpDesc 1462eventq_index=0 1463issueLat=1 1464opClass=SimdFloatMult 1465opLat=1 1466 1467[system.cpu2.fuPool.FUList5.opList18] 1468type=OpDesc 1469eventq_index=0 1470issueLat=1 1471opClass=SimdFloatMultAcc 1472opLat=1 1473 1474[system.cpu2.fuPool.FUList5.opList19] 1475type=OpDesc 1476eventq_index=0 1477issueLat=1 1478opClass=SimdFloatSqrt 1479opLat=1 1480 1481[system.cpu2.fuPool.FUList6] 1482type=FUDesc 1483children=opList 1484count=0 1485eventq_index=0 1486opList=system.cpu2.fuPool.FUList6.opList 1487 1488[system.cpu2.fuPool.FUList6.opList] 1489type=OpDesc 1490eventq_index=0 1491issueLat=1 1492opClass=MemWrite 1493opLat=1 1494 1495[system.cpu2.fuPool.FUList7] 1496type=FUDesc 1497children=opList0 opList1 1498count=4 1499eventq_index=0 1500opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1501 1502[system.cpu2.fuPool.FUList7.opList0] 1503type=OpDesc 1504eventq_index=0 1505issueLat=1 1506opClass=MemRead 1507opLat=1 1508 1509[system.cpu2.fuPool.FUList7.opList1] 1510type=OpDesc 1511eventq_index=0 1512issueLat=1 1513opClass=MemWrite 1514opLat=1 1515 1516[system.cpu2.fuPool.FUList8] 1517type=FUDesc 1518children=opList 1519count=1 1520eventq_index=0 1521opList=system.cpu2.fuPool.FUList8.opList 1522 1523[system.cpu2.fuPool.FUList8.opList] 1524type=OpDesc 1525eventq_index=0 1526issueLat=3 1527opClass=IprAccess 1528opLat=3 1529 1530[system.cpu2.icache] 1531type=BaseCache 1532children=tags 1533addr_ranges=0:18446744073709551615 1534assoc=1 1535clk_domain=system.cpu_clk_domain 1536eventq_index=0 1537forward_snoops=true 1538hit_latency=2 1539is_top_level=true 1540max_miss_count=0 1541mshrs=4 1542prefetch_on_access=false 1543prefetcher=Null 1544response_latency=2 1545sequential_access=false 1546size=32768 1547system=system 1548tags=system.cpu2.icache.tags 1549tgts_per_mshr=20 1550two_queue=false 1551write_buffers=8 1552cpu_side=system.cpu2.icache_port 1553mem_side=system.toL2Bus.slave[4] 1554 1555[system.cpu2.icache.tags] 1556type=LRU 1557assoc=1 1558block_size=64 1559clk_domain=system.cpu_clk_domain 1560eventq_index=0 1561hit_latency=2 1562sequential_access=false 1563size=32768 1564 1565[system.cpu2.interrupts] 1566type=SparcInterrupts 1567eventq_index=0 1568 1569[system.cpu2.isa] 1570type=SparcISA 1571eventq_index=0 1572 1573[system.cpu2.itb] 1574type=SparcTLB 1575eventq_index=0 1576size=64 1577 1578[system.cpu2.tracer] 1579type=ExeTracer 1580eventq_index=0 1581 1582[system.cpu3] 1583type=DerivO3CPU 1584children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1585LFSTSize=1024 1586LQEntries=32 1587LSQCheckLoads=true 1588LSQDepCheckShift=4 1589SQEntries=32 1590SSITSize=1024 1591activity=0 1592backComSize=5 1593branchPred=system.cpu3.branchPred 1594cachePorts=200 1595checker=Null 1596clk_domain=system.cpu_clk_domain 1597commitToDecodeDelay=1 1598commitToFetchDelay=1 1599commitToIEWDelay=1 1600commitToRenameDelay=1 1601commitWidth=8 1602cpu_id=3 1603decodeToFetchDelay=1 1604decodeToRenameDelay=1 1605decodeWidth=8 1606dispatchWidth=8 1607do_checkpoint_insts=true 1608do_quiesce=true 1609do_statistics_insts=true 1610dtb=system.cpu3.dtb 1611eventq_index=0 1612fetchBufferSize=64 1613fetchQueueSize=32 1614fetchToDecodeDelay=1 1615fetchTrapLatency=1 1616fetchWidth=8 1617forwardComSize=5 1618fuPool=system.cpu3.fuPool 1619function_trace=false 1620function_trace_start=0 1621iewToCommitDelay=1 1622iewToDecodeDelay=1 1623iewToFetchDelay=1 1624iewToRenameDelay=1 1625interrupts=system.cpu3.interrupts 1626isa=system.cpu3.isa 1627issueToExecuteDelay=1 1628issueWidth=8 1629itb=system.cpu3.itb 1630max_insts_all_threads=0 1631max_insts_any_thread=0 1632max_loads_all_threads=0 1633max_loads_any_thread=0 1634needsTSO=false 1635numIQEntries=64 1636numPhysCCRegs=0 1637numPhysFloatRegs=256 1638numPhysIntRegs=256 1639numROBEntries=192 1640numRobs=1 1641numThreads=1 1642profile=0 1643progress_interval=0 1644renameToDecodeDelay=1 1645renameToFetchDelay=1 1646renameToIEWDelay=2 1647renameToROBDelay=1 1648renameWidth=8 1649simpoint_start_insts= 1650smtCommitPolicy=RoundRobin 1651smtFetchPolicy=SingleThread 1652smtIQPolicy=Partitioned 1653smtIQThreshold=100 1654smtLSQPolicy=Partitioned 1655smtLSQThreshold=100 1656smtNumFetchingThreads=1 1657smtROBPolicy=Partitioned 1658smtROBThreshold=100 1659socket_id=0 1660squashWidth=8 1661store_set_clear_period=250000 1662switched_out=false 1663system=system 1664tracer=system.cpu3.tracer 1665trapLatency=13 1666wbWidth=8 1667workload=system.cpu0.workload 1668dcache_port=system.cpu3.dcache.cpu_side 1669icache_port=system.cpu3.icache.cpu_side 1670 1671[system.cpu3.branchPred] 1672type=BranchPredictor 1673BTBEntries=4096 1674BTBTagSize=16 1675RASSize=16 1676choiceCtrBits=2 1677choicePredictorSize=8192 1678eventq_index=0 1679globalCtrBits=2 1680globalPredictorSize=8192 1681instShiftAmt=2 1682localCtrBits=2 1683localHistoryTableSize=2048 1684localPredictorSize=2048 1685numThreads=1 1686predType=tournament 1687 1688[system.cpu3.dcache] 1689type=BaseCache 1690children=tags 1691addr_ranges=0:18446744073709551615 1692assoc=4 1693clk_domain=system.cpu_clk_domain 1694eventq_index=0 1695forward_snoops=true 1696hit_latency=2 1697is_top_level=true 1698max_miss_count=0 1699mshrs=4 1700prefetch_on_access=false 1701prefetcher=Null 1702response_latency=2 1703sequential_access=false 1704size=32768 1705system=system 1706tags=system.cpu3.dcache.tags 1707tgts_per_mshr=20 1708two_queue=false 1709write_buffers=8 1710cpu_side=system.cpu3.dcache_port 1711mem_side=system.toL2Bus.slave[7] 1712 1713[system.cpu3.dcache.tags] 1714type=LRU 1715assoc=4 1716block_size=64 1717clk_domain=system.cpu_clk_domain 1718eventq_index=0 1719hit_latency=2 1720sequential_access=false 1721size=32768 1722 1723[system.cpu3.dtb] 1724type=SparcTLB 1725eventq_index=0 1726size=64 1727 1728[system.cpu3.fuPool] 1729type=FUPool 1730children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1731FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1732eventq_index=0 1733 1734[system.cpu3.fuPool.FUList0] 1735type=FUDesc 1736children=opList 1737count=6 1738eventq_index=0 1739opList=system.cpu3.fuPool.FUList0.opList 1740 1741[system.cpu3.fuPool.FUList0.opList] 1742type=OpDesc 1743eventq_index=0 1744issueLat=1 1745opClass=IntAlu 1746opLat=1 1747 1748[system.cpu3.fuPool.FUList1] 1749type=FUDesc 1750children=opList0 opList1 1751count=2 1752eventq_index=0 1753opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1754 1755[system.cpu3.fuPool.FUList1.opList0] 1756type=OpDesc 1757eventq_index=0 1758issueLat=1 1759opClass=IntMult 1760opLat=3 1761 1762[system.cpu3.fuPool.FUList1.opList1] 1763type=OpDesc 1764eventq_index=0 1765issueLat=19 1766opClass=IntDiv 1767opLat=20 1768 1769[system.cpu3.fuPool.FUList2] 1770type=FUDesc 1771children=opList0 opList1 opList2 1772count=4 1773eventq_index=0 1774opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1775 1776[system.cpu3.fuPool.FUList2.opList0] 1777type=OpDesc 1778eventq_index=0 1779issueLat=1 1780opClass=FloatAdd 1781opLat=2 1782 1783[system.cpu3.fuPool.FUList2.opList1] 1784type=OpDesc 1785eventq_index=0 1786issueLat=1 1787opClass=FloatCmp 1788opLat=2 1789 1790[system.cpu3.fuPool.FUList2.opList2] 1791type=OpDesc 1792eventq_index=0 1793issueLat=1 1794opClass=FloatCvt 1795opLat=2 1796 1797[system.cpu3.fuPool.FUList3] 1798type=FUDesc 1799children=opList0 opList1 opList2 1800count=2 1801eventq_index=0 1802opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1803 1804[system.cpu3.fuPool.FUList3.opList0] 1805type=OpDesc 1806eventq_index=0 1807issueLat=1 1808opClass=FloatMult 1809opLat=4 1810 1811[system.cpu3.fuPool.FUList3.opList1] 1812type=OpDesc 1813eventq_index=0 1814issueLat=12 1815opClass=FloatDiv 1816opLat=12 1817 1818[system.cpu3.fuPool.FUList3.opList2] 1819type=OpDesc 1820eventq_index=0 1821issueLat=24 1822opClass=FloatSqrt 1823opLat=24 1824 1825[system.cpu3.fuPool.FUList4] 1826type=FUDesc 1827children=opList 1828count=0 1829eventq_index=0 1830opList=system.cpu3.fuPool.FUList4.opList 1831 1832[system.cpu3.fuPool.FUList4.opList] 1833type=OpDesc 1834eventq_index=0 1835issueLat=1 1836opClass=MemRead 1837opLat=1 1838 1839[system.cpu3.fuPool.FUList5] 1840type=FUDesc 1841children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1842count=4 1843eventq_index=0 1844opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1845 1846[system.cpu3.fuPool.FUList5.opList00] 1847type=OpDesc 1848eventq_index=0 1849issueLat=1 1850opClass=SimdAdd 1851opLat=1 1852 1853[system.cpu3.fuPool.FUList5.opList01] 1854type=OpDesc 1855eventq_index=0 1856issueLat=1 1857opClass=SimdAddAcc 1858opLat=1 1859 1860[system.cpu3.fuPool.FUList5.opList02] 1861type=OpDesc 1862eventq_index=0 1863issueLat=1 1864opClass=SimdAlu 1865opLat=1 1866 1867[system.cpu3.fuPool.FUList5.opList03] 1868type=OpDesc 1869eventq_index=0 1870issueLat=1 1871opClass=SimdCmp 1872opLat=1 1873 1874[system.cpu3.fuPool.FUList5.opList04] 1875type=OpDesc 1876eventq_index=0 1877issueLat=1 1878opClass=SimdCvt 1879opLat=1 1880 1881[system.cpu3.fuPool.FUList5.opList05] 1882type=OpDesc 1883eventq_index=0 1884issueLat=1 1885opClass=SimdMisc 1886opLat=1 1887 1888[system.cpu3.fuPool.FUList5.opList06] 1889type=OpDesc 1890eventq_index=0 1891issueLat=1 1892opClass=SimdMult 1893opLat=1 1894 1895[system.cpu3.fuPool.FUList5.opList07] 1896type=OpDesc 1897eventq_index=0 1898issueLat=1 1899opClass=SimdMultAcc 1900opLat=1 1901 1902[system.cpu3.fuPool.FUList5.opList08] 1903type=OpDesc 1904eventq_index=0 1905issueLat=1 1906opClass=SimdShift 1907opLat=1 1908 1909[system.cpu3.fuPool.FUList5.opList09] 1910type=OpDesc 1911eventq_index=0 1912issueLat=1 1913opClass=SimdShiftAcc 1914opLat=1 1915 1916[system.cpu3.fuPool.FUList5.opList10] 1917type=OpDesc 1918eventq_index=0 1919issueLat=1 1920opClass=SimdSqrt 1921opLat=1 1922 1923[system.cpu3.fuPool.FUList5.opList11] 1924type=OpDesc 1925eventq_index=0 1926issueLat=1 1927opClass=SimdFloatAdd 1928opLat=1 1929 1930[system.cpu3.fuPool.FUList5.opList12] 1931type=OpDesc 1932eventq_index=0 1933issueLat=1 1934opClass=SimdFloatAlu 1935opLat=1 1936 1937[system.cpu3.fuPool.FUList5.opList13] 1938type=OpDesc 1939eventq_index=0 1940issueLat=1 1941opClass=SimdFloatCmp 1942opLat=1 1943 1944[system.cpu3.fuPool.FUList5.opList14] 1945type=OpDesc 1946eventq_index=0 1947issueLat=1 1948opClass=SimdFloatCvt 1949opLat=1 1950 1951[system.cpu3.fuPool.FUList5.opList15] 1952type=OpDesc 1953eventq_index=0 1954issueLat=1 1955opClass=SimdFloatDiv 1956opLat=1 1957 1958[system.cpu3.fuPool.FUList5.opList16] 1959type=OpDesc 1960eventq_index=0 1961issueLat=1 1962opClass=SimdFloatMisc 1963opLat=1 1964 1965[system.cpu3.fuPool.FUList5.opList17] 1966type=OpDesc 1967eventq_index=0 1968issueLat=1 1969opClass=SimdFloatMult 1970opLat=1 1971 1972[system.cpu3.fuPool.FUList5.opList18] 1973type=OpDesc 1974eventq_index=0 1975issueLat=1 1976opClass=SimdFloatMultAcc 1977opLat=1 1978 1979[system.cpu3.fuPool.FUList5.opList19] 1980type=OpDesc 1981eventq_index=0 1982issueLat=1 1983opClass=SimdFloatSqrt 1984opLat=1 1985 1986[system.cpu3.fuPool.FUList6] 1987type=FUDesc 1988children=opList 1989count=0 1990eventq_index=0 1991opList=system.cpu3.fuPool.FUList6.opList 1992 1993[system.cpu3.fuPool.FUList6.opList] 1994type=OpDesc 1995eventq_index=0 1996issueLat=1 1997opClass=MemWrite 1998opLat=1 1999 2000[system.cpu3.fuPool.FUList7] 2001type=FUDesc 2002children=opList0 opList1 2003count=4 2004eventq_index=0 2005opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 2006 2007[system.cpu3.fuPool.FUList7.opList0] 2008type=OpDesc 2009eventq_index=0 2010issueLat=1 2011opClass=MemRead 2012opLat=1 2013 2014[system.cpu3.fuPool.FUList7.opList1] 2015type=OpDesc 2016eventq_index=0 2017issueLat=1 2018opClass=MemWrite 2019opLat=1 2020 2021[system.cpu3.fuPool.FUList8] 2022type=FUDesc 2023children=opList 2024count=1 2025eventq_index=0 2026opList=system.cpu3.fuPool.FUList8.opList 2027 2028[system.cpu3.fuPool.FUList8.opList] 2029type=OpDesc 2030eventq_index=0 2031issueLat=3 2032opClass=IprAccess 2033opLat=3 2034 2035[system.cpu3.icache] 2036type=BaseCache 2037children=tags 2038addr_ranges=0:18446744073709551615 2039assoc=1 2040clk_domain=system.cpu_clk_domain 2041eventq_index=0 2042forward_snoops=true 2043hit_latency=2 2044is_top_level=true 2045max_miss_count=0 2046mshrs=4 2047prefetch_on_access=false 2048prefetcher=Null 2049response_latency=2 2050sequential_access=false 2051size=32768 2052system=system 2053tags=system.cpu3.icache.tags 2054tgts_per_mshr=20 2055two_queue=false 2056write_buffers=8 2057cpu_side=system.cpu3.icache_port 2058mem_side=system.toL2Bus.slave[6] 2059 2060[system.cpu3.icache.tags] 2061type=LRU 2062assoc=1 2063block_size=64 2064clk_domain=system.cpu_clk_domain 2065eventq_index=0 2066hit_latency=2 2067sequential_access=false 2068size=32768 2069 2070[system.cpu3.interrupts] 2071type=SparcInterrupts 2072eventq_index=0 2073 2074[system.cpu3.isa] 2075type=SparcISA 2076eventq_index=0 2077 2078[system.cpu3.itb] 2079type=SparcTLB 2080eventq_index=0 2081size=64 2082 2083[system.cpu3.tracer] 2084type=ExeTracer 2085eventq_index=0 2086 2087[system.cpu_clk_domain] 2088type=SrcClockDomain 2089clock=500 2090domain_id=-1 2091eventq_index=0 2092init_perf_level=0 2093voltage_domain=system.voltage_domain 2094 2095[system.dvfs_handler] 2096type=DVFSHandler 2097domains= 2098enable=false 2099eventq_index=0 2100sys_clk_domain=system.clk_domain 2101transition_latency=100000000 2102 2103[system.l2c] 2104type=BaseCache 2105children=tags 2106addr_ranges=0:18446744073709551615 2107assoc=8 2108clk_domain=system.cpu_clk_domain 2109eventq_index=0 2110forward_snoops=true 2111hit_latency=20 2112is_top_level=false 2113max_miss_count=0 2114mshrs=20 2115prefetch_on_access=false 2116prefetcher=Null 2117response_latency=20 2118sequential_access=false 2119size=4194304 2120system=system 2121tags=system.l2c.tags 2122tgts_per_mshr=12 2123two_queue=false 2124write_buffers=8 2125cpu_side=system.toL2Bus.master[0] 2126mem_side=system.membus.slave[1] 2127 2128[system.l2c.tags] 2129type=LRU 2130assoc=8 2131block_size=64 2132clk_domain=system.cpu_clk_domain 2133eventq_index=0 2134hit_latency=20 2135sequential_access=false 2136size=4194304 2137 2138[system.membus] 2139type=CoherentXBar 2140clk_domain=system.clk_domain 2141eventq_index=0 2142header_cycles=1 2143snoop_filter=Null 2144system=system 2145use_default_range=false 2146width=8 2147master=system.physmem.port 2148slave=system.system_port system.l2c.mem_side 2149 2150[system.physmem] 2151type=DRAMCtrl 2152IDD0=0.075000 2153IDD02=0.000000 2154IDD2N=0.050000 2155IDD2N2=0.000000 2156IDD2P0=0.000000 2157IDD2P02=0.000000 2158IDD2P1=0.000000 2159IDD2P12=0.000000 2160IDD3N=0.057000 2161IDD3N2=0.000000 2162IDD3P0=0.000000 2163IDD3P02=0.000000 2164IDD3P1=0.000000 2165IDD3P12=0.000000 2166IDD4R=0.187000 2167IDD4R2=0.000000 2168IDD4W=0.165000 2169IDD4W2=0.000000 2170IDD5=0.220000 2171IDD52=0.000000 2172IDD6=0.000000 2173IDD62=0.000000 2174VDD=1.500000 2175VDD2=0.000000 2176activation_limit=4 2177addr_mapping=RoRaBaChCo 2178bank_groups_per_rank=0 2179banks_per_rank=8 2180burst_length=8 2181channels=1 2182clk_domain=system.clk_domain 2183conf_table_reported=true 2184device_bus_width=8 2185device_rowbuffer_size=1024 2186devices_per_rank=8 2187dll=true 2188eventq_index=0 2189in_addr_map=true 2190max_accesses_per_row=16 2191mem_sched_policy=frfcfs 2192min_writes_per_switch=16 2193null=false 2194page_policy=open_adaptive 2195range=0:134217727 2196ranks_per_channel=2 2197read_buffer_size=32 2198static_backend_latency=10000 2199static_frontend_latency=10000 2200tBURST=5000 2201tCCD_L=0 2202tCK=1250 2203tCL=13750 2204tCS=2500 2205tRAS=35000 2206tRCD=13750 2207tREFI=7800000 2208tRFC=260000 2209tRP=13750 2210tRRD=6000 2211tRRD_L=0 2212tRTP=7500 2213tRTW=2500 2214tWR=15000 2215tWTR=7500 2216tXAW=30000 2217tXP=0 2218tXPDLL=0 2219tXS=0 2220tXSDLL=0 2221write_buffer_size=64 2222write_high_thresh_perc=85 2223write_low_thresh_perc=50 2224port=system.membus.master[0] 2225 2226[system.toL2Bus] 2227type=CoherentXBar 2228clk_domain=system.cpu_clk_domain 2229eventq_index=0 2230header_cycles=1 2231snoop_filter=Null 2232system=system 2233use_default_range=false 2234width=8 2235master=system.l2c.cpu_side 2236slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2237 2238[system.voltage_domain] 2239type=VoltageDomain 2240eventq_index=0 2241voltage=1.000000 2242 2243