config.ini revision 10315
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu0] 47type=DerivO3CPU 48children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 49LFSTSize=1024 50LQEntries=32 51LSQCheckLoads=true 52LSQDepCheckShift=4 53SQEntries=32 54SSITSize=1024 55activity=0 56backComSize=5 57branchPred=system.cpu0.branchPred 58cachePorts=200 59checker=Null 60clk_domain=system.cpu_clk_domain 61commitToDecodeDelay=1 62commitToFetchDelay=1 63commitToIEWDelay=1 64commitToRenameDelay=1 65commitWidth=8 66cpu_id=0 67decodeToFetchDelay=1 68decodeToRenameDelay=1 69decodeWidth=8 70dispatchWidth=8 71do_checkpoint_insts=true 72do_quiesce=true 73do_statistics_insts=true 74dtb=system.cpu0.dtb 75eventq_index=0 76fetchBufferSize=64 77fetchToDecodeDelay=1 78fetchTrapLatency=1 79fetchWidth=8 80forwardComSize=5 81fuPool=system.cpu0.fuPool 82function_trace=false 83function_trace_start=0 84iewToCommitDelay=1 85iewToDecodeDelay=1 86iewToFetchDelay=1 87iewToRenameDelay=1 88interrupts=system.cpu0.interrupts 89isa=system.cpu0.isa 90issueToExecuteDelay=1 91issueWidth=8 92itb=system.cpu0.itb 93max_insts_all_threads=0 94max_insts_any_thread=0 95max_loads_all_threads=0 96max_loads_any_thread=0 97needsTSO=false 98numIQEntries=64 99numPhysCCRegs=0 100numPhysFloatRegs=256 101numPhysIntRegs=256 102numROBEntries=192 103numRobs=1 104numThreads=1 105profile=0 106progress_interval=0 107renameToDecodeDelay=1 108renameToFetchDelay=1 109renameToIEWDelay=2 110renameToROBDelay=1 111renameWidth=8 112simpoint_start_insts= 113smtCommitPolicy=RoundRobin 114smtFetchPolicy=SingleThread 115smtIQPolicy=Partitioned 116smtIQThreshold=100 117smtLSQPolicy=Partitioned 118smtLSQThreshold=100 119smtNumFetchingThreads=1 120smtROBPolicy=Partitioned 121smtROBThreshold=100 122socket_id=0 123squashWidth=8 124store_set_clear_period=250000 125switched_out=false 126system=system 127tracer=system.cpu0.tracer 128trapLatency=13 129wbDepth=1 130wbWidth=8 131workload=system.cpu0.workload 132dcache_port=system.cpu0.dcache.cpu_side 133icache_port=system.cpu0.icache.cpu_side 134 135[system.cpu0.branchPred] 136type=BranchPredictor 137BTBEntries=4096 138BTBTagSize=16 139RASSize=16 140choiceCtrBits=2 141choicePredictorSize=8192 142eventq_index=0 143globalCtrBits=2 144globalPredictorSize=8192 145instShiftAmt=2 146localCtrBits=2 147localHistoryTableSize=2048 148localPredictorSize=2048 149numThreads=1 150predType=tournament 151 152[system.cpu0.dcache] 153type=BaseCache 154children=tags 155addr_ranges=0:18446744073709551615 156assoc=4 157clk_domain=system.cpu_clk_domain 158eventq_index=0 159forward_snoops=true 160hit_latency=2 161is_top_level=true 162max_miss_count=0 163mshrs=4 164prefetch_on_access=false 165prefetcher=Null 166response_latency=2 167sequential_access=false 168size=32768 169system=system 170tags=system.cpu0.dcache.tags 171tgts_per_mshr=20 172two_queue=false 173write_buffers=8 174cpu_side=system.cpu0.dcache_port 175mem_side=system.toL2Bus.slave[1] 176 177[system.cpu0.dcache.tags] 178type=LRU 179assoc=4 180block_size=64 181clk_domain=system.cpu_clk_domain 182eventq_index=0 183hit_latency=2 184sequential_access=false 185size=32768 186 187[system.cpu0.dtb] 188type=SparcTLB 189eventq_index=0 190size=64 191 192[system.cpu0.fuPool] 193type=FUPool 194children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 195FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 196eventq_index=0 197 198[system.cpu0.fuPool.FUList0] 199type=FUDesc 200children=opList 201count=6 202eventq_index=0 203opList=system.cpu0.fuPool.FUList0.opList 204 205[system.cpu0.fuPool.FUList0.opList] 206type=OpDesc 207eventq_index=0 208issueLat=1 209opClass=IntAlu 210opLat=1 211 212[system.cpu0.fuPool.FUList1] 213type=FUDesc 214children=opList0 opList1 215count=2 216eventq_index=0 217opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 218 219[system.cpu0.fuPool.FUList1.opList0] 220type=OpDesc 221eventq_index=0 222issueLat=1 223opClass=IntMult 224opLat=3 225 226[system.cpu0.fuPool.FUList1.opList1] 227type=OpDesc 228eventq_index=0 229issueLat=19 230opClass=IntDiv 231opLat=20 232 233[system.cpu0.fuPool.FUList2] 234type=FUDesc 235children=opList0 opList1 opList2 236count=4 237eventq_index=0 238opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 239 240[system.cpu0.fuPool.FUList2.opList0] 241type=OpDesc 242eventq_index=0 243issueLat=1 244opClass=FloatAdd 245opLat=2 246 247[system.cpu0.fuPool.FUList2.opList1] 248type=OpDesc 249eventq_index=0 250issueLat=1 251opClass=FloatCmp 252opLat=2 253 254[system.cpu0.fuPool.FUList2.opList2] 255type=OpDesc 256eventq_index=0 257issueLat=1 258opClass=FloatCvt 259opLat=2 260 261[system.cpu0.fuPool.FUList3] 262type=FUDesc 263children=opList0 opList1 opList2 264count=2 265eventq_index=0 266opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 267 268[system.cpu0.fuPool.FUList3.opList0] 269type=OpDesc 270eventq_index=0 271issueLat=1 272opClass=FloatMult 273opLat=4 274 275[system.cpu0.fuPool.FUList3.opList1] 276type=OpDesc 277eventq_index=0 278issueLat=12 279opClass=FloatDiv 280opLat=12 281 282[system.cpu0.fuPool.FUList3.opList2] 283type=OpDesc 284eventq_index=0 285issueLat=24 286opClass=FloatSqrt 287opLat=24 288 289[system.cpu0.fuPool.FUList4] 290type=FUDesc 291children=opList 292count=0 293eventq_index=0 294opList=system.cpu0.fuPool.FUList4.opList 295 296[system.cpu0.fuPool.FUList4.opList] 297type=OpDesc 298eventq_index=0 299issueLat=1 300opClass=MemRead 301opLat=1 302 303[system.cpu0.fuPool.FUList5] 304type=FUDesc 305children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 306count=4 307eventq_index=0 308opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 309 310[system.cpu0.fuPool.FUList5.opList00] 311type=OpDesc 312eventq_index=0 313issueLat=1 314opClass=SimdAdd 315opLat=1 316 317[system.cpu0.fuPool.FUList5.opList01] 318type=OpDesc 319eventq_index=0 320issueLat=1 321opClass=SimdAddAcc 322opLat=1 323 324[system.cpu0.fuPool.FUList5.opList02] 325type=OpDesc 326eventq_index=0 327issueLat=1 328opClass=SimdAlu 329opLat=1 330 331[system.cpu0.fuPool.FUList5.opList03] 332type=OpDesc 333eventq_index=0 334issueLat=1 335opClass=SimdCmp 336opLat=1 337 338[system.cpu0.fuPool.FUList5.opList04] 339type=OpDesc 340eventq_index=0 341issueLat=1 342opClass=SimdCvt 343opLat=1 344 345[system.cpu0.fuPool.FUList5.opList05] 346type=OpDesc 347eventq_index=0 348issueLat=1 349opClass=SimdMisc 350opLat=1 351 352[system.cpu0.fuPool.FUList5.opList06] 353type=OpDesc 354eventq_index=0 355issueLat=1 356opClass=SimdMult 357opLat=1 358 359[system.cpu0.fuPool.FUList5.opList07] 360type=OpDesc 361eventq_index=0 362issueLat=1 363opClass=SimdMultAcc 364opLat=1 365 366[system.cpu0.fuPool.FUList5.opList08] 367type=OpDesc 368eventq_index=0 369issueLat=1 370opClass=SimdShift 371opLat=1 372 373[system.cpu0.fuPool.FUList5.opList09] 374type=OpDesc 375eventq_index=0 376issueLat=1 377opClass=SimdShiftAcc 378opLat=1 379 380[system.cpu0.fuPool.FUList5.opList10] 381type=OpDesc 382eventq_index=0 383issueLat=1 384opClass=SimdSqrt 385opLat=1 386 387[system.cpu0.fuPool.FUList5.opList11] 388type=OpDesc 389eventq_index=0 390issueLat=1 391opClass=SimdFloatAdd 392opLat=1 393 394[system.cpu0.fuPool.FUList5.opList12] 395type=OpDesc 396eventq_index=0 397issueLat=1 398opClass=SimdFloatAlu 399opLat=1 400 401[system.cpu0.fuPool.FUList5.opList13] 402type=OpDesc 403eventq_index=0 404issueLat=1 405opClass=SimdFloatCmp 406opLat=1 407 408[system.cpu0.fuPool.FUList5.opList14] 409type=OpDesc 410eventq_index=0 411issueLat=1 412opClass=SimdFloatCvt 413opLat=1 414 415[system.cpu0.fuPool.FUList5.opList15] 416type=OpDesc 417eventq_index=0 418issueLat=1 419opClass=SimdFloatDiv 420opLat=1 421 422[system.cpu0.fuPool.FUList5.opList16] 423type=OpDesc 424eventq_index=0 425issueLat=1 426opClass=SimdFloatMisc 427opLat=1 428 429[system.cpu0.fuPool.FUList5.opList17] 430type=OpDesc 431eventq_index=0 432issueLat=1 433opClass=SimdFloatMult 434opLat=1 435 436[system.cpu0.fuPool.FUList5.opList18] 437type=OpDesc 438eventq_index=0 439issueLat=1 440opClass=SimdFloatMultAcc 441opLat=1 442 443[system.cpu0.fuPool.FUList5.opList19] 444type=OpDesc 445eventq_index=0 446issueLat=1 447opClass=SimdFloatSqrt 448opLat=1 449 450[system.cpu0.fuPool.FUList6] 451type=FUDesc 452children=opList 453count=0 454eventq_index=0 455opList=system.cpu0.fuPool.FUList6.opList 456 457[system.cpu0.fuPool.FUList6.opList] 458type=OpDesc 459eventq_index=0 460issueLat=1 461opClass=MemWrite 462opLat=1 463 464[system.cpu0.fuPool.FUList7] 465type=FUDesc 466children=opList0 opList1 467count=4 468eventq_index=0 469opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 470 471[system.cpu0.fuPool.FUList7.opList0] 472type=OpDesc 473eventq_index=0 474issueLat=1 475opClass=MemRead 476opLat=1 477 478[system.cpu0.fuPool.FUList7.opList1] 479type=OpDesc 480eventq_index=0 481issueLat=1 482opClass=MemWrite 483opLat=1 484 485[system.cpu0.fuPool.FUList8] 486type=FUDesc 487children=opList 488count=1 489eventq_index=0 490opList=system.cpu0.fuPool.FUList8.opList 491 492[system.cpu0.fuPool.FUList8.opList] 493type=OpDesc 494eventq_index=0 495issueLat=3 496opClass=IprAccess 497opLat=3 498 499[system.cpu0.icache] 500type=BaseCache 501children=tags 502addr_ranges=0:18446744073709551615 503assoc=1 504clk_domain=system.cpu_clk_domain 505eventq_index=0 506forward_snoops=true 507hit_latency=2 508is_top_level=true 509max_miss_count=0 510mshrs=4 511prefetch_on_access=false 512prefetcher=Null 513response_latency=2 514sequential_access=false 515size=32768 516system=system 517tags=system.cpu0.icache.tags 518tgts_per_mshr=20 519two_queue=false 520write_buffers=8 521cpu_side=system.cpu0.icache_port 522mem_side=system.toL2Bus.slave[0] 523 524[system.cpu0.icache.tags] 525type=LRU 526assoc=1 527block_size=64 528clk_domain=system.cpu_clk_domain 529eventq_index=0 530hit_latency=2 531sequential_access=false 532size=32768 533 534[system.cpu0.interrupts] 535type=SparcInterrupts 536eventq_index=0 537 538[system.cpu0.isa] 539type=SparcISA 540eventq_index=0 541 542[system.cpu0.itb] 543type=SparcTLB 544eventq_index=0 545size=64 546 547[system.cpu0.tracer] 548type=ExeTracer 549eventq_index=0 550 551[system.cpu0.workload] 552type=LiveProcess 553cmd=test_atomic 4 554cwd= 555egid=100 556env= 557errout=cerr 558euid=100 559eventq_index=0 560executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic 561gid=100 562input=cin 563max_stack_size=67108864 564output=cout 565pid=100 566ppid=99 567simpoint=0 568system=system 569uid=100 570 571[system.cpu1] 572type=DerivO3CPU 573children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 574LFSTSize=1024 575LQEntries=32 576LSQCheckLoads=true 577LSQDepCheckShift=4 578SQEntries=32 579SSITSize=1024 580activity=0 581backComSize=5 582branchPred=system.cpu1.branchPred 583cachePorts=200 584checker=Null 585clk_domain=system.cpu_clk_domain 586commitToDecodeDelay=1 587commitToFetchDelay=1 588commitToIEWDelay=1 589commitToRenameDelay=1 590commitWidth=8 591cpu_id=1 592decodeToFetchDelay=1 593decodeToRenameDelay=1 594decodeWidth=8 595dispatchWidth=8 596do_checkpoint_insts=true 597do_quiesce=true 598do_statistics_insts=true 599dtb=system.cpu1.dtb 600eventq_index=0 601fetchBufferSize=64 602fetchToDecodeDelay=1 603fetchTrapLatency=1 604fetchWidth=8 605forwardComSize=5 606fuPool=system.cpu1.fuPool 607function_trace=false 608function_trace_start=0 609iewToCommitDelay=1 610iewToDecodeDelay=1 611iewToFetchDelay=1 612iewToRenameDelay=1 613interrupts=system.cpu1.interrupts 614isa=system.cpu1.isa 615issueToExecuteDelay=1 616issueWidth=8 617itb=system.cpu1.itb 618max_insts_all_threads=0 619max_insts_any_thread=0 620max_loads_all_threads=0 621max_loads_any_thread=0 622needsTSO=false 623numIQEntries=64 624numPhysCCRegs=0 625numPhysFloatRegs=256 626numPhysIntRegs=256 627numROBEntries=192 628numRobs=1 629numThreads=1 630profile=0 631progress_interval=0 632renameToDecodeDelay=1 633renameToFetchDelay=1 634renameToIEWDelay=2 635renameToROBDelay=1 636renameWidth=8 637simpoint_start_insts= 638smtCommitPolicy=RoundRobin 639smtFetchPolicy=SingleThread 640smtIQPolicy=Partitioned 641smtIQThreshold=100 642smtLSQPolicy=Partitioned 643smtLSQThreshold=100 644smtNumFetchingThreads=1 645smtROBPolicy=Partitioned 646smtROBThreshold=100 647socket_id=0 648squashWidth=8 649store_set_clear_period=250000 650switched_out=false 651system=system 652tracer=system.cpu1.tracer 653trapLatency=13 654wbDepth=1 655wbWidth=8 656workload=system.cpu0.workload 657dcache_port=system.cpu1.dcache.cpu_side 658icache_port=system.cpu1.icache.cpu_side 659 660[system.cpu1.branchPred] 661type=BranchPredictor 662BTBEntries=4096 663BTBTagSize=16 664RASSize=16 665choiceCtrBits=2 666choicePredictorSize=8192 667eventq_index=0 668globalCtrBits=2 669globalPredictorSize=8192 670instShiftAmt=2 671localCtrBits=2 672localHistoryTableSize=2048 673localPredictorSize=2048 674numThreads=1 675predType=tournament 676 677[system.cpu1.dcache] 678type=BaseCache 679children=tags 680addr_ranges=0:18446744073709551615 681assoc=4 682clk_domain=system.cpu_clk_domain 683eventq_index=0 684forward_snoops=true 685hit_latency=2 686is_top_level=true 687max_miss_count=0 688mshrs=4 689prefetch_on_access=false 690prefetcher=Null 691response_latency=2 692sequential_access=false 693size=32768 694system=system 695tags=system.cpu1.dcache.tags 696tgts_per_mshr=20 697two_queue=false 698write_buffers=8 699cpu_side=system.cpu1.dcache_port 700mem_side=system.toL2Bus.slave[3] 701 702[system.cpu1.dcache.tags] 703type=LRU 704assoc=4 705block_size=64 706clk_domain=system.cpu_clk_domain 707eventq_index=0 708hit_latency=2 709sequential_access=false 710size=32768 711 712[system.cpu1.dtb] 713type=SparcTLB 714eventq_index=0 715size=64 716 717[system.cpu1.fuPool] 718type=FUPool 719children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 720FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 721eventq_index=0 722 723[system.cpu1.fuPool.FUList0] 724type=FUDesc 725children=opList 726count=6 727eventq_index=0 728opList=system.cpu1.fuPool.FUList0.opList 729 730[system.cpu1.fuPool.FUList0.opList] 731type=OpDesc 732eventq_index=0 733issueLat=1 734opClass=IntAlu 735opLat=1 736 737[system.cpu1.fuPool.FUList1] 738type=FUDesc 739children=opList0 opList1 740count=2 741eventq_index=0 742opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 743 744[system.cpu1.fuPool.FUList1.opList0] 745type=OpDesc 746eventq_index=0 747issueLat=1 748opClass=IntMult 749opLat=3 750 751[system.cpu1.fuPool.FUList1.opList1] 752type=OpDesc 753eventq_index=0 754issueLat=19 755opClass=IntDiv 756opLat=20 757 758[system.cpu1.fuPool.FUList2] 759type=FUDesc 760children=opList0 opList1 opList2 761count=4 762eventq_index=0 763opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 764 765[system.cpu1.fuPool.FUList2.opList0] 766type=OpDesc 767eventq_index=0 768issueLat=1 769opClass=FloatAdd 770opLat=2 771 772[system.cpu1.fuPool.FUList2.opList1] 773type=OpDesc 774eventq_index=0 775issueLat=1 776opClass=FloatCmp 777opLat=2 778 779[system.cpu1.fuPool.FUList2.opList2] 780type=OpDesc 781eventq_index=0 782issueLat=1 783opClass=FloatCvt 784opLat=2 785 786[system.cpu1.fuPool.FUList3] 787type=FUDesc 788children=opList0 opList1 opList2 789count=2 790eventq_index=0 791opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 792 793[system.cpu1.fuPool.FUList3.opList0] 794type=OpDesc 795eventq_index=0 796issueLat=1 797opClass=FloatMult 798opLat=4 799 800[system.cpu1.fuPool.FUList3.opList1] 801type=OpDesc 802eventq_index=0 803issueLat=12 804opClass=FloatDiv 805opLat=12 806 807[system.cpu1.fuPool.FUList3.opList2] 808type=OpDesc 809eventq_index=0 810issueLat=24 811opClass=FloatSqrt 812opLat=24 813 814[system.cpu1.fuPool.FUList4] 815type=FUDesc 816children=opList 817count=0 818eventq_index=0 819opList=system.cpu1.fuPool.FUList4.opList 820 821[system.cpu1.fuPool.FUList4.opList] 822type=OpDesc 823eventq_index=0 824issueLat=1 825opClass=MemRead 826opLat=1 827 828[system.cpu1.fuPool.FUList5] 829type=FUDesc 830children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 831count=4 832eventq_index=0 833opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 834 835[system.cpu1.fuPool.FUList5.opList00] 836type=OpDesc 837eventq_index=0 838issueLat=1 839opClass=SimdAdd 840opLat=1 841 842[system.cpu1.fuPool.FUList5.opList01] 843type=OpDesc 844eventq_index=0 845issueLat=1 846opClass=SimdAddAcc 847opLat=1 848 849[system.cpu1.fuPool.FUList5.opList02] 850type=OpDesc 851eventq_index=0 852issueLat=1 853opClass=SimdAlu 854opLat=1 855 856[system.cpu1.fuPool.FUList5.opList03] 857type=OpDesc 858eventq_index=0 859issueLat=1 860opClass=SimdCmp 861opLat=1 862 863[system.cpu1.fuPool.FUList5.opList04] 864type=OpDesc 865eventq_index=0 866issueLat=1 867opClass=SimdCvt 868opLat=1 869 870[system.cpu1.fuPool.FUList5.opList05] 871type=OpDesc 872eventq_index=0 873issueLat=1 874opClass=SimdMisc 875opLat=1 876 877[system.cpu1.fuPool.FUList5.opList06] 878type=OpDesc 879eventq_index=0 880issueLat=1 881opClass=SimdMult 882opLat=1 883 884[system.cpu1.fuPool.FUList5.opList07] 885type=OpDesc 886eventq_index=0 887issueLat=1 888opClass=SimdMultAcc 889opLat=1 890 891[system.cpu1.fuPool.FUList5.opList08] 892type=OpDesc 893eventq_index=0 894issueLat=1 895opClass=SimdShift 896opLat=1 897 898[system.cpu1.fuPool.FUList5.opList09] 899type=OpDesc 900eventq_index=0 901issueLat=1 902opClass=SimdShiftAcc 903opLat=1 904 905[system.cpu1.fuPool.FUList5.opList10] 906type=OpDesc 907eventq_index=0 908issueLat=1 909opClass=SimdSqrt 910opLat=1 911 912[system.cpu1.fuPool.FUList5.opList11] 913type=OpDesc 914eventq_index=0 915issueLat=1 916opClass=SimdFloatAdd 917opLat=1 918 919[system.cpu1.fuPool.FUList5.opList12] 920type=OpDesc 921eventq_index=0 922issueLat=1 923opClass=SimdFloatAlu 924opLat=1 925 926[system.cpu1.fuPool.FUList5.opList13] 927type=OpDesc 928eventq_index=0 929issueLat=1 930opClass=SimdFloatCmp 931opLat=1 932 933[system.cpu1.fuPool.FUList5.opList14] 934type=OpDesc 935eventq_index=0 936issueLat=1 937opClass=SimdFloatCvt 938opLat=1 939 940[system.cpu1.fuPool.FUList5.opList15] 941type=OpDesc 942eventq_index=0 943issueLat=1 944opClass=SimdFloatDiv 945opLat=1 946 947[system.cpu1.fuPool.FUList5.opList16] 948type=OpDesc 949eventq_index=0 950issueLat=1 951opClass=SimdFloatMisc 952opLat=1 953 954[system.cpu1.fuPool.FUList5.opList17] 955type=OpDesc 956eventq_index=0 957issueLat=1 958opClass=SimdFloatMult 959opLat=1 960 961[system.cpu1.fuPool.FUList5.opList18] 962type=OpDesc 963eventq_index=0 964issueLat=1 965opClass=SimdFloatMultAcc 966opLat=1 967 968[system.cpu1.fuPool.FUList5.opList19] 969type=OpDesc 970eventq_index=0 971issueLat=1 972opClass=SimdFloatSqrt 973opLat=1 974 975[system.cpu1.fuPool.FUList6] 976type=FUDesc 977children=opList 978count=0 979eventq_index=0 980opList=system.cpu1.fuPool.FUList6.opList 981 982[system.cpu1.fuPool.FUList6.opList] 983type=OpDesc 984eventq_index=0 985issueLat=1 986opClass=MemWrite 987opLat=1 988 989[system.cpu1.fuPool.FUList7] 990type=FUDesc 991children=opList0 opList1 992count=4 993eventq_index=0 994opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 995 996[system.cpu1.fuPool.FUList7.opList0] 997type=OpDesc 998eventq_index=0 999issueLat=1 1000opClass=MemRead 1001opLat=1 1002 1003[system.cpu1.fuPool.FUList7.opList1] 1004type=OpDesc 1005eventq_index=0 1006issueLat=1 1007opClass=MemWrite 1008opLat=1 1009 1010[system.cpu1.fuPool.FUList8] 1011type=FUDesc 1012children=opList 1013count=1 1014eventq_index=0 1015opList=system.cpu1.fuPool.FUList8.opList 1016 1017[system.cpu1.fuPool.FUList8.opList] 1018type=OpDesc 1019eventq_index=0 1020issueLat=3 1021opClass=IprAccess 1022opLat=3 1023 1024[system.cpu1.icache] 1025type=BaseCache 1026children=tags 1027addr_ranges=0:18446744073709551615 1028assoc=1 1029clk_domain=system.cpu_clk_domain 1030eventq_index=0 1031forward_snoops=true 1032hit_latency=2 1033is_top_level=true 1034max_miss_count=0 1035mshrs=4 1036prefetch_on_access=false 1037prefetcher=Null 1038response_latency=2 1039sequential_access=false 1040size=32768 1041system=system 1042tags=system.cpu1.icache.tags 1043tgts_per_mshr=20 1044two_queue=false 1045write_buffers=8 1046cpu_side=system.cpu1.icache_port 1047mem_side=system.toL2Bus.slave[2] 1048 1049[system.cpu1.icache.tags] 1050type=LRU 1051assoc=1 1052block_size=64 1053clk_domain=system.cpu_clk_domain 1054eventq_index=0 1055hit_latency=2 1056sequential_access=false 1057size=32768 1058 1059[system.cpu1.interrupts] 1060type=SparcInterrupts 1061eventq_index=0 1062 1063[system.cpu1.isa] 1064type=SparcISA 1065eventq_index=0 1066 1067[system.cpu1.itb] 1068type=SparcTLB 1069eventq_index=0 1070size=64 1071 1072[system.cpu1.tracer] 1073type=ExeTracer 1074eventq_index=0 1075 1076[system.cpu2] 1077type=DerivO3CPU 1078children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1079LFSTSize=1024 1080LQEntries=32 1081LSQCheckLoads=true 1082LSQDepCheckShift=4 1083SQEntries=32 1084SSITSize=1024 1085activity=0 1086backComSize=5 1087branchPred=system.cpu2.branchPred 1088cachePorts=200 1089checker=Null 1090clk_domain=system.cpu_clk_domain 1091commitToDecodeDelay=1 1092commitToFetchDelay=1 1093commitToIEWDelay=1 1094commitToRenameDelay=1 1095commitWidth=8 1096cpu_id=2 1097decodeToFetchDelay=1 1098decodeToRenameDelay=1 1099decodeWidth=8 1100dispatchWidth=8 1101do_checkpoint_insts=true 1102do_quiesce=true 1103do_statistics_insts=true 1104dtb=system.cpu2.dtb 1105eventq_index=0 1106fetchBufferSize=64 1107fetchToDecodeDelay=1 1108fetchTrapLatency=1 1109fetchWidth=8 1110forwardComSize=5 1111fuPool=system.cpu2.fuPool 1112function_trace=false 1113function_trace_start=0 1114iewToCommitDelay=1 1115iewToDecodeDelay=1 1116iewToFetchDelay=1 1117iewToRenameDelay=1 1118interrupts=system.cpu2.interrupts 1119isa=system.cpu2.isa 1120issueToExecuteDelay=1 1121issueWidth=8 1122itb=system.cpu2.itb 1123max_insts_all_threads=0 1124max_insts_any_thread=0 1125max_loads_all_threads=0 1126max_loads_any_thread=0 1127needsTSO=false 1128numIQEntries=64 1129numPhysCCRegs=0 1130numPhysFloatRegs=256 1131numPhysIntRegs=256 1132numROBEntries=192 1133numRobs=1 1134numThreads=1 1135profile=0 1136progress_interval=0 1137renameToDecodeDelay=1 1138renameToFetchDelay=1 1139renameToIEWDelay=2 1140renameToROBDelay=1 1141renameWidth=8 1142simpoint_start_insts= 1143smtCommitPolicy=RoundRobin 1144smtFetchPolicy=SingleThread 1145smtIQPolicy=Partitioned 1146smtIQThreshold=100 1147smtLSQPolicy=Partitioned 1148smtLSQThreshold=100 1149smtNumFetchingThreads=1 1150smtROBPolicy=Partitioned 1151smtROBThreshold=100 1152socket_id=0 1153squashWidth=8 1154store_set_clear_period=250000 1155switched_out=false 1156system=system 1157tracer=system.cpu2.tracer 1158trapLatency=13 1159wbDepth=1 1160wbWidth=8 1161workload=system.cpu0.workload 1162dcache_port=system.cpu2.dcache.cpu_side 1163icache_port=system.cpu2.icache.cpu_side 1164 1165[system.cpu2.branchPred] 1166type=BranchPredictor 1167BTBEntries=4096 1168BTBTagSize=16 1169RASSize=16 1170choiceCtrBits=2 1171choicePredictorSize=8192 1172eventq_index=0 1173globalCtrBits=2 1174globalPredictorSize=8192 1175instShiftAmt=2 1176localCtrBits=2 1177localHistoryTableSize=2048 1178localPredictorSize=2048 1179numThreads=1 1180predType=tournament 1181 1182[system.cpu2.dcache] 1183type=BaseCache 1184children=tags 1185addr_ranges=0:18446744073709551615 1186assoc=4 1187clk_domain=system.cpu_clk_domain 1188eventq_index=0 1189forward_snoops=true 1190hit_latency=2 1191is_top_level=true 1192max_miss_count=0 1193mshrs=4 1194prefetch_on_access=false 1195prefetcher=Null 1196response_latency=2 1197sequential_access=false 1198size=32768 1199system=system 1200tags=system.cpu2.dcache.tags 1201tgts_per_mshr=20 1202two_queue=false 1203write_buffers=8 1204cpu_side=system.cpu2.dcache_port 1205mem_side=system.toL2Bus.slave[5] 1206 1207[system.cpu2.dcache.tags] 1208type=LRU 1209assoc=4 1210block_size=64 1211clk_domain=system.cpu_clk_domain 1212eventq_index=0 1213hit_latency=2 1214sequential_access=false 1215size=32768 1216 1217[system.cpu2.dtb] 1218type=SparcTLB 1219eventq_index=0 1220size=64 1221 1222[system.cpu2.fuPool] 1223type=FUPool 1224children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1225FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1226eventq_index=0 1227 1228[system.cpu2.fuPool.FUList0] 1229type=FUDesc 1230children=opList 1231count=6 1232eventq_index=0 1233opList=system.cpu2.fuPool.FUList0.opList 1234 1235[system.cpu2.fuPool.FUList0.opList] 1236type=OpDesc 1237eventq_index=0 1238issueLat=1 1239opClass=IntAlu 1240opLat=1 1241 1242[system.cpu2.fuPool.FUList1] 1243type=FUDesc 1244children=opList0 opList1 1245count=2 1246eventq_index=0 1247opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1248 1249[system.cpu2.fuPool.FUList1.opList0] 1250type=OpDesc 1251eventq_index=0 1252issueLat=1 1253opClass=IntMult 1254opLat=3 1255 1256[system.cpu2.fuPool.FUList1.opList1] 1257type=OpDesc 1258eventq_index=0 1259issueLat=19 1260opClass=IntDiv 1261opLat=20 1262 1263[system.cpu2.fuPool.FUList2] 1264type=FUDesc 1265children=opList0 opList1 opList2 1266count=4 1267eventq_index=0 1268opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1269 1270[system.cpu2.fuPool.FUList2.opList0] 1271type=OpDesc 1272eventq_index=0 1273issueLat=1 1274opClass=FloatAdd 1275opLat=2 1276 1277[system.cpu2.fuPool.FUList2.opList1] 1278type=OpDesc 1279eventq_index=0 1280issueLat=1 1281opClass=FloatCmp 1282opLat=2 1283 1284[system.cpu2.fuPool.FUList2.opList2] 1285type=OpDesc 1286eventq_index=0 1287issueLat=1 1288opClass=FloatCvt 1289opLat=2 1290 1291[system.cpu2.fuPool.FUList3] 1292type=FUDesc 1293children=opList0 opList1 opList2 1294count=2 1295eventq_index=0 1296opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1297 1298[system.cpu2.fuPool.FUList3.opList0] 1299type=OpDesc 1300eventq_index=0 1301issueLat=1 1302opClass=FloatMult 1303opLat=4 1304 1305[system.cpu2.fuPool.FUList3.opList1] 1306type=OpDesc 1307eventq_index=0 1308issueLat=12 1309opClass=FloatDiv 1310opLat=12 1311 1312[system.cpu2.fuPool.FUList3.opList2] 1313type=OpDesc 1314eventq_index=0 1315issueLat=24 1316opClass=FloatSqrt 1317opLat=24 1318 1319[system.cpu2.fuPool.FUList4] 1320type=FUDesc 1321children=opList 1322count=0 1323eventq_index=0 1324opList=system.cpu2.fuPool.FUList4.opList 1325 1326[system.cpu2.fuPool.FUList4.opList] 1327type=OpDesc 1328eventq_index=0 1329issueLat=1 1330opClass=MemRead 1331opLat=1 1332 1333[system.cpu2.fuPool.FUList5] 1334type=FUDesc 1335children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1336count=4 1337eventq_index=0 1338opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1339 1340[system.cpu2.fuPool.FUList5.opList00] 1341type=OpDesc 1342eventq_index=0 1343issueLat=1 1344opClass=SimdAdd 1345opLat=1 1346 1347[system.cpu2.fuPool.FUList5.opList01] 1348type=OpDesc 1349eventq_index=0 1350issueLat=1 1351opClass=SimdAddAcc 1352opLat=1 1353 1354[system.cpu2.fuPool.FUList5.opList02] 1355type=OpDesc 1356eventq_index=0 1357issueLat=1 1358opClass=SimdAlu 1359opLat=1 1360 1361[system.cpu2.fuPool.FUList5.opList03] 1362type=OpDesc 1363eventq_index=0 1364issueLat=1 1365opClass=SimdCmp 1366opLat=1 1367 1368[system.cpu2.fuPool.FUList5.opList04] 1369type=OpDesc 1370eventq_index=0 1371issueLat=1 1372opClass=SimdCvt 1373opLat=1 1374 1375[system.cpu2.fuPool.FUList5.opList05] 1376type=OpDesc 1377eventq_index=0 1378issueLat=1 1379opClass=SimdMisc 1380opLat=1 1381 1382[system.cpu2.fuPool.FUList5.opList06] 1383type=OpDesc 1384eventq_index=0 1385issueLat=1 1386opClass=SimdMult 1387opLat=1 1388 1389[system.cpu2.fuPool.FUList5.opList07] 1390type=OpDesc 1391eventq_index=0 1392issueLat=1 1393opClass=SimdMultAcc 1394opLat=1 1395 1396[system.cpu2.fuPool.FUList5.opList08] 1397type=OpDesc 1398eventq_index=0 1399issueLat=1 1400opClass=SimdShift 1401opLat=1 1402 1403[system.cpu2.fuPool.FUList5.opList09] 1404type=OpDesc 1405eventq_index=0 1406issueLat=1 1407opClass=SimdShiftAcc 1408opLat=1 1409 1410[system.cpu2.fuPool.FUList5.opList10] 1411type=OpDesc 1412eventq_index=0 1413issueLat=1 1414opClass=SimdSqrt 1415opLat=1 1416 1417[system.cpu2.fuPool.FUList5.opList11] 1418type=OpDesc 1419eventq_index=0 1420issueLat=1 1421opClass=SimdFloatAdd 1422opLat=1 1423 1424[system.cpu2.fuPool.FUList5.opList12] 1425type=OpDesc 1426eventq_index=0 1427issueLat=1 1428opClass=SimdFloatAlu 1429opLat=1 1430 1431[system.cpu2.fuPool.FUList5.opList13] 1432type=OpDesc 1433eventq_index=0 1434issueLat=1 1435opClass=SimdFloatCmp 1436opLat=1 1437 1438[system.cpu2.fuPool.FUList5.opList14] 1439type=OpDesc 1440eventq_index=0 1441issueLat=1 1442opClass=SimdFloatCvt 1443opLat=1 1444 1445[system.cpu2.fuPool.FUList5.opList15] 1446type=OpDesc 1447eventq_index=0 1448issueLat=1 1449opClass=SimdFloatDiv 1450opLat=1 1451 1452[system.cpu2.fuPool.FUList5.opList16] 1453type=OpDesc 1454eventq_index=0 1455issueLat=1 1456opClass=SimdFloatMisc 1457opLat=1 1458 1459[system.cpu2.fuPool.FUList5.opList17] 1460type=OpDesc 1461eventq_index=0 1462issueLat=1 1463opClass=SimdFloatMult 1464opLat=1 1465 1466[system.cpu2.fuPool.FUList5.opList18] 1467type=OpDesc 1468eventq_index=0 1469issueLat=1 1470opClass=SimdFloatMultAcc 1471opLat=1 1472 1473[system.cpu2.fuPool.FUList5.opList19] 1474type=OpDesc 1475eventq_index=0 1476issueLat=1 1477opClass=SimdFloatSqrt 1478opLat=1 1479 1480[system.cpu2.fuPool.FUList6] 1481type=FUDesc 1482children=opList 1483count=0 1484eventq_index=0 1485opList=system.cpu2.fuPool.FUList6.opList 1486 1487[system.cpu2.fuPool.FUList6.opList] 1488type=OpDesc 1489eventq_index=0 1490issueLat=1 1491opClass=MemWrite 1492opLat=1 1493 1494[system.cpu2.fuPool.FUList7] 1495type=FUDesc 1496children=opList0 opList1 1497count=4 1498eventq_index=0 1499opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1500 1501[system.cpu2.fuPool.FUList7.opList0] 1502type=OpDesc 1503eventq_index=0 1504issueLat=1 1505opClass=MemRead 1506opLat=1 1507 1508[system.cpu2.fuPool.FUList7.opList1] 1509type=OpDesc 1510eventq_index=0 1511issueLat=1 1512opClass=MemWrite 1513opLat=1 1514 1515[system.cpu2.fuPool.FUList8] 1516type=FUDesc 1517children=opList 1518count=1 1519eventq_index=0 1520opList=system.cpu2.fuPool.FUList8.opList 1521 1522[system.cpu2.fuPool.FUList8.opList] 1523type=OpDesc 1524eventq_index=0 1525issueLat=3 1526opClass=IprAccess 1527opLat=3 1528 1529[system.cpu2.icache] 1530type=BaseCache 1531children=tags 1532addr_ranges=0:18446744073709551615 1533assoc=1 1534clk_domain=system.cpu_clk_domain 1535eventq_index=0 1536forward_snoops=true 1537hit_latency=2 1538is_top_level=true 1539max_miss_count=0 1540mshrs=4 1541prefetch_on_access=false 1542prefetcher=Null 1543response_latency=2 1544sequential_access=false 1545size=32768 1546system=system 1547tags=system.cpu2.icache.tags 1548tgts_per_mshr=20 1549two_queue=false 1550write_buffers=8 1551cpu_side=system.cpu2.icache_port 1552mem_side=system.toL2Bus.slave[4] 1553 1554[system.cpu2.icache.tags] 1555type=LRU 1556assoc=1 1557block_size=64 1558clk_domain=system.cpu_clk_domain 1559eventq_index=0 1560hit_latency=2 1561sequential_access=false 1562size=32768 1563 1564[system.cpu2.interrupts] 1565type=SparcInterrupts 1566eventq_index=0 1567 1568[system.cpu2.isa] 1569type=SparcISA 1570eventq_index=0 1571 1572[system.cpu2.itb] 1573type=SparcTLB 1574eventq_index=0 1575size=64 1576 1577[system.cpu2.tracer] 1578type=ExeTracer 1579eventq_index=0 1580 1581[system.cpu3] 1582type=DerivO3CPU 1583children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1584LFSTSize=1024 1585LQEntries=32 1586LSQCheckLoads=true 1587LSQDepCheckShift=4 1588SQEntries=32 1589SSITSize=1024 1590activity=0 1591backComSize=5 1592branchPred=system.cpu3.branchPred 1593cachePorts=200 1594checker=Null 1595clk_domain=system.cpu_clk_domain 1596commitToDecodeDelay=1 1597commitToFetchDelay=1 1598commitToIEWDelay=1 1599commitToRenameDelay=1 1600commitWidth=8 1601cpu_id=3 1602decodeToFetchDelay=1 1603decodeToRenameDelay=1 1604decodeWidth=8 1605dispatchWidth=8 1606do_checkpoint_insts=true 1607do_quiesce=true 1608do_statistics_insts=true 1609dtb=system.cpu3.dtb 1610eventq_index=0 1611fetchBufferSize=64 1612fetchToDecodeDelay=1 1613fetchTrapLatency=1 1614fetchWidth=8 1615forwardComSize=5 1616fuPool=system.cpu3.fuPool 1617function_trace=false 1618function_trace_start=0 1619iewToCommitDelay=1 1620iewToDecodeDelay=1 1621iewToFetchDelay=1 1622iewToRenameDelay=1 1623interrupts=system.cpu3.interrupts 1624isa=system.cpu3.isa 1625issueToExecuteDelay=1 1626issueWidth=8 1627itb=system.cpu3.itb 1628max_insts_all_threads=0 1629max_insts_any_thread=0 1630max_loads_all_threads=0 1631max_loads_any_thread=0 1632needsTSO=false 1633numIQEntries=64 1634numPhysCCRegs=0 1635numPhysFloatRegs=256 1636numPhysIntRegs=256 1637numROBEntries=192 1638numRobs=1 1639numThreads=1 1640profile=0 1641progress_interval=0 1642renameToDecodeDelay=1 1643renameToFetchDelay=1 1644renameToIEWDelay=2 1645renameToROBDelay=1 1646renameWidth=8 1647simpoint_start_insts= 1648smtCommitPolicy=RoundRobin 1649smtFetchPolicy=SingleThread 1650smtIQPolicy=Partitioned 1651smtIQThreshold=100 1652smtLSQPolicy=Partitioned 1653smtLSQThreshold=100 1654smtNumFetchingThreads=1 1655smtROBPolicy=Partitioned 1656smtROBThreshold=100 1657socket_id=0 1658squashWidth=8 1659store_set_clear_period=250000 1660switched_out=false 1661system=system 1662tracer=system.cpu3.tracer 1663trapLatency=13 1664wbDepth=1 1665wbWidth=8 1666workload=system.cpu0.workload 1667dcache_port=system.cpu3.dcache.cpu_side 1668icache_port=system.cpu3.icache.cpu_side 1669 1670[system.cpu3.branchPred] 1671type=BranchPredictor 1672BTBEntries=4096 1673BTBTagSize=16 1674RASSize=16 1675choiceCtrBits=2 1676choicePredictorSize=8192 1677eventq_index=0 1678globalCtrBits=2 1679globalPredictorSize=8192 1680instShiftAmt=2 1681localCtrBits=2 1682localHistoryTableSize=2048 1683localPredictorSize=2048 1684numThreads=1 1685predType=tournament 1686 1687[system.cpu3.dcache] 1688type=BaseCache 1689children=tags 1690addr_ranges=0:18446744073709551615 1691assoc=4 1692clk_domain=system.cpu_clk_domain 1693eventq_index=0 1694forward_snoops=true 1695hit_latency=2 1696is_top_level=true 1697max_miss_count=0 1698mshrs=4 1699prefetch_on_access=false 1700prefetcher=Null 1701response_latency=2 1702sequential_access=false 1703size=32768 1704system=system 1705tags=system.cpu3.dcache.tags 1706tgts_per_mshr=20 1707two_queue=false 1708write_buffers=8 1709cpu_side=system.cpu3.dcache_port 1710mem_side=system.toL2Bus.slave[7] 1711 1712[system.cpu3.dcache.tags] 1713type=LRU 1714assoc=4 1715block_size=64 1716clk_domain=system.cpu_clk_domain 1717eventq_index=0 1718hit_latency=2 1719sequential_access=false 1720size=32768 1721 1722[system.cpu3.dtb] 1723type=SparcTLB 1724eventq_index=0 1725size=64 1726 1727[system.cpu3.fuPool] 1728type=FUPool 1729children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1730FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1731eventq_index=0 1732 1733[system.cpu3.fuPool.FUList0] 1734type=FUDesc 1735children=opList 1736count=6 1737eventq_index=0 1738opList=system.cpu3.fuPool.FUList0.opList 1739 1740[system.cpu3.fuPool.FUList0.opList] 1741type=OpDesc 1742eventq_index=0 1743issueLat=1 1744opClass=IntAlu 1745opLat=1 1746 1747[system.cpu3.fuPool.FUList1] 1748type=FUDesc 1749children=opList0 opList1 1750count=2 1751eventq_index=0 1752opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1753 1754[system.cpu3.fuPool.FUList1.opList0] 1755type=OpDesc 1756eventq_index=0 1757issueLat=1 1758opClass=IntMult 1759opLat=3 1760 1761[system.cpu3.fuPool.FUList1.opList1] 1762type=OpDesc 1763eventq_index=0 1764issueLat=19 1765opClass=IntDiv 1766opLat=20 1767 1768[system.cpu3.fuPool.FUList2] 1769type=FUDesc 1770children=opList0 opList1 opList2 1771count=4 1772eventq_index=0 1773opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1774 1775[system.cpu3.fuPool.FUList2.opList0] 1776type=OpDesc 1777eventq_index=0 1778issueLat=1 1779opClass=FloatAdd 1780opLat=2 1781 1782[system.cpu3.fuPool.FUList2.opList1] 1783type=OpDesc 1784eventq_index=0 1785issueLat=1 1786opClass=FloatCmp 1787opLat=2 1788 1789[system.cpu3.fuPool.FUList2.opList2] 1790type=OpDesc 1791eventq_index=0 1792issueLat=1 1793opClass=FloatCvt 1794opLat=2 1795 1796[system.cpu3.fuPool.FUList3] 1797type=FUDesc 1798children=opList0 opList1 opList2 1799count=2 1800eventq_index=0 1801opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1802 1803[system.cpu3.fuPool.FUList3.opList0] 1804type=OpDesc 1805eventq_index=0 1806issueLat=1 1807opClass=FloatMult 1808opLat=4 1809 1810[system.cpu3.fuPool.FUList3.opList1] 1811type=OpDesc 1812eventq_index=0 1813issueLat=12 1814opClass=FloatDiv 1815opLat=12 1816 1817[system.cpu3.fuPool.FUList3.opList2] 1818type=OpDesc 1819eventq_index=0 1820issueLat=24 1821opClass=FloatSqrt 1822opLat=24 1823 1824[system.cpu3.fuPool.FUList4] 1825type=FUDesc 1826children=opList 1827count=0 1828eventq_index=0 1829opList=system.cpu3.fuPool.FUList4.opList 1830 1831[system.cpu3.fuPool.FUList4.opList] 1832type=OpDesc 1833eventq_index=0 1834issueLat=1 1835opClass=MemRead 1836opLat=1 1837 1838[system.cpu3.fuPool.FUList5] 1839type=FUDesc 1840children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1841count=4 1842eventq_index=0 1843opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1844 1845[system.cpu3.fuPool.FUList5.opList00] 1846type=OpDesc 1847eventq_index=0 1848issueLat=1 1849opClass=SimdAdd 1850opLat=1 1851 1852[system.cpu3.fuPool.FUList5.opList01] 1853type=OpDesc 1854eventq_index=0 1855issueLat=1 1856opClass=SimdAddAcc 1857opLat=1 1858 1859[system.cpu3.fuPool.FUList5.opList02] 1860type=OpDesc 1861eventq_index=0 1862issueLat=1 1863opClass=SimdAlu 1864opLat=1 1865 1866[system.cpu3.fuPool.FUList5.opList03] 1867type=OpDesc 1868eventq_index=0 1869issueLat=1 1870opClass=SimdCmp 1871opLat=1 1872 1873[system.cpu3.fuPool.FUList5.opList04] 1874type=OpDesc 1875eventq_index=0 1876issueLat=1 1877opClass=SimdCvt 1878opLat=1 1879 1880[system.cpu3.fuPool.FUList5.opList05] 1881type=OpDesc 1882eventq_index=0 1883issueLat=1 1884opClass=SimdMisc 1885opLat=1 1886 1887[system.cpu3.fuPool.FUList5.opList06] 1888type=OpDesc 1889eventq_index=0 1890issueLat=1 1891opClass=SimdMult 1892opLat=1 1893 1894[system.cpu3.fuPool.FUList5.opList07] 1895type=OpDesc 1896eventq_index=0 1897issueLat=1 1898opClass=SimdMultAcc 1899opLat=1 1900 1901[system.cpu3.fuPool.FUList5.opList08] 1902type=OpDesc 1903eventq_index=0 1904issueLat=1 1905opClass=SimdShift 1906opLat=1 1907 1908[system.cpu3.fuPool.FUList5.opList09] 1909type=OpDesc 1910eventq_index=0 1911issueLat=1 1912opClass=SimdShiftAcc 1913opLat=1 1914 1915[system.cpu3.fuPool.FUList5.opList10] 1916type=OpDesc 1917eventq_index=0 1918issueLat=1 1919opClass=SimdSqrt 1920opLat=1 1921 1922[system.cpu3.fuPool.FUList5.opList11] 1923type=OpDesc 1924eventq_index=0 1925issueLat=1 1926opClass=SimdFloatAdd 1927opLat=1 1928 1929[system.cpu3.fuPool.FUList5.opList12] 1930type=OpDesc 1931eventq_index=0 1932issueLat=1 1933opClass=SimdFloatAlu 1934opLat=1 1935 1936[system.cpu3.fuPool.FUList5.opList13] 1937type=OpDesc 1938eventq_index=0 1939issueLat=1 1940opClass=SimdFloatCmp 1941opLat=1 1942 1943[system.cpu3.fuPool.FUList5.opList14] 1944type=OpDesc 1945eventq_index=0 1946issueLat=1 1947opClass=SimdFloatCvt 1948opLat=1 1949 1950[system.cpu3.fuPool.FUList5.opList15] 1951type=OpDesc 1952eventq_index=0 1953issueLat=1 1954opClass=SimdFloatDiv 1955opLat=1 1956 1957[system.cpu3.fuPool.FUList5.opList16] 1958type=OpDesc 1959eventq_index=0 1960issueLat=1 1961opClass=SimdFloatMisc 1962opLat=1 1963 1964[system.cpu3.fuPool.FUList5.opList17] 1965type=OpDesc 1966eventq_index=0 1967issueLat=1 1968opClass=SimdFloatMult 1969opLat=1 1970 1971[system.cpu3.fuPool.FUList5.opList18] 1972type=OpDesc 1973eventq_index=0 1974issueLat=1 1975opClass=SimdFloatMultAcc 1976opLat=1 1977 1978[system.cpu3.fuPool.FUList5.opList19] 1979type=OpDesc 1980eventq_index=0 1981issueLat=1 1982opClass=SimdFloatSqrt 1983opLat=1 1984 1985[system.cpu3.fuPool.FUList6] 1986type=FUDesc 1987children=opList 1988count=0 1989eventq_index=0 1990opList=system.cpu3.fuPool.FUList6.opList 1991 1992[system.cpu3.fuPool.FUList6.opList] 1993type=OpDesc 1994eventq_index=0 1995issueLat=1 1996opClass=MemWrite 1997opLat=1 1998 1999[system.cpu3.fuPool.FUList7] 2000type=FUDesc 2001children=opList0 opList1 2002count=4 2003eventq_index=0 2004opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 2005 2006[system.cpu3.fuPool.FUList7.opList0] 2007type=OpDesc 2008eventq_index=0 2009issueLat=1 2010opClass=MemRead 2011opLat=1 2012 2013[system.cpu3.fuPool.FUList7.opList1] 2014type=OpDesc 2015eventq_index=0 2016issueLat=1 2017opClass=MemWrite 2018opLat=1 2019 2020[system.cpu3.fuPool.FUList8] 2021type=FUDesc 2022children=opList 2023count=1 2024eventq_index=0 2025opList=system.cpu3.fuPool.FUList8.opList 2026 2027[system.cpu3.fuPool.FUList8.opList] 2028type=OpDesc 2029eventq_index=0 2030issueLat=3 2031opClass=IprAccess 2032opLat=3 2033 2034[system.cpu3.icache] 2035type=BaseCache 2036children=tags 2037addr_ranges=0:18446744073709551615 2038assoc=1 2039clk_domain=system.cpu_clk_domain 2040eventq_index=0 2041forward_snoops=true 2042hit_latency=2 2043is_top_level=true 2044max_miss_count=0 2045mshrs=4 2046prefetch_on_access=false 2047prefetcher=Null 2048response_latency=2 2049sequential_access=false 2050size=32768 2051system=system 2052tags=system.cpu3.icache.tags 2053tgts_per_mshr=20 2054two_queue=false 2055write_buffers=8 2056cpu_side=system.cpu3.icache_port 2057mem_side=system.toL2Bus.slave[6] 2058 2059[system.cpu3.icache.tags] 2060type=LRU 2061assoc=1 2062block_size=64 2063clk_domain=system.cpu_clk_domain 2064eventq_index=0 2065hit_latency=2 2066sequential_access=false 2067size=32768 2068 2069[system.cpu3.interrupts] 2070type=SparcInterrupts 2071eventq_index=0 2072 2073[system.cpu3.isa] 2074type=SparcISA 2075eventq_index=0 2076 2077[system.cpu3.itb] 2078type=SparcTLB 2079eventq_index=0 2080size=64 2081 2082[system.cpu3.tracer] 2083type=ExeTracer 2084eventq_index=0 2085 2086[system.cpu_clk_domain] 2087type=SrcClockDomain 2088clock=500 2089domain_id=-1 2090eventq_index=0 2091init_perf_level=0 2092voltage_domain=system.voltage_domain 2093 2094[system.dvfs_handler] 2095type=DVFSHandler 2096domains= 2097enable=false 2098eventq_index=0 2099sys_clk_domain=system.clk_domain 2100transition_latency=100000000 2101 2102[system.l2c] 2103type=BaseCache 2104children=tags 2105addr_ranges=0:18446744073709551615 2106assoc=8 2107clk_domain=system.cpu_clk_domain 2108eventq_index=0 2109forward_snoops=true 2110hit_latency=20 2111is_top_level=false 2112max_miss_count=0 2113mshrs=20 2114prefetch_on_access=false 2115prefetcher=Null 2116response_latency=20 2117sequential_access=false 2118size=4194304 2119system=system 2120tags=system.l2c.tags 2121tgts_per_mshr=12 2122two_queue=false 2123write_buffers=8 2124cpu_side=system.toL2Bus.master[0] 2125mem_side=system.membus.slave[1] 2126 2127[system.l2c.tags] 2128type=LRU 2129assoc=8 2130block_size=64 2131clk_domain=system.cpu_clk_domain 2132eventq_index=0 2133hit_latency=20 2134sequential_access=false 2135size=4194304 2136 2137[system.membus] 2138type=CoherentBus 2139clk_domain=system.clk_domain 2140eventq_index=0 2141header_cycles=1 2142system=system 2143use_default_range=false 2144width=8 2145master=system.physmem.port 2146slave=system.system_port system.l2c.mem_side 2147 2148[system.physmem] 2149type=DRAMCtrl 2150activation_limit=4 2151addr_mapping=RoRaBaChCo 2152banks_per_rank=8 2153burst_length=8 2154channels=1 2155clk_domain=system.clk_domain 2156conf_table_reported=true 2157device_bus_width=8 2158device_rowbuffer_size=1024 2159devices_per_rank=8 2160eventq_index=0 2161in_addr_map=true 2162max_accesses_per_row=16 2163mem_sched_policy=frfcfs 2164min_writes_per_switch=16 2165null=false 2166page_policy=open_adaptive 2167range=0:134217727 2168ranks_per_channel=2 2169read_buffer_size=32 2170static_backend_latency=10000 2171static_frontend_latency=10000 2172tBURST=5000 2173tCK=1250 2174tCL=13750 2175tRAS=35000 2176tRCD=13750 2177tREFI=7800000 2178tRFC=260000 2179tRP=13750 2180tRRD=6000 2181tRTP=7500 2182tRTW=2500 2183tWR=15000 2184tWTR=7500 2185tXAW=30000 2186write_buffer_size=64 2187write_high_thresh_perc=85 2188write_low_thresh_perc=50 2189port=system.membus.master[0] 2190 2191[system.toL2Bus] 2192type=CoherentBus 2193clk_domain=system.cpu_clk_domain 2194eventq_index=0 2195header_cycles=1 2196system=system 2197use_default_range=false 2198width=8 2199master=system.l2c.cpu_side 2200slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2201 2202[system.voltage_domain] 2203type=VoltageDomain 2204eventq_index=0 2205voltage=1.000000 2206 2207