config.ini revision 10242
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21load_offset=0 22mem_mode=timing 23mem_ranges= 24memories=system.physmem 25num_work_ids=16 26readfile= 27symbolfile= 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.clk_domain] 38type=SrcClockDomain 39clock=1000 40eventq_index=0 41voltage_domain=system.voltage_domain 42 43[system.cpu0] 44type=DerivO3CPU 45children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 46LFSTSize=1024 47LQEntries=32 48LSQCheckLoads=true 49LSQDepCheckShift=4 50SQEntries=32 51SSITSize=1024 52activity=0 53backComSize=5 54branchPred=system.cpu0.branchPred 55cachePorts=200 56checker=Null 57clk_domain=system.cpu_clk_domain 58commitToDecodeDelay=1 59commitToFetchDelay=1 60commitToIEWDelay=1 61commitToRenameDelay=1 62commitWidth=8 63cpu_id=0 64decodeToFetchDelay=1 65decodeToRenameDelay=1 66decodeWidth=8 67dispatchWidth=8 68do_checkpoint_insts=true 69do_quiesce=true 70do_statistics_insts=true 71dtb=system.cpu0.dtb 72eventq_index=0 73fetchBufferSize=64 74fetchToDecodeDelay=1 75fetchTrapLatency=1 76fetchWidth=8 77forwardComSize=5 78fuPool=system.cpu0.fuPool 79function_trace=false 80function_trace_start=0 81iewToCommitDelay=1 82iewToDecodeDelay=1 83iewToFetchDelay=1 84iewToRenameDelay=1 85interrupts=system.cpu0.interrupts 86isa=system.cpu0.isa 87issueToExecuteDelay=1 88issueWidth=8 89itb=system.cpu0.itb 90max_insts_all_threads=0 91max_insts_any_thread=0 92max_loads_all_threads=0 93max_loads_any_thread=0 94needsTSO=false 95numIQEntries=64 96numPhysCCRegs=0 97numPhysFloatRegs=256 98numPhysIntRegs=256 99numROBEntries=192 100numRobs=1 101numThreads=1 102profile=0 103progress_interval=0 104renameToDecodeDelay=1 105renameToFetchDelay=1 106renameToIEWDelay=2 107renameToROBDelay=1 108renameWidth=8 109simpoint_start_insts= 110smtCommitPolicy=RoundRobin 111smtFetchPolicy=SingleThread 112smtIQPolicy=Partitioned 113smtIQThreshold=100 114smtLSQPolicy=Partitioned 115smtLSQThreshold=100 116smtNumFetchingThreads=1 117smtROBPolicy=Partitioned 118smtROBThreshold=100 119socket_id=0 120squashWidth=8 121store_set_clear_period=250000 122switched_out=false 123system=system 124tracer=system.cpu0.tracer 125trapLatency=13 126wbDepth=1 127wbWidth=8 128workload=system.cpu0.workload 129dcache_port=system.cpu0.dcache.cpu_side 130icache_port=system.cpu0.icache.cpu_side 131 132[system.cpu0.branchPred] 133type=BranchPredictor 134BTBEntries=4096 135BTBTagSize=16 136RASSize=16 137choiceCtrBits=2 138choicePredictorSize=8192 139eventq_index=0 140globalCtrBits=2 141globalPredictorSize=8192 142instShiftAmt=2 143localCtrBits=2 144localHistoryTableSize=2048 145localPredictorSize=2048 146numThreads=1 147predType=tournament 148 149[system.cpu0.dcache] 150type=BaseCache 151children=tags 152addr_ranges=0:18446744073709551615 153assoc=4 154clk_domain=system.cpu_clk_domain 155eventq_index=0 156forward_snoops=true 157hit_latency=2 158is_top_level=true 159max_miss_count=0 160mshrs=4 161prefetch_on_access=false 162prefetcher=Null 163response_latency=2 164sequential_access=false 165size=32768 166system=system 167tags=system.cpu0.dcache.tags 168tgts_per_mshr=20 169two_queue=false 170write_buffers=8 171cpu_side=system.cpu0.dcache_port 172mem_side=system.toL2Bus.slave[1] 173 174[system.cpu0.dcache.tags] 175type=LRU 176assoc=4 177block_size=64 178clk_domain=system.cpu_clk_domain 179eventq_index=0 180hit_latency=2 181sequential_access=false 182size=32768 183 184[system.cpu0.dtb] 185type=SparcTLB 186eventq_index=0 187size=64 188 189[system.cpu0.fuPool] 190type=FUPool 191children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 192FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 193eventq_index=0 194 195[system.cpu0.fuPool.FUList0] 196type=FUDesc 197children=opList 198count=6 199eventq_index=0 200opList=system.cpu0.fuPool.FUList0.opList 201 202[system.cpu0.fuPool.FUList0.opList] 203type=OpDesc 204eventq_index=0 205issueLat=1 206opClass=IntAlu 207opLat=1 208 209[system.cpu0.fuPool.FUList1] 210type=FUDesc 211children=opList0 opList1 212count=2 213eventq_index=0 214opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 215 216[system.cpu0.fuPool.FUList1.opList0] 217type=OpDesc 218eventq_index=0 219issueLat=1 220opClass=IntMult 221opLat=3 222 223[system.cpu0.fuPool.FUList1.opList1] 224type=OpDesc 225eventq_index=0 226issueLat=19 227opClass=IntDiv 228opLat=20 229 230[system.cpu0.fuPool.FUList2] 231type=FUDesc 232children=opList0 opList1 opList2 233count=4 234eventq_index=0 235opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 236 237[system.cpu0.fuPool.FUList2.opList0] 238type=OpDesc 239eventq_index=0 240issueLat=1 241opClass=FloatAdd 242opLat=2 243 244[system.cpu0.fuPool.FUList2.opList1] 245type=OpDesc 246eventq_index=0 247issueLat=1 248opClass=FloatCmp 249opLat=2 250 251[system.cpu0.fuPool.FUList2.opList2] 252type=OpDesc 253eventq_index=0 254issueLat=1 255opClass=FloatCvt 256opLat=2 257 258[system.cpu0.fuPool.FUList3] 259type=FUDesc 260children=opList0 opList1 opList2 261count=2 262eventq_index=0 263opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 264 265[system.cpu0.fuPool.FUList3.opList0] 266type=OpDesc 267eventq_index=0 268issueLat=1 269opClass=FloatMult 270opLat=4 271 272[system.cpu0.fuPool.FUList3.opList1] 273type=OpDesc 274eventq_index=0 275issueLat=12 276opClass=FloatDiv 277opLat=12 278 279[system.cpu0.fuPool.FUList3.opList2] 280type=OpDesc 281eventq_index=0 282issueLat=24 283opClass=FloatSqrt 284opLat=24 285 286[system.cpu0.fuPool.FUList4] 287type=FUDesc 288children=opList 289count=0 290eventq_index=0 291opList=system.cpu0.fuPool.FUList4.opList 292 293[system.cpu0.fuPool.FUList4.opList] 294type=OpDesc 295eventq_index=0 296issueLat=1 297opClass=MemRead 298opLat=1 299 300[system.cpu0.fuPool.FUList5] 301type=FUDesc 302children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 303count=4 304eventq_index=0 305opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 306 307[system.cpu0.fuPool.FUList5.opList00] 308type=OpDesc 309eventq_index=0 310issueLat=1 311opClass=SimdAdd 312opLat=1 313 314[system.cpu0.fuPool.FUList5.opList01] 315type=OpDesc 316eventq_index=0 317issueLat=1 318opClass=SimdAddAcc 319opLat=1 320 321[system.cpu0.fuPool.FUList5.opList02] 322type=OpDesc 323eventq_index=0 324issueLat=1 325opClass=SimdAlu 326opLat=1 327 328[system.cpu0.fuPool.FUList5.opList03] 329type=OpDesc 330eventq_index=0 331issueLat=1 332opClass=SimdCmp 333opLat=1 334 335[system.cpu0.fuPool.FUList5.opList04] 336type=OpDesc 337eventq_index=0 338issueLat=1 339opClass=SimdCvt 340opLat=1 341 342[system.cpu0.fuPool.FUList5.opList05] 343type=OpDesc 344eventq_index=0 345issueLat=1 346opClass=SimdMisc 347opLat=1 348 349[system.cpu0.fuPool.FUList5.opList06] 350type=OpDesc 351eventq_index=0 352issueLat=1 353opClass=SimdMult 354opLat=1 355 356[system.cpu0.fuPool.FUList5.opList07] 357type=OpDesc 358eventq_index=0 359issueLat=1 360opClass=SimdMultAcc 361opLat=1 362 363[system.cpu0.fuPool.FUList5.opList08] 364type=OpDesc 365eventq_index=0 366issueLat=1 367opClass=SimdShift 368opLat=1 369 370[system.cpu0.fuPool.FUList5.opList09] 371type=OpDesc 372eventq_index=0 373issueLat=1 374opClass=SimdShiftAcc 375opLat=1 376 377[system.cpu0.fuPool.FUList5.opList10] 378type=OpDesc 379eventq_index=0 380issueLat=1 381opClass=SimdSqrt 382opLat=1 383 384[system.cpu0.fuPool.FUList5.opList11] 385type=OpDesc 386eventq_index=0 387issueLat=1 388opClass=SimdFloatAdd 389opLat=1 390 391[system.cpu0.fuPool.FUList5.opList12] 392type=OpDesc 393eventq_index=0 394issueLat=1 395opClass=SimdFloatAlu 396opLat=1 397 398[system.cpu0.fuPool.FUList5.opList13] 399type=OpDesc 400eventq_index=0 401issueLat=1 402opClass=SimdFloatCmp 403opLat=1 404 405[system.cpu0.fuPool.FUList5.opList14] 406type=OpDesc 407eventq_index=0 408issueLat=1 409opClass=SimdFloatCvt 410opLat=1 411 412[system.cpu0.fuPool.FUList5.opList15] 413type=OpDesc 414eventq_index=0 415issueLat=1 416opClass=SimdFloatDiv 417opLat=1 418 419[system.cpu0.fuPool.FUList5.opList16] 420type=OpDesc 421eventq_index=0 422issueLat=1 423opClass=SimdFloatMisc 424opLat=1 425 426[system.cpu0.fuPool.FUList5.opList17] 427type=OpDesc 428eventq_index=0 429issueLat=1 430opClass=SimdFloatMult 431opLat=1 432 433[system.cpu0.fuPool.FUList5.opList18] 434type=OpDesc 435eventq_index=0 436issueLat=1 437opClass=SimdFloatMultAcc 438opLat=1 439 440[system.cpu0.fuPool.FUList5.opList19] 441type=OpDesc 442eventq_index=0 443issueLat=1 444opClass=SimdFloatSqrt 445opLat=1 446 447[system.cpu0.fuPool.FUList6] 448type=FUDesc 449children=opList 450count=0 451eventq_index=0 452opList=system.cpu0.fuPool.FUList6.opList 453 454[system.cpu0.fuPool.FUList6.opList] 455type=OpDesc 456eventq_index=0 457issueLat=1 458opClass=MemWrite 459opLat=1 460 461[system.cpu0.fuPool.FUList7] 462type=FUDesc 463children=opList0 opList1 464count=4 465eventq_index=0 466opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 467 468[system.cpu0.fuPool.FUList7.opList0] 469type=OpDesc 470eventq_index=0 471issueLat=1 472opClass=MemRead 473opLat=1 474 475[system.cpu0.fuPool.FUList7.opList1] 476type=OpDesc 477eventq_index=0 478issueLat=1 479opClass=MemWrite 480opLat=1 481 482[system.cpu0.fuPool.FUList8] 483type=FUDesc 484children=opList 485count=1 486eventq_index=0 487opList=system.cpu0.fuPool.FUList8.opList 488 489[system.cpu0.fuPool.FUList8.opList] 490type=OpDesc 491eventq_index=0 492issueLat=3 493opClass=IprAccess 494opLat=3 495 496[system.cpu0.icache] 497type=BaseCache 498children=tags 499addr_ranges=0:18446744073709551615 500assoc=1 501clk_domain=system.cpu_clk_domain 502eventq_index=0 503forward_snoops=true 504hit_latency=2 505is_top_level=true 506max_miss_count=0 507mshrs=4 508prefetch_on_access=false 509prefetcher=Null 510response_latency=2 511sequential_access=false 512size=32768 513system=system 514tags=system.cpu0.icache.tags 515tgts_per_mshr=20 516two_queue=false 517write_buffers=8 518cpu_side=system.cpu0.icache_port 519mem_side=system.toL2Bus.slave[0] 520 521[system.cpu0.icache.tags] 522type=LRU 523assoc=1 524block_size=64 525clk_domain=system.cpu_clk_domain 526eventq_index=0 527hit_latency=2 528sequential_access=false 529size=32768 530 531[system.cpu0.interrupts] 532type=SparcInterrupts 533eventq_index=0 534 535[system.cpu0.isa] 536type=SparcISA 537eventq_index=0 538 539[system.cpu0.itb] 540type=SparcTLB 541eventq_index=0 542size=64 543 544[system.cpu0.tracer] 545type=ExeTracer 546eventq_index=0 547 548[system.cpu0.workload] 549type=LiveProcess 550cmd=test_atomic 4 551cwd= 552egid=100 553env= 554errout=cerr 555euid=100 556eventq_index=0 557executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic 558gid=100 559input=cin 560max_stack_size=67108864 561output=cout 562pid=100 563ppid=99 564simpoint=0 565system=system 566uid=100 567 568[system.cpu1] 569type=DerivO3CPU 570children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 571LFSTSize=1024 572LQEntries=32 573LSQCheckLoads=true 574LSQDepCheckShift=4 575SQEntries=32 576SSITSize=1024 577activity=0 578backComSize=5 579branchPred=system.cpu1.branchPred 580cachePorts=200 581checker=Null 582clk_domain=system.cpu_clk_domain 583commitToDecodeDelay=1 584commitToFetchDelay=1 585commitToIEWDelay=1 586commitToRenameDelay=1 587commitWidth=8 588cpu_id=1 589decodeToFetchDelay=1 590decodeToRenameDelay=1 591decodeWidth=8 592dispatchWidth=8 593do_checkpoint_insts=true 594do_quiesce=true 595do_statistics_insts=true 596dtb=system.cpu1.dtb 597eventq_index=0 598fetchBufferSize=64 599fetchToDecodeDelay=1 600fetchTrapLatency=1 601fetchWidth=8 602forwardComSize=5 603fuPool=system.cpu1.fuPool 604function_trace=false 605function_trace_start=0 606iewToCommitDelay=1 607iewToDecodeDelay=1 608iewToFetchDelay=1 609iewToRenameDelay=1 610interrupts=system.cpu1.interrupts 611isa=system.cpu1.isa 612issueToExecuteDelay=1 613issueWidth=8 614itb=system.cpu1.itb 615max_insts_all_threads=0 616max_insts_any_thread=0 617max_loads_all_threads=0 618max_loads_any_thread=0 619needsTSO=false 620numIQEntries=64 621numPhysCCRegs=0 622numPhysFloatRegs=256 623numPhysIntRegs=256 624numROBEntries=192 625numRobs=1 626numThreads=1 627profile=0 628progress_interval=0 629renameToDecodeDelay=1 630renameToFetchDelay=1 631renameToIEWDelay=2 632renameToROBDelay=1 633renameWidth=8 634simpoint_start_insts= 635smtCommitPolicy=RoundRobin 636smtFetchPolicy=SingleThread 637smtIQPolicy=Partitioned 638smtIQThreshold=100 639smtLSQPolicy=Partitioned 640smtLSQThreshold=100 641smtNumFetchingThreads=1 642smtROBPolicy=Partitioned 643smtROBThreshold=100 644socket_id=0 645squashWidth=8 646store_set_clear_period=250000 647switched_out=false 648system=system 649tracer=system.cpu1.tracer 650trapLatency=13 651wbDepth=1 652wbWidth=8 653workload=system.cpu0.workload 654dcache_port=system.cpu1.dcache.cpu_side 655icache_port=system.cpu1.icache.cpu_side 656 657[system.cpu1.branchPred] 658type=BranchPredictor 659BTBEntries=4096 660BTBTagSize=16 661RASSize=16 662choiceCtrBits=2 663choicePredictorSize=8192 664eventq_index=0 665globalCtrBits=2 666globalPredictorSize=8192 667instShiftAmt=2 668localCtrBits=2 669localHistoryTableSize=2048 670localPredictorSize=2048 671numThreads=1 672predType=tournament 673 674[system.cpu1.dcache] 675type=BaseCache 676children=tags 677addr_ranges=0:18446744073709551615 678assoc=4 679clk_domain=system.cpu_clk_domain 680eventq_index=0 681forward_snoops=true 682hit_latency=2 683is_top_level=true 684max_miss_count=0 685mshrs=4 686prefetch_on_access=false 687prefetcher=Null 688response_latency=2 689sequential_access=false 690size=32768 691system=system 692tags=system.cpu1.dcache.tags 693tgts_per_mshr=20 694two_queue=false 695write_buffers=8 696cpu_side=system.cpu1.dcache_port 697mem_side=system.toL2Bus.slave[3] 698 699[system.cpu1.dcache.tags] 700type=LRU 701assoc=4 702block_size=64 703clk_domain=system.cpu_clk_domain 704eventq_index=0 705hit_latency=2 706sequential_access=false 707size=32768 708 709[system.cpu1.dtb] 710type=SparcTLB 711eventq_index=0 712size=64 713 714[system.cpu1.fuPool] 715type=FUPool 716children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 717FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 718eventq_index=0 719 720[system.cpu1.fuPool.FUList0] 721type=FUDesc 722children=opList 723count=6 724eventq_index=0 725opList=system.cpu1.fuPool.FUList0.opList 726 727[system.cpu1.fuPool.FUList0.opList] 728type=OpDesc 729eventq_index=0 730issueLat=1 731opClass=IntAlu 732opLat=1 733 734[system.cpu1.fuPool.FUList1] 735type=FUDesc 736children=opList0 opList1 737count=2 738eventq_index=0 739opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 740 741[system.cpu1.fuPool.FUList1.opList0] 742type=OpDesc 743eventq_index=0 744issueLat=1 745opClass=IntMult 746opLat=3 747 748[system.cpu1.fuPool.FUList1.opList1] 749type=OpDesc 750eventq_index=0 751issueLat=19 752opClass=IntDiv 753opLat=20 754 755[system.cpu1.fuPool.FUList2] 756type=FUDesc 757children=opList0 opList1 opList2 758count=4 759eventq_index=0 760opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 761 762[system.cpu1.fuPool.FUList2.opList0] 763type=OpDesc 764eventq_index=0 765issueLat=1 766opClass=FloatAdd 767opLat=2 768 769[system.cpu1.fuPool.FUList2.opList1] 770type=OpDesc 771eventq_index=0 772issueLat=1 773opClass=FloatCmp 774opLat=2 775 776[system.cpu1.fuPool.FUList2.opList2] 777type=OpDesc 778eventq_index=0 779issueLat=1 780opClass=FloatCvt 781opLat=2 782 783[system.cpu1.fuPool.FUList3] 784type=FUDesc 785children=opList0 opList1 opList2 786count=2 787eventq_index=0 788opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 789 790[system.cpu1.fuPool.FUList3.opList0] 791type=OpDesc 792eventq_index=0 793issueLat=1 794opClass=FloatMult 795opLat=4 796 797[system.cpu1.fuPool.FUList3.opList1] 798type=OpDesc 799eventq_index=0 800issueLat=12 801opClass=FloatDiv 802opLat=12 803 804[system.cpu1.fuPool.FUList3.opList2] 805type=OpDesc 806eventq_index=0 807issueLat=24 808opClass=FloatSqrt 809opLat=24 810 811[system.cpu1.fuPool.FUList4] 812type=FUDesc 813children=opList 814count=0 815eventq_index=0 816opList=system.cpu1.fuPool.FUList4.opList 817 818[system.cpu1.fuPool.FUList4.opList] 819type=OpDesc 820eventq_index=0 821issueLat=1 822opClass=MemRead 823opLat=1 824 825[system.cpu1.fuPool.FUList5] 826type=FUDesc 827children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 828count=4 829eventq_index=0 830opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 831 832[system.cpu1.fuPool.FUList5.opList00] 833type=OpDesc 834eventq_index=0 835issueLat=1 836opClass=SimdAdd 837opLat=1 838 839[system.cpu1.fuPool.FUList5.opList01] 840type=OpDesc 841eventq_index=0 842issueLat=1 843opClass=SimdAddAcc 844opLat=1 845 846[system.cpu1.fuPool.FUList5.opList02] 847type=OpDesc 848eventq_index=0 849issueLat=1 850opClass=SimdAlu 851opLat=1 852 853[system.cpu1.fuPool.FUList5.opList03] 854type=OpDesc 855eventq_index=0 856issueLat=1 857opClass=SimdCmp 858opLat=1 859 860[system.cpu1.fuPool.FUList5.opList04] 861type=OpDesc 862eventq_index=0 863issueLat=1 864opClass=SimdCvt 865opLat=1 866 867[system.cpu1.fuPool.FUList5.opList05] 868type=OpDesc 869eventq_index=0 870issueLat=1 871opClass=SimdMisc 872opLat=1 873 874[system.cpu1.fuPool.FUList5.opList06] 875type=OpDesc 876eventq_index=0 877issueLat=1 878opClass=SimdMult 879opLat=1 880 881[system.cpu1.fuPool.FUList5.opList07] 882type=OpDesc 883eventq_index=0 884issueLat=1 885opClass=SimdMultAcc 886opLat=1 887 888[system.cpu1.fuPool.FUList5.opList08] 889type=OpDesc 890eventq_index=0 891issueLat=1 892opClass=SimdShift 893opLat=1 894 895[system.cpu1.fuPool.FUList5.opList09] 896type=OpDesc 897eventq_index=0 898issueLat=1 899opClass=SimdShiftAcc 900opLat=1 901 902[system.cpu1.fuPool.FUList5.opList10] 903type=OpDesc 904eventq_index=0 905issueLat=1 906opClass=SimdSqrt 907opLat=1 908 909[system.cpu1.fuPool.FUList5.opList11] 910type=OpDesc 911eventq_index=0 912issueLat=1 913opClass=SimdFloatAdd 914opLat=1 915 916[system.cpu1.fuPool.FUList5.opList12] 917type=OpDesc 918eventq_index=0 919issueLat=1 920opClass=SimdFloatAlu 921opLat=1 922 923[system.cpu1.fuPool.FUList5.opList13] 924type=OpDesc 925eventq_index=0 926issueLat=1 927opClass=SimdFloatCmp 928opLat=1 929 930[system.cpu1.fuPool.FUList5.opList14] 931type=OpDesc 932eventq_index=0 933issueLat=1 934opClass=SimdFloatCvt 935opLat=1 936 937[system.cpu1.fuPool.FUList5.opList15] 938type=OpDesc 939eventq_index=0 940issueLat=1 941opClass=SimdFloatDiv 942opLat=1 943 944[system.cpu1.fuPool.FUList5.opList16] 945type=OpDesc 946eventq_index=0 947issueLat=1 948opClass=SimdFloatMisc 949opLat=1 950 951[system.cpu1.fuPool.FUList5.opList17] 952type=OpDesc 953eventq_index=0 954issueLat=1 955opClass=SimdFloatMult 956opLat=1 957 958[system.cpu1.fuPool.FUList5.opList18] 959type=OpDesc 960eventq_index=0 961issueLat=1 962opClass=SimdFloatMultAcc 963opLat=1 964 965[system.cpu1.fuPool.FUList5.opList19] 966type=OpDesc 967eventq_index=0 968issueLat=1 969opClass=SimdFloatSqrt 970opLat=1 971 972[system.cpu1.fuPool.FUList6] 973type=FUDesc 974children=opList 975count=0 976eventq_index=0 977opList=system.cpu1.fuPool.FUList6.opList 978 979[system.cpu1.fuPool.FUList6.opList] 980type=OpDesc 981eventq_index=0 982issueLat=1 983opClass=MemWrite 984opLat=1 985 986[system.cpu1.fuPool.FUList7] 987type=FUDesc 988children=opList0 opList1 989count=4 990eventq_index=0 991opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 992 993[system.cpu1.fuPool.FUList7.opList0] 994type=OpDesc 995eventq_index=0 996issueLat=1 997opClass=MemRead 998opLat=1 999 1000[system.cpu1.fuPool.FUList7.opList1] 1001type=OpDesc 1002eventq_index=0 1003issueLat=1 1004opClass=MemWrite 1005opLat=1 1006 1007[system.cpu1.fuPool.FUList8] 1008type=FUDesc 1009children=opList 1010count=1 1011eventq_index=0 1012opList=system.cpu1.fuPool.FUList8.opList 1013 1014[system.cpu1.fuPool.FUList8.opList] 1015type=OpDesc 1016eventq_index=0 1017issueLat=3 1018opClass=IprAccess 1019opLat=3 1020 1021[system.cpu1.icache] 1022type=BaseCache 1023children=tags 1024addr_ranges=0:18446744073709551615 1025assoc=1 1026clk_domain=system.cpu_clk_domain 1027eventq_index=0 1028forward_snoops=true 1029hit_latency=2 1030is_top_level=true 1031max_miss_count=0 1032mshrs=4 1033prefetch_on_access=false 1034prefetcher=Null 1035response_latency=2 1036sequential_access=false 1037size=32768 1038system=system 1039tags=system.cpu1.icache.tags 1040tgts_per_mshr=20 1041two_queue=false 1042write_buffers=8 1043cpu_side=system.cpu1.icache_port 1044mem_side=system.toL2Bus.slave[2] 1045 1046[system.cpu1.icache.tags] 1047type=LRU 1048assoc=1 1049block_size=64 1050clk_domain=system.cpu_clk_domain 1051eventq_index=0 1052hit_latency=2 1053sequential_access=false 1054size=32768 1055 1056[system.cpu1.interrupts] 1057type=SparcInterrupts 1058eventq_index=0 1059 1060[system.cpu1.isa] 1061type=SparcISA 1062eventq_index=0 1063 1064[system.cpu1.itb] 1065type=SparcTLB 1066eventq_index=0 1067size=64 1068 1069[system.cpu1.tracer] 1070type=ExeTracer 1071eventq_index=0 1072 1073[system.cpu2] 1074type=DerivO3CPU 1075children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1076LFSTSize=1024 1077LQEntries=32 1078LSQCheckLoads=true 1079LSQDepCheckShift=4 1080SQEntries=32 1081SSITSize=1024 1082activity=0 1083backComSize=5 1084branchPred=system.cpu2.branchPred 1085cachePorts=200 1086checker=Null 1087clk_domain=system.cpu_clk_domain 1088commitToDecodeDelay=1 1089commitToFetchDelay=1 1090commitToIEWDelay=1 1091commitToRenameDelay=1 1092commitWidth=8 1093cpu_id=2 1094decodeToFetchDelay=1 1095decodeToRenameDelay=1 1096decodeWidth=8 1097dispatchWidth=8 1098do_checkpoint_insts=true 1099do_quiesce=true 1100do_statistics_insts=true 1101dtb=system.cpu2.dtb 1102eventq_index=0 1103fetchBufferSize=64 1104fetchToDecodeDelay=1 1105fetchTrapLatency=1 1106fetchWidth=8 1107forwardComSize=5 1108fuPool=system.cpu2.fuPool 1109function_trace=false 1110function_trace_start=0 1111iewToCommitDelay=1 1112iewToDecodeDelay=1 1113iewToFetchDelay=1 1114iewToRenameDelay=1 1115interrupts=system.cpu2.interrupts 1116isa=system.cpu2.isa 1117issueToExecuteDelay=1 1118issueWidth=8 1119itb=system.cpu2.itb 1120max_insts_all_threads=0 1121max_insts_any_thread=0 1122max_loads_all_threads=0 1123max_loads_any_thread=0 1124needsTSO=false 1125numIQEntries=64 1126numPhysCCRegs=0 1127numPhysFloatRegs=256 1128numPhysIntRegs=256 1129numROBEntries=192 1130numRobs=1 1131numThreads=1 1132profile=0 1133progress_interval=0 1134renameToDecodeDelay=1 1135renameToFetchDelay=1 1136renameToIEWDelay=2 1137renameToROBDelay=1 1138renameWidth=8 1139simpoint_start_insts= 1140smtCommitPolicy=RoundRobin 1141smtFetchPolicy=SingleThread 1142smtIQPolicy=Partitioned 1143smtIQThreshold=100 1144smtLSQPolicy=Partitioned 1145smtLSQThreshold=100 1146smtNumFetchingThreads=1 1147smtROBPolicy=Partitioned 1148smtROBThreshold=100 1149socket_id=0 1150squashWidth=8 1151store_set_clear_period=250000 1152switched_out=false 1153system=system 1154tracer=system.cpu2.tracer 1155trapLatency=13 1156wbDepth=1 1157wbWidth=8 1158workload=system.cpu0.workload 1159dcache_port=system.cpu2.dcache.cpu_side 1160icache_port=system.cpu2.icache.cpu_side 1161 1162[system.cpu2.branchPred] 1163type=BranchPredictor 1164BTBEntries=4096 1165BTBTagSize=16 1166RASSize=16 1167choiceCtrBits=2 1168choicePredictorSize=8192 1169eventq_index=0 1170globalCtrBits=2 1171globalPredictorSize=8192 1172instShiftAmt=2 1173localCtrBits=2 1174localHistoryTableSize=2048 1175localPredictorSize=2048 1176numThreads=1 1177predType=tournament 1178 1179[system.cpu2.dcache] 1180type=BaseCache 1181children=tags 1182addr_ranges=0:18446744073709551615 1183assoc=4 1184clk_domain=system.cpu_clk_domain 1185eventq_index=0 1186forward_snoops=true 1187hit_latency=2 1188is_top_level=true 1189max_miss_count=0 1190mshrs=4 1191prefetch_on_access=false 1192prefetcher=Null 1193response_latency=2 1194sequential_access=false 1195size=32768 1196system=system 1197tags=system.cpu2.dcache.tags 1198tgts_per_mshr=20 1199two_queue=false 1200write_buffers=8 1201cpu_side=system.cpu2.dcache_port 1202mem_side=system.toL2Bus.slave[5] 1203 1204[system.cpu2.dcache.tags] 1205type=LRU 1206assoc=4 1207block_size=64 1208clk_domain=system.cpu_clk_domain 1209eventq_index=0 1210hit_latency=2 1211sequential_access=false 1212size=32768 1213 1214[system.cpu2.dtb] 1215type=SparcTLB 1216eventq_index=0 1217size=64 1218 1219[system.cpu2.fuPool] 1220type=FUPool 1221children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1222FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1223eventq_index=0 1224 1225[system.cpu2.fuPool.FUList0] 1226type=FUDesc 1227children=opList 1228count=6 1229eventq_index=0 1230opList=system.cpu2.fuPool.FUList0.opList 1231 1232[system.cpu2.fuPool.FUList0.opList] 1233type=OpDesc 1234eventq_index=0 1235issueLat=1 1236opClass=IntAlu 1237opLat=1 1238 1239[system.cpu2.fuPool.FUList1] 1240type=FUDesc 1241children=opList0 opList1 1242count=2 1243eventq_index=0 1244opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1245 1246[system.cpu2.fuPool.FUList1.opList0] 1247type=OpDesc 1248eventq_index=0 1249issueLat=1 1250opClass=IntMult 1251opLat=3 1252 1253[system.cpu2.fuPool.FUList1.opList1] 1254type=OpDesc 1255eventq_index=0 1256issueLat=19 1257opClass=IntDiv 1258opLat=20 1259 1260[system.cpu2.fuPool.FUList2] 1261type=FUDesc 1262children=opList0 opList1 opList2 1263count=4 1264eventq_index=0 1265opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1266 1267[system.cpu2.fuPool.FUList2.opList0] 1268type=OpDesc 1269eventq_index=0 1270issueLat=1 1271opClass=FloatAdd 1272opLat=2 1273 1274[system.cpu2.fuPool.FUList2.opList1] 1275type=OpDesc 1276eventq_index=0 1277issueLat=1 1278opClass=FloatCmp 1279opLat=2 1280 1281[system.cpu2.fuPool.FUList2.opList2] 1282type=OpDesc 1283eventq_index=0 1284issueLat=1 1285opClass=FloatCvt 1286opLat=2 1287 1288[system.cpu2.fuPool.FUList3] 1289type=FUDesc 1290children=opList0 opList1 opList2 1291count=2 1292eventq_index=0 1293opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1294 1295[system.cpu2.fuPool.FUList3.opList0] 1296type=OpDesc 1297eventq_index=0 1298issueLat=1 1299opClass=FloatMult 1300opLat=4 1301 1302[system.cpu2.fuPool.FUList3.opList1] 1303type=OpDesc 1304eventq_index=0 1305issueLat=12 1306opClass=FloatDiv 1307opLat=12 1308 1309[system.cpu2.fuPool.FUList3.opList2] 1310type=OpDesc 1311eventq_index=0 1312issueLat=24 1313opClass=FloatSqrt 1314opLat=24 1315 1316[system.cpu2.fuPool.FUList4] 1317type=FUDesc 1318children=opList 1319count=0 1320eventq_index=0 1321opList=system.cpu2.fuPool.FUList4.opList 1322 1323[system.cpu2.fuPool.FUList4.opList] 1324type=OpDesc 1325eventq_index=0 1326issueLat=1 1327opClass=MemRead 1328opLat=1 1329 1330[system.cpu2.fuPool.FUList5] 1331type=FUDesc 1332children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1333count=4 1334eventq_index=0 1335opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1336 1337[system.cpu2.fuPool.FUList5.opList00] 1338type=OpDesc 1339eventq_index=0 1340issueLat=1 1341opClass=SimdAdd 1342opLat=1 1343 1344[system.cpu2.fuPool.FUList5.opList01] 1345type=OpDesc 1346eventq_index=0 1347issueLat=1 1348opClass=SimdAddAcc 1349opLat=1 1350 1351[system.cpu2.fuPool.FUList5.opList02] 1352type=OpDesc 1353eventq_index=0 1354issueLat=1 1355opClass=SimdAlu 1356opLat=1 1357 1358[system.cpu2.fuPool.FUList5.opList03] 1359type=OpDesc 1360eventq_index=0 1361issueLat=1 1362opClass=SimdCmp 1363opLat=1 1364 1365[system.cpu2.fuPool.FUList5.opList04] 1366type=OpDesc 1367eventq_index=0 1368issueLat=1 1369opClass=SimdCvt 1370opLat=1 1371 1372[system.cpu2.fuPool.FUList5.opList05] 1373type=OpDesc 1374eventq_index=0 1375issueLat=1 1376opClass=SimdMisc 1377opLat=1 1378 1379[system.cpu2.fuPool.FUList5.opList06] 1380type=OpDesc 1381eventq_index=0 1382issueLat=1 1383opClass=SimdMult 1384opLat=1 1385 1386[system.cpu2.fuPool.FUList5.opList07] 1387type=OpDesc 1388eventq_index=0 1389issueLat=1 1390opClass=SimdMultAcc 1391opLat=1 1392 1393[system.cpu2.fuPool.FUList5.opList08] 1394type=OpDesc 1395eventq_index=0 1396issueLat=1 1397opClass=SimdShift 1398opLat=1 1399 1400[system.cpu2.fuPool.FUList5.opList09] 1401type=OpDesc 1402eventq_index=0 1403issueLat=1 1404opClass=SimdShiftAcc 1405opLat=1 1406 1407[system.cpu2.fuPool.FUList5.opList10] 1408type=OpDesc 1409eventq_index=0 1410issueLat=1 1411opClass=SimdSqrt 1412opLat=1 1413 1414[system.cpu2.fuPool.FUList5.opList11] 1415type=OpDesc 1416eventq_index=0 1417issueLat=1 1418opClass=SimdFloatAdd 1419opLat=1 1420 1421[system.cpu2.fuPool.FUList5.opList12] 1422type=OpDesc 1423eventq_index=0 1424issueLat=1 1425opClass=SimdFloatAlu 1426opLat=1 1427 1428[system.cpu2.fuPool.FUList5.opList13] 1429type=OpDesc 1430eventq_index=0 1431issueLat=1 1432opClass=SimdFloatCmp 1433opLat=1 1434 1435[system.cpu2.fuPool.FUList5.opList14] 1436type=OpDesc 1437eventq_index=0 1438issueLat=1 1439opClass=SimdFloatCvt 1440opLat=1 1441 1442[system.cpu2.fuPool.FUList5.opList15] 1443type=OpDesc 1444eventq_index=0 1445issueLat=1 1446opClass=SimdFloatDiv 1447opLat=1 1448 1449[system.cpu2.fuPool.FUList5.opList16] 1450type=OpDesc 1451eventq_index=0 1452issueLat=1 1453opClass=SimdFloatMisc 1454opLat=1 1455 1456[system.cpu2.fuPool.FUList5.opList17] 1457type=OpDesc 1458eventq_index=0 1459issueLat=1 1460opClass=SimdFloatMult 1461opLat=1 1462 1463[system.cpu2.fuPool.FUList5.opList18] 1464type=OpDesc 1465eventq_index=0 1466issueLat=1 1467opClass=SimdFloatMultAcc 1468opLat=1 1469 1470[system.cpu2.fuPool.FUList5.opList19] 1471type=OpDesc 1472eventq_index=0 1473issueLat=1 1474opClass=SimdFloatSqrt 1475opLat=1 1476 1477[system.cpu2.fuPool.FUList6] 1478type=FUDesc 1479children=opList 1480count=0 1481eventq_index=0 1482opList=system.cpu2.fuPool.FUList6.opList 1483 1484[system.cpu2.fuPool.FUList6.opList] 1485type=OpDesc 1486eventq_index=0 1487issueLat=1 1488opClass=MemWrite 1489opLat=1 1490 1491[system.cpu2.fuPool.FUList7] 1492type=FUDesc 1493children=opList0 opList1 1494count=4 1495eventq_index=0 1496opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1497 1498[system.cpu2.fuPool.FUList7.opList0] 1499type=OpDesc 1500eventq_index=0 1501issueLat=1 1502opClass=MemRead 1503opLat=1 1504 1505[system.cpu2.fuPool.FUList7.opList1] 1506type=OpDesc 1507eventq_index=0 1508issueLat=1 1509opClass=MemWrite 1510opLat=1 1511 1512[system.cpu2.fuPool.FUList8] 1513type=FUDesc 1514children=opList 1515count=1 1516eventq_index=0 1517opList=system.cpu2.fuPool.FUList8.opList 1518 1519[system.cpu2.fuPool.FUList8.opList] 1520type=OpDesc 1521eventq_index=0 1522issueLat=3 1523opClass=IprAccess 1524opLat=3 1525 1526[system.cpu2.icache] 1527type=BaseCache 1528children=tags 1529addr_ranges=0:18446744073709551615 1530assoc=1 1531clk_domain=system.cpu_clk_domain 1532eventq_index=0 1533forward_snoops=true 1534hit_latency=2 1535is_top_level=true 1536max_miss_count=0 1537mshrs=4 1538prefetch_on_access=false 1539prefetcher=Null 1540response_latency=2 1541sequential_access=false 1542size=32768 1543system=system 1544tags=system.cpu2.icache.tags 1545tgts_per_mshr=20 1546two_queue=false 1547write_buffers=8 1548cpu_side=system.cpu2.icache_port 1549mem_side=system.toL2Bus.slave[4] 1550 1551[system.cpu2.icache.tags] 1552type=LRU 1553assoc=1 1554block_size=64 1555clk_domain=system.cpu_clk_domain 1556eventq_index=0 1557hit_latency=2 1558sequential_access=false 1559size=32768 1560 1561[system.cpu2.interrupts] 1562type=SparcInterrupts 1563eventq_index=0 1564 1565[system.cpu2.isa] 1566type=SparcISA 1567eventq_index=0 1568 1569[system.cpu2.itb] 1570type=SparcTLB 1571eventq_index=0 1572size=64 1573 1574[system.cpu2.tracer] 1575type=ExeTracer 1576eventq_index=0 1577 1578[system.cpu3] 1579type=DerivO3CPU 1580children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1581LFSTSize=1024 1582LQEntries=32 1583LSQCheckLoads=true 1584LSQDepCheckShift=4 1585SQEntries=32 1586SSITSize=1024 1587activity=0 1588backComSize=5 1589branchPred=system.cpu3.branchPred 1590cachePorts=200 1591checker=Null 1592clk_domain=system.cpu_clk_domain 1593commitToDecodeDelay=1 1594commitToFetchDelay=1 1595commitToIEWDelay=1 1596commitToRenameDelay=1 1597commitWidth=8 1598cpu_id=3 1599decodeToFetchDelay=1 1600decodeToRenameDelay=1 1601decodeWidth=8 1602dispatchWidth=8 1603do_checkpoint_insts=true 1604do_quiesce=true 1605do_statistics_insts=true 1606dtb=system.cpu3.dtb 1607eventq_index=0 1608fetchBufferSize=64 1609fetchToDecodeDelay=1 1610fetchTrapLatency=1 1611fetchWidth=8 1612forwardComSize=5 1613fuPool=system.cpu3.fuPool 1614function_trace=false 1615function_trace_start=0 1616iewToCommitDelay=1 1617iewToDecodeDelay=1 1618iewToFetchDelay=1 1619iewToRenameDelay=1 1620interrupts=system.cpu3.interrupts 1621isa=system.cpu3.isa 1622issueToExecuteDelay=1 1623issueWidth=8 1624itb=system.cpu3.itb 1625max_insts_all_threads=0 1626max_insts_any_thread=0 1627max_loads_all_threads=0 1628max_loads_any_thread=0 1629needsTSO=false 1630numIQEntries=64 1631numPhysCCRegs=0 1632numPhysFloatRegs=256 1633numPhysIntRegs=256 1634numROBEntries=192 1635numRobs=1 1636numThreads=1 1637profile=0 1638progress_interval=0 1639renameToDecodeDelay=1 1640renameToFetchDelay=1 1641renameToIEWDelay=2 1642renameToROBDelay=1 1643renameWidth=8 1644simpoint_start_insts= 1645smtCommitPolicy=RoundRobin 1646smtFetchPolicy=SingleThread 1647smtIQPolicy=Partitioned 1648smtIQThreshold=100 1649smtLSQPolicy=Partitioned 1650smtLSQThreshold=100 1651smtNumFetchingThreads=1 1652smtROBPolicy=Partitioned 1653smtROBThreshold=100 1654socket_id=0 1655squashWidth=8 1656store_set_clear_period=250000 1657switched_out=false 1658system=system 1659tracer=system.cpu3.tracer 1660trapLatency=13 1661wbDepth=1 1662wbWidth=8 1663workload=system.cpu0.workload 1664dcache_port=system.cpu3.dcache.cpu_side 1665icache_port=system.cpu3.icache.cpu_side 1666 1667[system.cpu3.branchPred] 1668type=BranchPredictor 1669BTBEntries=4096 1670BTBTagSize=16 1671RASSize=16 1672choiceCtrBits=2 1673choicePredictorSize=8192 1674eventq_index=0 1675globalCtrBits=2 1676globalPredictorSize=8192 1677instShiftAmt=2 1678localCtrBits=2 1679localHistoryTableSize=2048 1680localPredictorSize=2048 1681numThreads=1 1682predType=tournament 1683 1684[system.cpu3.dcache] 1685type=BaseCache 1686children=tags 1687addr_ranges=0:18446744073709551615 1688assoc=4 1689clk_domain=system.cpu_clk_domain 1690eventq_index=0 1691forward_snoops=true 1692hit_latency=2 1693is_top_level=true 1694max_miss_count=0 1695mshrs=4 1696prefetch_on_access=false 1697prefetcher=Null 1698response_latency=2 1699sequential_access=false 1700size=32768 1701system=system 1702tags=system.cpu3.dcache.tags 1703tgts_per_mshr=20 1704two_queue=false 1705write_buffers=8 1706cpu_side=system.cpu3.dcache_port 1707mem_side=system.toL2Bus.slave[7] 1708 1709[system.cpu3.dcache.tags] 1710type=LRU 1711assoc=4 1712block_size=64 1713clk_domain=system.cpu_clk_domain 1714eventq_index=0 1715hit_latency=2 1716sequential_access=false 1717size=32768 1718 1719[system.cpu3.dtb] 1720type=SparcTLB 1721eventq_index=0 1722size=64 1723 1724[system.cpu3.fuPool] 1725type=FUPool 1726children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1727FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1728eventq_index=0 1729 1730[system.cpu3.fuPool.FUList0] 1731type=FUDesc 1732children=opList 1733count=6 1734eventq_index=0 1735opList=system.cpu3.fuPool.FUList0.opList 1736 1737[system.cpu3.fuPool.FUList0.opList] 1738type=OpDesc 1739eventq_index=0 1740issueLat=1 1741opClass=IntAlu 1742opLat=1 1743 1744[system.cpu3.fuPool.FUList1] 1745type=FUDesc 1746children=opList0 opList1 1747count=2 1748eventq_index=0 1749opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1750 1751[system.cpu3.fuPool.FUList1.opList0] 1752type=OpDesc 1753eventq_index=0 1754issueLat=1 1755opClass=IntMult 1756opLat=3 1757 1758[system.cpu3.fuPool.FUList1.opList1] 1759type=OpDesc 1760eventq_index=0 1761issueLat=19 1762opClass=IntDiv 1763opLat=20 1764 1765[system.cpu3.fuPool.FUList2] 1766type=FUDesc 1767children=opList0 opList1 opList2 1768count=4 1769eventq_index=0 1770opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1771 1772[system.cpu3.fuPool.FUList2.opList0] 1773type=OpDesc 1774eventq_index=0 1775issueLat=1 1776opClass=FloatAdd 1777opLat=2 1778 1779[system.cpu3.fuPool.FUList2.opList1] 1780type=OpDesc 1781eventq_index=0 1782issueLat=1 1783opClass=FloatCmp 1784opLat=2 1785 1786[system.cpu3.fuPool.FUList2.opList2] 1787type=OpDesc 1788eventq_index=0 1789issueLat=1 1790opClass=FloatCvt 1791opLat=2 1792 1793[system.cpu3.fuPool.FUList3] 1794type=FUDesc 1795children=opList0 opList1 opList2 1796count=2 1797eventq_index=0 1798opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1799 1800[system.cpu3.fuPool.FUList3.opList0] 1801type=OpDesc 1802eventq_index=0 1803issueLat=1 1804opClass=FloatMult 1805opLat=4 1806 1807[system.cpu3.fuPool.FUList3.opList1] 1808type=OpDesc 1809eventq_index=0 1810issueLat=12 1811opClass=FloatDiv 1812opLat=12 1813 1814[system.cpu3.fuPool.FUList3.opList2] 1815type=OpDesc 1816eventq_index=0 1817issueLat=24 1818opClass=FloatSqrt 1819opLat=24 1820 1821[system.cpu3.fuPool.FUList4] 1822type=FUDesc 1823children=opList 1824count=0 1825eventq_index=0 1826opList=system.cpu3.fuPool.FUList4.opList 1827 1828[system.cpu3.fuPool.FUList4.opList] 1829type=OpDesc 1830eventq_index=0 1831issueLat=1 1832opClass=MemRead 1833opLat=1 1834 1835[system.cpu3.fuPool.FUList5] 1836type=FUDesc 1837children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1838count=4 1839eventq_index=0 1840opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1841 1842[system.cpu3.fuPool.FUList5.opList00] 1843type=OpDesc 1844eventq_index=0 1845issueLat=1 1846opClass=SimdAdd 1847opLat=1 1848 1849[system.cpu3.fuPool.FUList5.opList01] 1850type=OpDesc 1851eventq_index=0 1852issueLat=1 1853opClass=SimdAddAcc 1854opLat=1 1855 1856[system.cpu3.fuPool.FUList5.opList02] 1857type=OpDesc 1858eventq_index=0 1859issueLat=1 1860opClass=SimdAlu 1861opLat=1 1862 1863[system.cpu3.fuPool.FUList5.opList03] 1864type=OpDesc 1865eventq_index=0 1866issueLat=1 1867opClass=SimdCmp 1868opLat=1 1869 1870[system.cpu3.fuPool.FUList5.opList04] 1871type=OpDesc 1872eventq_index=0 1873issueLat=1 1874opClass=SimdCvt 1875opLat=1 1876 1877[system.cpu3.fuPool.FUList5.opList05] 1878type=OpDesc 1879eventq_index=0 1880issueLat=1 1881opClass=SimdMisc 1882opLat=1 1883 1884[system.cpu3.fuPool.FUList5.opList06] 1885type=OpDesc 1886eventq_index=0 1887issueLat=1 1888opClass=SimdMult 1889opLat=1 1890 1891[system.cpu3.fuPool.FUList5.opList07] 1892type=OpDesc 1893eventq_index=0 1894issueLat=1 1895opClass=SimdMultAcc 1896opLat=1 1897 1898[system.cpu3.fuPool.FUList5.opList08] 1899type=OpDesc 1900eventq_index=0 1901issueLat=1 1902opClass=SimdShift 1903opLat=1 1904 1905[system.cpu3.fuPool.FUList5.opList09] 1906type=OpDesc 1907eventq_index=0 1908issueLat=1 1909opClass=SimdShiftAcc 1910opLat=1 1911 1912[system.cpu3.fuPool.FUList5.opList10] 1913type=OpDesc 1914eventq_index=0 1915issueLat=1 1916opClass=SimdSqrt 1917opLat=1 1918 1919[system.cpu3.fuPool.FUList5.opList11] 1920type=OpDesc 1921eventq_index=0 1922issueLat=1 1923opClass=SimdFloatAdd 1924opLat=1 1925 1926[system.cpu3.fuPool.FUList5.opList12] 1927type=OpDesc 1928eventq_index=0 1929issueLat=1 1930opClass=SimdFloatAlu 1931opLat=1 1932 1933[system.cpu3.fuPool.FUList5.opList13] 1934type=OpDesc 1935eventq_index=0 1936issueLat=1 1937opClass=SimdFloatCmp 1938opLat=1 1939 1940[system.cpu3.fuPool.FUList5.opList14] 1941type=OpDesc 1942eventq_index=0 1943issueLat=1 1944opClass=SimdFloatCvt 1945opLat=1 1946 1947[system.cpu3.fuPool.FUList5.opList15] 1948type=OpDesc 1949eventq_index=0 1950issueLat=1 1951opClass=SimdFloatDiv 1952opLat=1 1953 1954[system.cpu3.fuPool.FUList5.opList16] 1955type=OpDesc 1956eventq_index=0 1957issueLat=1 1958opClass=SimdFloatMisc 1959opLat=1 1960 1961[system.cpu3.fuPool.FUList5.opList17] 1962type=OpDesc 1963eventq_index=0 1964issueLat=1 1965opClass=SimdFloatMult 1966opLat=1 1967 1968[system.cpu3.fuPool.FUList5.opList18] 1969type=OpDesc 1970eventq_index=0 1971issueLat=1 1972opClass=SimdFloatMultAcc 1973opLat=1 1974 1975[system.cpu3.fuPool.FUList5.opList19] 1976type=OpDesc 1977eventq_index=0 1978issueLat=1 1979opClass=SimdFloatSqrt 1980opLat=1 1981 1982[system.cpu3.fuPool.FUList6] 1983type=FUDesc 1984children=opList 1985count=0 1986eventq_index=0 1987opList=system.cpu3.fuPool.FUList6.opList 1988 1989[system.cpu3.fuPool.FUList6.opList] 1990type=OpDesc 1991eventq_index=0 1992issueLat=1 1993opClass=MemWrite 1994opLat=1 1995 1996[system.cpu3.fuPool.FUList7] 1997type=FUDesc 1998children=opList0 opList1 1999count=4 2000eventq_index=0 2001opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 2002 2003[system.cpu3.fuPool.FUList7.opList0] 2004type=OpDesc 2005eventq_index=0 2006issueLat=1 2007opClass=MemRead 2008opLat=1 2009 2010[system.cpu3.fuPool.FUList7.opList1] 2011type=OpDesc 2012eventq_index=0 2013issueLat=1 2014opClass=MemWrite 2015opLat=1 2016 2017[system.cpu3.fuPool.FUList8] 2018type=FUDesc 2019children=opList 2020count=1 2021eventq_index=0 2022opList=system.cpu3.fuPool.FUList8.opList 2023 2024[system.cpu3.fuPool.FUList8.opList] 2025type=OpDesc 2026eventq_index=0 2027issueLat=3 2028opClass=IprAccess 2029opLat=3 2030 2031[system.cpu3.icache] 2032type=BaseCache 2033children=tags 2034addr_ranges=0:18446744073709551615 2035assoc=1 2036clk_domain=system.cpu_clk_domain 2037eventq_index=0 2038forward_snoops=true 2039hit_latency=2 2040is_top_level=true 2041max_miss_count=0 2042mshrs=4 2043prefetch_on_access=false 2044prefetcher=Null 2045response_latency=2 2046sequential_access=false 2047size=32768 2048system=system 2049tags=system.cpu3.icache.tags 2050tgts_per_mshr=20 2051two_queue=false 2052write_buffers=8 2053cpu_side=system.cpu3.icache_port 2054mem_side=system.toL2Bus.slave[6] 2055 2056[system.cpu3.icache.tags] 2057type=LRU 2058assoc=1 2059block_size=64 2060clk_domain=system.cpu_clk_domain 2061eventq_index=0 2062hit_latency=2 2063sequential_access=false 2064size=32768 2065 2066[system.cpu3.interrupts] 2067type=SparcInterrupts 2068eventq_index=0 2069 2070[system.cpu3.isa] 2071type=SparcISA 2072eventq_index=0 2073 2074[system.cpu3.itb] 2075type=SparcTLB 2076eventq_index=0 2077size=64 2078 2079[system.cpu3.tracer] 2080type=ExeTracer 2081eventq_index=0 2082 2083[system.cpu_clk_domain] 2084type=SrcClockDomain 2085clock=500 2086eventq_index=0 2087voltage_domain=system.voltage_domain 2088 2089[system.l2c] 2090type=BaseCache 2091children=tags 2092addr_ranges=0:18446744073709551615 2093assoc=8 2094clk_domain=system.cpu_clk_domain 2095eventq_index=0 2096forward_snoops=true 2097hit_latency=20 2098is_top_level=false 2099max_miss_count=0 2100mshrs=20 2101prefetch_on_access=false 2102prefetcher=Null 2103response_latency=20 2104sequential_access=false 2105size=4194304 2106system=system 2107tags=system.l2c.tags 2108tgts_per_mshr=12 2109two_queue=false 2110write_buffers=8 2111cpu_side=system.toL2Bus.master[0] 2112mem_side=system.membus.slave[1] 2113 2114[system.l2c.tags] 2115type=LRU 2116assoc=8 2117block_size=64 2118clk_domain=system.cpu_clk_domain 2119eventq_index=0 2120hit_latency=20 2121sequential_access=false 2122size=4194304 2123 2124[system.membus] 2125type=CoherentBus 2126clk_domain=system.clk_domain 2127eventq_index=0 2128header_cycles=1 2129system=system 2130use_default_range=false 2131width=8 2132master=system.physmem.port 2133slave=system.system_port system.l2c.mem_side 2134 2135[system.physmem] 2136type=DRAMCtrl 2137activation_limit=4 2138addr_mapping=RoRaBaChCo 2139banks_per_rank=8 2140burst_length=8 2141channels=1 2142clk_domain=system.clk_domain 2143conf_table_reported=true 2144device_bus_width=8 2145device_rowbuffer_size=1024 2146devices_per_rank=8 2147eventq_index=0 2148in_addr_map=true 2149max_accesses_per_row=16 2150mem_sched_policy=frfcfs 2151min_writes_per_switch=16 2152null=false 2153page_policy=open_adaptive 2154range=0:134217727 2155ranks_per_channel=2 2156read_buffer_size=32 2157static_backend_latency=10000 2158static_frontend_latency=10000 2159tBURST=5000 2160tCK=1250 2161tCL=13750 2162tRAS=35000 2163tRCD=13750 2164tREFI=7800000 2165tRFC=260000 2166tRP=13750 2167tRRD=6000 2168tRTP=7500 2169tRTW=2500 2170tWR=15000 2171tWTR=7500 2172tXAW=30000 2173write_buffer_size=64 2174write_high_thresh_perc=85 2175write_low_thresh_perc=50 2176port=system.membus.master[0] 2177 2178[system.toL2Bus] 2179type=CoherentBus 2180clk_domain=system.cpu_clk_domain 2181eventq_index=0 2182header_cycles=1 2183system=system 2184use_default_range=false 2185width=8 2186master=system.l2c.cpu_side 2187slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2188 2189[system.voltage_domain] 2190type=VoltageDomain 2191eventq_index=0 2192voltage=1.000000 2193 2194