config.ini revision 10036
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= 26symbolfile= 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.clk_domain] 37type=SrcClockDomain 38clock=1000 39eventq_index=0 40voltage_domain=system.voltage_domain 41 42[system.cpu0] 43type=DerivO3CPU 44children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 45LFSTSize=1024 46LQEntries=32 47LSQCheckLoads=true 48LSQDepCheckShift=4 49SQEntries=32 50SSITSize=1024 51activity=0 52backComSize=5 53branchPred=system.cpu0.branchPred 54cachePorts=200 55checker=Null 56clk_domain=system.cpu_clk_domain 57commitToDecodeDelay=1 58commitToFetchDelay=1 59commitToIEWDelay=1 60commitToRenameDelay=1 61commitWidth=8 62cpu_id=0 63decodeToFetchDelay=1 64decodeToRenameDelay=1 65decodeWidth=8 66dispatchWidth=8 67do_checkpoint_insts=true 68do_quiesce=true 69do_statistics_insts=true 70dtb=system.cpu0.dtb 71eventq_index=0 72fetchBufferSize=64 73fetchToDecodeDelay=1 74fetchTrapLatency=1 75fetchWidth=8 76forwardComSize=5 77fuPool=system.cpu0.fuPool 78function_trace=false 79function_trace_start=0 80iewToCommitDelay=1 81iewToDecodeDelay=1 82iewToFetchDelay=1 83iewToRenameDelay=1 84interrupts=system.cpu0.interrupts 85isa=system.cpu0.isa 86issueToExecuteDelay=1 87issueWidth=8 88itb=system.cpu0.itb 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=false 94numIQEntries=64 95numPhysCCRegs=0 96numPhysFloatRegs=256 97numPhysIntRegs=256 98numROBEntries=192 99numRobs=1 100numThreads=1 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108simpoint_start_insts= 109smtCommitPolicy=RoundRobin 110smtFetchPolicy=SingleThread 111smtIQPolicy=Partitioned 112smtIQThreshold=100 113smtLSQPolicy=Partitioned 114smtLSQThreshold=100 115smtNumFetchingThreads=1 116smtROBPolicy=Partitioned 117smtROBThreshold=100 118squashWidth=8 119store_set_clear_period=250000 120switched_out=false 121system=system 122tracer=system.cpu0.tracer 123trapLatency=13 124wbDepth=1 125wbWidth=8 126workload=system.cpu0.workload 127dcache_port=system.cpu0.dcache.cpu_side 128icache_port=system.cpu0.icache.cpu_side 129 130[system.cpu0.branchPred] 131type=BranchPredictor 132BTBEntries=4096 133BTBTagSize=16 134RASSize=16 135choiceCtrBits=2 136choicePredictorSize=8192 137eventq_index=0 138globalCtrBits=2 139globalPredictorSize=8192 140instShiftAmt=2 141localCtrBits=2 142localHistoryTableSize=2048 143localPredictorSize=2048 144numThreads=1 145predType=tournament 146 147[system.cpu0.dcache] 148type=BaseCache 149children=tags 150addr_ranges=0:18446744073709551615 151assoc=4 152clk_domain=system.cpu_clk_domain 153eventq_index=0 154forward_snoops=true 155hit_latency=2 156is_top_level=true 157max_miss_count=0 158mshrs=4 159prefetch_on_access=false 160prefetcher=Null 161response_latency=2 162sequential_access=false 163size=32768 164system=system 165tags=system.cpu0.dcache.tags 166tgts_per_mshr=20 167two_queue=false 168write_buffers=8 169cpu_side=system.cpu0.dcache_port 170mem_side=system.toL2Bus.slave[1] 171 172[system.cpu0.dcache.tags] 173type=LRU 174assoc=4 175block_size=64 176clk_domain=system.cpu_clk_domain 177eventq_index=0 178hit_latency=2 179sequential_access=false 180size=32768 181 182[system.cpu0.dtb] 183type=SparcTLB 184eventq_index=0 185size=64 186 187[system.cpu0.fuPool] 188type=FUPool 189children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 190FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 191eventq_index=0 192 193[system.cpu0.fuPool.FUList0] 194type=FUDesc 195children=opList 196count=6 197eventq_index=0 198opList=system.cpu0.fuPool.FUList0.opList 199 200[system.cpu0.fuPool.FUList0.opList] 201type=OpDesc 202eventq_index=0 203issueLat=1 204opClass=IntAlu 205opLat=1 206 207[system.cpu0.fuPool.FUList1] 208type=FUDesc 209children=opList0 opList1 210count=2 211eventq_index=0 212opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 213 214[system.cpu0.fuPool.FUList1.opList0] 215type=OpDesc 216eventq_index=0 217issueLat=1 218opClass=IntMult 219opLat=3 220 221[system.cpu0.fuPool.FUList1.opList1] 222type=OpDesc 223eventq_index=0 224issueLat=19 225opClass=IntDiv 226opLat=20 227 228[system.cpu0.fuPool.FUList2] 229type=FUDesc 230children=opList0 opList1 opList2 231count=4 232eventq_index=0 233opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 234 235[system.cpu0.fuPool.FUList2.opList0] 236type=OpDesc 237eventq_index=0 238issueLat=1 239opClass=FloatAdd 240opLat=2 241 242[system.cpu0.fuPool.FUList2.opList1] 243type=OpDesc 244eventq_index=0 245issueLat=1 246opClass=FloatCmp 247opLat=2 248 249[system.cpu0.fuPool.FUList2.opList2] 250type=OpDesc 251eventq_index=0 252issueLat=1 253opClass=FloatCvt 254opLat=2 255 256[system.cpu0.fuPool.FUList3] 257type=FUDesc 258children=opList0 opList1 opList2 259count=2 260eventq_index=0 261opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 262 263[system.cpu0.fuPool.FUList3.opList0] 264type=OpDesc 265eventq_index=0 266issueLat=1 267opClass=FloatMult 268opLat=4 269 270[system.cpu0.fuPool.FUList3.opList1] 271type=OpDesc 272eventq_index=0 273issueLat=12 274opClass=FloatDiv 275opLat=12 276 277[system.cpu0.fuPool.FUList3.opList2] 278type=OpDesc 279eventq_index=0 280issueLat=24 281opClass=FloatSqrt 282opLat=24 283 284[system.cpu0.fuPool.FUList4] 285type=FUDesc 286children=opList 287count=0 288eventq_index=0 289opList=system.cpu0.fuPool.FUList4.opList 290 291[system.cpu0.fuPool.FUList4.opList] 292type=OpDesc 293eventq_index=0 294issueLat=1 295opClass=MemRead 296opLat=1 297 298[system.cpu0.fuPool.FUList5] 299type=FUDesc 300children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 301count=4 302eventq_index=0 303opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 304 305[system.cpu0.fuPool.FUList5.opList00] 306type=OpDesc 307eventq_index=0 308issueLat=1 309opClass=SimdAdd 310opLat=1 311 312[system.cpu0.fuPool.FUList5.opList01] 313type=OpDesc 314eventq_index=0 315issueLat=1 316opClass=SimdAddAcc 317opLat=1 318 319[system.cpu0.fuPool.FUList5.opList02] 320type=OpDesc 321eventq_index=0 322issueLat=1 323opClass=SimdAlu 324opLat=1 325 326[system.cpu0.fuPool.FUList5.opList03] 327type=OpDesc 328eventq_index=0 329issueLat=1 330opClass=SimdCmp 331opLat=1 332 333[system.cpu0.fuPool.FUList5.opList04] 334type=OpDesc 335eventq_index=0 336issueLat=1 337opClass=SimdCvt 338opLat=1 339 340[system.cpu0.fuPool.FUList5.opList05] 341type=OpDesc 342eventq_index=0 343issueLat=1 344opClass=SimdMisc 345opLat=1 346 347[system.cpu0.fuPool.FUList5.opList06] 348type=OpDesc 349eventq_index=0 350issueLat=1 351opClass=SimdMult 352opLat=1 353 354[system.cpu0.fuPool.FUList5.opList07] 355type=OpDesc 356eventq_index=0 357issueLat=1 358opClass=SimdMultAcc 359opLat=1 360 361[system.cpu0.fuPool.FUList5.opList08] 362type=OpDesc 363eventq_index=0 364issueLat=1 365opClass=SimdShift 366opLat=1 367 368[system.cpu0.fuPool.FUList5.opList09] 369type=OpDesc 370eventq_index=0 371issueLat=1 372opClass=SimdShiftAcc 373opLat=1 374 375[system.cpu0.fuPool.FUList5.opList10] 376type=OpDesc 377eventq_index=0 378issueLat=1 379opClass=SimdSqrt 380opLat=1 381 382[system.cpu0.fuPool.FUList5.opList11] 383type=OpDesc 384eventq_index=0 385issueLat=1 386opClass=SimdFloatAdd 387opLat=1 388 389[system.cpu0.fuPool.FUList5.opList12] 390type=OpDesc 391eventq_index=0 392issueLat=1 393opClass=SimdFloatAlu 394opLat=1 395 396[system.cpu0.fuPool.FUList5.opList13] 397type=OpDesc 398eventq_index=0 399issueLat=1 400opClass=SimdFloatCmp 401opLat=1 402 403[system.cpu0.fuPool.FUList5.opList14] 404type=OpDesc 405eventq_index=0 406issueLat=1 407opClass=SimdFloatCvt 408opLat=1 409 410[system.cpu0.fuPool.FUList5.opList15] 411type=OpDesc 412eventq_index=0 413issueLat=1 414opClass=SimdFloatDiv 415opLat=1 416 417[system.cpu0.fuPool.FUList5.opList16] 418type=OpDesc 419eventq_index=0 420issueLat=1 421opClass=SimdFloatMisc 422opLat=1 423 424[system.cpu0.fuPool.FUList5.opList17] 425type=OpDesc 426eventq_index=0 427issueLat=1 428opClass=SimdFloatMult 429opLat=1 430 431[system.cpu0.fuPool.FUList5.opList18] 432type=OpDesc 433eventq_index=0 434issueLat=1 435opClass=SimdFloatMultAcc 436opLat=1 437 438[system.cpu0.fuPool.FUList5.opList19] 439type=OpDesc 440eventq_index=0 441issueLat=1 442opClass=SimdFloatSqrt 443opLat=1 444 445[system.cpu0.fuPool.FUList6] 446type=FUDesc 447children=opList 448count=0 449eventq_index=0 450opList=system.cpu0.fuPool.FUList6.opList 451 452[system.cpu0.fuPool.FUList6.opList] 453type=OpDesc 454eventq_index=0 455issueLat=1 456opClass=MemWrite 457opLat=1 458 459[system.cpu0.fuPool.FUList7] 460type=FUDesc 461children=opList0 opList1 462count=4 463eventq_index=0 464opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 465 466[system.cpu0.fuPool.FUList7.opList0] 467type=OpDesc 468eventq_index=0 469issueLat=1 470opClass=MemRead 471opLat=1 472 473[system.cpu0.fuPool.FUList7.opList1] 474type=OpDesc 475eventq_index=0 476issueLat=1 477opClass=MemWrite 478opLat=1 479 480[system.cpu0.fuPool.FUList8] 481type=FUDesc 482children=opList 483count=1 484eventq_index=0 485opList=system.cpu0.fuPool.FUList8.opList 486 487[system.cpu0.fuPool.FUList8.opList] 488type=OpDesc 489eventq_index=0 490issueLat=3 491opClass=IprAccess 492opLat=3 493 494[system.cpu0.icache] 495type=BaseCache 496children=tags 497addr_ranges=0:18446744073709551615 498assoc=1 499clk_domain=system.cpu_clk_domain 500eventq_index=0 501forward_snoops=true 502hit_latency=2 503is_top_level=true 504max_miss_count=0 505mshrs=4 506prefetch_on_access=false 507prefetcher=Null 508response_latency=2 509sequential_access=false 510size=32768 511system=system 512tags=system.cpu0.icache.tags 513tgts_per_mshr=20 514two_queue=false 515write_buffers=8 516cpu_side=system.cpu0.icache_port 517mem_side=system.toL2Bus.slave[0] 518 519[system.cpu0.icache.tags] 520type=LRU 521assoc=1 522block_size=64 523clk_domain=system.cpu_clk_domain 524eventq_index=0 525hit_latency=2 526sequential_access=false 527size=32768 528 529[system.cpu0.interrupts] 530type=SparcInterrupts 531eventq_index=0 532 533[system.cpu0.isa] 534type=SparcISA 535eventq_index=0 536 537[system.cpu0.itb] 538type=SparcTLB 539eventq_index=0 540size=64 541 542[system.cpu0.tracer] 543type=ExeTracer 544eventq_index=0 545 546[system.cpu0.workload] 547type=LiveProcess 548cmd=test_atomic 4 549cwd= 550egid=100 551env= 552errout=cerr 553euid=100 554eventq_index=0 555executable=/dist/test-progs/m5threads/bin/sparc/linux/test_atomic 556gid=100 557input=cin 558max_stack_size=67108864 559output=cout 560pid=100 561ppid=99 562simpoint=0 563system=system 564uid=100 565 566[system.cpu1] 567type=DerivO3CPU 568children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 569LFSTSize=1024 570LQEntries=32 571LSQCheckLoads=true 572LSQDepCheckShift=4 573SQEntries=32 574SSITSize=1024 575activity=0 576backComSize=5 577branchPred=system.cpu1.branchPred 578cachePorts=200 579checker=Null 580clk_domain=system.cpu_clk_domain 581commitToDecodeDelay=1 582commitToFetchDelay=1 583commitToIEWDelay=1 584commitToRenameDelay=1 585commitWidth=8 586cpu_id=1 587decodeToFetchDelay=1 588decodeToRenameDelay=1 589decodeWidth=8 590dispatchWidth=8 591do_checkpoint_insts=true 592do_quiesce=true 593do_statistics_insts=true 594dtb=system.cpu1.dtb 595eventq_index=0 596fetchBufferSize=64 597fetchToDecodeDelay=1 598fetchTrapLatency=1 599fetchWidth=8 600forwardComSize=5 601fuPool=system.cpu1.fuPool 602function_trace=false 603function_trace_start=0 604iewToCommitDelay=1 605iewToDecodeDelay=1 606iewToFetchDelay=1 607iewToRenameDelay=1 608interrupts=system.cpu1.interrupts 609isa=system.cpu1.isa 610issueToExecuteDelay=1 611issueWidth=8 612itb=system.cpu1.itb 613max_insts_all_threads=0 614max_insts_any_thread=0 615max_loads_all_threads=0 616max_loads_any_thread=0 617needsTSO=false 618numIQEntries=64 619numPhysCCRegs=0 620numPhysFloatRegs=256 621numPhysIntRegs=256 622numROBEntries=192 623numRobs=1 624numThreads=1 625profile=0 626progress_interval=0 627renameToDecodeDelay=1 628renameToFetchDelay=1 629renameToIEWDelay=2 630renameToROBDelay=1 631renameWidth=8 632simpoint_start_insts= 633smtCommitPolicy=RoundRobin 634smtFetchPolicy=SingleThread 635smtIQPolicy=Partitioned 636smtIQThreshold=100 637smtLSQPolicy=Partitioned 638smtLSQThreshold=100 639smtNumFetchingThreads=1 640smtROBPolicy=Partitioned 641smtROBThreshold=100 642squashWidth=8 643store_set_clear_period=250000 644switched_out=false 645system=system 646tracer=system.cpu1.tracer 647trapLatency=13 648wbDepth=1 649wbWidth=8 650workload=system.cpu0.workload 651dcache_port=system.cpu1.dcache.cpu_side 652icache_port=system.cpu1.icache.cpu_side 653 654[system.cpu1.branchPred] 655type=BranchPredictor 656BTBEntries=4096 657BTBTagSize=16 658RASSize=16 659choiceCtrBits=2 660choicePredictorSize=8192 661eventq_index=0 662globalCtrBits=2 663globalPredictorSize=8192 664instShiftAmt=2 665localCtrBits=2 666localHistoryTableSize=2048 667localPredictorSize=2048 668numThreads=1 669predType=tournament 670 671[system.cpu1.dcache] 672type=BaseCache 673children=tags 674addr_ranges=0:18446744073709551615 675assoc=4 676clk_domain=system.cpu_clk_domain 677eventq_index=0 678forward_snoops=true 679hit_latency=2 680is_top_level=true 681max_miss_count=0 682mshrs=4 683prefetch_on_access=false 684prefetcher=Null 685response_latency=2 686sequential_access=false 687size=32768 688system=system 689tags=system.cpu1.dcache.tags 690tgts_per_mshr=20 691two_queue=false 692write_buffers=8 693cpu_side=system.cpu1.dcache_port 694mem_side=system.toL2Bus.slave[3] 695 696[system.cpu1.dcache.tags] 697type=LRU 698assoc=4 699block_size=64 700clk_domain=system.cpu_clk_domain 701eventq_index=0 702hit_latency=2 703sequential_access=false 704size=32768 705 706[system.cpu1.dtb] 707type=SparcTLB 708eventq_index=0 709size=64 710 711[system.cpu1.fuPool] 712type=FUPool 713children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 714FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 715eventq_index=0 716 717[system.cpu1.fuPool.FUList0] 718type=FUDesc 719children=opList 720count=6 721eventq_index=0 722opList=system.cpu1.fuPool.FUList0.opList 723 724[system.cpu1.fuPool.FUList0.opList] 725type=OpDesc 726eventq_index=0 727issueLat=1 728opClass=IntAlu 729opLat=1 730 731[system.cpu1.fuPool.FUList1] 732type=FUDesc 733children=opList0 opList1 734count=2 735eventq_index=0 736opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 737 738[system.cpu1.fuPool.FUList1.opList0] 739type=OpDesc 740eventq_index=0 741issueLat=1 742opClass=IntMult 743opLat=3 744 745[system.cpu1.fuPool.FUList1.opList1] 746type=OpDesc 747eventq_index=0 748issueLat=19 749opClass=IntDiv 750opLat=20 751 752[system.cpu1.fuPool.FUList2] 753type=FUDesc 754children=opList0 opList1 opList2 755count=4 756eventq_index=0 757opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 758 759[system.cpu1.fuPool.FUList2.opList0] 760type=OpDesc 761eventq_index=0 762issueLat=1 763opClass=FloatAdd 764opLat=2 765 766[system.cpu1.fuPool.FUList2.opList1] 767type=OpDesc 768eventq_index=0 769issueLat=1 770opClass=FloatCmp 771opLat=2 772 773[system.cpu1.fuPool.FUList2.opList2] 774type=OpDesc 775eventq_index=0 776issueLat=1 777opClass=FloatCvt 778opLat=2 779 780[system.cpu1.fuPool.FUList3] 781type=FUDesc 782children=opList0 opList1 opList2 783count=2 784eventq_index=0 785opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 786 787[system.cpu1.fuPool.FUList3.opList0] 788type=OpDesc 789eventq_index=0 790issueLat=1 791opClass=FloatMult 792opLat=4 793 794[system.cpu1.fuPool.FUList3.opList1] 795type=OpDesc 796eventq_index=0 797issueLat=12 798opClass=FloatDiv 799opLat=12 800 801[system.cpu1.fuPool.FUList3.opList2] 802type=OpDesc 803eventq_index=0 804issueLat=24 805opClass=FloatSqrt 806opLat=24 807 808[system.cpu1.fuPool.FUList4] 809type=FUDesc 810children=opList 811count=0 812eventq_index=0 813opList=system.cpu1.fuPool.FUList4.opList 814 815[system.cpu1.fuPool.FUList4.opList] 816type=OpDesc 817eventq_index=0 818issueLat=1 819opClass=MemRead 820opLat=1 821 822[system.cpu1.fuPool.FUList5] 823type=FUDesc 824children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 825count=4 826eventq_index=0 827opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 828 829[system.cpu1.fuPool.FUList5.opList00] 830type=OpDesc 831eventq_index=0 832issueLat=1 833opClass=SimdAdd 834opLat=1 835 836[system.cpu1.fuPool.FUList5.opList01] 837type=OpDesc 838eventq_index=0 839issueLat=1 840opClass=SimdAddAcc 841opLat=1 842 843[system.cpu1.fuPool.FUList5.opList02] 844type=OpDesc 845eventq_index=0 846issueLat=1 847opClass=SimdAlu 848opLat=1 849 850[system.cpu1.fuPool.FUList5.opList03] 851type=OpDesc 852eventq_index=0 853issueLat=1 854opClass=SimdCmp 855opLat=1 856 857[system.cpu1.fuPool.FUList5.opList04] 858type=OpDesc 859eventq_index=0 860issueLat=1 861opClass=SimdCvt 862opLat=1 863 864[system.cpu1.fuPool.FUList5.opList05] 865type=OpDesc 866eventq_index=0 867issueLat=1 868opClass=SimdMisc 869opLat=1 870 871[system.cpu1.fuPool.FUList5.opList06] 872type=OpDesc 873eventq_index=0 874issueLat=1 875opClass=SimdMult 876opLat=1 877 878[system.cpu1.fuPool.FUList5.opList07] 879type=OpDesc 880eventq_index=0 881issueLat=1 882opClass=SimdMultAcc 883opLat=1 884 885[system.cpu1.fuPool.FUList5.opList08] 886type=OpDesc 887eventq_index=0 888issueLat=1 889opClass=SimdShift 890opLat=1 891 892[system.cpu1.fuPool.FUList5.opList09] 893type=OpDesc 894eventq_index=0 895issueLat=1 896opClass=SimdShiftAcc 897opLat=1 898 899[system.cpu1.fuPool.FUList5.opList10] 900type=OpDesc 901eventq_index=0 902issueLat=1 903opClass=SimdSqrt 904opLat=1 905 906[system.cpu1.fuPool.FUList5.opList11] 907type=OpDesc 908eventq_index=0 909issueLat=1 910opClass=SimdFloatAdd 911opLat=1 912 913[system.cpu1.fuPool.FUList5.opList12] 914type=OpDesc 915eventq_index=0 916issueLat=1 917opClass=SimdFloatAlu 918opLat=1 919 920[system.cpu1.fuPool.FUList5.opList13] 921type=OpDesc 922eventq_index=0 923issueLat=1 924opClass=SimdFloatCmp 925opLat=1 926 927[system.cpu1.fuPool.FUList5.opList14] 928type=OpDesc 929eventq_index=0 930issueLat=1 931opClass=SimdFloatCvt 932opLat=1 933 934[system.cpu1.fuPool.FUList5.opList15] 935type=OpDesc 936eventq_index=0 937issueLat=1 938opClass=SimdFloatDiv 939opLat=1 940 941[system.cpu1.fuPool.FUList5.opList16] 942type=OpDesc 943eventq_index=0 944issueLat=1 945opClass=SimdFloatMisc 946opLat=1 947 948[system.cpu1.fuPool.FUList5.opList17] 949type=OpDesc 950eventq_index=0 951issueLat=1 952opClass=SimdFloatMult 953opLat=1 954 955[system.cpu1.fuPool.FUList5.opList18] 956type=OpDesc 957eventq_index=0 958issueLat=1 959opClass=SimdFloatMultAcc 960opLat=1 961 962[system.cpu1.fuPool.FUList5.opList19] 963type=OpDesc 964eventq_index=0 965issueLat=1 966opClass=SimdFloatSqrt 967opLat=1 968 969[system.cpu1.fuPool.FUList6] 970type=FUDesc 971children=opList 972count=0 973eventq_index=0 974opList=system.cpu1.fuPool.FUList6.opList 975 976[system.cpu1.fuPool.FUList6.opList] 977type=OpDesc 978eventq_index=0 979issueLat=1 980opClass=MemWrite 981opLat=1 982 983[system.cpu1.fuPool.FUList7] 984type=FUDesc 985children=opList0 opList1 986count=4 987eventq_index=0 988opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 989 990[system.cpu1.fuPool.FUList7.opList0] 991type=OpDesc 992eventq_index=0 993issueLat=1 994opClass=MemRead 995opLat=1 996 997[system.cpu1.fuPool.FUList7.opList1] 998type=OpDesc 999eventq_index=0 1000issueLat=1 1001opClass=MemWrite 1002opLat=1 1003 1004[system.cpu1.fuPool.FUList8] 1005type=FUDesc 1006children=opList 1007count=1 1008eventq_index=0 1009opList=system.cpu1.fuPool.FUList8.opList 1010 1011[system.cpu1.fuPool.FUList8.opList] 1012type=OpDesc 1013eventq_index=0 1014issueLat=3 1015opClass=IprAccess 1016opLat=3 1017 1018[system.cpu1.icache] 1019type=BaseCache 1020children=tags 1021addr_ranges=0:18446744073709551615 1022assoc=1 1023clk_domain=system.cpu_clk_domain 1024eventq_index=0 1025forward_snoops=true 1026hit_latency=2 1027is_top_level=true 1028max_miss_count=0 1029mshrs=4 1030prefetch_on_access=false 1031prefetcher=Null 1032response_latency=2 1033sequential_access=false 1034size=32768 1035system=system 1036tags=system.cpu1.icache.tags 1037tgts_per_mshr=20 1038two_queue=false 1039write_buffers=8 1040cpu_side=system.cpu1.icache_port 1041mem_side=system.toL2Bus.slave[2] 1042 1043[system.cpu1.icache.tags] 1044type=LRU 1045assoc=1 1046block_size=64 1047clk_domain=system.cpu_clk_domain 1048eventq_index=0 1049hit_latency=2 1050sequential_access=false 1051size=32768 1052 1053[system.cpu1.interrupts] 1054type=SparcInterrupts 1055eventq_index=0 1056 1057[system.cpu1.isa] 1058type=SparcISA 1059eventq_index=0 1060 1061[system.cpu1.itb] 1062type=SparcTLB 1063eventq_index=0 1064size=64 1065 1066[system.cpu1.tracer] 1067type=ExeTracer 1068eventq_index=0 1069 1070[system.cpu2] 1071type=DerivO3CPU 1072children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1073LFSTSize=1024 1074LQEntries=32 1075LSQCheckLoads=true 1076LSQDepCheckShift=4 1077SQEntries=32 1078SSITSize=1024 1079activity=0 1080backComSize=5 1081branchPred=system.cpu2.branchPred 1082cachePorts=200 1083checker=Null 1084clk_domain=system.cpu_clk_domain 1085commitToDecodeDelay=1 1086commitToFetchDelay=1 1087commitToIEWDelay=1 1088commitToRenameDelay=1 1089commitWidth=8 1090cpu_id=2 1091decodeToFetchDelay=1 1092decodeToRenameDelay=1 1093decodeWidth=8 1094dispatchWidth=8 1095do_checkpoint_insts=true 1096do_quiesce=true 1097do_statistics_insts=true 1098dtb=system.cpu2.dtb 1099eventq_index=0 1100fetchBufferSize=64 1101fetchToDecodeDelay=1 1102fetchTrapLatency=1 1103fetchWidth=8 1104forwardComSize=5 1105fuPool=system.cpu2.fuPool 1106function_trace=false 1107function_trace_start=0 1108iewToCommitDelay=1 1109iewToDecodeDelay=1 1110iewToFetchDelay=1 1111iewToRenameDelay=1 1112interrupts=system.cpu2.interrupts 1113isa=system.cpu2.isa 1114issueToExecuteDelay=1 1115issueWidth=8 1116itb=system.cpu2.itb 1117max_insts_all_threads=0 1118max_insts_any_thread=0 1119max_loads_all_threads=0 1120max_loads_any_thread=0 1121needsTSO=false 1122numIQEntries=64 1123numPhysCCRegs=0 1124numPhysFloatRegs=256 1125numPhysIntRegs=256 1126numROBEntries=192 1127numRobs=1 1128numThreads=1 1129profile=0 1130progress_interval=0 1131renameToDecodeDelay=1 1132renameToFetchDelay=1 1133renameToIEWDelay=2 1134renameToROBDelay=1 1135renameWidth=8 1136simpoint_start_insts= 1137smtCommitPolicy=RoundRobin 1138smtFetchPolicy=SingleThread 1139smtIQPolicy=Partitioned 1140smtIQThreshold=100 1141smtLSQPolicy=Partitioned 1142smtLSQThreshold=100 1143smtNumFetchingThreads=1 1144smtROBPolicy=Partitioned 1145smtROBThreshold=100 1146squashWidth=8 1147store_set_clear_period=250000 1148switched_out=false 1149system=system 1150tracer=system.cpu2.tracer 1151trapLatency=13 1152wbDepth=1 1153wbWidth=8 1154workload=system.cpu0.workload 1155dcache_port=system.cpu2.dcache.cpu_side 1156icache_port=system.cpu2.icache.cpu_side 1157 1158[system.cpu2.branchPred] 1159type=BranchPredictor 1160BTBEntries=4096 1161BTBTagSize=16 1162RASSize=16 1163choiceCtrBits=2 1164choicePredictorSize=8192 1165eventq_index=0 1166globalCtrBits=2 1167globalPredictorSize=8192 1168instShiftAmt=2 1169localCtrBits=2 1170localHistoryTableSize=2048 1171localPredictorSize=2048 1172numThreads=1 1173predType=tournament 1174 1175[system.cpu2.dcache] 1176type=BaseCache 1177children=tags 1178addr_ranges=0:18446744073709551615 1179assoc=4 1180clk_domain=system.cpu_clk_domain 1181eventq_index=0 1182forward_snoops=true 1183hit_latency=2 1184is_top_level=true 1185max_miss_count=0 1186mshrs=4 1187prefetch_on_access=false 1188prefetcher=Null 1189response_latency=2 1190sequential_access=false 1191size=32768 1192system=system 1193tags=system.cpu2.dcache.tags 1194tgts_per_mshr=20 1195two_queue=false 1196write_buffers=8 1197cpu_side=system.cpu2.dcache_port 1198mem_side=system.toL2Bus.slave[5] 1199 1200[system.cpu2.dcache.tags] 1201type=LRU 1202assoc=4 1203block_size=64 1204clk_domain=system.cpu_clk_domain 1205eventq_index=0 1206hit_latency=2 1207sequential_access=false 1208size=32768 1209 1210[system.cpu2.dtb] 1211type=SparcTLB 1212eventq_index=0 1213size=64 1214 1215[system.cpu2.fuPool] 1216type=FUPool 1217children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1218FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1219eventq_index=0 1220 1221[system.cpu2.fuPool.FUList0] 1222type=FUDesc 1223children=opList 1224count=6 1225eventq_index=0 1226opList=system.cpu2.fuPool.FUList0.opList 1227 1228[system.cpu2.fuPool.FUList0.opList] 1229type=OpDesc 1230eventq_index=0 1231issueLat=1 1232opClass=IntAlu 1233opLat=1 1234 1235[system.cpu2.fuPool.FUList1] 1236type=FUDesc 1237children=opList0 opList1 1238count=2 1239eventq_index=0 1240opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1241 1242[system.cpu2.fuPool.FUList1.opList0] 1243type=OpDesc 1244eventq_index=0 1245issueLat=1 1246opClass=IntMult 1247opLat=3 1248 1249[system.cpu2.fuPool.FUList1.opList1] 1250type=OpDesc 1251eventq_index=0 1252issueLat=19 1253opClass=IntDiv 1254opLat=20 1255 1256[system.cpu2.fuPool.FUList2] 1257type=FUDesc 1258children=opList0 opList1 opList2 1259count=4 1260eventq_index=0 1261opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1262 1263[system.cpu2.fuPool.FUList2.opList0] 1264type=OpDesc 1265eventq_index=0 1266issueLat=1 1267opClass=FloatAdd 1268opLat=2 1269 1270[system.cpu2.fuPool.FUList2.opList1] 1271type=OpDesc 1272eventq_index=0 1273issueLat=1 1274opClass=FloatCmp 1275opLat=2 1276 1277[system.cpu2.fuPool.FUList2.opList2] 1278type=OpDesc 1279eventq_index=0 1280issueLat=1 1281opClass=FloatCvt 1282opLat=2 1283 1284[system.cpu2.fuPool.FUList3] 1285type=FUDesc 1286children=opList0 opList1 opList2 1287count=2 1288eventq_index=0 1289opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1290 1291[system.cpu2.fuPool.FUList3.opList0] 1292type=OpDesc 1293eventq_index=0 1294issueLat=1 1295opClass=FloatMult 1296opLat=4 1297 1298[system.cpu2.fuPool.FUList3.opList1] 1299type=OpDesc 1300eventq_index=0 1301issueLat=12 1302opClass=FloatDiv 1303opLat=12 1304 1305[system.cpu2.fuPool.FUList3.opList2] 1306type=OpDesc 1307eventq_index=0 1308issueLat=24 1309opClass=FloatSqrt 1310opLat=24 1311 1312[system.cpu2.fuPool.FUList4] 1313type=FUDesc 1314children=opList 1315count=0 1316eventq_index=0 1317opList=system.cpu2.fuPool.FUList4.opList 1318 1319[system.cpu2.fuPool.FUList4.opList] 1320type=OpDesc 1321eventq_index=0 1322issueLat=1 1323opClass=MemRead 1324opLat=1 1325 1326[system.cpu2.fuPool.FUList5] 1327type=FUDesc 1328children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1329count=4 1330eventq_index=0 1331opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1332 1333[system.cpu2.fuPool.FUList5.opList00] 1334type=OpDesc 1335eventq_index=0 1336issueLat=1 1337opClass=SimdAdd 1338opLat=1 1339 1340[system.cpu2.fuPool.FUList5.opList01] 1341type=OpDesc 1342eventq_index=0 1343issueLat=1 1344opClass=SimdAddAcc 1345opLat=1 1346 1347[system.cpu2.fuPool.FUList5.opList02] 1348type=OpDesc 1349eventq_index=0 1350issueLat=1 1351opClass=SimdAlu 1352opLat=1 1353 1354[system.cpu2.fuPool.FUList5.opList03] 1355type=OpDesc 1356eventq_index=0 1357issueLat=1 1358opClass=SimdCmp 1359opLat=1 1360 1361[system.cpu2.fuPool.FUList5.opList04] 1362type=OpDesc 1363eventq_index=0 1364issueLat=1 1365opClass=SimdCvt 1366opLat=1 1367 1368[system.cpu2.fuPool.FUList5.opList05] 1369type=OpDesc 1370eventq_index=0 1371issueLat=1 1372opClass=SimdMisc 1373opLat=1 1374 1375[system.cpu2.fuPool.FUList5.opList06] 1376type=OpDesc 1377eventq_index=0 1378issueLat=1 1379opClass=SimdMult 1380opLat=1 1381 1382[system.cpu2.fuPool.FUList5.opList07] 1383type=OpDesc 1384eventq_index=0 1385issueLat=1 1386opClass=SimdMultAcc 1387opLat=1 1388 1389[system.cpu2.fuPool.FUList5.opList08] 1390type=OpDesc 1391eventq_index=0 1392issueLat=1 1393opClass=SimdShift 1394opLat=1 1395 1396[system.cpu2.fuPool.FUList5.opList09] 1397type=OpDesc 1398eventq_index=0 1399issueLat=1 1400opClass=SimdShiftAcc 1401opLat=1 1402 1403[system.cpu2.fuPool.FUList5.opList10] 1404type=OpDesc 1405eventq_index=0 1406issueLat=1 1407opClass=SimdSqrt 1408opLat=1 1409 1410[system.cpu2.fuPool.FUList5.opList11] 1411type=OpDesc 1412eventq_index=0 1413issueLat=1 1414opClass=SimdFloatAdd 1415opLat=1 1416 1417[system.cpu2.fuPool.FUList5.opList12] 1418type=OpDesc 1419eventq_index=0 1420issueLat=1 1421opClass=SimdFloatAlu 1422opLat=1 1423 1424[system.cpu2.fuPool.FUList5.opList13] 1425type=OpDesc 1426eventq_index=0 1427issueLat=1 1428opClass=SimdFloatCmp 1429opLat=1 1430 1431[system.cpu2.fuPool.FUList5.opList14] 1432type=OpDesc 1433eventq_index=0 1434issueLat=1 1435opClass=SimdFloatCvt 1436opLat=1 1437 1438[system.cpu2.fuPool.FUList5.opList15] 1439type=OpDesc 1440eventq_index=0 1441issueLat=1 1442opClass=SimdFloatDiv 1443opLat=1 1444 1445[system.cpu2.fuPool.FUList5.opList16] 1446type=OpDesc 1447eventq_index=0 1448issueLat=1 1449opClass=SimdFloatMisc 1450opLat=1 1451 1452[system.cpu2.fuPool.FUList5.opList17] 1453type=OpDesc 1454eventq_index=0 1455issueLat=1 1456opClass=SimdFloatMult 1457opLat=1 1458 1459[system.cpu2.fuPool.FUList5.opList18] 1460type=OpDesc 1461eventq_index=0 1462issueLat=1 1463opClass=SimdFloatMultAcc 1464opLat=1 1465 1466[system.cpu2.fuPool.FUList5.opList19] 1467type=OpDesc 1468eventq_index=0 1469issueLat=1 1470opClass=SimdFloatSqrt 1471opLat=1 1472 1473[system.cpu2.fuPool.FUList6] 1474type=FUDesc 1475children=opList 1476count=0 1477eventq_index=0 1478opList=system.cpu2.fuPool.FUList6.opList 1479 1480[system.cpu2.fuPool.FUList6.opList] 1481type=OpDesc 1482eventq_index=0 1483issueLat=1 1484opClass=MemWrite 1485opLat=1 1486 1487[system.cpu2.fuPool.FUList7] 1488type=FUDesc 1489children=opList0 opList1 1490count=4 1491eventq_index=0 1492opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1493 1494[system.cpu2.fuPool.FUList7.opList0] 1495type=OpDesc 1496eventq_index=0 1497issueLat=1 1498opClass=MemRead 1499opLat=1 1500 1501[system.cpu2.fuPool.FUList7.opList1] 1502type=OpDesc 1503eventq_index=0 1504issueLat=1 1505opClass=MemWrite 1506opLat=1 1507 1508[system.cpu2.fuPool.FUList8] 1509type=FUDesc 1510children=opList 1511count=1 1512eventq_index=0 1513opList=system.cpu2.fuPool.FUList8.opList 1514 1515[system.cpu2.fuPool.FUList8.opList] 1516type=OpDesc 1517eventq_index=0 1518issueLat=3 1519opClass=IprAccess 1520opLat=3 1521 1522[system.cpu2.icache] 1523type=BaseCache 1524children=tags 1525addr_ranges=0:18446744073709551615 1526assoc=1 1527clk_domain=system.cpu_clk_domain 1528eventq_index=0 1529forward_snoops=true 1530hit_latency=2 1531is_top_level=true 1532max_miss_count=0 1533mshrs=4 1534prefetch_on_access=false 1535prefetcher=Null 1536response_latency=2 1537sequential_access=false 1538size=32768 1539system=system 1540tags=system.cpu2.icache.tags 1541tgts_per_mshr=20 1542two_queue=false 1543write_buffers=8 1544cpu_side=system.cpu2.icache_port 1545mem_side=system.toL2Bus.slave[4] 1546 1547[system.cpu2.icache.tags] 1548type=LRU 1549assoc=1 1550block_size=64 1551clk_domain=system.cpu_clk_domain 1552eventq_index=0 1553hit_latency=2 1554sequential_access=false 1555size=32768 1556 1557[system.cpu2.interrupts] 1558type=SparcInterrupts 1559eventq_index=0 1560 1561[system.cpu2.isa] 1562type=SparcISA 1563eventq_index=0 1564 1565[system.cpu2.itb] 1566type=SparcTLB 1567eventq_index=0 1568size=64 1569 1570[system.cpu2.tracer] 1571type=ExeTracer 1572eventq_index=0 1573 1574[system.cpu3] 1575type=DerivO3CPU 1576children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1577LFSTSize=1024 1578LQEntries=32 1579LSQCheckLoads=true 1580LSQDepCheckShift=4 1581SQEntries=32 1582SSITSize=1024 1583activity=0 1584backComSize=5 1585branchPred=system.cpu3.branchPred 1586cachePorts=200 1587checker=Null 1588clk_domain=system.cpu_clk_domain 1589commitToDecodeDelay=1 1590commitToFetchDelay=1 1591commitToIEWDelay=1 1592commitToRenameDelay=1 1593commitWidth=8 1594cpu_id=3 1595decodeToFetchDelay=1 1596decodeToRenameDelay=1 1597decodeWidth=8 1598dispatchWidth=8 1599do_checkpoint_insts=true 1600do_quiesce=true 1601do_statistics_insts=true 1602dtb=system.cpu3.dtb 1603eventq_index=0 1604fetchBufferSize=64 1605fetchToDecodeDelay=1 1606fetchTrapLatency=1 1607fetchWidth=8 1608forwardComSize=5 1609fuPool=system.cpu3.fuPool 1610function_trace=false 1611function_trace_start=0 1612iewToCommitDelay=1 1613iewToDecodeDelay=1 1614iewToFetchDelay=1 1615iewToRenameDelay=1 1616interrupts=system.cpu3.interrupts 1617isa=system.cpu3.isa 1618issueToExecuteDelay=1 1619issueWidth=8 1620itb=system.cpu3.itb 1621max_insts_all_threads=0 1622max_insts_any_thread=0 1623max_loads_all_threads=0 1624max_loads_any_thread=0 1625needsTSO=false 1626numIQEntries=64 1627numPhysCCRegs=0 1628numPhysFloatRegs=256 1629numPhysIntRegs=256 1630numROBEntries=192 1631numRobs=1 1632numThreads=1 1633profile=0 1634progress_interval=0 1635renameToDecodeDelay=1 1636renameToFetchDelay=1 1637renameToIEWDelay=2 1638renameToROBDelay=1 1639renameWidth=8 1640simpoint_start_insts= 1641smtCommitPolicy=RoundRobin 1642smtFetchPolicy=SingleThread 1643smtIQPolicy=Partitioned 1644smtIQThreshold=100 1645smtLSQPolicy=Partitioned 1646smtLSQThreshold=100 1647smtNumFetchingThreads=1 1648smtROBPolicy=Partitioned 1649smtROBThreshold=100 1650squashWidth=8 1651store_set_clear_period=250000 1652switched_out=false 1653system=system 1654tracer=system.cpu3.tracer 1655trapLatency=13 1656wbDepth=1 1657wbWidth=8 1658workload=system.cpu0.workload 1659dcache_port=system.cpu3.dcache.cpu_side 1660icache_port=system.cpu3.icache.cpu_side 1661 1662[system.cpu3.branchPred] 1663type=BranchPredictor 1664BTBEntries=4096 1665BTBTagSize=16 1666RASSize=16 1667choiceCtrBits=2 1668choicePredictorSize=8192 1669eventq_index=0 1670globalCtrBits=2 1671globalPredictorSize=8192 1672instShiftAmt=2 1673localCtrBits=2 1674localHistoryTableSize=2048 1675localPredictorSize=2048 1676numThreads=1 1677predType=tournament 1678 1679[system.cpu3.dcache] 1680type=BaseCache 1681children=tags 1682addr_ranges=0:18446744073709551615 1683assoc=4 1684clk_domain=system.cpu_clk_domain 1685eventq_index=0 1686forward_snoops=true 1687hit_latency=2 1688is_top_level=true 1689max_miss_count=0 1690mshrs=4 1691prefetch_on_access=false 1692prefetcher=Null 1693response_latency=2 1694sequential_access=false 1695size=32768 1696system=system 1697tags=system.cpu3.dcache.tags 1698tgts_per_mshr=20 1699two_queue=false 1700write_buffers=8 1701cpu_side=system.cpu3.dcache_port 1702mem_side=system.toL2Bus.slave[7] 1703 1704[system.cpu3.dcache.tags] 1705type=LRU 1706assoc=4 1707block_size=64 1708clk_domain=system.cpu_clk_domain 1709eventq_index=0 1710hit_latency=2 1711sequential_access=false 1712size=32768 1713 1714[system.cpu3.dtb] 1715type=SparcTLB 1716eventq_index=0 1717size=64 1718 1719[system.cpu3.fuPool] 1720type=FUPool 1721children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1722FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1723eventq_index=0 1724 1725[system.cpu3.fuPool.FUList0] 1726type=FUDesc 1727children=opList 1728count=6 1729eventq_index=0 1730opList=system.cpu3.fuPool.FUList0.opList 1731 1732[system.cpu3.fuPool.FUList0.opList] 1733type=OpDesc 1734eventq_index=0 1735issueLat=1 1736opClass=IntAlu 1737opLat=1 1738 1739[system.cpu3.fuPool.FUList1] 1740type=FUDesc 1741children=opList0 opList1 1742count=2 1743eventq_index=0 1744opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1745 1746[system.cpu3.fuPool.FUList1.opList0] 1747type=OpDesc 1748eventq_index=0 1749issueLat=1 1750opClass=IntMult 1751opLat=3 1752 1753[system.cpu3.fuPool.FUList1.opList1] 1754type=OpDesc 1755eventq_index=0 1756issueLat=19 1757opClass=IntDiv 1758opLat=20 1759 1760[system.cpu3.fuPool.FUList2] 1761type=FUDesc 1762children=opList0 opList1 opList2 1763count=4 1764eventq_index=0 1765opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1766 1767[system.cpu3.fuPool.FUList2.opList0] 1768type=OpDesc 1769eventq_index=0 1770issueLat=1 1771opClass=FloatAdd 1772opLat=2 1773 1774[system.cpu3.fuPool.FUList2.opList1] 1775type=OpDesc 1776eventq_index=0 1777issueLat=1 1778opClass=FloatCmp 1779opLat=2 1780 1781[system.cpu3.fuPool.FUList2.opList2] 1782type=OpDesc 1783eventq_index=0 1784issueLat=1 1785opClass=FloatCvt 1786opLat=2 1787 1788[system.cpu3.fuPool.FUList3] 1789type=FUDesc 1790children=opList0 opList1 opList2 1791count=2 1792eventq_index=0 1793opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1794 1795[system.cpu3.fuPool.FUList3.opList0] 1796type=OpDesc 1797eventq_index=0 1798issueLat=1 1799opClass=FloatMult 1800opLat=4 1801 1802[system.cpu3.fuPool.FUList3.opList1] 1803type=OpDesc 1804eventq_index=0 1805issueLat=12 1806opClass=FloatDiv 1807opLat=12 1808 1809[system.cpu3.fuPool.FUList3.opList2] 1810type=OpDesc 1811eventq_index=0 1812issueLat=24 1813opClass=FloatSqrt 1814opLat=24 1815 1816[system.cpu3.fuPool.FUList4] 1817type=FUDesc 1818children=opList 1819count=0 1820eventq_index=0 1821opList=system.cpu3.fuPool.FUList4.opList 1822 1823[system.cpu3.fuPool.FUList4.opList] 1824type=OpDesc 1825eventq_index=0 1826issueLat=1 1827opClass=MemRead 1828opLat=1 1829 1830[system.cpu3.fuPool.FUList5] 1831type=FUDesc 1832children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1833count=4 1834eventq_index=0 1835opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1836 1837[system.cpu3.fuPool.FUList5.opList00] 1838type=OpDesc 1839eventq_index=0 1840issueLat=1 1841opClass=SimdAdd 1842opLat=1 1843 1844[system.cpu3.fuPool.FUList5.opList01] 1845type=OpDesc 1846eventq_index=0 1847issueLat=1 1848opClass=SimdAddAcc 1849opLat=1 1850 1851[system.cpu3.fuPool.FUList5.opList02] 1852type=OpDesc 1853eventq_index=0 1854issueLat=1 1855opClass=SimdAlu 1856opLat=1 1857 1858[system.cpu3.fuPool.FUList5.opList03] 1859type=OpDesc 1860eventq_index=0 1861issueLat=1 1862opClass=SimdCmp 1863opLat=1 1864 1865[system.cpu3.fuPool.FUList5.opList04] 1866type=OpDesc 1867eventq_index=0 1868issueLat=1 1869opClass=SimdCvt 1870opLat=1 1871 1872[system.cpu3.fuPool.FUList5.opList05] 1873type=OpDesc 1874eventq_index=0 1875issueLat=1 1876opClass=SimdMisc 1877opLat=1 1878 1879[system.cpu3.fuPool.FUList5.opList06] 1880type=OpDesc 1881eventq_index=0 1882issueLat=1 1883opClass=SimdMult 1884opLat=1 1885 1886[system.cpu3.fuPool.FUList5.opList07] 1887type=OpDesc 1888eventq_index=0 1889issueLat=1 1890opClass=SimdMultAcc 1891opLat=1 1892 1893[system.cpu3.fuPool.FUList5.opList08] 1894type=OpDesc 1895eventq_index=0 1896issueLat=1 1897opClass=SimdShift 1898opLat=1 1899 1900[system.cpu3.fuPool.FUList5.opList09] 1901type=OpDesc 1902eventq_index=0 1903issueLat=1 1904opClass=SimdShiftAcc 1905opLat=1 1906 1907[system.cpu3.fuPool.FUList5.opList10] 1908type=OpDesc 1909eventq_index=0 1910issueLat=1 1911opClass=SimdSqrt 1912opLat=1 1913 1914[system.cpu3.fuPool.FUList5.opList11] 1915type=OpDesc 1916eventq_index=0 1917issueLat=1 1918opClass=SimdFloatAdd 1919opLat=1 1920 1921[system.cpu3.fuPool.FUList5.opList12] 1922type=OpDesc 1923eventq_index=0 1924issueLat=1 1925opClass=SimdFloatAlu 1926opLat=1 1927 1928[system.cpu3.fuPool.FUList5.opList13] 1929type=OpDesc 1930eventq_index=0 1931issueLat=1 1932opClass=SimdFloatCmp 1933opLat=1 1934 1935[system.cpu3.fuPool.FUList5.opList14] 1936type=OpDesc 1937eventq_index=0 1938issueLat=1 1939opClass=SimdFloatCvt 1940opLat=1 1941 1942[system.cpu3.fuPool.FUList5.opList15] 1943type=OpDesc 1944eventq_index=0 1945issueLat=1 1946opClass=SimdFloatDiv 1947opLat=1 1948 1949[system.cpu3.fuPool.FUList5.opList16] 1950type=OpDesc 1951eventq_index=0 1952issueLat=1 1953opClass=SimdFloatMisc 1954opLat=1 1955 1956[system.cpu3.fuPool.FUList5.opList17] 1957type=OpDesc 1958eventq_index=0 1959issueLat=1 1960opClass=SimdFloatMult 1961opLat=1 1962 1963[system.cpu3.fuPool.FUList5.opList18] 1964type=OpDesc 1965eventq_index=0 1966issueLat=1 1967opClass=SimdFloatMultAcc 1968opLat=1 1969 1970[system.cpu3.fuPool.FUList5.opList19] 1971type=OpDesc 1972eventq_index=0 1973issueLat=1 1974opClass=SimdFloatSqrt 1975opLat=1 1976 1977[system.cpu3.fuPool.FUList6] 1978type=FUDesc 1979children=opList 1980count=0 1981eventq_index=0 1982opList=system.cpu3.fuPool.FUList6.opList 1983 1984[system.cpu3.fuPool.FUList6.opList] 1985type=OpDesc 1986eventq_index=0 1987issueLat=1 1988opClass=MemWrite 1989opLat=1 1990 1991[system.cpu3.fuPool.FUList7] 1992type=FUDesc 1993children=opList0 opList1 1994count=4 1995eventq_index=0 1996opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 1997 1998[system.cpu3.fuPool.FUList7.opList0] 1999type=OpDesc 2000eventq_index=0 2001issueLat=1 2002opClass=MemRead 2003opLat=1 2004 2005[system.cpu3.fuPool.FUList7.opList1] 2006type=OpDesc 2007eventq_index=0 2008issueLat=1 2009opClass=MemWrite 2010opLat=1 2011 2012[system.cpu3.fuPool.FUList8] 2013type=FUDesc 2014children=opList 2015count=1 2016eventq_index=0 2017opList=system.cpu3.fuPool.FUList8.opList 2018 2019[system.cpu3.fuPool.FUList8.opList] 2020type=OpDesc 2021eventq_index=0 2022issueLat=3 2023opClass=IprAccess 2024opLat=3 2025 2026[system.cpu3.icache] 2027type=BaseCache 2028children=tags 2029addr_ranges=0:18446744073709551615 2030assoc=1 2031clk_domain=system.cpu_clk_domain 2032eventq_index=0 2033forward_snoops=true 2034hit_latency=2 2035is_top_level=true 2036max_miss_count=0 2037mshrs=4 2038prefetch_on_access=false 2039prefetcher=Null 2040response_latency=2 2041sequential_access=false 2042size=32768 2043system=system 2044tags=system.cpu3.icache.tags 2045tgts_per_mshr=20 2046two_queue=false 2047write_buffers=8 2048cpu_side=system.cpu3.icache_port 2049mem_side=system.toL2Bus.slave[6] 2050 2051[system.cpu3.icache.tags] 2052type=LRU 2053assoc=1 2054block_size=64 2055clk_domain=system.cpu_clk_domain 2056eventq_index=0 2057hit_latency=2 2058sequential_access=false 2059size=32768 2060 2061[system.cpu3.interrupts] 2062type=SparcInterrupts 2063eventq_index=0 2064 2065[system.cpu3.isa] 2066type=SparcISA 2067eventq_index=0 2068 2069[system.cpu3.itb] 2070type=SparcTLB 2071eventq_index=0 2072size=64 2073 2074[system.cpu3.tracer] 2075type=ExeTracer 2076eventq_index=0 2077 2078[system.cpu_clk_domain] 2079type=SrcClockDomain 2080clock=500 2081eventq_index=0 2082voltage_domain=system.voltage_domain 2083 2084[system.l2c] 2085type=BaseCache 2086children=tags 2087addr_ranges=0:18446744073709551615 2088assoc=8 2089clk_domain=system.cpu_clk_domain 2090eventq_index=0 2091forward_snoops=true 2092hit_latency=20 2093is_top_level=false 2094max_miss_count=0 2095mshrs=20 2096prefetch_on_access=false 2097prefetcher=Null 2098response_latency=20 2099sequential_access=false 2100size=4194304 2101system=system 2102tags=system.l2c.tags 2103tgts_per_mshr=12 2104two_queue=false 2105write_buffers=8 2106cpu_side=system.toL2Bus.master[0] 2107mem_side=system.membus.slave[1] 2108 2109[system.l2c.tags] 2110type=LRU 2111assoc=8 2112block_size=64 2113clk_domain=system.cpu_clk_domain 2114eventq_index=0 2115hit_latency=20 2116sequential_access=false 2117size=4194304 2118 2119[system.membus] 2120type=CoherentBus 2121clk_domain=system.clk_domain 2122eventq_index=0 2123header_cycles=1 2124system=system 2125use_default_range=false 2126width=8 2127master=system.physmem.port 2128slave=system.system_port system.l2c.mem_side 2129 2130[system.physmem] 2131type=SimpleDRAM 2132activation_limit=4 2133addr_mapping=RaBaChCo 2134banks_per_rank=8 2135burst_length=8 2136channels=1 2137clk_domain=system.clk_domain 2138conf_table_reported=true 2139device_bus_width=8 2140device_rowbuffer_size=1024 2141devices_per_rank=8 2142eventq_index=0 2143in_addr_map=true 2144mem_sched_policy=frfcfs 2145null=false 2146page_policy=open 2147range=0:134217727 2148ranks_per_channel=2 2149read_buffer_size=32 2150static_backend_latency=10000 2151static_frontend_latency=10000 2152tBURST=5000 2153tCL=13750 2154tRAS=35000 2155tRCD=13750 2156tREFI=7800000 2157tRFC=300000 2158tRP=13750 2159tRRD=6250 2160tWTR=7500 2161tXAW=40000 2162write_buffer_size=32 2163write_high_thresh_perc=70 2164write_low_thresh_perc=0 2165port=system.membus.master[0] 2166 2167[system.toL2Bus] 2168type=CoherentBus 2169clk_domain=system.cpu_clk_domain 2170eventq_index=0 2171header_cycles=1 2172system=system 2173use_default_range=false 2174width=8 2175master=system.l2c.cpu_side 2176slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2177 2178[system.voltage_domain] 2179type=VoltageDomain 2180eventq_index=0 2181voltage=1.000000 2182 2183