config.ini revision 8546
1[root] 2type=Root 3children=system 4time_sync_enable=false 5time_sync_period=100000000000 6time_sync_spin_threshold=100000000 7 8[system] 9type=System 10children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus 11mem_mode=timing 12memories=system.physmem 13physmem=system.physmem 14work_begin_ckpt_count=0 15work_begin_cpu_id_exit=-1 16work_begin_exit_count=0 17work_cpus_ckpt_count=0 18work_end_ckpt_count=0 19work_end_exit_count=0 20work_item_id=-1 21 22[system.cpu0] 23type=DerivO3CPU 24children=dcache dtb fuPool icache itb tracer workload 25BTBEntries=4096 26BTBTagSize=16 27LFSTSize=1024 28LQEntries=32 29LSQCheckLoads=true 30LSQDepCheckShift=4 31RASSize=16 32SQEntries=32 33SSITSize=1024 34activity=0 35backComSize=5 36cachePorts=200 37checker=Null 38choiceCtrBits=2 39choicePredictorSize=8192 40clock=500 41commitToDecodeDelay=1 42commitToFetchDelay=1 43commitToIEWDelay=1 44commitToRenameDelay=1 45commitWidth=8 46cpu_id=0 47decodeToFetchDelay=1 48decodeToRenameDelay=1 49decodeWidth=8 50defer_registration=false 51dispatchWidth=8 52do_checkpoint_insts=true 53do_statistics_insts=true 54dtb=system.cpu0.dtb 55fetchToDecodeDelay=1 56fetchTrapLatency=1 57fetchWidth=8 58forwardComSize=5 59fuPool=system.cpu0.fuPool 60function_trace=false 61function_trace_start=0 62globalCtrBits=2 63globalHistoryBits=13 64globalPredictorSize=8192 65iewToCommitDelay=1 66iewToDecodeDelay=1 67iewToFetchDelay=1 68iewToRenameDelay=1 69instShiftAmt=2 70issueToExecuteDelay=1 71issueWidth=8 72itb=system.cpu0.itb 73localCtrBits=2 74localHistoryBits=11 75localHistoryTableSize=2048 76localPredictorSize=2048 77max_insts_all_threads=0 78max_insts_any_thread=0 79max_loads_all_threads=0 80max_loads_any_thread=0 81numIQEntries=64 82numPhysFloatRegs=256 83numPhysIntRegs=256 84numROBEntries=192 85numRobs=1 86numThreads=1 87phase=0 88predType=tournament 89progress_interval=0 90renameToDecodeDelay=1 91renameToFetchDelay=1 92renameToIEWDelay=2 93renameToROBDelay=1 94renameWidth=8 95smtCommitPolicy=RoundRobin 96smtFetchPolicy=SingleThread 97smtIQPolicy=Partitioned 98smtIQThreshold=100 99smtLSQPolicy=Partitioned 100smtLSQThreshold=100 101smtNumFetchingThreads=1 102smtROBPolicy=Partitioned 103smtROBThreshold=100 104squashWidth=8 105store_set_clear_period=250000 106system=system 107tracer=system.cpu0.tracer 108trapLatency=13 109wbDepth=1 110wbWidth=8 111workload=system.cpu0.workload 112dcache_port=system.cpu0.dcache.cpu_side 113icache_port=system.cpu0.icache.cpu_side 114 115[system.cpu0.dcache] 116type=BaseCache 117addr_range=0:18446744073709551615 118assoc=4 119block_size=64 120forward_snoops=true 121hash_delay=1 122is_top_level=true 123latency=1000 124max_miss_count=0 125mshrs=4 126num_cpus=1 127prefetch_data_accesses_only=false 128prefetch_degree=1 129prefetch_latency=10000 130prefetch_on_access=false 131prefetch_past_page=false 132prefetch_policy=none 133prefetch_serial_squash=false 134prefetch_use_cpu_id=true 135prefetcher_size=100 136prioritizeRequests=false 137repl=Null 138size=32768 139subblock_size=0 140tgts_per_mshr=20 141trace_addr=0 142two_queue=false 143write_buffers=8 144cpu_side=system.cpu0.dcache_port 145mem_side=system.toL2Bus.port[2] 146 147[system.cpu0.dtb] 148type=SparcTLB 149size=64 150 151[system.cpu0.fuPool] 152type=FUPool 153children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 154FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 155 156[system.cpu0.fuPool.FUList0] 157type=FUDesc 158children=opList 159count=6 160opList=system.cpu0.fuPool.FUList0.opList 161 162[system.cpu0.fuPool.FUList0.opList] 163type=OpDesc 164issueLat=1 165opClass=IntAlu 166opLat=1 167 168[system.cpu0.fuPool.FUList1] 169type=FUDesc 170children=opList0 opList1 171count=2 172opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 173 174[system.cpu0.fuPool.FUList1.opList0] 175type=OpDesc 176issueLat=1 177opClass=IntMult 178opLat=3 179 180[system.cpu0.fuPool.FUList1.opList1] 181type=OpDesc 182issueLat=19 183opClass=IntDiv 184opLat=20 185 186[system.cpu0.fuPool.FUList2] 187type=FUDesc 188children=opList0 opList1 opList2 189count=4 190opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 191 192[system.cpu0.fuPool.FUList2.opList0] 193type=OpDesc 194issueLat=1 195opClass=FloatAdd 196opLat=2 197 198[system.cpu0.fuPool.FUList2.opList1] 199type=OpDesc 200issueLat=1 201opClass=FloatCmp 202opLat=2 203 204[system.cpu0.fuPool.FUList2.opList2] 205type=OpDesc 206issueLat=1 207opClass=FloatCvt 208opLat=2 209 210[system.cpu0.fuPool.FUList3] 211type=FUDesc 212children=opList0 opList1 opList2 213count=2 214opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 215 216[system.cpu0.fuPool.FUList3.opList0] 217type=OpDesc 218issueLat=1 219opClass=FloatMult 220opLat=4 221 222[system.cpu0.fuPool.FUList3.opList1] 223type=OpDesc 224issueLat=12 225opClass=FloatDiv 226opLat=12 227 228[system.cpu0.fuPool.FUList3.opList2] 229type=OpDesc 230issueLat=24 231opClass=FloatSqrt 232opLat=24 233 234[system.cpu0.fuPool.FUList4] 235type=FUDesc 236children=opList 237count=0 238opList=system.cpu0.fuPool.FUList4.opList 239 240[system.cpu0.fuPool.FUList4.opList] 241type=OpDesc 242issueLat=1 243opClass=MemRead 244opLat=1 245 246[system.cpu0.fuPool.FUList5] 247type=FUDesc 248children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 249count=4 250opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 251 252[system.cpu0.fuPool.FUList5.opList00] 253type=OpDesc 254issueLat=1 255opClass=SimdAdd 256opLat=1 257 258[system.cpu0.fuPool.FUList5.opList01] 259type=OpDesc 260issueLat=1 261opClass=SimdAddAcc 262opLat=1 263 264[system.cpu0.fuPool.FUList5.opList02] 265type=OpDesc 266issueLat=1 267opClass=SimdAlu 268opLat=1 269 270[system.cpu0.fuPool.FUList5.opList03] 271type=OpDesc 272issueLat=1 273opClass=SimdCmp 274opLat=1 275 276[system.cpu0.fuPool.FUList5.opList04] 277type=OpDesc 278issueLat=1 279opClass=SimdCvt 280opLat=1 281 282[system.cpu0.fuPool.FUList5.opList05] 283type=OpDesc 284issueLat=1 285opClass=SimdMisc 286opLat=1 287 288[system.cpu0.fuPool.FUList5.opList06] 289type=OpDesc 290issueLat=1 291opClass=SimdMult 292opLat=1 293 294[system.cpu0.fuPool.FUList5.opList07] 295type=OpDesc 296issueLat=1 297opClass=SimdMultAcc 298opLat=1 299 300[system.cpu0.fuPool.FUList5.opList08] 301type=OpDesc 302issueLat=1 303opClass=SimdShift 304opLat=1 305 306[system.cpu0.fuPool.FUList5.opList09] 307type=OpDesc 308issueLat=1 309opClass=SimdShiftAcc 310opLat=1 311 312[system.cpu0.fuPool.FUList5.opList10] 313type=OpDesc 314issueLat=1 315opClass=SimdSqrt 316opLat=1 317 318[system.cpu0.fuPool.FUList5.opList11] 319type=OpDesc 320issueLat=1 321opClass=SimdFloatAdd 322opLat=1 323 324[system.cpu0.fuPool.FUList5.opList12] 325type=OpDesc 326issueLat=1 327opClass=SimdFloatAlu 328opLat=1 329 330[system.cpu0.fuPool.FUList5.opList13] 331type=OpDesc 332issueLat=1 333opClass=SimdFloatCmp 334opLat=1 335 336[system.cpu0.fuPool.FUList5.opList14] 337type=OpDesc 338issueLat=1 339opClass=SimdFloatCvt 340opLat=1 341 342[system.cpu0.fuPool.FUList5.opList15] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatDiv 346opLat=1 347 348[system.cpu0.fuPool.FUList5.opList16] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatMisc 352opLat=1 353 354[system.cpu0.fuPool.FUList5.opList17] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatMult 358opLat=1 359 360[system.cpu0.fuPool.FUList5.opList18] 361type=OpDesc 362issueLat=1 363opClass=SimdFloatMultAcc 364opLat=1 365 366[system.cpu0.fuPool.FUList5.opList19] 367type=OpDesc 368issueLat=1 369opClass=SimdFloatSqrt 370opLat=1 371 372[system.cpu0.fuPool.FUList6] 373type=FUDesc 374children=opList 375count=0 376opList=system.cpu0.fuPool.FUList6.opList 377 378[system.cpu0.fuPool.FUList6.opList] 379type=OpDesc 380issueLat=1 381opClass=MemWrite 382opLat=1 383 384[system.cpu0.fuPool.FUList7] 385type=FUDesc 386children=opList0 opList1 387count=4 388opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 389 390[system.cpu0.fuPool.FUList7.opList0] 391type=OpDesc 392issueLat=1 393opClass=MemRead 394opLat=1 395 396[system.cpu0.fuPool.FUList7.opList1] 397type=OpDesc 398issueLat=1 399opClass=MemWrite 400opLat=1 401 402[system.cpu0.fuPool.FUList8] 403type=FUDesc 404children=opList 405count=1 406opList=system.cpu0.fuPool.FUList8.opList 407 408[system.cpu0.fuPool.FUList8.opList] 409type=OpDesc 410issueLat=3 411opClass=IprAccess 412opLat=3 413 414[system.cpu0.icache] 415type=BaseCache 416addr_range=0:18446744073709551615 417assoc=1 418block_size=64 419forward_snoops=true 420hash_delay=1 421is_top_level=true 422latency=1000 423max_miss_count=0 424mshrs=4 425num_cpus=1 426prefetch_data_accesses_only=false 427prefetch_degree=1 428prefetch_latency=10000 429prefetch_on_access=false 430prefetch_past_page=false 431prefetch_policy=none 432prefetch_serial_squash=false 433prefetch_use_cpu_id=true 434prefetcher_size=100 435prioritizeRequests=false 436repl=Null 437size=32768 438subblock_size=0 439tgts_per_mshr=20 440trace_addr=0 441two_queue=false 442write_buffers=8 443cpu_side=system.cpu0.icache_port 444mem_side=system.toL2Bus.port[1] 445 446[system.cpu0.itb] 447type=SparcTLB 448size=64 449 450[system.cpu0.tracer] 451type=ExeTracer 452 453[system.cpu0.workload] 454type=LiveProcess 455cmd=test_atomic 4 456cwd= 457egid=100 458env= 459errout=cerr 460euid=100 461executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic 462gid=100 463input=cin 464max_stack_size=67108864 465output=cout 466pid=100 467ppid=99 468simpoint=0 469system=system 470uid=100 471 472[system.cpu1] 473type=DerivO3CPU 474children=dcache dtb fuPool icache itb tracer 475BTBEntries=4096 476BTBTagSize=16 477LFSTSize=1024 478LQEntries=32 479LSQCheckLoads=true 480LSQDepCheckShift=4 481RASSize=16 482SQEntries=32 483SSITSize=1024 484activity=0 485backComSize=5 486cachePorts=200 487checker=Null 488choiceCtrBits=2 489choicePredictorSize=8192 490clock=500 491commitToDecodeDelay=1 492commitToFetchDelay=1 493commitToIEWDelay=1 494commitToRenameDelay=1 495commitWidth=8 496cpu_id=1 497decodeToFetchDelay=1 498decodeToRenameDelay=1 499decodeWidth=8 500defer_registration=false 501dispatchWidth=8 502do_checkpoint_insts=true 503do_statistics_insts=true 504dtb=system.cpu1.dtb 505fetchToDecodeDelay=1 506fetchTrapLatency=1 507fetchWidth=8 508forwardComSize=5 509fuPool=system.cpu1.fuPool 510function_trace=false 511function_trace_start=0 512globalCtrBits=2 513globalHistoryBits=13 514globalPredictorSize=8192 515iewToCommitDelay=1 516iewToDecodeDelay=1 517iewToFetchDelay=1 518iewToRenameDelay=1 519instShiftAmt=2 520issueToExecuteDelay=1 521issueWidth=8 522itb=system.cpu1.itb 523localCtrBits=2 524localHistoryBits=11 525localHistoryTableSize=2048 526localPredictorSize=2048 527max_insts_all_threads=0 528max_insts_any_thread=0 529max_loads_all_threads=0 530max_loads_any_thread=0 531numIQEntries=64 532numPhysFloatRegs=256 533numPhysIntRegs=256 534numROBEntries=192 535numRobs=1 536numThreads=1 537phase=0 538predType=tournament 539progress_interval=0 540renameToDecodeDelay=1 541renameToFetchDelay=1 542renameToIEWDelay=2 543renameToROBDelay=1 544renameWidth=8 545smtCommitPolicy=RoundRobin 546smtFetchPolicy=SingleThread 547smtIQPolicy=Partitioned 548smtIQThreshold=100 549smtLSQPolicy=Partitioned 550smtLSQThreshold=100 551smtNumFetchingThreads=1 552smtROBPolicy=Partitioned 553smtROBThreshold=100 554squashWidth=8 555store_set_clear_period=250000 556system=system 557tracer=system.cpu1.tracer 558trapLatency=13 559wbDepth=1 560wbWidth=8 561workload=system.cpu0.workload 562dcache_port=system.cpu1.dcache.cpu_side 563icache_port=system.cpu1.icache.cpu_side 564 565[system.cpu1.dcache] 566type=BaseCache 567addr_range=0:18446744073709551615 568assoc=4 569block_size=64 570forward_snoops=true 571hash_delay=1 572is_top_level=true 573latency=1000 574max_miss_count=0 575mshrs=4 576num_cpus=1 577prefetch_data_accesses_only=false 578prefetch_degree=1 579prefetch_latency=10000 580prefetch_on_access=false 581prefetch_past_page=false 582prefetch_policy=none 583prefetch_serial_squash=false 584prefetch_use_cpu_id=true 585prefetcher_size=100 586prioritizeRequests=false 587repl=Null 588size=32768 589subblock_size=0 590tgts_per_mshr=20 591trace_addr=0 592two_queue=false 593write_buffers=8 594cpu_side=system.cpu1.dcache_port 595mem_side=system.toL2Bus.port[4] 596 597[system.cpu1.dtb] 598type=SparcTLB 599size=64 600 601[system.cpu1.fuPool] 602type=FUPool 603children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 604FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 605 606[system.cpu1.fuPool.FUList0] 607type=FUDesc 608children=opList 609count=6 610opList=system.cpu1.fuPool.FUList0.opList 611 612[system.cpu1.fuPool.FUList0.opList] 613type=OpDesc 614issueLat=1 615opClass=IntAlu 616opLat=1 617 618[system.cpu1.fuPool.FUList1] 619type=FUDesc 620children=opList0 opList1 621count=2 622opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 623 624[system.cpu1.fuPool.FUList1.opList0] 625type=OpDesc 626issueLat=1 627opClass=IntMult 628opLat=3 629 630[system.cpu1.fuPool.FUList1.opList1] 631type=OpDesc 632issueLat=19 633opClass=IntDiv 634opLat=20 635 636[system.cpu1.fuPool.FUList2] 637type=FUDesc 638children=opList0 opList1 opList2 639count=4 640opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 641 642[system.cpu1.fuPool.FUList2.opList0] 643type=OpDesc 644issueLat=1 645opClass=FloatAdd 646opLat=2 647 648[system.cpu1.fuPool.FUList2.opList1] 649type=OpDesc 650issueLat=1 651opClass=FloatCmp 652opLat=2 653 654[system.cpu1.fuPool.FUList2.opList2] 655type=OpDesc 656issueLat=1 657opClass=FloatCvt 658opLat=2 659 660[system.cpu1.fuPool.FUList3] 661type=FUDesc 662children=opList0 opList1 opList2 663count=2 664opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 665 666[system.cpu1.fuPool.FUList3.opList0] 667type=OpDesc 668issueLat=1 669opClass=FloatMult 670opLat=4 671 672[system.cpu1.fuPool.FUList3.opList1] 673type=OpDesc 674issueLat=12 675opClass=FloatDiv 676opLat=12 677 678[system.cpu1.fuPool.FUList3.opList2] 679type=OpDesc 680issueLat=24 681opClass=FloatSqrt 682opLat=24 683 684[system.cpu1.fuPool.FUList4] 685type=FUDesc 686children=opList 687count=0 688opList=system.cpu1.fuPool.FUList4.opList 689 690[system.cpu1.fuPool.FUList4.opList] 691type=OpDesc 692issueLat=1 693opClass=MemRead 694opLat=1 695 696[system.cpu1.fuPool.FUList5] 697type=FUDesc 698children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 699count=4 700opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 701 702[system.cpu1.fuPool.FUList5.opList00] 703type=OpDesc 704issueLat=1 705opClass=SimdAdd 706opLat=1 707 708[system.cpu1.fuPool.FUList5.opList01] 709type=OpDesc 710issueLat=1 711opClass=SimdAddAcc 712opLat=1 713 714[system.cpu1.fuPool.FUList5.opList02] 715type=OpDesc 716issueLat=1 717opClass=SimdAlu 718opLat=1 719 720[system.cpu1.fuPool.FUList5.opList03] 721type=OpDesc 722issueLat=1 723opClass=SimdCmp 724opLat=1 725 726[system.cpu1.fuPool.FUList5.opList04] 727type=OpDesc 728issueLat=1 729opClass=SimdCvt 730opLat=1 731 732[system.cpu1.fuPool.FUList5.opList05] 733type=OpDesc 734issueLat=1 735opClass=SimdMisc 736opLat=1 737 738[system.cpu1.fuPool.FUList5.opList06] 739type=OpDesc 740issueLat=1 741opClass=SimdMult 742opLat=1 743 744[system.cpu1.fuPool.FUList5.opList07] 745type=OpDesc 746issueLat=1 747opClass=SimdMultAcc 748opLat=1 749 750[system.cpu1.fuPool.FUList5.opList08] 751type=OpDesc 752issueLat=1 753opClass=SimdShift 754opLat=1 755 756[system.cpu1.fuPool.FUList5.opList09] 757type=OpDesc 758issueLat=1 759opClass=SimdShiftAcc 760opLat=1 761 762[system.cpu1.fuPool.FUList5.opList10] 763type=OpDesc 764issueLat=1 765opClass=SimdSqrt 766opLat=1 767 768[system.cpu1.fuPool.FUList5.opList11] 769type=OpDesc 770issueLat=1 771opClass=SimdFloatAdd 772opLat=1 773 774[system.cpu1.fuPool.FUList5.opList12] 775type=OpDesc 776issueLat=1 777opClass=SimdFloatAlu 778opLat=1 779 780[system.cpu1.fuPool.FUList5.opList13] 781type=OpDesc 782issueLat=1 783opClass=SimdFloatCmp 784opLat=1 785 786[system.cpu1.fuPool.FUList5.opList14] 787type=OpDesc 788issueLat=1 789opClass=SimdFloatCvt 790opLat=1 791 792[system.cpu1.fuPool.FUList5.opList15] 793type=OpDesc 794issueLat=1 795opClass=SimdFloatDiv 796opLat=1 797 798[system.cpu1.fuPool.FUList5.opList16] 799type=OpDesc 800issueLat=1 801opClass=SimdFloatMisc 802opLat=1 803 804[system.cpu1.fuPool.FUList5.opList17] 805type=OpDesc 806issueLat=1 807opClass=SimdFloatMult 808opLat=1 809 810[system.cpu1.fuPool.FUList5.opList18] 811type=OpDesc 812issueLat=1 813opClass=SimdFloatMultAcc 814opLat=1 815 816[system.cpu1.fuPool.FUList5.opList19] 817type=OpDesc 818issueLat=1 819opClass=SimdFloatSqrt 820opLat=1 821 822[system.cpu1.fuPool.FUList6] 823type=FUDesc 824children=opList 825count=0 826opList=system.cpu1.fuPool.FUList6.opList 827 828[system.cpu1.fuPool.FUList6.opList] 829type=OpDesc 830issueLat=1 831opClass=MemWrite 832opLat=1 833 834[system.cpu1.fuPool.FUList7] 835type=FUDesc 836children=opList0 opList1 837count=4 838opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 839 840[system.cpu1.fuPool.FUList7.opList0] 841type=OpDesc 842issueLat=1 843opClass=MemRead 844opLat=1 845 846[system.cpu1.fuPool.FUList7.opList1] 847type=OpDesc 848issueLat=1 849opClass=MemWrite 850opLat=1 851 852[system.cpu1.fuPool.FUList8] 853type=FUDesc 854children=opList 855count=1 856opList=system.cpu1.fuPool.FUList8.opList 857 858[system.cpu1.fuPool.FUList8.opList] 859type=OpDesc 860issueLat=3 861opClass=IprAccess 862opLat=3 863 864[system.cpu1.icache] 865type=BaseCache 866addr_range=0:18446744073709551615 867assoc=1 868block_size=64 869forward_snoops=true 870hash_delay=1 871is_top_level=true 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1542issueLat=24 1543opClass=FloatSqrt 1544opLat=24 1545 1546[system.cpu3.fuPool.FUList4] 1547type=FUDesc 1548children=opList 1549count=0 1550opList=system.cpu3.fuPool.FUList4.opList 1551 1552[system.cpu3.fuPool.FUList4.opList] 1553type=OpDesc 1554issueLat=1 1555opClass=MemRead 1556opLat=1 1557 1558[system.cpu3.fuPool.FUList5] 1559type=FUDesc 1560children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1561count=4 1562opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1563 1564[system.cpu3.fuPool.FUList5.opList00] 1565type=OpDesc 1566issueLat=1 1567opClass=SimdAdd 1568opLat=1 1569 1570[system.cpu3.fuPool.FUList5.opList01] 1571type=OpDesc 1572issueLat=1 1573opClass=SimdAddAcc 1574opLat=1 1575 1576[system.cpu3.fuPool.FUList5.opList02] 1577type=OpDesc 1578issueLat=1 1579opClass=SimdAlu 1580opLat=1 1581 1582[system.cpu3.fuPool.FUList5.opList03] 1583type=OpDesc 1584issueLat=1 1585opClass=SimdCmp 1586opLat=1 1587 1588[system.cpu3.fuPool.FUList5.opList04] 1589type=OpDesc 1590issueLat=1 1591opClass=SimdCvt 1592opLat=1 1593 1594[system.cpu3.fuPool.FUList5.opList05] 1595type=OpDesc 1596issueLat=1 1597opClass=SimdMisc 1598opLat=1 1599 1600[system.cpu3.fuPool.FUList5.opList06] 1601type=OpDesc 1602issueLat=1 1603opClass=SimdMult 1604opLat=1 1605 1606[system.cpu3.fuPool.FUList5.opList07] 1607type=OpDesc 1608issueLat=1 1609opClass=SimdMultAcc 1610opLat=1 1611 1612[system.cpu3.fuPool.FUList5.opList08] 1613type=OpDesc 1614issueLat=1 1615opClass=SimdShift 1616opLat=1 1617 1618[system.cpu3.fuPool.FUList5.opList09] 1619type=OpDesc 1620issueLat=1 1621opClass=SimdShiftAcc 1622opLat=1 1623 1624[system.cpu3.fuPool.FUList5.opList10] 1625type=OpDesc 1626issueLat=1 1627opClass=SimdSqrt 1628opLat=1 1629 1630[system.cpu3.fuPool.FUList5.opList11] 1631type=OpDesc 1632issueLat=1 1633opClass=SimdFloatAdd 1634opLat=1 1635 1636[system.cpu3.fuPool.FUList5.opList12] 1637type=OpDesc 1638issueLat=1 1639opClass=SimdFloatAlu 1640opLat=1 1641 1642[system.cpu3.fuPool.FUList5.opList13] 1643type=OpDesc 1644issueLat=1 1645opClass=SimdFloatCmp 1646opLat=1 1647 1648[system.cpu3.fuPool.FUList5.opList14] 1649type=OpDesc 1650issueLat=1 1651opClass=SimdFloatCvt 1652opLat=1 1653 1654[system.cpu3.fuPool.FUList5.opList15] 1655type=OpDesc 1656issueLat=1 1657opClass=SimdFloatDiv 1658opLat=1 1659 1660[system.cpu3.fuPool.FUList5.opList16] 1661type=OpDesc 1662issueLat=1 1663opClass=SimdFloatMisc 1664opLat=1 1665 1666[system.cpu3.fuPool.FUList5.opList17] 1667type=OpDesc 1668issueLat=1 1669opClass=SimdFloatMult 1670opLat=1 1671 1672[system.cpu3.fuPool.FUList5.opList18] 1673type=OpDesc 1674issueLat=1 1675opClass=SimdFloatMultAcc 1676opLat=1 1677 1678[system.cpu3.fuPool.FUList5.opList19] 1679type=OpDesc 1680issueLat=1 1681opClass=SimdFloatSqrt 1682opLat=1 1683 1684[system.cpu3.fuPool.FUList6] 1685type=FUDesc 1686children=opList 1687count=0 1688opList=system.cpu3.fuPool.FUList6.opList 1689 1690[system.cpu3.fuPool.FUList6.opList] 1691type=OpDesc 1692issueLat=1 1693opClass=MemWrite 1694opLat=1 1695 1696[system.cpu3.fuPool.FUList7] 1697type=FUDesc 1698children=opList0 opList1 1699count=4 1700opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 1701 1702[system.cpu3.fuPool.FUList7.opList0] 1703type=OpDesc 1704issueLat=1 1705opClass=MemRead 1706opLat=1 1707 1708[system.cpu3.fuPool.FUList7.opList1] 1709type=OpDesc 1710issueLat=1 1711opClass=MemWrite 1712opLat=1 1713 1714[system.cpu3.fuPool.FUList8] 1715type=FUDesc 1716children=opList 1717count=1 1718opList=system.cpu3.fuPool.FUList8.opList 1719 1720[system.cpu3.fuPool.FUList8.opList] 1721type=OpDesc 1722issueLat=3 1723opClass=IprAccess 1724opLat=3 1725 1726[system.cpu3.icache] 1727type=BaseCache 1728addr_range=0:18446744073709551615 1729assoc=1 1730block_size=64 1731forward_snoops=true 1732hash_delay=1 1733is_top_level=true 1734latency=1000 1735max_miss_count=0 1736mshrs=4 1737num_cpus=1 1738prefetch_data_accesses_only=false 1739prefetch_degree=1 1740prefetch_latency=10000 1741prefetch_on_access=false 1742prefetch_past_page=false 1743prefetch_policy=none 1744prefetch_serial_squash=false 1745prefetch_use_cpu_id=true 1746prefetcher_size=100 1747prioritizeRequests=false 1748repl=Null 1749size=32768 1750subblock_size=0 1751tgts_per_mshr=20 1752trace_addr=0 1753two_queue=false 1754write_buffers=8 1755cpu_side=system.cpu3.icache_port 1756mem_side=system.toL2Bus.port[7] 1757 1758[system.cpu3.itb] 1759type=SparcTLB 1760size=64 1761 1762[system.cpu3.tracer] 1763type=ExeTracer 1764 1765[system.l2c] 1766type=BaseCache 1767addr_range=0:18446744073709551615 1768assoc=8 1769block_size=64 1770forward_snoops=true 1771hash_delay=1 1772is_top_level=false 1773latency=10000 1774max_miss_count=0 1775mshrs=92 1776num_cpus=4 1777prefetch_data_accesses_only=false 1778prefetch_degree=1 1779prefetch_latency=100000 1780prefetch_on_access=false 1781prefetch_past_page=false 1782prefetch_policy=none 1783prefetch_serial_squash=false 1784prefetch_use_cpu_id=true 1785prefetcher_size=100 1786prioritizeRequests=false 1787repl=Null 1788size=4194304 1789subblock_size=0 1790tgts_per_mshr=16 1791trace_addr=0 1792two_queue=false 1793write_buffers=8 1794cpu_side=system.toL2Bus.port[0] 1795mem_side=system.membus.port[0] 1796 1797[system.membus] 1798type=Bus 1799block_size=64 1800bus_id=0 1801clock=1000 1802header_cycles=1 1803use_default_range=false 1804width=64 1805port=system.l2c.mem_side system.physmem.port[0] 1806 1807[system.physmem] 1808type=PhysicalMemory 1809file= 1810latency=30000 1811latency_var=0 1812null=false 1813range=0:134217727 1814zero=false 1815port=system.membus.port[1] 1816 1817[system.toL2Bus] 1818type=Bus 1819block_size=64 1820bus_id=0 1821clock=1000 1822header_cycles=1 1823use_default_range=false 1824width=64 1825port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 1826 1827