config.ini revision 8464
1[root] 2type=Root 3children=system 4time_sync_enable=false 5time_sync_period=100000000000 6time_sync_spin_threshold=100000000 7 8[system] 9type=System 10children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus 11mem_mode=timing 12memories=system.physmem 13physmem=system.physmem 14work_begin_ckpt_count=0 15work_begin_cpu_id_exit=-1 16work_begin_exit_count=0 17work_cpus_ckpt_count=0 18work_end_ckpt_count=0 19work_end_exit_count=0 20work_item_id=-1 21 22[system.cpu0] 23type=DerivO3CPU 24children=dcache dtb fuPool icache itb tracer workload 25BTBEntries=4096 26BTBTagSize=16 27LFSTSize=1024 28LQEntries=32 29LSQCheckLoads=true 30LSQDepCheckShift=4 31RASSize=16 32SQEntries=32 33SSITSize=1024 34activity=0 35backComSize=5 36cachePorts=200 37checker=Null 38choiceCtrBits=2 39choicePredictorSize=8192 40clock=500 41commitToDecodeDelay=1 42commitToFetchDelay=1 43commitToIEWDelay=1 44commitToRenameDelay=1 45commitWidth=8 46cpu_id=0 47decodeToFetchDelay=1 48decodeToRenameDelay=1 49decodeWidth=8 50defer_registration=false 51dispatchWidth=8 52do_checkpoint_insts=true 53do_statistics_insts=true 54dtb=system.cpu0.dtb 55fetchToDecodeDelay=1 56fetchTrapLatency=1 57fetchWidth=8 58forwardComSize=5 59fuPool=system.cpu0.fuPool 60function_trace=false 61function_trace_start=0 62globalCtrBits=2 63globalHistoryBits=13 64globalPredictorSize=8192 65iewToCommitDelay=1 66iewToDecodeDelay=1 67iewToFetchDelay=1 68iewToRenameDelay=1 69instShiftAmt=2 70issueToExecuteDelay=1 71issueWidth=8 72itb=system.cpu0.itb 73localCtrBits=2 74localHistoryBits=11 75localHistoryTableSize=2048 76localPredictorSize=2048 77max_insts_all_threads=0 78max_insts_any_thread=0 79max_loads_all_threads=0 80max_loads_any_thread=0 81numIQEntries=64 82numPhysFloatRegs=256 83numPhysIntRegs=256 84numROBEntries=192 85numRobs=1 86numThreads=1 87phase=0 88predType=tournament 89progress_interval=0 90renameToDecodeDelay=1 91renameToFetchDelay=1 92renameToIEWDelay=2 93renameToROBDelay=1 94renameWidth=8 95smtCommitPolicy=RoundRobin 96smtFetchPolicy=SingleThread 97smtIQPolicy=Partitioned 98smtIQThreshold=100 99smtLSQPolicy=Partitioned 100smtLSQThreshold=100 101smtNumFetchingThreads=1 102smtROBPolicy=Partitioned 103smtROBThreshold=100 104squashWidth=8 105system=system 106tracer=system.cpu0.tracer 107trapLatency=13 108wbDepth=1 109wbWidth=8 110workload=system.cpu0.workload 111dcache_port=system.cpu0.dcache.cpu_side 112icache_port=system.cpu0.icache.cpu_side 113 114[system.cpu0.dcache] 115type=BaseCache 116addr_range=0:18446744073709551615 117assoc=4 118block_size=64 119forward_snoops=true 120hash_delay=1 121is_top_level=true 122latency=1000 123max_miss_count=0 124mshrs=4 125num_cpus=1 126prefetch_data_accesses_only=false 127prefetch_degree=1 128prefetch_latency=10000 129prefetch_on_access=false 130prefetch_past_page=false 131prefetch_policy=none 132prefetch_serial_squash=false 133prefetch_use_cpu_id=true 134prefetcher_size=100 135prioritizeRequests=false 136repl=Null 137size=32768 138subblock_size=0 139tgts_per_mshr=20 140trace_addr=0 141two_queue=false 142write_buffers=8 143cpu_side=system.cpu0.dcache_port 144mem_side=system.toL2Bus.port[2] 145 146[system.cpu0.dtb] 147type=SparcTLB 148size=64 149 150[system.cpu0.fuPool] 151type=FUPool 152children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 153FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 154 155[system.cpu0.fuPool.FUList0] 156type=FUDesc 157children=opList 158count=6 159opList=system.cpu0.fuPool.FUList0.opList 160 161[system.cpu0.fuPool.FUList0.opList] 162type=OpDesc 163issueLat=1 164opClass=IntAlu 165opLat=1 166 167[system.cpu0.fuPool.FUList1] 168type=FUDesc 169children=opList0 opList1 170count=2 171opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 172 173[system.cpu0.fuPool.FUList1.opList0] 174type=OpDesc 175issueLat=1 176opClass=IntMult 177opLat=3 178 179[system.cpu0.fuPool.FUList1.opList1] 180type=OpDesc 181issueLat=19 182opClass=IntDiv 183opLat=20 184 185[system.cpu0.fuPool.FUList2] 186type=FUDesc 187children=opList0 opList1 opList2 188count=4 189opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 190 191[system.cpu0.fuPool.FUList2.opList0] 192type=OpDesc 193issueLat=1 194opClass=FloatAdd 195opLat=2 196 197[system.cpu0.fuPool.FUList2.opList1] 198type=OpDesc 199issueLat=1 200opClass=FloatCmp 201opLat=2 202 203[system.cpu0.fuPool.FUList2.opList2] 204type=OpDesc 205issueLat=1 206opClass=FloatCvt 207opLat=2 208 209[system.cpu0.fuPool.FUList3] 210type=FUDesc 211children=opList0 opList1 opList2 212count=2 213opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 214 215[system.cpu0.fuPool.FUList3.opList0] 216type=OpDesc 217issueLat=1 218opClass=FloatMult 219opLat=4 220 221[system.cpu0.fuPool.FUList3.opList1] 222type=OpDesc 223issueLat=12 224opClass=FloatDiv 225opLat=12 226 227[system.cpu0.fuPool.FUList3.opList2] 228type=OpDesc 229issueLat=24 230opClass=FloatSqrt 231opLat=24 232 233[system.cpu0.fuPool.FUList4] 234type=FUDesc 235children=opList 236count=0 237opList=system.cpu0.fuPool.FUList4.opList 238 239[system.cpu0.fuPool.FUList4.opList] 240type=OpDesc 241issueLat=1 242opClass=MemRead 243opLat=1 244 245[system.cpu0.fuPool.FUList5] 246type=FUDesc 247children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 248count=4 249opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 250 251[system.cpu0.fuPool.FUList5.opList00] 252type=OpDesc 253issueLat=1 254opClass=SimdAdd 255opLat=1 256 257[system.cpu0.fuPool.FUList5.opList01] 258type=OpDesc 259issueLat=1 260opClass=SimdAddAcc 261opLat=1 262 263[system.cpu0.fuPool.FUList5.opList02] 264type=OpDesc 265issueLat=1 266opClass=SimdAlu 267opLat=1 268 269[system.cpu0.fuPool.FUList5.opList03] 270type=OpDesc 271issueLat=1 272opClass=SimdCmp 273opLat=1 274 275[system.cpu0.fuPool.FUList5.opList04] 276type=OpDesc 277issueLat=1 278opClass=SimdCvt 279opLat=1 280 281[system.cpu0.fuPool.FUList5.opList05] 282type=OpDesc 283issueLat=1 284opClass=SimdMisc 285opLat=1 286 287[system.cpu0.fuPool.FUList5.opList06] 288type=OpDesc 289issueLat=1 290opClass=SimdMult 291opLat=1 292 293[system.cpu0.fuPool.FUList5.opList07] 294type=OpDesc 295issueLat=1 296opClass=SimdMultAcc 297opLat=1 298 299[system.cpu0.fuPool.FUList5.opList08] 300type=OpDesc 301issueLat=1 302opClass=SimdShift 303opLat=1 304 305[system.cpu0.fuPool.FUList5.opList09] 306type=OpDesc 307issueLat=1 308opClass=SimdShiftAcc 309opLat=1 310 311[system.cpu0.fuPool.FUList5.opList10] 312type=OpDesc 313issueLat=1 314opClass=SimdSqrt 315opLat=1 316 317[system.cpu0.fuPool.FUList5.opList11] 318type=OpDesc 319issueLat=1 320opClass=SimdFloatAdd 321opLat=1 322 323[system.cpu0.fuPool.FUList5.opList12] 324type=OpDesc 325issueLat=1 326opClass=SimdFloatAlu 327opLat=1 328 329[system.cpu0.fuPool.FUList5.opList13] 330type=OpDesc 331issueLat=1 332opClass=SimdFloatCmp 333opLat=1 334 335[system.cpu0.fuPool.FUList5.opList14] 336type=OpDesc 337issueLat=1 338opClass=SimdFloatCvt 339opLat=1 340 341[system.cpu0.fuPool.FUList5.opList15] 342type=OpDesc 343issueLat=1 344opClass=SimdFloatDiv 345opLat=1 346 347[system.cpu0.fuPool.FUList5.opList16] 348type=OpDesc 349issueLat=1 350opClass=SimdFloatMisc 351opLat=1 352 353[system.cpu0.fuPool.FUList5.opList17] 354type=OpDesc 355issueLat=1 356opClass=SimdFloatMult 357opLat=1 358 359[system.cpu0.fuPool.FUList5.opList18] 360type=OpDesc 361issueLat=1 362opClass=SimdFloatMultAcc 363opLat=1 364 365[system.cpu0.fuPool.FUList5.opList19] 366type=OpDesc 367issueLat=1 368opClass=SimdFloatSqrt 369opLat=1 370 371[system.cpu0.fuPool.FUList6] 372type=FUDesc 373children=opList 374count=0 375opList=system.cpu0.fuPool.FUList6.opList 376 377[system.cpu0.fuPool.FUList6.opList] 378type=OpDesc 379issueLat=1 380opClass=MemWrite 381opLat=1 382 383[system.cpu0.fuPool.FUList7] 384type=FUDesc 385children=opList0 opList1 386count=4 387opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 388 389[system.cpu0.fuPool.FUList7.opList0] 390type=OpDesc 391issueLat=1 392opClass=MemRead 393opLat=1 394 395[system.cpu0.fuPool.FUList7.opList1] 396type=OpDesc 397issueLat=1 398opClass=MemWrite 399opLat=1 400 401[system.cpu0.fuPool.FUList8] 402type=FUDesc 403children=opList 404count=1 405opList=system.cpu0.fuPool.FUList8.opList 406 407[system.cpu0.fuPool.FUList8.opList] 408type=OpDesc 409issueLat=3 410opClass=IprAccess 411opLat=3 412 413[system.cpu0.icache] 414type=BaseCache 415addr_range=0:18446744073709551615 416assoc=1 417block_size=64 418forward_snoops=true 419hash_delay=1 420is_top_level=true 421latency=1000 422max_miss_count=0 423mshrs=4 424num_cpus=1 425prefetch_data_accesses_only=false 426prefetch_degree=1 427prefetch_latency=10000 428prefetch_on_access=false 429prefetch_past_page=false 430prefetch_policy=none 431prefetch_serial_squash=false 432prefetch_use_cpu_id=true 433prefetcher_size=100 434prioritizeRequests=false 435repl=Null 436size=32768 437subblock_size=0 438tgts_per_mshr=20 439trace_addr=0 440two_queue=false 441write_buffers=8 442cpu_side=system.cpu0.icache_port 443mem_side=system.toL2Bus.port[1] 444 445[system.cpu0.itb] 446type=SparcTLB 447size=64 448 449[system.cpu0.tracer] 450type=ExeTracer 451 452[system.cpu0.workload] 453type=LiveProcess 454cmd=test_atomic 4 455cwd= 456egid=100 457env= 458errout=cerr 459euid=100 460executable=/chips/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic 461gid=100 462input=cin 463max_stack_size=67108864 464output=cout 465pid=100 466ppid=99 467simpoint=0 468system=system 469uid=100 470 471[system.cpu1] 472type=DerivO3CPU 473children=dcache dtb fuPool icache itb tracer 474BTBEntries=4096 475BTBTagSize=16 476LFSTSize=1024 477LQEntries=32 478LSQCheckLoads=true 479LSQDepCheckShift=4 480RASSize=16 481SQEntries=32 482SSITSize=1024 483activity=0 484backComSize=5 485cachePorts=200 486checker=Null 487choiceCtrBits=2 488choicePredictorSize=8192 489clock=500 490commitToDecodeDelay=1 491commitToFetchDelay=1 492commitToIEWDelay=1 493commitToRenameDelay=1 494commitWidth=8 495cpu_id=1 496decodeToFetchDelay=1 497decodeToRenameDelay=1 498decodeWidth=8 499defer_registration=false 500dispatchWidth=8 501do_checkpoint_insts=true 502do_statistics_insts=true 503dtb=system.cpu1.dtb 504fetchToDecodeDelay=1 505fetchTrapLatency=1 506fetchWidth=8 507forwardComSize=5 508fuPool=system.cpu1.fuPool 509function_trace=false 510function_trace_start=0 511globalCtrBits=2 512globalHistoryBits=13 513globalPredictorSize=8192 514iewToCommitDelay=1 515iewToDecodeDelay=1 516iewToFetchDelay=1 517iewToRenameDelay=1 518instShiftAmt=2 519issueToExecuteDelay=1 520issueWidth=8 521itb=system.cpu1.itb 522localCtrBits=2 523localHistoryBits=11 524localHistoryTableSize=2048 525localPredictorSize=2048 526max_insts_all_threads=0 527max_insts_any_thread=0 528max_loads_all_threads=0 529max_loads_any_thread=0 530numIQEntries=64 531numPhysFloatRegs=256 532numPhysIntRegs=256 533numROBEntries=192 534numRobs=1 535numThreads=1 536phase=0 537predType=tournament 538progress_interval=0 539renameToDecodeDelay=1 540renameToFetchDelay=1 541renameToIEWDelay=2 542renameToROBDelay=1 543renameWidth=8 544smtCommitPolicy=RoundRobin 545smtFetchPolicy=SingleThread 546smtIQPolicy=Partitioned 547smtIQThreshold=100 548smtLSQPolicy=Partitioned 549smtLSQThreshold=100 550smtNumFetchingThreads=1 551smtROBPolicy=Partitioned 552smtROBThreshold=100 553squashWidth=8 554system=system 555tracer=system.cpu1.tracer 556trapLatency=13 557wbDepth=1 558wbWidth=8 559workload=system.cpu0.workload 560dcache_port=system.cpu1.dcache.cpu_side 561icache_port=system.cpu1.icache.cpu_side 562 563[system.cpu1.dcache] 564type=BaseCache 565addr_range=0:18446744073709551615 566assoc=4 567block_size=64 568forward_snoops=true 569hash_delay=1 570is_top_level=true 571latency=1000 572max_miss_count=0 573mshrs=4 574num_cpus=1 575prefetch_data_accesses_only=false 576prefetch_degree=1 577prefetch_latency=10000 578prefetch_on_access=false 579prefetch_past_page=false 580prefetch_policy=none 581prefetch_serial_squash=false 582prefetch_use_cpu_id=true 583prefetcher_size=100 584prioritizeRequests=false 585repl=Null 586size=32768 587subblock_size=0 588tgts_per_mshr=20 589trace_addr=0 590two_queue=false 591write_buffers=8 592cpu_side=system.cpu1.dcache_port 593mem_side=system.toL2Bus.port[4] 594 595[system.cpu1.dtb] 596type=SparcTLB 597size=64 598 599[system.cpu1.fuPool] 600type=FUPool 601children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 602FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 603 604[system.cpu1.fuPool.FUList0] 605type=FUDesc 606children=opList 607count=6 608opList=system.cpu1.fuPool.FUList0.opList 609 610[system.cpu1.fuPool.FUList0.opList] 611type=OpDesc 612issueLat=1 613opClass=IntAlu 614opLat=1 615 616[system.cpu1.fuPool.FUList1] 617type=FUDesc 618children=opList0 opList1 619count=2 620opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 621 622[system.cpu1.fuPool.FUList1.opList0] 623type=OpDesc 624issueLat=1 625opClass=IntMult 626opLat=3 627 628[system.cpu1.fuPool.FUList1.opList1] 629type=OpDesc 630issueLat=19 631opClass=IntDiv 632opLat=20 633 634[system.cpu1.fuPool.FUList2] 635type=FUDesc 636children=opList0 opList1 opList2 637count=4 638opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 639 640[system.cpu1.fuPool.FUList2.opList0] 641type=OpDesc 642issueLat=1 643opClass=FloatAdd 644opLat=2 645 646[system.cpu1.fuPool.FUList2.opList1] 647type=OpDesc 648issueLat=1 649opClass=FloatCmp 650opLat=2 651 652[system.cpu1.fuPool.FUList2.opList2] 653type=OpDesc 654issueLat=1 655opClass=FloatCvt 656opLat=2 657 658[system.cpu1.fuPool.FUList3] 659type=FUDesc 660children=opList0 opList1 opList2 661count=2 662opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 663 664[system.cpu1.fuPool.FUList3.opList0] 665type=OpDesc 666issueLat=1 667opClass=FloatMult 668opLat=4 669 670[system.cpu1.fuPool.FUList3.opList1] 671type=OpDesc 672issueLat=12 673opClass=FloatDiv 674opLat=12 675 676[system.cpu1.fuPool.FUList3.opList2] 677type=OpDesc 678issueLat=24 679opClass=FloatSqrt 680opLat=24 681 682[system.cpu1.fuPool.FUList4] 683type=FUDesc 684children=opList 685count=0 686opList=system.cpu1.fuPool.FUList4.opList 687 688[system.cpu1.fuPool.FUList4.opList] 689type=OpDesc 690issueLat=1 691opClass=MemRead 692opLat=1 693 694[system.cpu1.fuPool.FUList5] 695type=FUDesc 696children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 697count=4 698opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 699 700[system.cpu1.fuPool.FUList5.opList00] 701type=OpDesc 702issueLat=1 703opClass=SimdAdd 704opLat=1 705 706[system.cpu1.fuPool.FUList5.opList01] 707type=OpDesc 708issueLat=1 709opClass=SimdAddAcc 710opLat=1 711 712[system.cpu1.fuPool.FUList5.opList02] 713type=OpDesc 714issueLat=1 715opClass=SimdAlu 716opLat=1 717 718[system.cpu1.fuPool.FUList5.opList03] 719type=OpDesc 720issueLat=1 721opClass=SimdCmp 722opLat=1 723 724[system.cpu1.fuPool.FUList5.opList04] 725type=OpDesc 726issueLat=1 727opClass=SimdCvt 728opLat=1 729 730[system.cpu1.fuPool.FUList5.opList05] 731type=OpDesc 732issueLat=1 733opClass=SimdMisc 734opLat=1 735 736[system.cpu1.fuPool.FUList5.opList06] 737type=OpDesc 738issueLat=1 739opClass=SimdMult 740opLat=1 741 742[system.cpu1.fuPool.FUList5.opList07] 743type=OpDesc 744issueLat=1 745opClass=SimdMultAcc 746opLat=1 747 748[system.cpu1.fuPool.FUList5.opList08] 749type=OpDesc 750issueLat=1 751opClass=SimdShift 752opLat=1 753 754[system.cpu1.fuPool.FUList5.opList09] 755type=OpDesc 756issueLat=1 757opClass=SimdShiftAcc 758opLat=1 759 760[system.cpu1.fuPool.FUList5.opList10] 761type=OpDesc 762issueLat=1 763opClass=SimdSqrt 764opLat=1 765 766[system.cpu1.fuPool.FUList5.opList11] 767type=OpDesc 768issueLat=1 769opClass=SimdFloatAdd 770opLat=1 771 772[system.cpu1.fuPool.FUList5.opList12] 773type=OpDesc 774issueLat=1 775opClass=SimdFloatAlu 776opLat=1 777 778[system.cpu1.fuPool.FUList5.opList13] 779type=OpDesc 780issueLat=1 781opClass=SimdFloatCmp 782opLat=1 783 784[system.cpu1.fuPool.FUList5.opList14] 785type=OpDesc 786issueLat=1 787opClass=SimdFloatCvt 788opLat=1 789 790[system.cpu1.fuPool.FUList5.opList15] 791type=OpDesc 792issueLat=1 793opClass=SimdFloatDiv 794opLat=1 795 796[system.cpu1.fuPool.FUList5.opList16] 797type=OpDesc 798issueLat=1 799opClass=SimdFloatMisc 800opLat=1 801 802[system.cpu1.fuPool.FUList5.opList17] 803type=OpDesc 804issueLat=1 805opClass=SimdFloatMult 806opLat=1 807 808[system.cpu1.fuPool.FUList5.opList18] 809type=OpDesc 810issueLat=1 811opClass=SimdFloatMultAcc 812opLat=1 813 814[system.cpu1.fuPool.FUList5.opList19] 815type=OpDesc 816issueLat=1 817opClass=SimdFloatSqrt 818opLat=1 819 820[system.cpu1.fuPool.FUList6] 821type=FUDesc 822children=opList 823count=0 824opList=system.cpu1.fuPool.FUList6.opList 825 826[system.cpu1.fuPool.FUList6.opList] 827type=OpDesc 828issueLat=1 829opClass=MemWrite 830opLat=1 831 832[system.cpu1.fuPool.FUList7] 833type=FUDesc 834children=opList0 opList1 835count=4 836opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 837 838[system.cpu1.fuPool.FUList7.opList0] 839type=OpDesc 840issueLat=1 841opClass=MemRead 842opLat=1 843 844[system.cpu1.fuPool.FUList7.opList1] 845type=OpDesc 846issueLat=1 847opClass=MemWrite 848opLat=1 849 850[system.cpu1.fuPool.FUList8] 851type=FUDesc 852children=opList 853count=1 854opList=system.cpu1.fuPool.FUList8.opList 855 856[system.cpu1.fuPool.FUList8.opList] 857type=OpDesc 858issueLat=3 859opClass=IprAccess 860opLat=3 861 862[system.cpu1.icache] 863type=BaseCache 864addr_range=0:18446744073709551615 865assoc=1 866block_size=64 867forward_snoops=true 868hash_delay=1 869is_top_level=true 870latency=1000 871max_miss_count=0 872mshrs=4 873num_cpus=1 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1543type=FUDesc 1544children=opList 1545count=0 1546opList=system.cpu3.fuPool.FUList4.opList 1547 1548[system.cpu3.fuPool.FUList4.opList] 1549type=OpDesc 1550issueLat=1 1551opClass=MemRead 1552opLat=1 1553 1554[system.cpu3.fuPool.FUList5] 1555type=FUDesc 1556children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1557count=4 1558opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1559 1560[system.cpu3.fuPool.FUList5.opList00] 1561type=OpDesc 1562issueLat=1 1563opClass=SimdAdd 1564opLat=1 1565 1566[system.cpu3.fuPool.FUList5.opList01] 1567type=OpDesc 1568issueLat=1 1569opClass=SimdAddAcc 1570opLat=1 1571 1572[system.cpu3.fuPool.FUList5.opList02] 1573type=OpDesc 1574issueLat=1 1575opClass=SimdAlu 1576opLat=1 1577 1578[system.cpu3.fuPool.FUList5.opList03] 1579type=OpDesc 1580issueLat=1 1581opClass=SimdCmp 1582opLat=1 1583 1584[system.cpu3.fuPool.FUList5.opList04] 1585type=OpDesc 1586issueLat=1 1587opClass=SimdCvt 1588opLat=1 1589 1590[system.cpu3.fuPool.FUList5.opList05] 1591type=OpDesc 1592issueLat=1 1593opClass=SimdMisc 1594opLat=1 1595 1596[system.cpu3.fuPool.FUList5.opList06] 1597type=OpDesc 1598issueLat=1 1599opClass=SimdMult 1600opLat=1 1601 1602[system.cpu3.fuPool.FUList5.opList07] 1603type=OpDesc 1604issueLat=1 1605opClass=SimdMultAcc 1606opLat=1 1607 1608[system.cpu3.fuPool.FUList5.opList08] 1609type=OpDesc 1610issueLat=1 1611opClass=SimdShift 1612opLat=1 1613 1614[system.cpu3.fuPool.FUList5.opList09] 1615type=OpDesc 1616issueLat=1 1617opClass=SimdShiftAcc 1618opLat=1 1619 1620[system.cpu3.fuPool.FUList5.opList10] 1621type=OpDesc 1622issueLat=1 1623opClass=SimdSqrt 1624opLat=1 1625 1626[system.cpu3.fuPool.FUList5.opList11] 1627type=OpDesc 1628issueLat=1 1629opClass=SimdFloatAdd 1630opLat=1 1631 1632[system.cpu3.fuPool.FUList5.opList12] 1633type=OpDesc 1634issueLat=1 1635opClass=SimdFloatAlu 1636opLat=1 1637 1638[system.cpu3.fuPool.FUList5.opList13] 1639type=OpDesc 1640issueLat=1 1641opClass=SimdFloatCmp 1642opLat=1 1643 1644[system.cpu3.fuPool.FUList5.opList14] 1645type=OpDesc 1646issueLat=1 1647opClass=SimdFloatCvt 1648opLat=1 1649 1650[system.cpu3.fuPool.FUList5.opList15] 1651type=OpDesc 1652issueLat=1 1653opClass=SimdFloatDiv 1654opLat=1 1655 1656[system.cpu3.fuPool.FUList5.opList16] 1657type=OpDesc 1658issueLat=1 1659opClass=SimdFloatMisc 1660opLat=1 1661 1662[system.cpu3.fuPool.FUList5.opList17] 1663type=OpDesc 1664issueLat=1 1665opClass=SimdFloatMult 1666opLat=1 1667 1668[system.cpu3.fuPool.FUList5.opList18] 1669type=OpDesc 1670issueLat=1 1671opClass=SimdFloatMultAcc 1672opLat=1 1673 1674[system.cpu3.fuPool.FUList5.opList19] 1675type=OpDesc 1676issueLat=1 1677opClass=SimdFloatSqrt 1678opLat=1 1679 1680[system.cpu3.fuPool.FUList6] 1681type=FUDesc 1682children=opList 1683count=0 1684opList=system.cpu3.fuPool.FUList6.opList 1685 1686[system.cpu3.fuPool.FUList6.opList] 1687type=OpDesc 1688issueLat=1 1689opClass=MemWrite 1690opLat=1 1691 1692[system.cpu3.fuPool.FUList7] 1693type=FUDesc 1694children=opList0 opList1 1695count=4 1696opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 1697 1698[system.cpu3.fuPool.FUList7.opList0] 1699type=OpDesc 1700issueLat=1 1701opClass=MemRead 1702opLat=1 1703 1704[system.cpu3.fuPool.FUList7.opList1] 1705type=OpDesc 1706issueLat=1 1707opClass=MemWrite 1708opLat=1 1709 1710[system.cpu3.fuPool.FUList8] 1711type=FUDesc 1712children=opList 1713count=1 1714opList=system.cpu3.fuPool.FUList8.opList 1715 1716[system.cpu3.fuPool.FUList8.opList] 1717type=OpDesc 1718issueLat=3 1719opClass=IprAccess 1720opLat=3 1721 1722[system.cpu3.icache] 1723type=BaseCache 1724addr_range=0:18446744073709551615 1725assoc=1 1726block_size=64 1727forward_snoops=true 1728hash_delay=1 1729is_top_level=true 1730latency=1000 1731max_miss_count=0 1732mshrs=4 1733num_cpus=1 1734prefetch_data_accesses_only=false 1735prefetch_degree=1 1736prefetch_latency=10000 1737prefetch_on_access=false 1738prefetch_past_page=false 1739prefetch_policy=none 1740prefetch_serial_squash=false 1741prefetch_use_cpu_id=true 1742prefetcher_size=100 1743prioritizeRequests=false 1744repl=Null 1745size=32768 1746subblock_size=0 1747tgts_per_mshr=20 1748trace_addr=0 1749two_queue=false 1750write_buffers=8 1751cpu_side=system.cpu3.icache_port 1752mem_side=system.toL2Bus.port[7] 1753 1754[system.cpu3.itb] 1755type=SparcTLB 1756size=64 1757 1758[system.cpu3.tracer] 1759type=ExeTracer 1760 1761[system.l2c] 1762type=BaseCache 1763addr_range=0:18446744073709551615 1764assoc=8 1765block_size=64 1766forward_snoops=true 1767hash_delay=1 1768is_top_level=false 1769latency=10000 1770max_miss_count=0 1771mshrs=92 1772num_cpus=4 1773prefetch_data_accesses_only=false 1774prefetch_degree=1 1775prefetch_latency=100000 1776prefetch_on_access=false 1777prefetch_past_page=false 1778prefetch_policy=none 1779prefetch_serial_squash=false 1780prefetch_use_cpu_id=true 1781prefetcher_size=100 1782prioritizeRequests=false 1783repl=Null 1784size=4194304 1785subblock_size=0 1786tgts_per_mshr=16 1787trace_addr=0 1788two_queue=false 1789write_buffers=8 1790cpu_side=system.toL2Bus.port[0] 1791mem_side=system.membus.port[0] 1792 1793[system.membus] 1794type=Bus 1795block_size=64 1796bus_id=0 1797clock=1000 1798header_cycles=1 1799use_default_range=false 1800width=64 1801port=system.l2c.mem_side system.physmem.port[0] 1802 1803[system.physmem] 1804type=PhysicalMemory 1805file= 1806latency=30000 1807latency_var=0 1808null=false 1809range=0:134217727 1810zero=false 1811port=system.membus.port[1] 1812 1813[system.toL2Bus] 1814type=Bus 1815block_size=64 1816bus_id=0 1817clock=1000 1818header_cycles=1 1819use_default_range=false 1820width=64 1821port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 1822 1823