config.ini revision 8241
1[root] 2type=Root 3children=system 4time_sync_enable=false 5time_sync_period=100000000000 6time_sync_spin_threshold=100000000 7 8[system] 9type=System 10children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus 11mem_mode=timing 12physmem=system.physmem 13work_begin_ckpt_count=0 14work_begin_cpu_id_exit=-1 15work_begin_exit_count=0 16work_cpus_ckpt_count=0 17work_end_ckpt_count=0 18work_end_exit_count=0 19work_item_id=-1 20 21[system.cpu0] 22type=DerivO3CPU 23children=dcache dtb fuPool icache itb tracer workload 24BTBEntries=4096 25BTBTagSize=16 26LFSTSize=1024 27LQEntries=32 28LSQCheckLoads=true 29LSQDepCheckShift=4 30RASSize=16 31SQEntries=32 32SSITSize=1024 33activity=0 34backComSize=5 35cachePorts=200 36checker=Null 37choiceCtrBits=2 38choicePredictorSize=8192 39clock=500 40commitToDecodeDelay=1 41commitToFetchDelay=1 42commitToIEWDelay=1 43commitToRenameDelay=1 44commitWidth=8 45cpu_id=0 46decodeToFetchDelay=1 47decodeToRenameDelay=1 48decodeWidth=8 49defer_registration=false 50dispatchWidth=8 51do_checkpoint_insts=true 52do_statistics_insts=true 53dtb=system.cpu0.dtb 54fetchToDecodeDelay=1 55fetchTrapLatency=1 56fetchWidth=8 57forwardComSize=5 58fuPool=system.cpu0.fuPool 59function_trace=false 60function_trace_start=0 61globalCtrBits=2 62globalHistoryBits=13 63globalPredictorSize=8192 64iewToCommitDelay=1 65iewToDecodeDelay=1 66iewToFetchDelay=1 67iewToRenameDelay=1 68instShiftAmt=2 69issueToExecuteDelay=1 70issueWidth=8 71itb=system.cpu0.itb 72localCtrBits=2 73localHistoryBits=11 74localHistoryTableSize=2048 75localPredictorSize=2048 76max_insts_all_threads=0 77max_insts_any_thread=0 78max_loads_all_threads=0 79max_loads_any_thread=0 80numIQEntries=64 81numPhysFloatRegs=256 82numPhysIntRegs=256 83numROBEntries=192 84numRobs=1 85numThreads=1 86phase=0 87predType=tournament 88progress_interval=0 89renameToDecodeDelay=1 90renameToFetchDelay=1 91renameToIEWDelay=2 92renameToROBDelay=1 93renameWidth=8 94smtCommitPolicy=RoundRobin 95smtFetchPolicy=SingleThread 96smtIQPolicy=Partitioned 97smtIQThreshold=100 98smtLSQPolicy=Partitioned 99smtLSQThreshold=100 100smtNumFetchingThreads=1 101smtROBPolicy=Partitioned 102smtROBThreshold=100 103squashWidth=8 104system=system 105tracer=system.cpu0.tracer 106trapLatency=13 107wbDepth=1 108wbWidth=8 109workload=system.cpu0.workload 110dcache_port=system.cpu0.dcache.cpu_side 111icache_port=system.cpu0.icache.cpu_side 112 113[system.cpu0.dcache] 114type=BaseCache 115addr_range=0:18446744073709551615 116assoc=4 117block_size=64 118forward_snoops=true 119hash_delay=1 120is_top_level=true 121latency=1000 122max_miss_count=0 123mshrs=4 124num_cpus=1 125prefetch_data_accesses_only=false 126prefetch_degree=1 127prefetch_latency=10000 128prefetch_on_access=false 129prefetch_past_page=false 130prefetch_policy=none 131prefetch_serial_squash=false 132prefetch_use_cpu_id=true 133prefetcher_size=100 134prioritizeRequests=false 135repl=Null 136size=32768 137subblock_size=0 138tgts_per_mshr=20 139trace_addr=0 140two_queue=false 141write_buffers=8 142cpu_side=system.cpu0.dcache_port 143mem_side=system.toL2Bus.port[2] 144 145[system.cpu0.dtb] 146type=SparcTLB 147size=64 148 149[system.cpu0.fuPool] 150type=FUPool 151children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 152FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 153 154[system.cpu0.fuPool.FUList0] 155type=FUDesc 156children=opList 157count=6 158opList=system.cpu0.fuPool.FUList0.opList 159 160[system.cpu0.fuPool.FUList0.opList] 161type=OpDesc 162issueLat=1 163opClass=IntAlu 164opLat=1 165 166[system.cpu0.fuPool.FUList1] 167type=FUDesc 168children=opList0 opList1 169count=2 170opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 171 172[system.cpu0.fuPool.FUList1.opList0] 173type=OpDesc 174issueLat=1 175opClass=IntMult 176opLat=3 177 178[system.cpu0.fuPool.FUList1.opList1] 179type=OpDesc 180issueLat=19 181opClass=IntDiv 182opLat=20 183 184[system.cpu0.fuPool.FUList2] 185type=FUDesc 186children=opList0 opList1 opList2 187count=4 188opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 189 190[system.cpu0.fuPool.FUList2.opList0] 191type=OpDesc 192issueLat=1 193opClass=FloatAdd 194opLat=2 195 196[system.cpu0.fuPool.FUList2.opList1] 197type=OpDesc 198issueLat=1 199opClass=FloatCmp 200opLat=2 201 202[system.cpu0.fuPool.FUList2.opList2] 203type=OpDesc 204issueLat=1 205opClass=FloatCvt 206opLat=2 207 208[system.cpu0.fuPool.FUList3] 209type=FUDesc 210children=opList0 opList1 opList2 211count=2 212opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 213 214[system.cpu0.fuPool.FUList3.opList0] 215type=OpDesc 216issueLat=1 217opClass=FloatMult 218opLat=4 219 220[system.cpu0.fuPool.FUList3.opList1] 221type=OpDesc 222issueLat=12 223opClass=FloatDiv 224opLat=12 225 226[system.cpu0.fuPool.FUList3.opList2] 227type=OpDesc 228issueLat=24 229opClass=FloatSqrt 230opLat=24 231 232[system.cpu0.fuPool.FUList4] 233type=FUDesc 234children=opList 235count=0 236opList=system.cpu0.fuPool.FUList4.opList 237 238[system.cpu0.fuPool.FUList4.opList] 239type=OpDesc 240issueLat=1 241opClass=MemRead 242opLat=1 243 244[system.cpu0.fuPool.FUList5] 245type=FUDesc 246children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 247count=4 248opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 249 250[system.cpu0.fuPool.FUList5.opList00] 251type=OpDesc 252issueLat=1 253opClass=SimdAdd 254opLat=1 255 256[system.cpu0.fuPool.FUList5.opList01] 257type=OpDesc 258issueLat=1 259opClass=SimdAddAcc 260opLat=1 261 262[system.cpu0.fuPool.FUList5.opList02] 263type=OpDesc 264issueLat=1 265opClass=SimdAlu 266opLat=1 267 268[system.cpu0.fuPool.FUList5.opList03] 269type=OpDesc 270issueLat=1 271opClass=SimdCmp 272opLat=1 273 274[system.cpu0.fuPool.FUList5.opList04] 275type=OpDesc 276issueLat=1 277opClass=SimdCvt 278opLat=1 279 280[system.cpu0.fuPool.FUList5.opList05] 281type=OpDesc 282issueLat=1 283opClass=SimdMisc 284opLat=1 285 286[system.cpu0.fuPool.FUList5.opList06] 287type=OpDesc 288issueLat=1 289opClass=SimdMult 290opLat=1 291 292[system.cpu0.fuPool.FUList5.opList07] 293type=OpDesc 294issueLat=1 295opClass=SimdMultAcc 296opLat=1 297 298[system.cpu0.fuPool.FUList5.opList08] 299type=OpDesc 300issueLat=1 301opClass=SimdShift 302opLat=1 303 304[system.cpu0.fuPool.FUList5.opList09] 305type=OpDesc 306issueLat=1 307opClass=SimdShiftAcc 308opLat=1 309 310[system.cpu0.fuPool.FUList5.opList10] 311type=OpDesc 312issueLat=1 313opClass=SimdSqrt 314opLat=1 315 316[system.cpu0.fuPool.FUList5.opList11] 317type=OpDesc 318issueLat=1 319opClass=SimdFloatAdd 320opLat=1 321 322[system.cpu0.fuPool.FUList5.opList12] 323type=OpDesc 324issueLat=1 325opClass=SimdFloatAlu 326opLat=1 327 328[system.cpu0.fuPool.FUList5.opList13] 329type=OpDesc 330issueLat=1 331opClass=SimdFloatCmp 332opLat=1 333 334[system.cpu0.fuPool.FUList5.opList14] 335type=OpDesc 336issueLat=1 337opClass=SimdFloatCvt 338opLat=1 339 340[system.cpu0.fuPool.FUList5.opList15] 341type=OpDesc 342issueLat=1 343opClass=SimdFloatDiv 344opLat=1 345 346[system.cpu0.fuPool.FUList5.opList16] 347type=OpDesc 348issueLat=1 349opClass=SimdFloatMisc 350opLat=1 351 352[system.cpu0.fuPool.FUList5.opList17] 353type=OpDesc 354issueLat=1 355opClass=SimdFloatMult 356opLat=1 357 358[system.cpu0.fuPool.FUList5.opList18] 359type=OpDesc 360issueLat=1 361opClass=SimdFloatMultAcc 362opLat=1 363 364[system.cpu0.fuPool.FUList5.opList19] 365type=OpDesc 366issueLat=1 367opClass=SimdFloatSqrt 368opLat=1 369 370[system.cpu0.fuPool.FUList6] 371type=FUDesc 372children=opList 373count=0 374opList=system.cpu0.fuPool.FUList6.opList 375 376[system.cpu0.fuPool.FUList6.opList] 377type=OpDesc 378issueLat=1 379opClass=MemWrite 380opLat=1 381 382[system.cpu0.fuPool.FUList7] 383type=FUDesc 384children=opList0 opList1 385count=4 386opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 387 388[system.cpu0.fuPool.FUList7.opList0] 389type=OpDesc 390issueLat=1 391opClass=MemRead 392opLat=1 393 394[system.cpu0.fuPool.FUList7.opList1] 395type=OpDesc 396issueLat=1 397opClass=MemWrite 398opLat=1 399 400[system.cpu0.fuPool.FUList8] 401type=FUDesc 402children=opList 403count=1 404opList=system.cpu0.fuPool.FUList8.opList 405 406[system.cpu0.fuPool.FUList8.opList] 407type=OpDesc 408issueLat=3 409opClass=IprAccess 410opLat=3 411 412[system.cpu0.icache] 413type=BaseCache 414addr_range=0:18446744073709551615 415assoc=1 416block_size=64 417forward_snoops=true 418hash_delay=1 419is_top_level=true 420latency=1000 421max_miss_count=0 422mshrs=4 423num_cpus=1 424prefetch_data_accesses_only=false 425prefetch_degree=1 426prefetch_latency=10000 427prefetch_on_access=false 428prefetch_past_page=false 429prefetch_policy=none 430prefetch_serial_squash=false 431prefetch_use_cpu_id=true 432prefetcher_size=100 433prioritizeRequests=false 434repl=Null 435size=32768 436subblock_size=0 437tgts_per_mshr=20 438trace_addr=0 439two_queue=false 440write_buffers=8 441cpu_side=system.cpu0.icache_port 442mem_side=system.toL2Bus.port[1] 443 444[system.cpu0.itb] 445type=SparcTLB 446size=64 447 448[system.cpu0.tracer] 449type=ExeTracer 450 451[system.cpu0.workload] 452type=LiveProcess 453cmd=test_atomic 4 454cwd= 455egid=100 456env= 457errout=cerr 458euid=100 459executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic 460gid=100 461input=cin 462max_stack_size=67108864 463output=cout 464pid=100 465ppid=99 466simpoint=0 467system=system 468uid=100 469 470[system.cpu1] 471type=DerivO3CPU 472children=dcache dtb fuPool icache itb tracer 473BTBEntries=4096 474BTBTagSize=16 475LFSTSize=1024 476LQEntries=32 477LSQCheckLoads=true 478LSQDepCheckShift=4 479RASSize=16 480SQEntries=32 481SSITSize=1024 482activity=0 483backComSize=5 484cachePorts=200 485checker=Null 486choiceCtrBits=2 487choicePredictorSize=8192 488clock=500 489commitToDecodeDelay=1 490commitToFetchDelay=1 491commitToIEWDelay=1 492commitToRenameDelay=1 493commitWidth=8 494cpu_id=1 495decodeToFetchDelay=1 496decodeToRenameDelay=1 497decodeWidth=8 498defer_registration=false 499dispatchWidth=8 500do_checkpoint_insts=true 501do_statistics_insts=true 502dtb=system.cpu1.dtb 503fetchToDecodeDelay=1 504fetchTrapLatency=1 505fetchWidth=8 506forwardComSize=5 507fuPool=system.cpu1.fuPool 508function_trace=false 509function_trace_start=0 510globalCtrBits=2 511globalHistoryBits=13 512globalPredictorSize=8192 513iewToCommitDelay=1 514iewToDecodeDelay=1 515iewToFetchDelay=1 516iewToRenameDelay=1 517instShiftAmt=2 518issueToExecuteDelay=1 519issueWidth=8 520itb=system.cpu1.itb 521localCtrBits=2 522localHistoryBits=11 523localHistoryTableSize=2048 524localPredictorSize=2048 525max_insts_all_threads=0 526max_insts_any_thread=0 527max_loads_all_threads=0 528max_loads_any_thread=0 529numIQEntries=64 530numPhysFloatRegs=256 531numPhysIntRegs=256 532numROBEntries=192 533numRobs=1 534numThreads=1 535phase=0 536predType=tournament 537progress_interval=0 538renameToDecodeDelay=1 539renameToFetchDelay=1 540renameToIEWDelay=2 541renameToROBDelay=1 542renameWidth=8 543smtCommitPolicy=RoundRobin 544smtFetchPolicy=SingleThread 545smtIQPolicy=Partitioned 546smtIQThreshold=100 547smtLSQPolicy=Partitioned 548smtLSQThreshold=100 549smtNumFetchingThreads=1 550smtROBPolicy=Partitioned 551smtROBThreshold=100 552squashWidth=8 553system=system 554tracer=system.cpu1.tracer 555trapLatency=13 556wbDepth=1 557wbWidth=8 558workload=system.cpu0.workload 559dcache_port=system.cpu1.dcache.cpu_side 560icache_port=system.cpu1.icache.cpu_side 561 562[system.cpu1.dcache] 563type=BaseCache 564addr_range=0:18446744073709551615 565assoc=4 566block_size=64 567forward_snoops=true 568hash_delay=1 569is_top_level=true 570latency=1000 571max_miss_count=0 572mshrs=4 573num_cpus=1 574prefetch_data_accesses_only=false 575prefetch_degree=1 576prefetch_latency=10000 577prefetch_on_access=false 578prefetch_past_page=false 579prefetch_policy=none 580prefetch_serial_squash=false 581prefetch_use_cpu_id=true 582prefetcher_size=100 583prioritizeRequests=false 584repl=Null 585size=32768 586subblock_size=0 587tgts_per_mshr=20 588trace_addr=0 589two_queue=false 590write_buffers=8 591cpu_side=system.cpu1.dcache_port 592mem_side=system.toL2Bus.port[4] 593 594[system.cpu1.dtb] 595type=SparcTLB 596size=64 597 598[system.cpu1.fuPool] 599type=FUPool 600children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 601FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 602 603[system.cpu1.fuPool.FUList0] 604type=FUDesc 605children=opList 606count=6 607opList=system.cpu1.fuPool.FUList0.opList 608 609[system.cpu1.fuPool.FUList0.opList] 610type=OpDesc 611issueLat=1 612opClass=IntAlu 613opLat=1 614 615[system.cpu1.fuPool.FUList1] 616type=FUDesc 617children=opList0 opList1 618count=2 619opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 620 621[system.cpu1.fuPool.FUList1.opList0] 622type=OpDesc 623issueLat=1 624opClass=IntMult 625opLat=3 626 627[system.cpu1.fuPool.FUList1.opList1] 628type=OpDesc 629issueLat=19 630opClass=IntDiv 631opLat=20 632 633[system.cpu1.fuPool.FUList2] 634type=FUDesc 635children=opList0 opList1 opList2 636count=4 637opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 638 639[system.cpu1.fuPool.FUList2.opList0] 640type=OpDesc 641issueLat=1 642opClass=FloatAdd 643opLat=2 644 645[system.cpu1.fuPool.FUList2.opList1] 646type=OpDesc 647issueLat=1 648opClass=FloatCmp 649opLat=2 650 651[system.cpu1.fuPool.FUList2.opList2] 652type=OpDesc 653issueLat=1 654opClass=FloatCvt 655opLat=2 656 657[system.cpu1.fuPool.FUList3] 658type=FUDesc 659children=opList0 opList1 opList2 660count=2 661opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 662 663[system.cpu1.fuPool.FUList3.opList0] 664type=OpDesc 665issueLat=1 666opClass=FloatMult 667opLat=4 668 669[system.cpu1.fuPool.FUList3.opList1] 670type=OpDesc 671issueLat=12 672opClass=FloatDiv 673opLat=12 674 675[system.cpu1.fuPool.FUList3.opList2] 676type=OpDesc 677issueLat=24 678opClass=FloatSqrt 679opLat=24 680 681[system.cpu1.fuPool.FUList4] 682type=FUDesc 683children=opList 684count=0 685opList=system.cpu1.fuPool.FUList4.opList 686 687[system.cpu1.fuPool.FUList4.opList] 688type=OpDesc 689issueLat=1 690opClass=MemRead 691opLat=1 692 693[system.cpu1.fuPool.FUList5] 694type=FUDesc 695children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 696count=4 697opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 698 699[system.cpu1.fuPool.FUList5.opList00] 700type=OpDesc 701issueLat=1 702opClass=SimdAdd 703opLat=1 704 705[system.cpu1.fuPool.FUList5.opList01] 706type=OpDesc 707issueLat=1 708opClass=SimdAddAcc 709opLat=1 710 711[system.cpu1.fuPool.FUList5.opList02] 712type=OpDesc 713issueLat=1 714opClass=SimdAlu 715opLat=1 716 717[system.cpu1.fuPool.FUList5.opList03] 718type=OpDesc 719issueLat=1 720opClass=SimdCmp 721opLat=1 722 723[system.cpu1.fuPool.FUList5.opList04] 724type=OpDesc 725issueLat=1 726opClass=SimdCvt 727opLat=1 728 729[system.cpu1.fuPool.FUList5.opList05] 730type=OpDesc 731issueLat=1 732opClass=SimdMisc 733opLat=1 734 735[system.cpu1.fuPool.FUList5.opList06] 736type=OpDesc 737issueLat=1 738opClass=SimdMult 739opLat=1 740 741[system.cpu1.fuPool.FUList5.opList07] 742type=OpDesc 743issueLat=1 744opClass=SimdMultAcc 745opLat=1 746 747[system.cpu1.fuPool.FUList5.opList08] 748type=OpDesc 749issueLat=1 750opClass=SimdShift 751opLat=1 752 753[system.cpu1.fuPool.FUList5.opList09] 754type=OpDesc 755issueLat=1 756opClass=SimdShiftAcc 757opLat=1 758 759[system.cpu1.fuPool.FUList5.opList10] 760type=OpDesc 761issueLat=1 762opClass=SimdSqrt 763opLat=1 764 765[system.cpu1.fuPool.FUList5.opList11] 766type=OpDesc 767issueLat=1 768opClass=SimdFloatAdd 769opLat=1 770 771[system.cpu1.fuPool.FUList5.opList12] 772type=OpDesc 773issueLat=1 774opClass=SimdFloatAlu 775opLat=1 776 777[system.cpu1.fuPool.FUList5.opList13] 778type=OpDesc 779issueLat=1 780opClass=SimdFloatCmp 781opLat=1 782 783[system.cpu1.fuPool.FUList5.opList14] 784type=OpDesc 785issueLat=1 786opClass=SimdFloatCvt 787opLat=1 788 789[system.cpu1.fuPool.FUList5.opList15] 790type=OpDesc 791issueLat=1 792opClass=SimdFloatDiv 793opLat=1 794 795[system.cpu1.fuPool.FUList5.opList16] 796type=OpDesc 797issueLat=1 798opClass=SimdFloatMisc 799opLat=1 800 801[system.cpu1.fuPool.FUList5.opList17] 802type=OpDesc 803issueLat=1 804opClass=SimdFloatMult 805opLat=1 806 807[system.cpu1.fuPool.FUList5.opList18] 808type=OpDesc 809issueLat=1 810opClass=SimdFloatMultAcc 811opLat=1 812 813[system.cpu1.fuPool.FUList5.opList19] 814type=OpDesc 815issueLat=1 816opClass=SimdFloatSqrt 817opLat=1 818 819[system.cpu1.fuPool.FUList6] 820type=FUDesc 821children=opList 822count=0 823opList=system.cpu1.fuPool.FUList6.opList 824 825[system.cpu1.fuPool.FUList6.opList] 826type=OpDesc 827issueLat=1 828opClass=MemWrite 829opLat=1 830 831[system.cpu1.fuPool.FUList7] 832type=FUDesc 833children=opList0 opList1 834count=4 835opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 836 837[system.cpu1.fuPool.FUList7.opList0] 838type=OpDesc 839issueLat=1 840opClass=MemRead 841opLat=1 842 843[system.cpu1.fuPool.FUList7.opList1] 844type=OpDesc 845issueLat=1 846opClass=MemWrite 847opLat=1 848 849[system.cpu1.fuPool.FUList8] 850type=FUDesc 851children=opList 852count=1 853opList=system.cpu1.fuPool.FUList8.opList 854 855[system.cpu1.fuPool.FUList8.opList] 856type=OpDesc 857issueLat=3 858opClass=IprAccess 859opLat=3 860 861[system.cpu1.icache] 862type=BaseCache 863addr_range=0:18446744073709551615 864assoc=1 865block_size=64 866forward_snoops=true 867hash_delay=1 868is_top_level=true 869latency=1000 870max_miss_count=0 871mshrs=4 872num_cpus=1 873prefetch_data_accesses_only=false 874prefetch_degree=1 875prefetch_latency=10000 876prefetch_on_access=false 877prefetch_past_page=false 878prefetch_policy=none 879prefetch_serial_squash=false 880prefetch_use_cpu_id=true 881prefetcher_size=100 882prioritizeRequests=false 883repl=Null 884size=32768 885subblock_size=0 886tgts_per_mshr=20 887trace_addr=0 888two_queue=false 889write_buffers=8 890cpu_side=system.cpu1.icache_port 891mem_side=system.toL2Bus.port[3] 892 893[system.cpu1.itb] 894type=SparcTLB 895size=64 896 897[system.cpu1.tracer] 898type=ExeTracer 899 900[system.cpu2] 901type=DerivO3CPU 902children=dcache dtb fuPool icache itb tracer 903BTBEntries=4096 904BTBTagSize=16 905LFSTSize=1024 906LQEntries=32 907LSQCheckLoads=true 908LSQDepCheckShift=4 909RASSize=16 910SQEntries=32 911SSITSize=1024 912activity=0 913backComSize=5 914cachePorts=200 915checker=Null 916choiceCtrBits=2 917choicePredictorSize=8192 918clock=500 919commitToDecodeDelay=1 920commitToFetchDelay=1 921commitToIEWDelay=1 922commitToRenameDelay=1 923commitWidth=8 924cpu_id=2 925decodeToFetchDelay=1 926decodeToRenameDelay=1 927decodeWidth=8 928defer_registration=false 929dispatchWidth=8 930do_checkpoint_insts=true 931do_statistics_insts=true 932dtb=system.cpu2.dtb 933fetchToDecodeDelay=1 934fetchTrapLatency=1 935fetchWidth=8 936forwardComSize=5 937fuPool=system.cpu2.fuPool 938function_trace=false 939function_trace_start=0 940globalCtrBits=2 941globalHistoryBits=13 942globalPredictorSize=8192 943iewToCommitDelay=1 944iewToDecodeDelay=1 945iewToFetchDelay=1 946iewToRenameDelay=1 947instShiftAmt=2 948issueToExecuteDelay=1 949issueWidth=8 950itb=system.cpu2.itb 951localCtrBits=2 952localHistoryBits=11 953localHistoryTableSize=2048 954localPredictorSize=2048 955max_insts_all_threads=0 956max_insts_any_thread=0 957max_loads_all_threads=0 958max_loads_any_thread=0 959numIQEntries=64 960numPhysFloatRegs=256 961numPhysIntRegs=256 962numROBEntries=192 963numRobs=1 964numThreads=1 965phase=0 966predType=tournament 967progress_interval=0 968renameToDecodeDelay=1 969renameToFetchDelay=1 970renameToIEWDelay=2 971renameToROBDelay=1 972renameWidth=8 973smtCommitPolicy=RoundRobin 974smtFetchPolicy=SingleThread 975smtIQPolicy=Partitioned 976smtIQThreshold=100 977smtLSQPolicy=Partitioned 978smtLSQThreshold=100 979smtNumFetchingThreads=1 980smtROBPolicy=Partitioned 981smtROBThreshold=100 982squashWidth=8 983system=system 984tracer=system.cpu2.tracer 985trapLatency=13 986wbDepth=1 987wbWidth=8 988workload=system.cpu0.workload 989dcache_port=system.cpu2.dcache.cpu_side 990icache_port=system.cpu2.icache.cpu_side 991 992[system.cpu2.dcache] 993type=BaseCache 994addr_range=0:18446744073709551615 995assoc=4 996block_size=64 997forward_snoops=true 998hash_delay=1 999is_top_level=true 1000latency=1000 1001max_miss_count=0 1002mshrs=4 1003num_cpus=1 1004prefetch_data_accesses_only=false 1005prefetch_degree=1 1006prefetch_latency=10000 1007prefetch_on_access=false 1008prefetch_past_page=false 1009prefetch_policy=none 1010prefetch_serial_squash=false 1011prefetch_use_cpu_id=true 1012prefetcher_size=100 1013prioritizeRequests=false 1014repl=Null 1015size=32768 1016subblock_size=0 1017tgts_per_mshr=20 1018trace_addr=0 1019two_queue=false 1020write_buffers=8 1021cpu_side=system.cpu2.dcache_port 1022mem_side=system.toL2Bus.port[6] 1023 1024[system.cpu2.dtb] 1025type=SparcTLB 1026size=64 1027 1028[system.cpu2.fuPool] 1029type=FUPool 1030children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1031FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1032 1033[system.cpu2.fuPool.FUList0] 1034type=FUDesc 1035children=opList 1036count=6 1037opList=system.cpu2.fuPool.FUList0.opList 1038 1039[system.cpu2.fuPool.FUList0.opList] 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1085opLat=2 1086 1087[system.cpu2.fuPool.FUList3] 1088type=FUDesc 1089children=opList0 opList1 opList2 1090count=2 1091opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1092 1093[system.cpu2.fuPool.FUList3.opList0] 1094type=OpDesc 1095issueLat=1 1096opClass=FloatMult 1097opLat=4 1098 1099[system.cpu2.fuPool.FUList3.opList1] 1100type=OpDesc 1101issueLat=12 1102opClass=FloatDiv 1103opLat=12 1104 1105[system.cpu2.fuPool.FUList3.opList2] 1106type=OpDesc 1107issueLat=24 1108opClass=FloatSqrt 1109opLat=24 1110 1111[system.cpu2.fuPool.FUList4] 1112type=FUDesc 1113children=opList 1114count=0 1115opList=system.cpu2.fuPool.FUList4.opList 1116 1117[system.cpu2.fuPool.FUList4.opList] 1118type=OpDesc 1119issueLat=1 1120opClass=MemRead 1121opLat=1 1122 1123[system.cpu2.fuPool.FUList5] 1124type=FUDesc 1125children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1126count=4 1127opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1128 1129[system.cpu2.fuPool.FUList5.opList00] 1130type=OpDesc 1131issueLat=1 1132opClass=SimdAdd 1133opLat=1 1134 1135[system.cpu2.fuPool.FUList5.opList01] 1136type=OpDesc 1137issueLat=1 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1243[system.cpu2.fuPool.FUList5.opList19] 1244type=OpDesc 1245issueLat=1 1246opClass=SimdFloatSqrt 1247opLat=1 1248 1249[system.cpu2.fuPool.FUList6] 1250type=FUDesc 1251children=opList 1252count=0 1253opList=system.cpu2.fuPool.FUList6.opList 1254 1255[system.cpu2.fuPool.FUList6.opList] 1256type=OpDesc 1257issueLat=1 1258opClass=MemWrite 1259opLat=1 1260 1261[system.cpu2.fuPool.FUList7] 1262type=FUDesc 1263children=opList0 opList1 1264count=4 1265opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1266 1267[system.cpu2.fuPool.FUList7.opList0] 1268type=OpDesc 1269issueLat=1 1270opClass=MemRead 1271opLat=1 1272 1273[system.cpu2.fuPool.FUList7.opList1] 1274type=OpDesc 1275issueLat=1 1276opClass=MemWrite 1277opLat=1 1278 1279[system.cpu2.fuPool.FUList8] 1280type=FUDesc 1281children=opList 1282count=1 1283opList=system.cpu2.fuPool.FUList8.opList 1284 1285[system.cpu2.fuPool.FUList8.opList] 1286type=OpDesc 1287issueLat=3 1288opClass=IprAccess 1289opLat=3 1290 1291[system.cpu2.icache] 1292type=BaseCache 1293addr_range=0:18446744073709551615 1294assoc=1 1295block_size=64 1296forward_snoops=true 1297hash_delay=1 1298is_top_level=true 1299latency=1000 1300max_miss_count=0 1301mshrs=4 1302num_cpus=1 1303prefetch_data_accesses_only=false 1304prefetch_degree=1 1305prefetch_latency=10000 1306prefetch_on_access=false 1307prefetch_past_page=false 1308prefetch_policy=none 1309prefetch_serial_squash=false 1310prefetch_use_cpu_id=true 1311prefetcher_size=100 1312prioritizeRequests=false 1313repl=Null 1314size=32768 1315subblock_size=0 1316tgts_per_mshr=20 1317trace_addr=0 1318two_queue=false 1319write_buffers=8 1320cpu_side=system.cpu2.icache_port 1321mem_side=system.toL2Bus.port[5] 1322 1323[system.cpu2.itb] 1324type=SparcTLB 1325size=64 1326 1327[system.cpu2.tracer] 1328type=ExeTracer 1329 1330[system.cpu3] 1331type=DerivO3CPU 1332children=dcache dtb fuPool icache itb tracer 1333BTBEntries=4096 1334BTBTagSize=16 1335LFSTSize=1024 1336LQEntries=32 1337LSQCheckLoads=true 1338LSQDepCheckShift=4 1339RASSize=16 1340SQEntries=32 1341SSITSize=1024 1342activity=0 1343backComSize=5 1344cachePorts=200 1345checker=Null 1346choiceCtrBits=2 1347choicePredictorSize=8192 1348clock=500 1349commitToDecodeDelay=1 1350commitToFetchDelay=1 1351commitToIEWDelay=1 1352commitToRenameDelay=1 1353commitWidth=8 1354cpu_id=3 1355decodeToFetchDelay=1 1356decodeToRenameDelay=1 1357decodeWidth=8 1358defer_registration=false 1359dispatchWidth=8 1360do_checkpoint_insts=true 1361do_statistics_insts=true 1362dtb=system.cpu3.dtb 1363fetchToDecodeDelay=1 1364fetchTrapLatency=1 1365fetchWidth=8 1366forwardComSize=5 1367fuPool=system.cpu3.fuPool 1368function_trace=false 1369function_trace_start=0 1370globalCtrBits=2 1371globalHistoryBits=13 1372globalPredictorSize=8192 1373iewToCommitDelay=1 1374iewToDecodeDelay=1 1375iewToFetchDelay=1 1376iewToRenameDelay=1 1377instShiftAmt=2 1378issueToExecuteDelay=1 1379issueWidth=8 1380itb=system.cpu3.itb 1381localCtrBits=2 1382localHistoryBits=11 1383localHistoryTableSize=2048 1384localPredictorSize=2048 1385max_insts_all_threads=0 1386max_insts_any_thread=0 1387max_loads_all_threads=0 1388max_loads_any_thread=0 1389numIQEntries=64 1390numPhysFloatRegs=256 1391numPhysIntRegs=256 1392numROBEntries=192 1393numRobs=1 1394numThreads=1 1395phase=0 1396predType=tournament 1397progress_interval=0 1398renameToDecodeDelay=1 1399renameToFetchDelay=1 1400renameToIEWDelay=2 1401renameToROBDelay=1 1402renameWidth=8 1403smtCommitPolicy=RoundRobin 1404smtFetchPolicy=SingleThread 1405smtIQPolicy=Partitioned 1406smtIQThreshold=100 1407smtLSQPolicy=Partitioned 1408smtLSQThreshold=100 1409smtNumFetchingThreads=1 1410smtROBPolicy=Partitioned 1411smtROBThreshold=100 1412squashWidth=8 1413system=system 1414tracer=system.cpu3.tracer 1415trapLatency=13 1416wbDepth=1 1417wbWidth=8 1418workload=system.cpu0.workload 1419dcache_port=system.cpu3.dcache.cpu_side 1420icache_port=system.cpu3.icache.cpu_side 1421 1422[system.cpu3.dcache] 1423type=BaseCache 1424addr_range=0:18446744073709551615 1425assoc=4 1426block_size=64 1427forward_snoops=true 1428hash_delay=1 1429is_top_level=true 1430latency=1000 1431max_miss_count=0 1432mshrs=4 1433num_cpus=1 1434prefetch_data_accesses_only=false 1435prefetch_degree=1 1436prefetch_latency=10000 1437prefetch_on_access=false 1438prefetch_past_page=false 1439prefetch_policy=none 1440prefetch_serial_squash=false 1441prefetch_use_cpu_id=true 1442prefetcher_size=100 1443prioritizeRequests=false 1444repl=Null 1445size=32768 1446subblock_size=0 1447tgts_per_mshr=20 1448trace_addr=0 1449two_queue=false 1450write_buffers=8 1451cpu_side=system.cpu3.dcache_port 1452mem_side=system.toL2Bus.port[8] 1453 1454[system.cpu3.dtb] 1455type=SparcTLB 1456size=64 1457 1458[system.cpu3.fuPool] 1459type=FUPool 1460children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1461FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1462 1463[system.cpu3.fuPool.FUList0] 1464type=FUDesc 1465children=opList 1466count=6 1467opList=system.cpu3.fuPool.FUList0.opList 1468 1469[system.cpu3.fuPool.FUList0.opList] 1470type=OpDesc 1471issueLat=1 1472opClass=IntAlu 1473opLat=1 1474 1475[system.cpu3.fuPool.FUList1] 1476type=FUDesc 1477children=opList0 opList1 1478count=2 1479opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1480 1481[system.cpu3.fuPool.FUList1.opList0] 1482type=OpDesc 1483issueLat=1 1484opClass=IntMult 1485opLat=3 1486 1487[system.cpu3.fuPool.FUList1.opList1] 1488type=OpDesc 1489issueLat=19 1490opClass=IntDiv 1491opLat=20 1492 1493[system.cpu3.fuPool.FUList2] 1494type=FUDesc 1495children=opList0 opList1 opList2 1496count=4 1497opList=system.cpu3.fuPool.FUList2.opList0 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system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1558 1559[system.cpu3.fuPool.FUList5.opList00] 1560type=OpDesc 1561issueLat=1 1562opClass=SimdAdd 1563opLat=1 1564 1565[system.cpu3.fuPool.FUList5.opList01] 1566type=OpDesc 1567issueLat=1 1568opClass=SimdAddAcc 1569opLat=1 1570 1571[system.cpu3.fuPool.FUList5.opList02] 1572type=OpDesc 1573issueLat=1 1574opClass=SimdAlu 1575opLat=1 1576 1577[system.cpu3.fuPool.FUList5.opList03] 1578type=OpDesc 1579issueLat=1 1580opClass=SimdCmp 1581opLat=1 1582 1583[system.cpu3.fuPool.FUList5.opList04] 1584type=OpDesc 1585issueLat=1 1586opClass=SimdCvt 1587opLat=1 1588 1589[system.cpu3.fuPool.FUList5.opList05] 1590type=OpDesc 1591issueLat=1 1592opClass=SimdMisc 1593opLat=1 1594 1595[system.cpu3.fuPool.FUList5.opList06] 1596type=OpDesc 1597issueLat=1 1598opClass=SimdMult 1599opLat=1 1600 1601[system.cpu3.fuPool.FUList5.opList07] 1602type=OpDesc 1603issueLat=1 1604opClass=SimdMultAcc 1605opLat=1 1606 1607[system.cpu3.fuPool.FUList5.opList08] 1608type=OpDesc 1609issueLat=1 1610opClass=SimdShift 1611opLat=1 1612 1613[system.cpu3.fuPool.FUList5.opList09] 1614type=OpDesc 1615issueLat=1 1616opClass=SimdShiftAcc 1617opLat=1 1618 1619[system.cpu3.fuPool.FUList5.opList10] 1620type=OpDesc 1621issueLat=1 1622opClass=SimdSqrt 1623opLat=1 1624 1625[system.cpu3.fuPool.FUList5.opList11] 1626type=OpDesc 1627issueLat=1 1628opClass=SimdFloatAdd 1629opLat=1 1630 1631[system.cpu3.fuPool.FUList5.opList12] 1632type=OpDesc 1633issueLat=1 1634opClass=SimdFloatAlu 1635opLat=1 1636 1637[system.cpu3.fuPool.FUList5.opList13] 1638type=OpDesc 1639issueLat=1 1640opClass=SimdFloatCmp 1641opLat=1 1642 1643[system.cpu3.fuPool.FUList5.opList14] 1644type=OpDesc 1645issueLat=1 1646opClass=SimdFloatCvt 1647opLat=1 1648 1649[system.cpu3.fuPool.FUList5.opList15] 1650type=OpDesc 1651issueLat=1 1652opClass=SimdFloatDiv 1653opLat=1 1654 1655[system.cpu3.fuPool.FUList5.opList16] 1656type=OpDesc 1657issueLat=1 1658opClass=SimdFloatMisc 1659opLat=1 1660 1661[system.cpu3.fuPool.FUList5.opList17] 1662type=OpDesc 1663issueLat=1 1664opClass=SimdFloatMult 1665opLat=1 1666 1667[system.cpu3.fuPool.FUList5.opList18] 1668type=OpDesc 1669issueLat=1 1670opClass=SimdFloatMultAcc 1671opLat=1 1672 1673[system.cpu3.fuPool.FUList5.opList19] 1674type=OpDesc 1675issueLat=1 1676opClass=SimdFloatSqrt 1677opLat=1 1678 1679[system.cpu3.fuPool.FUList6] 1680type=FUDesc 1681children=opList 1682count=0 1683opList=system.cpu3.fuPool.FUList6.opList 1684 1685[system.cpu3.fuPool.FUList6.opList] 1686type=OpDesc 1687issueLat=1 1688opClass=MemWrite 1689opLat=1 1690 1691[system.cpu3.fuPool.FUList7] 1692type=FUDesc 1693children=opList0 opList1 1694count=4 1695opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 1696 1697[system.cpu3.fuPool.FUList7.opList0] 1698type=OpDesc 1699issueLat=1 1700opClass=MemRead 1701opLat=1 1702 1703[system.cpu3.fuPool.FUList7.opList1] 1704type=OpDesc 1705issueLat=1 1706opClass=MemWrite 1707opLat=1 1708 1709[system.cpu3.fuPool.FUList8] 1710type=FUDesc 1711children=opList 1712count=1 1713opList=system.cpu3.fuPool.FUList8.opList 1714 1715[system.cpu3.fuPool.FUList8.opList] 1716type=OpDesc 1717issueLat=3 1718opClass=IprAccess 1719opLat=3 1720 1721[system.cpu3.icache] 1722type=BaseCache 1723addr_range=0:18446744073709551615 1724assoc=1 1725block_size=64 1726forward_snoops=true 1727hash_delay=1 1728is_top_level=true 1729latency=1000 1730max_miss_count=0 1731mshrs=4 1732num_cpus=1 1733prefetch_data_accesses_only=false 1734prefetch_degree=1 1735prefetch_latency=10000 1736prefetch_on_access=false 1737prefetch_past_page=false 1738prefetch_policy=none 1739prefetch_serial_squash=false 1740prefetch_use_cpu_id=true 1741prefetcher_size=100 1742prioritizeRequests=false 1743repl=Null 1744size=32768 1745subblock_size=0 1746tgts_per_mshr=20 1747trace_addr=0 1748two_queue=false 1749write_buffers=8 1750cpu_side=system.cpu3.icache_port 1751mem_side=system.toL2Bus.port[7] 1752 1753[system.cpu3.itb] 1754type=SparcTLB 1755size=64 1756 1757[system.cpu3.tracer] 1758type=ExeTracer 1759 1760[system.l2c] 1761type=BaseCache 1762addr_range=0:18446744073709551615 1763assoc=8 1764block_size=64 1765forward_snoops=true 1766hash_delay=1 1767is_top_level=false 1768latency=10000 1769max_miss_count=0 1770mshrs=92 1771num_cpus=4 1772prefetch_data_accesses_only=false 1773prefetch_degree=1 1774prefetch_latency=100000 1775prefetch_on_access=false 1776prefetch_past_page=false 1777prefetch_policy=none 1778prefetch_serial_squash=false 1779prefetch_use_cpu_id=true 1780prefetcher_size=100 1781prioritizeRequests=false 1782repl=Null 1783size=4194304 1784subblock_size=0 1785tgts_per_mshr=16 1786trace_addr=0 1787two_queue=false 1788write_buffers=8 1789cpu_side=system.toL2Bus.port[0] 1790mem_side=system.membus.port[0] 1791 1792[system.membus] 1793type=Bus 1794block_size=64 1795bus_id=0 1796clock=1000 1797header_cycles=1 1798use_default_range=false 1799width=64 1800port=system.l2c.mem_side system.physmem.port[0] 1801 1802[system.physmem] 1803type=PhysicalMemory 1804file= 1805latency=30000 1806latency_var=0 1807null=false 1808range=0:134217727 1809zero=false 1810port=system.membus.port[1] 1811 1812[system.toL2Bus] 1813type=Bus 1814block_size=64 1815bus_id=0 1816clock=1000 1817header_cycles=1 1818use_default_range=false 1819width=64 1820port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 1821 1822