config.ini revision 8200
1[root] 2type=Root 3children=system 4time_sync_enable=false 5time_sync_period=100000000000 6time_sync_spin_threshold=100000000 7 8[system] 9type=System 10children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus 11mem_mode=timing 12physmem=system.physmem 13work_begin_ckpt_count=0 14work_begin_cpu_id_exit=-1 15work_begin_exit_count=0 16work_cpus_ckpt_count=0 17work_end_ckpt_count=0 18work_end_exit_count=0 19work_item_id=-1 20 21[system.cpu0] 22type=DerivO3CPU 23children=dcache dtb fuPool icache itb tracer workload 24BTBEntries=4096 25BTBTagSize=16 26LFSTSize=1024 27LQEntries=32 28RASSize=16 29SQEntries=32 30SSITSize=1024 31activity=0 32backComSize=5 33cachePorts=200 34checker=Null 35choiceCtrBits=2 36choicePredictorSize=8192 37clock=500 38commitToDecodeDelay=1 39commitToFetchDelay=1 40commitToIEWDelay=1 41commitToRenameDelay=1 42commitWidth=8 43cpu_id=0 44decodeToFetchDelay=1 45decodeToRenameDelay=1 46decodeWidth=8 47defer_registration=false 48dispatchWidth=8 49do_checkpoint_insts=true 50do_statistics_insts=true 51dtb=system.cpu0.dtb 52fetchToDecodeDelay=1 53fetchTrapLatency=1 54fetchWidth=8 55forwardComSize=5 56fuPool=system.cpu0.fuPool 57function_trace=false 58function_trace_start=0 59globalCtrBits=2 60globalHistoryBits=13 61globalPredictorSize=8192 62iewToCommitDelay=1 63iewToDecodeDelay=1 64iewToFetchDelay=1 65iewToRenameDelay=1 66instShiftAmt=2 67issueToExecuteDelay=1 68issueWidth=8 69itb=system.cpu0.itb 70localCtrBits=2 71localHistoryBits=11 72localHistoryTableSize=2048 73localPredictorSize=2048 74max_insts_all_threads=0 75max_insts_any_thread=0 76max_loads_all_threads=0 77max_loads_any_thread=0 78numIQEntries=64 79numPhysFloatRegs=256 80numPhysIntRegs=256 81numROBEntries=192 82numRobs=1 83numThreads=1 84phase=0 85predType=tournament 86progress_interval=0 87renameToDecodeDelay=1 88renameToFetchDelay=1 89renameToIEWDelay=2 90renameToROBDelay=1 91renameWidth=8 92smtCommitPolicy=RoundRobin 93smtFetchPolicy=SingleThread 94smtIQPolicy=Partitioned 95smtIQThreshold=100 96smtLSQPolicy=Partitioned 97smtLSQThreshold=100 98smtNumFetchingThreads=1 99smtROBPolicy=Partitioned 100smtROBThreshold=100 101squashWidth=8 102system=system 103tracer=system.cpu0.tracer 104trapLatency=13 105wbDepth=1 106wbWidth=8 107workload=system.cpu0.workload 108dcache_port=system.cpu0.dcache.cpu_side 109icache_port=system.cpu0.icache.cpu_side 110 111[system.cpu0.dcache] 112type=BaseCache 113addr_range=0:18446744073709551615 114assoc=4 115block_size=64 116forward_snoops=true 117hash_delay=1 118is_top_level=true 119latency=1000 120max_miss_count=0 121mshrs=4 122num_cpus=1 123prefetch_data_accesses_only=false 124prefetch_degree=1 125prefetch_latency=10000 126prefetch_on_access=false 127prefetch_past_page=false 128prefetch_policy=none 129prefetch_serial_squash=false 130prefetch_use_cpu_id=true 131prefetcher_size=100 132prioritizeRequests=false 133repl=Null 134size=32768 135subblock_size=0 136tgts_per_mshr=20 137trace_addr=0 138two_queue=false 139write_buffers=8 140cpu_side=system.cpu0.dcache_port 141mem_side=system.toL2Bus.port[2] 142 143[system.cpu0.dtb] 144type=SparcTLB 145size=64 146 147[system.cpu0.fuPool] 148type=FUPool 149children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 150FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 151 152[system.cpu0.fuPool.FUList0] 153type=FUDesc 154children=opList 155count=6 156opList=system.cpu0.fuPool.FUList0.opList 157 158[system.cpu0.fuPool.FUList0.opList] 159type=OpDesc 160issueLat=1 161opClass=IntAlu 162opLat=1 163 164[system.cpu0.fuPool.FUList1] 165type=FUDesc 166children=opList0 opList1 167count=2 168opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 169 170[system.cpu0.fuPool.FUList1.opList0] 171type=OpDesc 172issueLat=1 173opClass=IntMult 174opLat=3 175 176[system.cpu0.fuPool.FUList1.opList1] 177type=OpDesc 178issueLat=19 179opClass=IntDiv 180opLat=20 181 182[system.cpu0.fuPool.FUList2] 183type=FUDesc 184children=opList0 opList1 opList2 185count=4 186opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 187 188[system.cpu0.fuPool.FUList2.opList0] 189type=OpDesc 190issueLat=1 191opClass=FloatAdd 192opLat=2 193 194[system.cpu0.fuPool.FUList2.opList1] 195type=OpDesc 196issueLat=1 197opClass=FloatCmp 198opLat=2 199 200[system.cpu0.fuPool.FUList2.opList2] 201type=OpDesc 202issueLat=1 203opClass=FloatCvt 204opLat=2 205 206[system.cpu0.fuPool.FUList3] 207type=FUDesc 208children=opList0 opList1 opList2 209count=2 210opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 211 212[system.cpu0.fuPool.FUList3.opList0] 213type=OpDesc 214issueLat=1 215opClass=FloatMult 216opLat=4 217 218[system.cpu0.fuPool.FUList3.opList1] 219type=OpDesc 220issueLat=12 221opClass=FloatDiv 222opLat=12 223 224[system.cpu0.fuPool.FUList3.opList2] 225type=OpDesc 226issueLat=24 227opClass=FloatSqrt 228opLat=24 229 230[system.cpu0.fuPool.FUList4] 231type=FUDesc 232children=opList 233count=0 234opList=system.cpu0.fuPool.FUList4.opList 235 236[system.cpu0.fuPool.FUList4.opList] 237type=OpDesc 238issueLat=1 239opClass=MemRead 240opLat=1 241 242[system.cpu0.fuPool.FUList5] 243type=FUDesc 244children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 245count=4 246opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 247 248[system.cpu0.fuPool.FUList5.opList00] 249type=OpDesc 250issueLat=1 251opClass=SimdAdd 252opLat=1 253 254[system.cpu0.fuPool.FUList5.opList01] 255type=OpDesc 256issueLat=1 257opClass=SimdAddAcc 258opLat=1 259 260[system.cpu0.fuPool.FUList5.opList02] 261type=OpDesc 262issueLat=1 263opClass=SimdAlu 264opLat=1 265 266[system.cpu0.fuPool.FUList5.opList03] 267type=OpDesc 268issueLat=1 269opClass=SimdCmp 270opLat=1 271 272[system.cpu0.fuPool.FUList5.opList04] 273type=OpDesc 274issueLat=1 275opClass=SimdCvt 276opLat=1 277 278[system.cpu0.fuPool.FUList5.opList05] 279type=OpDesc 280issueLat=1 281opClass=SimdMisc 282opLat=1 283 284[system.cpu0.fuPool.FUList5.opList06] 285type=OpDesc 286issueLat=1 287opClass=SimdMult 288opLat=1 289 290[system.cpu0.fuPool.FUList5.opList07] 291type=OpDesc 292issueLat=1 293opClass=SimdMultAcc 294opLat=1 295 296[system.cpu0.fuPool.FUList5.opList08] 297type=OpDesc 298issueLat=1 299opClass=SimdShift 300opLat=1 301 302[system.cpu0.fuPool.FUList5.opList09] 303type=OpDesc 304issueLat=1 305opClass=SimdShiftAcc 306opLat=1 307 308[system.cpu0.fuPool.FUList5.opList10] 309type=OpDesc 310issueLat=1 311opClass=SimdSqrt 312opLat=1 313 314[system.cpu0.fuPool.FUList5.opList11] 315type=OpDesc 316issueLat=1 317opClass=SimdFloatAdd 318opLat=1 319 320[system.cpu0.fuPool.FUList5.opList12] 321type=OpDesc 322issueLat=1 323opClass=SimdFloatAlu 324opLat=1 325 326[system.cpu0.fuPool.FUList5.opList13] 327type=OpDesc 328issueLat=1 329opClass=SimdFloatCmp 330opLat=1 331 332[system.cpu0.fuPool.FUList5.opList14] 333type=OpDesc 334issueLat=1 335opClass=SimdFloatCvt 336opLat=1 337 338[system.cpu0.fuPool.FUList5.opList15] 339type=OpDesc 340issueLat=1 341opClass=SimdFloatDiv 342opLat=1 343 344[system.cpu0.fuPool.FUList5.opList16] 345type=OpDesc 346issueLat=1 347opClass=SimdFloatMisc 348opLat=1 349 350[system.cpu0.fuPool.FUList5.opList17] 351type=OpDesc 352issueLat=1 353opClass=SimdFloatMult 354opLat=1 355 356[system.cpu0.fuPool.FUList5.opList18] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatMultAcc 360opLat=1 361 362[system.cpu0.fuPool.FUList5.opList19] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatSqrt 366opLat=1 367 368[system.cpu0.fuPool.FUList6] 369type=FUDesc 370children=opList 371count=0 372opList=system.cpu0.fuPool.FUList6.opList 373 374[system.cpu0.fuPool.FUList6.opList] 375type=OpDesc 376issueLat=1 377opClass=MemWrite 378opLat=1 379 380[system.cpu0.fuPool.FUList7] 381type=FUDesc 382children=opList0 opList1 383count=4 384opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 385 386[system.cpu0.fuPool.FUList7.opList0] 387type=OpDesc 388issueLat=1 389opClass=MemRead 390opLat=1 391 392[system.cpu0.fuPool.FUList7.opList1] 393type=OpDesc 394issueLat=1 395opClass=MemWrite 396opLat=1 397 398[system.cpu0.fuPool.FUList8] 399type=FUDesc 400children=opList 401count=1 402opList=system.cpu0.fuPool.FUList8.opList 403 404[system.cpu0.fuPool.FUList8.opList] 405type=OpDesc 406issueLat=3 407opClass=IprAccess 408opLat=3 409 410[system.cpu0.icache] 411type=BaseCache 412addr_range=0:18446744073709551615 413assoc=1 414block_size=64 415forward_snoops=true 416hash_delay=1 417is_top_level=true 418latency=1000 419max_miss_count=0 420mshrs=4 421num_cpus=1 422prefetch_data_accesses_only=false 423prefetch_degree=1 424prefetch_latency=10000 425prefetch_on_access=false 426prefetch_past_page=false 427prefetch_policy=none 428prefetch_serial_squash=false 429prefetch_use_cpu_id=true 430prefetcher_size=100 431prioritizeRequests=false 432repl=Null 433size=32768 434subblock_size=0 435tgts_per_mshr=20 436trace_addr=0 437two_queue=false 438write_buffers=8 439cpu_side=system.cpu0.icache_port 440mem_side=system.toL2Bus.port[1] 441 442[system.cpu0.itb] 443type=SparcTLB 444size=64 445 446[system.cpu0.tracer] 447type=ExeTracer 448 449[system.cpu0.workload] 450type=LiveProcess 451cmd=test_atomic 4 452cwd= 453egid=100 454env= 455errout=cerr 456euid=100 457executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic 458gid=100 459input=cin 460max_stack_size=67108864 461output=cout 462pid=100 463ppid=99 464simpoint=0 465system=system 466uid=100 467 468[system.cpu1] 469type=DerivO3CPU 470children=dcache dtb fuPool icache itb tracer 471BTBEntries=4096 472BTBTagSize=16 473LFSTSize=1024 474LQEntries=32 475RASSize=16 476SQEntries=32 477SSITSize=1024 478activity=0 479backComSize=5 480cachePorts=200 481checker=Null 482choiceCtrBits=2 483choicePredictorSize=8192 484clock=500 485commitToDecodeDelay=1 486commitToFetchDelay=1 487commitToIEWDelay=1 488commitToRenameDelay=1 489commitWidth=8 490cpu_id=1 491decodeToFetchDelay=1 492decodeToRenameDelay=1 493decodeWidth=8 494defer_registration=false 495dispatchWidth=8 496do_checkpoint_insts=true 497do_statistics_insts=true 498dtb=system.cpu1.dtb 499fetchToDecodeDelay=1 500fetchTrapLatency=1 501fetchWidth=8 502forwardComSize=5 503fuPool=system.cpu1.fuPool 504function_trace=false 505function_trace_start=0 506globalCtrBits=2 507globalHistoryBits=13 508globalPredictorSize=8192 509iewToCommitDelay=1 510iewToDecodeDelay=1 511iewToFetchDelay=1 512iewToRenameDelay=1 513instShiftAmt=2 514issueToExecuteDelay=1 515issueWidth=8 516itb=system.cpu1.itb 517localCtrBits=2 518localHistoryBits=11 519localHistoryTableSize=2048 520localPredictorSize=2048 521max_insts_all_threads=0 522max_insts_any_thread=0 523max_loads_all_threads=0 524max_loads_any_thread=0 525numIQEntries=64 526numPhysFloatRegs=256 527numPhysIntRegs=256 528numROBEntries=192 529numRobs=1 530numThreads=1 531phase=0 532predType=tournament 533progress_interval=0 534renameToDecodeDelay=1 535renameToFetchDelay=1 536renameToIEWDelay=2 537renameToROBDelay=1 538renameWidth=8 539smtCommitPolicy=RoundRobin 540smtFetchPolicy=SingleThread 541smtIQPolicy=Partitioned 542smtIQThreshold=100 543smtLSQPolicy=Partitioned 544smtLSQThreshold=100 545smtNumFetchingThreads=1 546smtROBPolicy=Partitioned 547smtROBThreshold=100 548squashWidth=8 549system=system 550tracer=system.cpu1.tracer 551trapLatency=13 552wbDepth=1 553wbWidth=8 554workload=system.cpu0.workload 555dcache_port=system.cpu1.dcache.cpu_side 556icache_port=system.cpu1.icache.cpu_side 557 558[system.cpu1.dcache] 559type=BaseCache 560addr_range=0:18446744073709551615 561assoc=4 562block_size=64 563forward_snoops=true 564hash_delay=1 565is_top_level=true 566latency=1000 567max_miss_count=0 568mshrs=4 569num_cpus=1 570prefetch_data_accesses_only=false 571prefetch_degree=1 572prefetch_latency=10000 573prefetch_on_access=false 574prefetch_past_page=false 575prefetch_policy=none 576prefetch_serial_squash=false 577prefetch_use_cpu_id=true 578prefetcher_size=100 579prioritizeRequests=false 580repl=Null 581size=32768 582subblock_size=0 583tgts_per_mshr=20 584trace_addr=0 585two_queue=false 586write_buffers=8 587cpu_side=system.cpu1.dcache_port 588mem_side=system.toL2Bus.port[4] 589 590[system.cpu1.dtb] 591type=SparcTLB 592size=64 593 594[system.cpu1.fuPool] 595type=FUPool 596children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 597FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 598 599[system.cpu1.fuPool.FUList0] 600type=FUDesc 601children=opList 602count=6 603opList=system.cpu1.fuPool.FUList0.opList 604 605[system.cpu1.fuPool.FUList0.opList] 606type=OpDesc 607issueLat=1 608opClass=IntAlu 609opLat=1 610 611[system.cpu1.fuPool.FUList1] 612type=FUDesc 613children=opList0 opList1 614count=2 615opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 616 617[system.cpu1.fuPool.FUList1.opList0] 618type=OpDesc 619issueLat=1 620opClass=IntMult 621opLat=3 622 623[system.cpu1.fuPool.FUList1.opList1] 624type=OpDesc 625issueLat=19 626opClass=IntDiv 627opLat=20 628 629[system.cpu1.fuPool.FUList2] 630type=FUDesc 631children=opList0 opList1 opList2 632count=4 633opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 634 635[system.cpu1.fuPool.FUList2.opList0] 636type=OpDesc 637issueLat=1 638opClass=FloatAdd 639opLat=2 640 641[system.cpu1.fuPool.FUList2.opList1] 642type=OpDesc 643issueLat=1 644opClass=FloatCmp 645opLat=2 646 647[system.cpu1.fuPool.FUList2.opList2] 648type=OpDesc 649issueLat=1 650opClass=FloatCvt 651opLat=2 652 653[system.cpu1.fuPool.FUList3] 654type=FUDesc 655children=opList0 opList1 opList2 656count=2 657opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 658 659[system.cpu1.fuPool.FUList3.opList0] 660type=OpDesc 661issueLat=1 662opClass=FloatMult 663opLat=4 664 665[system.cpu1.fuPool.FUList3.opList1] 666type=OpDesc 667issueLat=12 668opClass=FloatDiv 669opLat=12 670 671[system.cpu1.fuPool.FUList3.opList2] 672type=OpDesc 673issueLat=24 674opClass=FloatSqrt 675opLat=24 676 677[system.cpu1.fuPool.FUList4] 678type=FUDesc 679children=opList 680count=0 681opList=system.cpu1.fuPool.FUList4.opList 682 683[system.cpu1.fuPool.FUList4.opList] 684type=OpDesc 685issueLat=1 686opClass=MemRead 687opLat=1 688 689[system.cpu1.fuPool.FUList5] 690type=FUDesc 691children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 692count=4 693opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 694 695[system.cpu1.fuPool.FUList5.opList00] 696type=OpDesc 697issueLat=1 698opClass=SimdAdd 699opLat=1 700 701[system.cpu1.fuPool.FUList5.opList01] 702type=OpDesc 703issueLat=1 704opClass=SimdAddAcc 705opLat=1 706 707[system.cpu1.fuPool.FUList5.opList02] 708type=OpDesc 709issueLat=1 710opClass=SimdAlu 711opLat=1 712 713[system.cpu1.fuPool.FUList5.opList03] 714type=OpDesc 715issueLat=1 716opClass=SimdCmp 717opLat=1 718 719[system.cpu1.fuPool.FUList5.opList04] 720type=OpDesc 721issueLat=1 722opClass=SimdCvt 723opLat=1 724 725[system.cpu1.fuPool.FUList5.opList05] 726type=OpDesc 727issueLat=1 728opClass=SimdMisc 729opLat=1 730 731[system.cpu1.fuPool.FUList5.opList06] 732type=OpDesc 733issueLat=1 734opClass=SimdMult 735opLat=1 736 737[system.cpu1.fuPool.FUList5.opList07] 738type=OpDesc 739issueLat=1 740opClass=SimdMultAcc 741opLat=1 742 743[system.cpu1.fuPool.FUList5.opList08] 744type=OpDesc 745issueLat=1 746opClass=SimdShift 747opLat=1 748 749[system.cpu1.fuPool.FUList5.opList09] 750type=OpDesc 751issueLat=1 752opClass=SimdShiftAcc 753opLat=1 754 755[system.cpu1.fuPool.FUList5.opList10] 756type=OpDesc 757issueLat=1 758opClass=SimdSqrt 759opLat=1 760 761[system.cpu1.fuPool.FUList5.opList11] 762type=OpDesc 763issueLat=1 764opClass=SimdFloatAdd 765opLat=1 766 767[system.cpu1.fuPool.FUList5.opList12] 768type=OpDesc 769issueLat=1 770opClass=SimdFloatAlu 771opLat=1 772 773[system.cpu1.fuPool.FUList5.opList13] 774type=OpDesc 775issueLat=1 776opClass=SimdFloatCmp 777opLat=1 778 779[system.cpu1.fuPool.FUList5.opList14] 780type=OpDesc 781issueLat=1 782opClass=SimdFloatCvt 783opLat=1 784 785[system.cpu1.fuPool.FUList5.opList15] 786type=OpDesc 787issueLat=1 788opClass=SimdFloatDiv 789opLat=1 790 791[system.cpu1.fuPool.FUList5.opList16] 792type=OpDesc 793issueLat=1 794opClass=SimdFloatMisc 795opLat=1 796 797[system.cpu1.fuPool.FUList5.opList17] 798type=OpDesc 799issueLat=1 800opClass=SimdFloatMult 801opLat=1 802 803[system.cpu1.fuPool.FUList5.opList18] 804type=OpDesc 805issueLat=1 806opClass=SimdFloatMultAcc 807opLat=1 808 809[system.cpu1.fuPool.FUList5.opList19] 810type=OpDesc 811issueLat=1 812opClass=SimdFloatSqrt 813opLat=1 814 815[system.cpu1.fuPool.FUList6] 816type=FUDesc 817children=opList 818count=0 819opList=system.cpu1.fuPool.FUList6.opList 820 821[system.cpu1.fuPool.FUList6.opList] 822type=OpDesc 823issueLat=1 824opClass=MemWrite 825opLat=1 826 827[system.cpu1.fuPool.FUList7] 828type=FUDesc 829children=opList0 opList1 830count=4 831opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 832 833[system.cpu1.fuPool.FUList7.opList0] 834type=OpDesc 835issueLat=1 836opClass=MemRead 837opLat=1 838 839[system.cpu1.fuPool.FUList7.opList1] 840type=OpDesc 841issueLat=1 842opClass=MemWrite 843opLat=1 844 845[system.cpu1.fuPool.FUList8] 846type=FUDesc 847children=opList 848count=1 849opList=system.cpu1.fuPool.FUList8.opList 850 851[system.cpu1.fuPool.FUList8.opList] 852type=OpDesc 853issueLat=3 854opClass=IprAccess 855opLat=3 856 857[system.cpu1.icache] 858type=BaseCache 859addr_range=0:18446744073709551615 860assoc=1 861block_size=64 862forward_snoops=true 863hash_delay=1 864is_top_level=true 865latency=1000 866max_miss_count=0 867mshrs=4 868num_cpus=1 869prefetch_data_accesses_only=false 870prefetch_degree=1 871prefetch_latency=10000 872prefetch_on_access=false 873prefetch_past_page=false 874prefetch_policy=none 875prefetch_serial_squash=false 876prefetch_use_cpu_id=true 877prefetcher_size=100 878prioritizeRequests=false 879repl=Null 880size=32768 881subblock_size=0 882tgts_per_mshr=20 883trace_addr=0 884two_queue=false 885write_buffers=8 886cpu_side=system.cpu1.icache_port 887mem_side=system.toL2Bus.port[3] 888 889[system.cpu1.itb] 890type=SparcTLB 891size=64 892 893[system.cpu1.tracer] 894type=ExeTracer 895 896[system.cpu2] 897type=DerivO3CPU 898children=dcache dtb fuPool icache itb tracer 899BTBEntries=4096 900BTBTagSize=16 901LFSTSize=1024 902LQEntries=32 903RASSize=16 904SQEntries=32 905SSITSize=1024 906activity=0 907backComSize=5 908cachePorts=200 909checker=Null 910choiceCtrBits=2 911choicePredictorSize=8192 912clock=500 913commitToDecodeDelay=1 914commitToFetchDelay=1 915commitToIEWDelay=1 916commitToRenameDelay=1 917commitWidth=8 918cpu_id=2 919decodeToFetchDelay=1 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1290forward_snoops=true 1291hash_delay=1 1292is_top_level=true 1293latency=1000 1294max_miss_count=0 1295mshrs=4 1296num_cpus=1 1297prefetch_data_accesses_only=false 1298prefetch_degree=1 1299prefetch_latency=10000 1300prefetch_on_access=false 1301prefetch_past_page=false 1302prefetch_policy=none 1303prefetch_serial_squash=false 1304prefetch_use_cpu_id=true 1305prefetcher_size=100 1306prioritizeRequests=false 1307repl=Null 1308size=32768 1309subblock_size=0 1310tgts_per_mshr=20 1311trace_addr=0 1312two_queue=false 1313write_buffers=8 1314cpu_side=system.cpu2.icache_port 1315mem_side=system.toL2Bus.port[5] 1316 1317[system.cpu2.itb] 1318type=SparcTLB 1319size=64 1320 1321[system.cpu2.tracer] 1322type=ExeTracer 1323 1324[system.cpu3] 1325type=DerivO3CPU 1326children=dcache dtb fuPool icache itb tracer 1327BTBEntries=4096 1328BTBTagSize=16 1329LFSTSize=1024 1330LQEntries=32 1331RASSize=16 1332SQEntries=32 1333SSITSize=1024 1334activity=0 1335backComSize=5 1336cachePorts=200 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system.cpu3.fuPool.FUList5.opList19 1550 1551[system.cpu3.fuPool.FUList5.opList00] 1552type=OpDesc 1553issueLat=1 1554opClass=SimdAdd 1555opLat=1 1556 1557[system.cpu3.fuPool.FUList5.opList01] 1558type=OpDesc 1559issueLat=1 1560opClass=SimdAddAcc 1561opLat=1 1562 1563[system.cpu3.fuPool.FUList5.opList02] 1564type=OpDesc 1565issueLat=1 1566opClass=SimdAlu 1567opLat=1 1568 1569[system.cpu3.fuPool.FUList5.opList03] 1570type=OpDesc 1571issueLat=1 1572opClass=SimdCmp 1573opLat=1 1574 1575[system.cpu3.fuPool.FUList5.opList04] 1576type=OpDesc 1577issueLat=1 1578opClass=SimdCvt 1579opLat=1 1580 1581[system.cpu3.fuPool.FUList5.opList05] 1582type=OpDesc 1583issueLat=1 1584opClass=SimdMisc 1585opLat=1 1586 1587[system.cpu3.fuPool.FUList5.opList06] 1588type=OpDesc 1589issueLat=1 1590opClass=SimdMult 1591opLat=1 1592 1593[system.cpu3.fuPool.FUList5.opList07] 1594type=OpDesc 1595issueLat=1 1596opClass=SimdMultAcc 1597opLat=1 1598 1599[system.cpu3.fuPool.FUList5.opList08] 1600type=OpDesc 1601issueLat=1 1602opClass=SimdShift 1603opLat=1 1604 1605[system.cpu3.fuPool.FUList5.opList09] 1606type=OpDesc 1607issueLat=1 1608opClass=SimdShiftAcc 1609opLat=1 1610 1611[system.cpu3.fuPool.FUList5.opList10] 1612type=OpDesc 1613issueLat=1 1614opClass=SimdSqrt 1615opLat=1 1616 1617[system.cpu3.fuPool.FUList5.opList11] 1618type=OpDesc 1619issueLat=1 1620opClass=SimdFloatAdd 1621opLat=1 1622 1623[system.cpu3.fuPool.FUList5.opList12] 1624type=OpDesc 1625issueLat=1 1626opClass=SimdFloatAlu 1627opLat=1 1628 1629[system.cpu3.fuPool.FUList5.opList13] 1630type=OpDesc 1631issueLat=1 1632opClass=SimdFloatCmp 1633opLat=1 1634 1635[system.cpu3.fuPool.FUList5.opList14] 1636type=OpDesc 1637issueLat=1 1638opClass=SimdFloatCvt 1639opLat=1 1640 1641[system.cpu3.fuPool.FUList5.opList15] 1642type=OpDesc 1643issueLat=1 1644opClass=SimdFloatDiv 1645opLat=1 1646 1647[system.cpu3.fuPool.FUList5.opList16] 1648type=OpDesc 1649issueLat=1 1650opClass=SimdFloatMisc 1651opLat=1 1652 1653[system.cpu3.fuPool.FUList5.opList17] 1654type=OpDesc 1655issueLat=1 1656opClass=SimdFloatMult 1657opLat=1 1658 1659[system.cpu3.fuPool.FUList5.opList18] 1660type=OpDesc 1661issueLat=1 1662opClass=SimdFloatMultAcc 1663opLat=1 1664 1665[system.cpu3.fuPool.FUList5.opList19] 1666type=OpDesc 1667issueLat=1 1668opClass=SimdFloatSqrt 1669opLat=1 1670 1671[system.cpu3.fuPool.FUList6] 1672type=FUDesc 1673children=opList 1674count=0 1675opList=system.cpu3.fuPool.FUList6.opList 1676 1677[system.cpu3.fuPool.FUList6.opList] 1678type=OpDesc 1679issueLat=1 1680opClass=MemWrite 1681opLat=1 1682 1683[system.cpu3.fuPool.FUList7] 1684type=FUDesc 1685children=opList0 opList1 1686count=4 1687opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 1688 1689[system.cpu3.fuPool.FUList7.opList0] 1690type=OpDesc 1691issueLat=1 1692opClass=MemRead 1693opLat=1 1694 1695[system.cpu3.fuPool.FUList7.opList1] 1696type=OpDesc 1697issueLat=1 1698opClass=MemWrite 1699opLat=1 1700 1701[system.cpu3.fuPool.FUList8] 1702type=FUDesc 1703children=opList 1704count=1 1705opList=system.cpu3.fuPool.FUList8.opList 1706 1707[system.cpu3.fuPool.FUList8.opList] 1708type=OpDesc 1709issueLat=3 1710opClass=IprAccess 1711opLat=3 1712 1713[system.cpu3.icache] 1714type=BaseCache 1715addr_range=0:18446744073709551615 1716assoc=1 1717block_size=64 1718forward_snoops=true 1719hash_delay=1 1720is_top_level=true 1721latency=1000 1722max_miss_count=0 1723mshrs=4 1724num_cpus=1 1725prefetch_data_accesses_only=false 1726prefetch_degree=1 1727prefetch_latency=10000 1728prefetch_on_access=false 1729prefetch_past_page=false 1730prefetch_policy=none 1731prefetch_serial_squash=false 1732prefetch_use_cpu_id=true 1733prefetcher_size=100 1734prioritizeRequests=false 1735repl=Null 1736size=32768 1737subblock_size=0 1738tgts_per_mshr=20 1739trace_addr=0 1740two_queue=false 1741write_buffers=8 1742cpu_side=system.cpu3.icache_port 1743mem_side=system.toL2Bus.port[7] 1744 1745[system.cpu3.itb] 1746type=SparcTLB 1747size=64 1748 1749[system.cpu3.tracer] 1750type=ExeTracer 1751 1752[system.l2c] 1753type=BaseCache 1754addr_range=0:18446744073709551615 1755assoc=8 1756block_size=64 1757forward_snoops=true 1758hash_delay=1 1759is_top_level=false 1760latency=10000 1761max_miss_count=0 1762mshrs=92 1763num_cpus=4 1764prefetch_data_accesses_only=false 1765prefetch_degree=1 1766prefetch_latency=100000 1767prefetch_on_access=false 1768prefetch_past_page=false 1769prefetch_policy=none 1770prefetch_serial_squash=false 1771prefetch_use_cpu_id=true 1772prefetcher_size=100 1773prioritizeRequests=false 1774repl=Null 1775size=4194304 1776subblock_size=0 1777tgts_per_mshr=16 1778trace_addr=0 1779two_queue=false 1780write_buffers=8 1781cpu_side=system.toL2Bus.port[0] 1782mem_side=system.membus.port[0] 1783 1784[system.membus] 1785type=Bus 1786block_size=64 1787bus_id=0 1788clock=1000 1789header_cycles=1 1790use_default_range=false 1791width=64 1792port=system.l2c.mem_side system.physmem.port[0] 1793 1794[system.physmem] 1795type=PhysicalMemory 1796file= 1797latency=30000 1798latency_var=0 1799null=false 1800range=0:134217727 1801zero=false 1802port=system.membus.port[1] 1803 1804[system.toL2Bus] 1805type=Bus 1806block_size=64 1807bus_id=0 1808clock=1000 1809header_cycles=1 1810use_default_range=false 1811width=64 1812port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 1813 1814