config.ini revision 7935
1[root] 2type=Root 3children=system 4time_sync_enable=false 5time_sync_period=100000000000 6time_sync_spin_threshold=100000000 7 8[system] 9type=System 10children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus 11mem_mode=timing 12physmem=system.physmem 13work_begin_ckpt_count=0 14work_begin_cpu_id_exit=-1 15work_begin_exit_count=0 16work_cpus_ckpt_count=0 17work_end_ckpt_count=0 18work_end_exit_count=0 19work_item_id=-1 20 21[system.cpu0] 22type=DerivO3CPU 23children=dcache dtb fuPool icache itb tracer workload 24BTBEntries=4096 25BTBTagSize=16 26LFSTSize=1024 27LQEntries=32 28RASSize=16 29SQEntries=32 30SSITSize=1024 31activity=0 32backComSize=5 33cachePorts=200 34checker=Null 35choiceCtrBits=2 36choicePredictorSize=8192 37clock=500 38commitToDecodeDelay=1 39commitToFetchDelay=1 40commitToIEWDelay=1 41commitToRenameDelay=1 42commitWidth=8 43cpu_id=0 44decodeToFetchDelay=1 45decodeToRenameDelay=1 46decodeWidth=8 47defer_registration=false 48dispatchWidth=8 49do_checkpoint_insts=true 50do_statistics_insts=true 51dtb=system.cpu0.dtb 52fetchToDecodeDelay=1 53fetchTrapLatency=1 54fetchWidth=8 55forwardComSize=5 56fuPool=system.cpu0.fuPool 57function_trace=false 58function_trace_start=0 59globalCtrBits=2 60globalHistoryBits=13 61globalPredictorSize=8192 62iewToCommitDelay=1 63iewToDecodeDelay=1 64iewToFetchDelay=1 65iewToRenameDelay=1 66instShiftAmt=2 67issueToExecuteDelay=1 68issueWidth=8 69itb=system.cpu0.itb 70localCtrBits=2 71localHistoryBits=11 72localHistoryTableSize=2048 73localPredictorSize=2048 74max_insts_all_threads=0 75max_insts_any_thread=0 76max_loads_all_threads=0 77max_loads_any_thread=0 78numIQEntries=64 79numPhysFloatRegs=256 80numPhysIntRegs=256 81numROBEntries=192 82numRobs=1 83numThreads=1 84phase=0 85predType=tournament 86progress_interval=0 87renameToDecodeDelay=1 88renameToFetchDelay=1 89renameToIEWDelay=2 90renameToROBDelay=1 91renameWidth=8 92smtCommitPolicy=RoundRobin 93smtFetchPolicy=SingleThread 94smtIQPolicy=Partitioned 95smtIQThreshold=100 96smtLSQPolicy=Partitioned 97smtLSQThreshold=100 98smtNumFetchingThreads=1 99smtROBPolicy=Partitioned 100smtROBThreshold=100 101squashWidth=8 102system=system 103tracer=system.cpu0.tracer 104trapLatency=13 105wbDepth=1 106wbWidth=8 107workload=system.cpu0.workload 108dcache_port=system.cpu0.dcache.cpu_side 109icache_port=system.cpu0.icache.cpu_side 110 111[system.cpu0.dcache] 112type=BaseCache 113addr_range=0:18446744073709551615 114assoc=4 115block_size=64 116forward_snoops=true 117hash_delay=1 118latency=1000 119max_miss_count=0 120mshrs=4 121num_cpus=1 122prefetch_data_accesses_only=false 123prefetch_degree=1 124prefetch_latency=10000 125prefetch_on_access=false 126prefetch_past_page=false 127prefetch_policy=none 128prefetch_serial_squash=false 129prefetch_use_cpu_id=true 130prefetcher_size=100 131prioritizeRequests=false 132repl=Null 133size=32768 134subblock_size=0 135tgts_per_mshr=20 136trace_addr=0 137two_queue=false 138write_buffers=8 139cpu_side=system.cpu0.dcache_port 140mem_side=system.toL2Bus.port[2] 141 142[system.cpu0.dtb] 143type=SparcTLB 144size=64 145 146[system.cpu0.fuPool] 147type=FUPool 148children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 149FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 150 151[system.cpu0.fuPool.FUList0] 152type=FUDesc 153children=opList 154count=6 155opList=system.cpu0.fuPool.FUList0.opList 156 157[system.cpu0.fuPool.FUList0.opList] 158type=OpDesc 159issueLat=1 160opClass=IntAlu 161opLat=1 162 163[system.cpu0.fuPool.FUList1] 164type=FUDesc 165children=opList0 opList1 166count=2 167opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 168 169[system.cpu0.fuPool.FUList1.opList0] 170type=OpDesc 171issueLat=1 172opClass=IntMult 173opLat=3 174 175[system.cpu0.fuPool.FUList1.opList1] 176type=OpDesc 177issueLat=19 178opClass=IntDiv 179opLat=20 180 181[system.cpu0.fuPool.FUList2] 182type=FUDesc 183children=opList0 opList1 opList2 184count=4 185opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 186 187[system.cpu0.fuPool.FUList2.opList0] 188type=OpDesc 189issueLat=1 190opClass=FloatAdd 191opLat=2 192 193[system.cpu0.fuPool.FUList2.opList1] 194type=OpDesc 195issueLat=1 196opClass=FloatCmp 197opLat=2 198 199[system.cpu0.fuPool.FUList2.opList2] 200type=OpDesc 201issueLat=1 202opClass=FloatCvt 203opLat=2 204 205[system.cpu0.fuPool.FUList3] 206type=FUDesc 207children=opList0 opList1 opList2 208count=2 209opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 210 211[system.cpu0.fuPool.FUList3.opList0] 212type=OpDesc 213issueLat=1 214opClass=FloatMult 215opLat=4 216 217[system.cpu0.fuPool.FUList3.opList1] 218type=OpDesc 219issueLat=12 220opClass=FloatDiv 221opLat=12 222 223[system.cpu0.fuPool.FUList3.opList2] 224type=OpDesc 225issueLat=24 226opClass=FloatSqrt 227opLat=24 228 229[system.cpu0.fuPool.FUList4] 230type=FUDesc 231children=opList 232count=0 233opList=system.cpu0.fuPool.FUList4.opList 234 235[system.cpu0.fuPool.FUList4.opList] 236type=OpDesc 237issueLat=1 238opClass=MemRead 239opLat=1 240 241[system.cpu0.fuPool.FUList5] 242type=FUDesc 243children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 244count=4 245opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 246 247[system.cpu0.fuPool.FUList5.opList00] 248type=OpDesc 249issueLat=1 250opClass=SimdAdd 251opLat=1 252 253[system.cpu0.fuPool.FUList5.opList01] 254type=OpDesc 255issueLat=1 256opClass=SimdAddAcc 257opLat=1 258 259[system.cpu0.fuPool.FUList5.opList02] 260type=OpDesc 261issueLat=1 262opClass=SimdAlu 263opLat=1 264 265[system.cpu0.fuPool.FUList5.opList03] 266type=OpDesc 267issueLat=1 268opClass=SimdCmp 269opLat=1 270 271[system.cpu0.fuPool.FUList5.opList04] 272type=OpDesc 273issueLat=1 274opClass=SimdCvt 275opLat=1 276 277[system.cpu0.fuPool.FUList5.opList05] 278type=OpDesc 279issueLat=1 280opClass=SimdMisc 281opLat=1 282 283[system.cpu0.fuPool.FUList5.opList06] 284type=OpDesc 285issueLat=1 286opClass=SimdMult 287opLat=1 288 289[system.cpu0.fuPool.FUList5.opList07] 290type=OpDesc 291issueLat=1 292opClass=SimdMultAcc 293opLat=1 294 295[system.cpu0.fuPool.FUList5.opList08] 296type=OpDesc 297issueLat=1 298opClass=SimdShift 299opLat=1 300 301[system.cpu0.fuPool.FUList5.opList09] 302type=OpDesc 303issueLat=1 304opClass=SimdShiftAcc 305opLat=1 306 307[system.cpu0.fuPool.FUList5.opList10] 308type=OpDesc 309issueLat=1 310opClass=SimdSqrt 311opLat=1 312 313[system.cpu0.fuPool.FUList5.opList11] 314type=OpDesc 315issueLat=1 316opClass=SimdFloatAdd 317opLat=1 318 319[system.cpu0.fuPool.FUList5.opList12] 320type=OpDesc 321issueLat=1 322opClass=SimdFloatAlu 323opLat=1 324 325[system.cpu0.fuPool.FUList5.opList13] 326type=OpDesc 327issueLat=1 328opClass=SimdFloatCmp 329opLat=1 330 331[system.cpu0.fuPool.FUList5.opList14] 332type=OpDesc 333issueLat=1 334opClass=SimdFloatCvt 335opLat=1 336 337[system.cpu0.fuPool.FUList5.opList15] 338type=OpDesc 339issueLat=1 340opClass=SimdFloatDiv 341opLat=1 342 343[system.cpu0.fuPool.FUList5.opList16] 344type=OpDesc 345issueLat=1 346opClass=SimdFloatMisc 347opLat=1 348 349[system.cpu0.fuPool.FUList5.opList17] 350type=OpDesc 351issueLat=1 352opClass=SimdFloatMult 353opLat=1 354 355[system.cpu0.fuPool.FUList5.opList18] 356type=OpDesc 357issueLat=1 358opClass=SimdFloatMultAcc 359opLat=1 360 361[system.cpu0.fuPool.FUList5.opList19] 362type=OpDesc 363issueLat=1 364opClass=SimdFloatSqrt 365opLat=1 366 367[system.cpu0.fuPool.FUList6] 368type=FUDesc 369children=opList 370count=0 371opList=system.cpu0.fuPool.FUList6.opList 372 373[system.cpu0.fuPool.FUList6.opList] 374type=OpDesc 375issueLat=1 376opClass=MemWrite 377opLat=1 378 379[system.cpu0.fuPool.FUList7] 380type=FUDesc 381children=opList0 opList1 382count=4 383opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 384 385[system.cpu0.fuPool.FUList7.opList0] 386type=OpDesc 387issueLat=1 388opClass=MemRead 389opLat=1 390 391[system.cpu0.fuPool.FUList7.opList1] 392type=OpDesc 393issueLat=1 394opClass=MemWrite 395opLat=1 396 397[system.cpu0.fuPool.FUList8] 398type=FUDesc 399children=opList 400count=1 401opList=system.cpu0.fuPool.FUList8.opList 402 403[system.cpu0.fuPool.FUList8.opList] 404type=OpDesc 405issueLat=3 406opClass=IprAccess 407opLat=3 408 409[system.cpu0.icache] 410type=BaseCache 411addr_range=0:18446744073709551615 412assoc=1 413block_size=64 414forward_snoops=true 415hash_delay=1 416latency=1000 417max_miss_count=0 418mshrs=4 419num_cpus=1 420prefetch_data_accesses_only=false 421prefetch_degree=1 422prefetch_latency=10000 423prefetch_on_access=false 424prefetch_past_page=false 425prefetch_policy=none 426prefetch_serial_squash=false 427prefetch_use_cpu_id=true 428prefetcher_size=100 429prioritizeRequests=false 430repl=Null 431size=32768 432subblock_size=0 433tgts_per_mshr=20 434trace_addr=0 435two_queue=false 436write_buffers=8 437cpu_side=system.cpu0.icache_port 438mem_side=system.toL2Bus.port[1] 439 440[system.cpu0.itb] 441type=SparcTLB 442size=64 443 444[system.cpu0.tracer] 445type=ExeTracer 446 447[system.cpu0.workload] 448type=LiveProcess 449cmd=test_atomic 4 450cwd= 451egid=100 452env= 453errout=cerr 454euid=100 455executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic 456gid=100 457input=cin 458max_stack_size=67108864 459output=cout 460pid=100 461ppid=99 462simpoint=0 463system=system 464uid=100 465 466[system.cpu1] 467type=DerivO3CPU 468children=dcache dtb fuPool icache itb tracer 469BTBEntries=4096 470BTBTagSize=16 471LFSTSize=1024 472LQEntries=32 473RASSize=16 474SQEntries=32 475SSITSize=1024 476activity=0 477backComSize=5 478cachePorts=200 479checker=Null 480choiceCtrBits=2 481choicePredictorSize=8192 482clock=500 483commitToDecodeDelay=1 484commitToFetchDelay=1 485commitToIEWDelay=1 486commitToRenameDelay=1 487commitWidth=8 488cpu_id=1 489decodeToFetchDelay=1 490decodeToRenameDelay=1 491decodeWidth=8 492defer_registration=false 493dispatchWidth=8 494do_checkpoint_insts=true 495do_statistics_insts=true 496dtb=system.cpu1.dtb 497fetchToDecodeDelay=1 498fetchTrapLatency=1 499fetchWidth=8 500forwardComSize=5 501fuPool=system.cpu1.fuPool 502function_trace=false 503function_trace_start=0 504globalCtrBits=2 505globalHistoryBits=13 506globalPredictorSize=8192 507iewToCommitDelay=1 508iewToDecodeDelay=1 509iewToFetchDelay=1 510iewToRenameDelay=1 511instShiftAmt=2 512issueToExecuteDelay=1 513issueWidth=8 514itb=system.cpu1.itb 515localCtrBits=2 516localHistoryBits=11 517localHistoryTableSize=2048 518localPredictorSize=2048 519max_insts_all_threads=0 520max_insts_any_thread=0 521max_loads_all_threads=0 522max_loads_any_thread=0 523numIQEntries=64 524numPhysFloatRegs=256 525numPhysIntRegs=256 526numROBEntries=192 527numRobs=1 528numThreads=1 529phase=0 530predType=tournament 531progress_interval=0 532renameToDecodeDelay=1 533renameToFetchDelay=1 534renameToIEWDelay=2 535renameToROBDelay=1 536renameWidth=8 537smtCommitPolicy=RoundRobin 538smtFetchPolicy=SingleThread 539smtIQPolicy=Partitioned 540smtIQThreshold=100 541smtLSQPolicy=Partitioned 542smtLSQThreshold=100 543smtNumFetchingThreads=1 544smtROBPolicy=Partitioned 545smtROBThreshold=100 546squashWidth=8 547system=system 548tracer=system.cpu1.tracer 549trapLatency=13 550wbDepth=1 551wbWidth=8 552workload=system.cpu0.workload 553dcache_port=system.cpu1.dcache.cpu_side 554icache_port=system.cpu1.icache.cpu_side 555 556[system.cpu1.dcache] 557type=BaseCache 558addr_range=0:18446744073709551615 559assoc=4 560block_size=64 561forward_snoops=true 562hash_delay=1 563latency=1000 564max_miss_count=0 565mshrs=4 566num_cpus=1 567prefetch_data_accesses_only=false 568prefetch_degree=1 569prefetch_latency=10000 570prefetch_on_access=false 571prefetch_past_page=false 572prefetch_policy=none 573prefetch_serial_squash=false 574prefetch_use_cpu_id=true 575prefetcher_size=100 576prioritizeRequests=false 577repl=Null 578size=32768 579subblock_size=0 580tgts_per_mshr=20 581trace_addr=0 582two_queue=false 583write_buffers=8 584cpu_side=system.cpu1.dcache_port 585mem_side=system.toL2Bus.port[4] 586 587[system.cpu1.dtb] 588type=SparcTLB 589size=64 590 591[system.cpu1.fuPool] 592type=FUPool 593children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 594FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 595 596[system.cpu1.fuPool.FUList0] 597type=FUDesc 598children=opList 599count=6 600opList=system.cpu1.fuPool.FUList0.opList 601 602[system.cpu1.fuPool.FUList0.opList] 603type=OpDesc 604issueLat=1 605opClass=IntAlu 606opLat=1 607 608[system.cpu1.fuPool.FUList1] 609type=FUDesc 610children=opList0 opList1 611count=2 612opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 613 614[system.cpu1.fuPool.FUList1.opList0] 615type=OpDesc 616issueLat=1 617opClass=IntMult 618opLat=3 619 620[system.cpu1.fuPool.FUList1.opList1] 621type=OpDesc 622issueLat=19 623opClass=IntDiv 624opLat=20 625 626[system.cpu1.fuPool.FUList2] 627type=FUDesc 628children=opList0 opList1 opList2 629count=4 630opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 631 632[system.cpu1.fuPool.FUList2.opList0] 633type=OpDesc 634issueLat=1 635opClass=FloatAdd 636opLat=2 637 638[system.cpu1.fuPool.FUList2.opList1] 639type=OpDesc 640issueLat=1 641opClass=FloatCmp 642opLat=2 643 644[system.cpu1.fuPool.FUList2.opList2] 645type=OpDesc 646issueLat=1 647opClass=FloatCvt 648opLat=2 649 650[system.cpu1.fuPool.FUList3] 651type=FUDesc 652children=opList0 opList1 opList2 653count=2 654opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 655 656[system.cpu1.fuPool.FUList3.opList0] 657type=OpDesc 658issueLat=1 659opClass=FloatMult 660opLat=4 661 662[system.cpu1.fuPool.FUList3.opList1] 663type=OpDesc 664issueLat=12 665opClass=FloatDiv 666opLat=12 667 668[system.cpu1.fuPool.FUList3.opList2] 669type=OpDesc 670issueLat=24 671opClass=FloatSqrt 672opLat=24 673 674[system.cpu1.fuPool.FUList4] 675type=FUDesc 676children=opList 677count=0 678opList=system.cpu1.fuPool.FUList4.opList 679 680[system.cpu1.fuPool.FUList4.opList] 681type=OpDesc 682issueLat=1 683opClass=MemRead 684opLat=1 685 686[system.cpu1.fuPool.FUList5] 687type=FUDesc 688children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 689count=4 690opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 691 692[system.cpu1.fuPool.FUList5.opList00] 693type=OpDesc 694issueLat=1 695opClass=SimdAdd 696opLat=1 697 698[system.cpu1.fuPool.FUList5.opList01] 699type=OpDesc 700issueLat=1 701opClass=SimdAddAcc 702opLat=1 703 704[system.cpu1.fuPool.FUList5.opList02] 705type=OpDesc 706issueLat=1 707opClass=SimdAlu 708opLat=1 709 710[system.cpu1.fuPool.FUList5.opList03] 711type=OpDesc 712issueLat=1 713opClass=SimdCmp 714opLat=1 715 716[system.cpu1.fuPool.FUList5.opList04] 717type=OpDesc 718issueLat=1 719opClass=SimdCvt 720opLat=1 721 722[system.cpu1.fuPool.FUList5.opList05] 723type=OpDesc 724issueLat=1 725opClass=SimdMisc 726opLat=1 727 728[system.cpu1.fuPool.FUList5.opList06] 729type=OpDesc 730issueLat=1 731opClass=SimdMult 732opLat=1 733 734[system.cpu1.fuPool.FUList5.opList07] 735type=OpDesc 736issueLat=1 737opClass=SimdMultAcc 738opLat=1 739 740[system.cpu1.fuPool.FUList5.opList08] 741type=OpDesc 742issueLat=1 743opClass=SimdShift 744opLat=1 745 746[system.cpu1.fuPool.FUList5.opList09] 747type=OpDesc 748issueLat=1 749opClass=SimdShiftAcc 750opLat=1 751 752[system.cpu1.fuPool.FUList5.opList10] 753type=OpDesc 754issueLat=1 755opClass=SimdSqrt 756opLat=1 757 758[system.cpu1.fuPool.FUList5.opList11] 759type=OpDesc 760issueLat=1 761opClass=SimdFloatAdd 762opLat=1 763 764[system.cpu1.fuPool.FUList5.opList12] 765type=OpDesc 766issueLat=1 767opClass=SimdFloatAlu 768opLat=1 769 770[system.cpu1.fuPool.FUList5.opList13] 771type=OpDesc 772issueLat=1 773opClass=SimdFloatCmp 774opLat=1 775 776[system.cpu1.fuPool.FUList5.opList14] 777type=OpDesc 778issueLat=1 779opClass=SimdFloatCvt 780opLat=1 781 782[system.cpu1.fuPool.FUList5.opList15] 783type=OpDesc 784issueLat=1 785opClass=SimdFloatDiv 786opLat=1 787 788[system.cpu1.fuPool.FUList5.opList16] 789type=OpDesc 790issueLat=1 791opClass=SimdFloatMisc 792opLat=1 793 794[system.cpu1.fuPool.FUList5.opList17] 795type=OpDesc 796issueLat=1 797opClass=SimdFloatMult 798opLat=1 799 800[system.cpu1.fuPool.FUList5.opList18] 801type=OpDesc 802issueLat=1 803opClass=SimdFloatMultAcc 804opLat=1 805 806[system.cpu1.fuPool.FUList5.opList19] 807type=OpDesc 808issueLat=1 809opClass=SimdFloatSqrt 810opLat=1 811 812[system.cpu1.fuPool.FUList6] 813type=FUDesc 814children=opList 815count=0 816opList=system.cpu1.fuPool.FUList6.opList 817 818[system.cpu1.fuPool.FUList6.opList] 819type=OpDesc 820issueLat=1 821opClass=MemWrite 822opLat=1 823 824[system.cpu1.fuPool.FUList7] 825type=FUDesc 826children=opList0 opList1 827count=4 828opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 829 830[system.cpu1.fuPool.FUList7.opList0] 831type=OpDesc 832issueLat=1 833opClass=MemRead 834opLat=1 835 836[system.cpu1.fuPool.FUList7.opList1] 837type=OpDesc 838issueLat=1 839opClass=MemWrite 840opLat=1 841 842[system.cpu1.fuPool.FUList8] 843type=FUDesc 844children=opList 845count=1 846opList=system.cpu1.fuPool.FUList8.opList 847 848[system.cpu1.fuPool.FUList8.opList] 849type=OpDesc 850issueLat=3 851opClass=IprAccess 852opLat=3 853 854[system.cpu1.icache] 855type=BaseCache 856addr_range=0:18446744073709551615 857assoc=1 858block_size=64 859forward_snoops=true 860hash_delay=1 861latency=1000 862max_miss_count=0 863mshrs=4 864num_cpus=1 865prefetch_data_accesses_only=false 866prefetch_degree=1 867prefetch_latency=10000 868prefetch_on_access=false 869prefetch_past_page=false 870prefetch_policy=none 871prefetch_serial_squash=false 872prefetch_use_cpu_id=true 873prefetcher_size=100 874prioritizeRequests=false 875repl=Null 876size=32768 877subblock_size=0 878tgts_per_mshr=20 879trace_addr=0 880two_queue=false 881write_buffers=8 882cpu_side=system.cpu1.icache_port 883mem_side=system.toL2Bus.port[3] 884 885[system.cpu1.itb] 886type=SparcTLB 887size=64 888 889[system.cpu1.tracer] 890type=ExeTracer 891 892[system.cpu2] 893type=DerivO3CPU 894children=dcache dtb fuPool icache itb tracer 895BTBEntries=4096 896BTBTagSize=16 897LFSTSize=1024 898LQEntries=32 899RASSize=16 900SQEntries=32 901SSITSize=1024 902activity=0 903backComSize=5 904cachePorts=200 905checker=Null 906choiceCtrBits=2 907choicePredictorSize=8192 908clock=500 909commitToDecodeDelay=1 910commitToFetchDelay=1 911commitToIEWDelay=1 912commitToRenameDelay=1 913commitWidth=8 914cpu_id=2 915decodeToFetchDelay=1 916decodeToRenameDelay=1 917decodeWidth=8 918defer_registration=false 919dispatchWidth=8 920do_checkpoint_insts=true 921do_statistics_insts=true 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1554opLat=1 1555 1556[system.cpu3.fuPool.FUList5.opList02] 1557type=OpDesc 1558issueLat=1 1559opClass=SimdAlu 1560opLat=1 1561 1562[system.cpu3.fuPool.FUList5.opList03] 1563type=OpDesc 1564issueLat=1 1565opClass=SimdCmp 1566opLat=1 1567 1568[system.cpu3.fuPool.FUList5.opList04] 1569type=OpDesc 1570issueLat=1 1571opClass=SimdCvt 1572opLat=1 1573 1574[system.cpu3.fuPool.FUList5.opList05] 1575type=OpDesc 1576issueLat=1 1577opClass=SimdMisc 1578opLat=1 1579 1580[system.cpu3.fuPool.FUList5.opList06] 1581type=OpDesc 1582issueLat=1 1583opClass=SimdMult 1584opLat=1 1585 1586[system.cpu3.fuPool.FUList5.opList07] 1587type=OpDesc 1588issueLat=1 1589opClass=SimdMultAcc 1590opLat=1 1591 1592[system.cpu3.fuPool.FUList5.opList08] 1593type=OpDesc 1594issueLat=1 1595opClass=SimdShift 1596opLat=1 1597 1598[system.cpu3.fuPool.FUList5.opList09] 1599type=OpDesc 1600issueLat=1 1601opClass=SimdShiftAcc 1602opLat=1 1603 1604[system.cpu3.fuPool.FUList5.opList10] 1605type=OpDesc 1606issueLat=1 1607opClass=SimdSqrt 1608opLat=1 1609 1610[system.cpu3.fuPool.FUList5.opList11] 1611type=OpDesc 1612issueLat=1 1613opClass=SimdFloatAdd 1614opLat=1 1615 1616[system.cpu3.fuPool.FUList5.opList12] 1617type=OpDesc 1618issueLat=1 1619opClass=SimdFloatAlu 1620opLat=1 1621 1622[system.cpu3.fuPool.FUList5.opList13] 1623type=OpDesc 1624issueLat=1 1625opClass=SimdFloatCmp 1626opLat=1 1627 1628[system.cpu3.fuPool.FUList5.opList14] 1629type=OpDesc 1630issueLat=1 1631opClass=SimdFloatCvt 1632opLat=1 1633 1634[system.cpu3.fuPool.FUList5.opList15] 1635type=OpDesc 1636issueLat=1 1637opClass=SimdFloatDiv 1638opLat=1 1639 1640[system.cpu3.fuPool.FUList5.opList16] 1641type=OpDesc 1642issueLat=1 1643opClass=SimdFloatMisc 1644opLat=1 1645 1646[system.cpu3.fuPool.FUList5.opList17] 1647type=OpDesc 1648issueLat=1 1649opClass=SimdFloatMult 1650opLat=1 1651 1652[system.cpu3.fuPool.FUList5.opList18] 1653type=OpDesc 1654issueLat=1 1655opClass=SimdFloatMultAcc 1656opLat=1 1657 1658[system.cpu3.fuPool.FUList5.opList19] 1659type=OpDesc 1660issueLat=1 1661opClass=SimdFloatSqrt 1662opLat=1 1663 1664[system.cpu3.fuPool.FUList6] 1665type=FUDesc 1666children=opList 1667count=0 1668opList=system.cpu3.fuPool.FUList6.opList 1669 1670[system.cpu3.fuPool.FUList6.opList] 1671type=OpDesc 1672issueLat=1 1673opClass=MemWrite 1674opLat=1 1675 1676[system.cpu3.fuPool.FUList7] 1677type=FUDesc 1678children=opList0 opList1 1679count=4 1680opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 1681 1682[system.cpu3.fuPool.FUList7.opList0] 1683type=OpDesc 1684issueLat=1 1685opClass=MemRead 1686opLat=1 1687 1688[system.cpu3.fuPool.FUList7.opList1] 1689type=OpDesc 1690issueLat=1 1691opClass=MemWrite 1692opLat=1 1693 1694[system.cpu3.fuPool.FUList8] 1695type=FUDesc 1696children=opList 1697count=1 1698opList=system.cpu3.fuPool.FUList8.opList 1699 1700[system.cpu3.fuPool.FUList8.opList] 1701type=OpDesc 1702issueLat=3 1703opClass=IprAccess 1704opLat=3 1705 1706[system.cpu3.icache] 1707type=BaseCache 1708addr_range=0:18446744073709551615 1709assoc=1 1710block_size=64 1711forward_snoops=true 1712hash_delay=1 1713latency=1000 1714max_miss_count=0 1715mshrs=4 1716num_cpus=1 1717prefetch_data_accesses_only=false 1718prefetch_degree=1 1719prefetch_latency=10000 1720prefetch_on_access=false 1721prefetch_past_page=false 1722prefetch_policy=none 1723prefetch_serial_squash=false 1724prefetch_use_cpu_id=true 1725prefetcher_size=100 1726prioritizeRequests=false 1727repl=Null 1728size=32768 1729subblock_size=0 1730tgts_per_mshr=20 1731trace_addr=0 1732two_queue=false 1733write_buffers=8 1734cpu_side=system.cpu3.icache_port 1735mem_side=system.toL2Bus.port[7] 1736 1737[system.cpu3.itb] 1738type=SparcTLB 1739size=64 1740 1741[system.cpu3.tracer] 1742type=ExeTracer 1743 1744[system.l2c] 1745type=BaseCache 1746addr_range=0:18446744073709551615 1747assoc=8 1748block_size=64 1749forward_snoops=true 1750hash_delay=1 1751latency=10000 1752max_miss_count=0 1753mshrs=92 1754num_cpus=4 1755prefetch_data_accesses_only=false 1756prefetch_degree=1 1757prefetch_latency=100000 1758prefetch_on_access=false 1759prefetch_past_page=false 1760prefetch_policy=none 1761prefetch_serial_squash=false 1762prefetch_use_cpu_id=true 1763prefetcher_size=100 1764prioritizeRequests=false 1765repl=Null 1766size=4194304 1767subblock_size=0 1768tgts_per_mshr=16 1769trace_addr=0 1770two_queue=false 1771write_buffers=8 1772cpu_side=system.toL2Bus.port[0] 1773mem_side=system.membus.port[0] 1774 1775[system.membus] 1776type=Bus 1777block_size=64 1778bus_id=0 1779clock=1000 1780header_cycles=1 1781use_default_range=false 1782width=64 1783port=system.l2c.mem_side system.physmem.port[0] 1784 1785[system.physmem] 1786type=PhysicalMemory 1787file= 1788latency=30000 1789latency_var=0 1790null=false 1791range=0:134217727 1792zero=false 1793port=system.membus.port[1] 1794 1795[system.toL2Bus] 1796type=Bus 1797block_size=64 1798bus_id=0 1799clock=1000 1800header_cycles=1 1801use_default_range=false 1802width=64 1803port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 1804 1805