stats.txt revision 11955:1170d039b31e
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.147164 # Number of seconds simulated 4sim_ticks 147164058500 # Number of ticks simulated 5final_tick 147164058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1482184 # Simulator instruction rate (inst/s) 8host_op_rate 1489549 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2408165715 # Simulator tick rate (ticks/s) 10host_mem_usage 404112 # Number of bytes of host memory used 11host_seconds 61.11 # Real time elapsed on the host 12sim_insts 90576862 # Number of instructions simulated 13sim_ops 91026991 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory 19system.physmem.bytes_read::total 981760 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 250931 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 6420263 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 6671194 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 250931 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 250931 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 250931 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 6420263 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 6671194 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states 36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 45system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 46system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 47system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 48system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 49system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 51system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 53system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 54system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 55system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 56system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states 66system.cpu.dtb.walker.walks 0 # Table walker walks requested 67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.inst_hits 0 # ITB inst hits 75system.cpu.dtb.inst_misses 0 # ITB inst misses 76system.cpu.dtb.read_hits 0 # DTB read hits 77system.cpu.dtb.read_misses 0 # DTB read misses 78system.cpu.dtb.write_hits 0 # DTB write hits 79system.cpu.dtb.write_misses 0 # DTB write misses 80system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 81system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 82system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 83system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 84system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 85system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 86system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 89system.cpu.dtb.read_accesses 0 # DTB read accesses 90system.cpu.dtb.write_accesses 0 # DTB write accesses 91system.cpu.dtb.inst_accesses 0 # ITB inst accesses 92system.cpu.dtb.hits 0 # DTB hits 93system.cpu.dtb.misses 0 # DTB misses 94system.cpu.dtb.accesses 0 # DTB accesses 95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states 96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 105system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 106system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 107system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 108system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 109system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 110system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 111system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 114system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 115system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 116system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states 126system.cpu.itb.walker.walks 0 # Table walker walks requested 127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.inst_hits 0 # ITB inst hits 135system.cpu.itb.inst_misses 0 # ITB inst misses 136system.cpu.itb.read_hits 0 # DTB read hits 137system.cpu.itb.read_misses 0 # DTB read misses 138system.cpu.itb.write_hits 0 # DTB write hits 139system.cpu.itb.write_misses 0 # DTB write misses 140system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 141system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 142system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 143system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 144system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 145system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 146system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 147system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.itb.read_accesses 0 # DTB read accesses 150system.cpu.itb.write_accesses 0 # DTB write accesses 151system.cpu.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.itb.hits 0 # DTB hits 153system.cpu.itb.misses 0 # DTB misses 154system.cpu.itb.accesses 0 # DTB accesses 155system.cpu.workload.numSyscalls 442 # Number of system calls 156system.cpu.pwrStateResidencyTicks::ON 147164058500 # Cumulative time (in ticks) in various power states 157system.cpu.numCycles 294328117 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 90576862 # Number of instructions committed 161system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses 164system.cpu.num_func_calls 112245 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls 166system.cpu.num_int_insts 72326352 # number of integer instructions 167system.cpu.num_fp_insts 48 # number of float instructions 168system.cpu.num_int_register_reads 124236934 # number of times the integer registers were read 169system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written 170system.cpu.num_fp_register_reads 54 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 30 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written 174system.cpu.num_mem_refs 27220755 # number of memory refs 175system.cpu.num_load_insts 22475911 # Number of load instructions 176system.cpu.num_store_insts 4744844 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 178system.cpu.num_busy_cycles 294328116.998000 # Number of busy cycles 179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 181system.cpu.Branches 18732305 # Number of branches fetched 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction 184system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction 187system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction 188system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction 189system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction 190system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% # Class of executed instruction 191system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction 192system.cpu.op_class::FloatMisc 0 0.00% 70.10% # Class of executed instruction 193system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction 194system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction 195system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction 196system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction 197system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction 198system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction 199system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction 200system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction 201system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction 202system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction 203system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction 204system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction 205system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction 206system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction 207system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction 208system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction 209system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction 210system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction 211system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction 212system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction 213system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction 214system.cpu.op_class::MemRead 22475905 24.68% 94.79% # Class of executed instruction 215system.cpu.op_class::MemWrite 4744822 5.21% 100.00% # Class of executed instruction 216system.cpu.op_class::FloatMemRead 6 0.00% 100.00% # Class of executed instruction 217system.cpu.op_class::FloatMemWrite 22 0.00% 100.00% # Class of executed instruction 218system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 219system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 220system.cpu.op_class::total 91054081 # Class of executed instruction 221system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states 222system.cpu.dcache.tags.replacements 942702 # number of replacements 223system.cpu.dcache.tags.tagsinuse 3565.461526 # Cycle average of tags in use 224system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. 225system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. 226system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. 227system.cpu.dcache.tags.warmup_cycle 54459450500 # Cycle when the warmup percentage was hit. 228system.cpu.dcache.tags.occ_blocks::cpu.data 3565.461526 # Average occupied blocks per requestor 229system.cpu.dcache.tags.occ_percent::cpu.data 0.870474 # Average percentage of cache occupancy 230system.cpu.dcache.tags.occ_percent::total 0.870474 # Average percentage of cache occupancy 231system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 232system.cpu.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id 233system.cpu.dcache.tags.age_task_id_blocks_1024::1 1358 # Occupied blocks per task id 234system.cpu.dcache.tags.age_task_id_blocks_1024::2 2564 # Occupied blocks per task id 235system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id 236system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 237system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses 238system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses 239system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states 240system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits 241system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits 242system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits 243system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits 244system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits 245system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits 246system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 247system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 248system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 249system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 250system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits 251system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits 252system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits 253system.cpu.dcache.overall_hits::total 26245827 # number of overall hits 254system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses 255system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses 256system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses 257system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses 258system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses 259system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses 260system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses 261system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses 262system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses 263system.cpu.dcache.overall_misses::total 946799 # number of overall misses 264system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713223000 # number of ReadReq miss cycles 265system.cpu.dcache.ReadReq_miss_latency::total 11713223000 # number of ReadReq miss cycles 266system.cpu.dcache.WriteReq_miss_latency::cpu.data 1333567500 # number of WriteReq miss cycles 267system.cpu.dcache.WriteReq_miss_latency::total 1333567500 # number of WriteReq miss cycles 268system.cpu.dcache.demand_miss_latency::cpu.data 13046790500 # number of demand (read+write) miss cycles 269system.cpu.dcache.demand_miss_latency::total 13046790500 # number of demand (read+write) miss cycles 270system.cpu.dcache.overall_miss_latency::cpu.data 13046790500 # number of overall miss cycles 271system.cpu.dcache.overall_miss_latency::total 13046790500 # number of overall miss cycles 272system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) 273system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) 274system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 275system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 276system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) 277system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) 278system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 279system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 280system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 281system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 282system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses 283system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses 284system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses 285system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses 286system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses 287system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses 288system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses 289system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses 290system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses 291system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses 292system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses 293system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses 294system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses 295system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses 296system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.988620 # average ReadReq miss latency 297system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.988620 # average ReadReq miss latency 298system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28611.802442 # average WriteReq miss latency 299system.cpu.dcache.WriteReq_avg_miss_latency::total 28611.802442 # average WriteReq miss latency 300system.cpu.dcache.demand_avg_miss_latency::cpu.data 13779.938339 # average overall miss latency 301system.cpu.dcache.demand_avg_miss_latency::total 13779.938339 # average overall miss latency 302system.cpu.dcache.overall_avg_miss_latency::cpu.data 13779.894677 # average overall miss latency 303system.cpu.dcache.overall_avg_miss_latency::total 13779.894677 # average overall miss latency 304system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 305system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 306system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 307system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 308system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 309system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 310system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks 311system.cpu.dcache.writebacks::total 942334 # number of writebacks 312system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 313system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 314system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 315system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 316system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 317system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits 318system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses 319system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses 320system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses 321system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses 322system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 323system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 324system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses 325system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses 326system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses 327system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses 328system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812989000 # number of ReadReq MSHR miss cycles 329system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812989000 # number of ReadReq MSHR miss cycles 330system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1286958500 # number of WriteReq MSHR miss cycles 331system.cpu.dcache.WriteReq_mshr_miss_latency::total 1286958500 # number of WriteReq MSHR miss cycles 332system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 136000 # number of SoftPFReq MSHR miss cycles 333system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 136000 # number of SoftPFReq MSHR miss cycles 334system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12099947500 # number of demand (read+write) MSHR miss cycles 335system.cpu.dcache.demand_mshr_miss_latency::total 12099947500 # number of demand (read+write) MSHR miss cycles 336system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12100083500 # number of overall MSHR miss cycles 337system.cpu.dcache.overall_mshr_miss_latency::total 12100083500 # number of overall MSHR miss cycles 338system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses 339system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses 340system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses 341system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses 342system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses 343system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses 344system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses 345system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses 346system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses 347system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses 348system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.949753 # average ReadReq mshr miss latency 349system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.949753 # average ReadReq mshr miss latency 350system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27611.802442 # average WriteReq mshr miss latency 351system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27611.802442 # average WriteReq mshr miss latency 352system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 45333.333333 # average SoftPFReq mshr miss latency 353system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 45333.333333 # average SoftPFReq mshr miss latency 354system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12779.902196 # average overall mshr miss latency 355system.cpu.dcache.demand_avg_mshr_miss_latency::total 12779.902196 # average overall mshr miss latency 356system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12780.005344 # average overall mshr miss latency 357system.cpu.dcache.overall_avg_mshr_miss_latency::total 12780.005344 # average overall mshr miss latency 358system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states 359system.cpu.icache.tags.replacements 2 # number of replacements 360system.cpu.icache.tags.tagsinuse 510.110453 # Cycle average of tags in use 361system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. 362system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. 363system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. 364system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 365system.cpu.icache.tags.occ_blocks::cpu.inst 510.110453 # Average occupied blocks per requestor 366system.cpu.icache.tags.occ_percent::cpu.inst 0.249077 # Average percentage of cache occupancy 367system.cpu.icache.tags.occ_percent::total 0.249077 # Average percentage of cache occupancy 368system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id 369system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 370system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 371system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 372system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id 373system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id 374system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses 375system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses 376system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states 377system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits 378system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits 379system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits 380system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits 381system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits 382system.cpu.icache.overall_hits::total 107830173 # number of overall hits 383system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses 384system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses 385system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses 386system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses 387system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses 388system.cpu.icache.overall_misses::total 599 # number of overall misses 389system.cpu.icache.ReadReq_miss_latency::cpu.inst 36670000 # number of ReadReq miss cycles 390system.cpu.icache.ReadReq_miss_latency::total 36670000 # number of ReadReq miss cycles 391system.cpu.icache.demand_miss_latency::cpu.inst 36670000 # number of demand (read+write) miss cycles 392system.cpu.icache.demand_miss_latency::total 36670000 # number of demand (read+write) miss cycles 393system.cpu.icache.overall_miss_latency::cpu.inst 36670000 # number of overall miss cycles 394system.cpu.icache.overall_miss_latency::total 36670000 # number of overall miss cycles 395system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses) 396system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses) 397system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses 398system.cpu.icache.demand_accesses::total 107830772 # number of demand (read+write) accesses 399system.cpu.icache.overall_accesses::cpu.inst 107830772 # number of overall (read+write) accesses 400system.cpu.icache.overall_accesses::total 107830772 # number of overall (read+write) accesses 401system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses 402system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses 403system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses 404system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses 405system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses 406system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses 407system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61218.697830 # average ReadReq miss latency 408system.cpu.icache.ReadReq_avg_miss_latency::total 61218.697830 # average ReadReq miss latency 409system.cpu.icache.demand_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency 410system.cpu.icache.demand_avg_miss_latency::total 61218.697830 # average overall miss latency 411system.cpu.icache.overall_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency 412system.cpu.icache.overall_avg_miss_latency::total 61218.697830 # average overall miss latency 413system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 414system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 415system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 416system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 417system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 418system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 419system.cpu.icache.writebacks::writebacks 2 # number of writebacks 420system.cpu.icache.writebacks::total 2 # number of writebacks 421system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses 422system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses 423system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses 424system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses 425system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses 426system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses 427system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36071000 # number of ReadReq MSHR miss cycles 428system.cpu.icache.ReadReq_mshr_miss_latency::total 36071000 # number of ReadReq MSHR miss cycles 429system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36071000 # number of demand (read+write) MSHR miss cycles 430system.cpu.icache.demand_mshr_miss_latency::total 36071000 # number of demand (read+write) MSHR miss cycles 431system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071000 # number of overall MSHR miss cycles 432system.cpu.icache.overall_mshr_miss_latency::total 36071000 # number of overall MSHR miss cycles 433system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses 434system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses 435system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses 436system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses 437system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses 438system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses 439system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60218.697830 # average ReadReq mshr miss latency 440system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60218.697830 # average ReadReq mshr miss latency 441system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60218.697830 # average overall mshr miss latency 442system.cpu.icache.demand_avg_mshr_miss_latency::total 60218.697830 # average overall mshr miss latency 443system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60218.697830 # average overall mshr miss latency 444system.cpu.icache.overall_avg_mshr_miss_latency::total 60218.697830 # average overall mshr miss latency 445system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states 446system.cpu.l2cache.tags.replacements 0 # number of replacements 447system.cpu.l2cache.tags.tagsinuse 10666.571104 # Cycle average of tags in use 448system.cpu.l2cache.tags.total_refs 1874647 # Total number of references to valid blocks. 449system.cpu.l2cache.tags.sampled_refs 15340 # Sample count of references to valid blocks. 450system.cpu.l2cache.tags.avg_refs 122.206454 # Average number of references to valid blocks. 451system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 452system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.163402 # Average occupied blocks per requestor 453system.cpu.l2cache.tags.occ_blocks::cpu.data 10172.407702 # Average occupied blocks per requestor 454system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy 455system.cpu.l2cache.tags.occ_percent::cpu.data 0.310437 # Average percentage of cache occupancy 456system.cpu.l2cache.tags.occ_percent::total 0.325518 # Average percentage of cache occupancy 457system.cpu.l2cache.tags.occ_task_id_blocks::1024 15340 # Occupied blocks per task id 458system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 459system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 460system.cpu.l2cache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id 461system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 462system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15229 # Occupied blocks per task id 463system.cpu.l2cache.tags.occ_task_id_percent::1024 0.468140 # Percentage of cache occupancy per task id 464system.cpu.l2cache.tags.tag_accesses 15135236 # Number of tag accesses 465system.cpu.l2cache.tags.data_accesses 15135236 # Number of data accesses 466system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states 467system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits 468system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits 469system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 470system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 471system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits 472system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits 473system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits 474system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits 475system.cpu.l2cache.ReadSharedReq_hits::cpu.data 899974 # number of ReadSharedReq hits 476system.cpu.l2cache.ReadSharedReq_hits::total 899974 # number of ReadSharedReq hits 477system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits 478system.cpu.l2cache.demand_hits::cpu.data 932035 # number of demand (read+write) hits 479system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits 480system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits 481system.cpu.l2cache.overall_hits::cpu.data 932035 # number of overall hits 482system.cpu.l2cache.overall_hits::total 932057 # number of overall hits 483system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses 484system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses 485system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 577 # number of ReadCleanReq misses 486system.cpu.l2cache.ReadCleanReq_misses::total 577 # number of ReadCleanReq misses 487system.cpu.l2cache.ReadSharedReq_misses::cpu.data 215 # number of ReadSharedReq misses 488system.cpu.l2cache.ReadSharedReq_misses::total 215 # number of ReadSharedReq misses 489system.cpu.l2cache.demand_misses::cpu.inst 577 # number of demand (read+write) misses 490system.cpu.l2cache.demand_misses::cpu.data 14763 # number of demand (read+write) misses 491system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses 492system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses 493system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses 494system.cpu.l2cache.overall_misses::total 15340 # number of overall misses 495system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 880404500 # number of ReadExReq miss cycles 496system.cpu.l2cache.ReadExReq_miss_latency::total 880404500 # number of ReadExReq miss cycles 497system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34920500 # number of ReadCleanReq miss cycles 498system.cpu.l2cache.ReadCleanReq_miss_latency::total 34920500 # number of ReadCleanReq miss cycles 499system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13009500 # number of ReadSharedReq miss cycles 500system.cpu.l2cache.ReadSharedReq_miss_latency::total 13009500 # number of ReadSharedReq miss cycles 501system.cpu.l2cache.demand_miss_latency::cpu.inst 34920500 # number of demand (read+write) miss cycles 502system.cpu.l2cache.demand_miss_latency::cpu.data 893414000 # number of demand (read+write) miss cycles 503system.cpu.l2cache.demand_miss_latency::total 928334500 # number of demand (read+write) miss cycles 504system.cpu.l2cache.overall_miss_latency::cpu.inst 34920500 # number of overall miss cycles 505system.cpu.l2cache.overall_miss_latency::cpu.data 893414000 # number of overall miss cycles 506system.cpu.l2cache.overall_miss_latency::total 928334500 # number of overall miss cycles 507system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses) 508system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses) 509system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 510system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 511system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses) 512system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses) 513system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 599 # number of ReadCleanReq accesses(hits+misses) 514system.cpu.l2cache.ReadCleanReq_accesses::total 599 # number of ReadCleanReq accesses(hits+misses) 515system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 900189 # number of ReadSharedReq accesses(hits+misses) 516system.cpu.l2cache.ReadSharedReq_accesses::total 900189 # number of ReadSharedReq accesses(hits+misses) 517system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses 518system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses 519system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses 520system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses 521system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses 522system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses 523system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses 524system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses 525system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.963272 # miss rate for ReadCleanReq accesses 526system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.963272 # miss rate for ReadCleanReq accesses 527system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000239 # miss rate for ReadSharedReq accesses 528system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000239 # miss rate for ReadSharedReq accesses 529system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963272 # miss rate for demand accesses 530system.cpu.l2cache.demand_miss_rate::cpu.data 0.015593 # miss rate for demand accesses 531system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses 532system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses 533system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses 534system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses 535system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60517.218862 # average ReadExReq miss latency 536system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60517.218862 # average ReadExReq miss latency 537system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60520.797227 # average ReadCleanReq miss latency 538system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60520.797227 # average ReadCleanReq miss latency 539system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60509.302326 # average ReadSharedReq miss latency 540system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60509.302326 # average ReadSharedReq miss latency 541system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60520.797227 # average overall miss latency 542system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60517.103570 # average overall miss latency 543system.cpu.l2cache.demand_avg_miss_latency::total 60517.242503 # average overall miss latency 544system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60520.797227 # average overall miss latency 545system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60517.103570 # average overall miss latency 546system.cpu.l2cache.overall_avg_miss_latency::total 60517.242503 # average overall miss latency 547system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 548system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 550system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 551system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 552system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 553system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses 554system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses 555system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses 556system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 # number of ReadCleanReq MSHR misses 557system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 # number of ReadSharedReq MSHR misses 558system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses 559system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses 560system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses 561system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses 562system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses 563system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses 564system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses 565system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 734924500 # number of ReadExReq MSHR miss cycles 566system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 734924500 # number of ReadExReq MSHR miss cycles 567system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 29150500 # number of ReadCleanReq MSHR miss cycles 568system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 29150500 # number of ReadCleanReq MSHR miss cycles 569system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10859500 # number of ReadSharedReq MSHR miss cycles 570system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10859500 # number of ReadSharedReq MSHR miss cycles 571system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29150500 # number of demand (read+write) MSHR miss cycles 572system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 745784000 # number of demand (read+write) MSHR miss cycles 573system.cpu.l2cache.demand_mshr_miss_latency::total 774934500 # number of demand (read+write) MSHR miss cycles 574system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29150500 # number of overall MSHR miss cycles 575system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 745784000 # number of overall MSHR miss cycles 576system.cpu.l2cache.overall_mshr_miss_latency::total 774934500 # number of overall MSHR miss cycles 577system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses 578system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses 579system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses 580system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.963272 # mshr miss rate for ReadCleanReq accesses 581system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000239 # mshr miss rate for ReadSharedReq accesses 582system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000239 # mshr miss rate for ReadSharedReq accesses 583system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for demand accesses 584system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for demand accesses 585system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses 586system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses 587system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses 588system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses 589system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50517.218862 # average ReadExReq mshr miss latency 590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50517.218862 # average ReadExReq mshr miss latency 591system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50520.797227 # average ReadCleanReq mshr miss latency 592system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50520.797227 # average ReadCleanReq mshr miss latency 593system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50509.302326 # average ReadSharedReq mshr miss latency 594system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50509.302326 # average ReadSharedReq mshr miss latency 595system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50520.797227 # average overall mshr miss latency 596system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50517.103570 # average overall mshr miss latency 597system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50517.242503 # average overall mshr miss latency 598system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50520.797227 # average overall mshr miss latency 599system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50517.103570 # average overall mshr miss latency 600system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50517.242503 # average overall mshr miss latency 601system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. 602system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. 603system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 604system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 605system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 606system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 607system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states 608system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution 610system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution 612system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution 613system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution 614system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution 615system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution 616system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1200 # Packet count per connected master and slave (bytes) 617system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836298 # Packet count per connected master and slave (bytes) 618system.cpu.toL2Bus.pkt_count::total 2837498 # Packet count per connected master and slave (bytes) 619system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38464 # Cumulative packet size per connected master and slave (bytes) 620system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) 621system.cpu.toL2Bus.pkt_size::total 120942912 # Cumulative packet size per connected master and slave (bytes) 622system.cpu.toL2Bus.snoops 0 # Total snoops (count) 623system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 624system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram 625system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram 626system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 # Request fanout histogram 627system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 628system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% # Request fanout histogram 629system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% # Request fanout histogram 630system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 631system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 632system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 633system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 634system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram 635system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks) 636system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 637system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) 638system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 639system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) 640system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 641system.membus.snoop_filter.tot_requests 15340 # Total number of requests made to the snoop filter. 642system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 643system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 644system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 645system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 646system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 647system.membus.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states 648system.membus.trans_dist::ReadResp 792 # Transaction distribution 649system.membus.trans_dist::ReadExReq 14548 # Transaction distribution 650system.membus.trans_dist::ReadExResp 14548 # Transaction distribution 651system.membus.trans_dist::ReadSharedReq 792 # Transaction distribution 652system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) 653system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) 654system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) 655system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) 656system.membus.snoops 0 # Total snoops (count) 657system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 658system.membus.snoop_fanout::samples 15340 # Request fanout histogram 659system.membus.snoop_fanout::mean 0 # Request fanout histogram 660system.membus.snoop_fanout::stdev 0 # Request fanout histogram 661system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 662system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram 663system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 664system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 665system.membus.snoop_fanout::min_value 0 # Request fanout histogram 666system.membus.snoop_fanout::max_value 0 # Request fanout histogram 667system.membus.snoop_fanout::total 15340 # Request fanout histogram 668system.membus.reqLayer0.occupancy 15604500 # Layer occupancy (ticks) 669system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 670system.membus.respLayer1.occupancy 76700000 # Layer occupancy (ticks) 671system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 672 673---------- End Simulation Statistics ---------- 674