111308Santhony.gutierrez@amd.com 211308Santhony.gutierrez@amd.com---------- Begin Simulation Statistics ---------- 311308Santhony.gutierrez@amd.comsim_seconds 0.000469 # Number of seconds simulated 411308Santhony.gutierrez@amd.comsim_ticks 468854500 # Number of ticks simulated 511308Santhony.gutierrez@amd.comfinal_tick 468854500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611308Santhony.gutierrez@amd.comsim_freq 1000000000000 # Frequency of simulated ticks 711308Santhony.gutierrez@amd.comhost_inst_rate 67943 # Simulator instruction rate (inst/s) 811308Santhony.gutierrez@amd.comhost_op_rate 139717 # Simulator op (including micro ops) rate (op/s) 911308Santhony.gutierrez@amd.comhost_tick_rate 475693968 # Simulator tick rate (ticks/s) 1011308Santhony.gutierrez@amd.comhost_mem_usage 1301796 # Number of bytes of host memory used 1111308Santhony.gutierrez@amd.comhost_seconds 0.99 # Real time elapsed on the host 1211308Santhony.gutierrez@amd.comsim_insts 66963 # Number of instructions simulated 1311308Santhony.gutierrez@amd.comsim_ops 137705 # Number of ops (including micro ops) simulated 1411308Santhony.gutierrez@amd.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511308Santhony.gutierrez@amd.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytes_read::dir_cntrl0 100032 # Number of bytes read from this memory 1711308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytes_read::total 100032 # Number of bytes read from this memory 1811308Santhony.gutierrez@amd.comsystem.mem_ctrls.num_reads::dir_cntrl0 1563 # Number of read requests responded to by this memory 1911308Santhony.gutierrez@amd.comsystem.mem_ctrls.num_reads::total 1563 # Number of read requests responded to by this memory 2011308Santhony.gutierrez@amd.comsystem.mem_ctrls.bw_read::dir_cntrl0 213354036 # Total read bandwidth from this memory (bytes/s) 2111308Santhony.gutierrez@amd.comsystem.mem_ctrls.bw_read::total 213354036 # Total read bandwidth from this memory (bytes/s) 2211308Santhony.gutierrez@amd.comsystem.mem_ctrls.bw_total::dir_cntrl0 213354036 # Total bandwidth to/from this memory (bytes/s) 2311308Santhony.gutierrez@amd.comsystem.mem_ctrls.bw_total::total 213354036 # Total bandwidth to/from this memory (bytes/s) 2411308Santhony.gutierrez@amd.comsystem.mem_ctrls.readReqs 1563 # Number of read requests accepted 2511308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeReqs 0 # Number of write requests accepted 2611308Santhony.gutierrez@amd.comsystem.mem_ctrls.readBursts 1563 # Number of DRAM read bursts, including those serviced by the write queue 2711308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 2811308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesReadDRAM 100032 # Total number of bytes read from DRAM 2911308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue 3011308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM 3111308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesReadSys 100032 # Total read bytes from the system interface side 3211308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side 3311308Santhony.gutierrez@amd.comsystem.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 3411308Santhony.gutierrez@amd.comsystem.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 3511308Santhony.gutierrez@amd.comsystem.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 3611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts 3711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts 3811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts 3911308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts 4011308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts 4111308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts 4211308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts 4311308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts 4411308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts 4511308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts 4611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::10 183 # Per bank write bursts 4711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::11 90 # Per bank write bursts 4811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::12 225 # Per bank write bursts 4911308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::13 125 # Per bank write bursts 5011308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::14 51 # Per bank write bursts 5111308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::15 94 # Per bank write bursts 5211308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts 5311308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts 5411308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts 5511308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts 5611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts 5711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts 5811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts 5911308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts 6011308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts 6111308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts 6211308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts 6311308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts 6411308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts 6511308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts 6611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts 6711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts 6811308Santhony.gutierrez@amd.comsystem.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 6911308Santhony.gutierrez@amd.comsystem.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 7011308Santhony.gutierrez@amd.comsystem.mem_ctrls.totGap 468627000 # Total gap between requests 7111308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 7211308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 7311308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 7411308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 7511308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 7611308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 7711308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::6 1563 # Read request sizes (log2) 7811308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 7911308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 8011308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 8111308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 8211308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 8311308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 8411308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) 8511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::0 1548 # What read queue length does an incoming req see 8611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::1 4 # What read queue length does an incoming req see 8711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::2 2 # What read queue length does an incoming req see 8811308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::3 2 # What read queue length does an incoming req see 8911308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see 9011308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see 9111308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see 9211308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see 9311308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 9411308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 9511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 9611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 9711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 9811308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 9911308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 10011308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 10111308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 10211308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 10311308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 10411308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 10511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 10611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 10711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 10811308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 10911308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 11011308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 11111308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 11211308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 11311308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 11411308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 11511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 11611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 11711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see 11811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see 11911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see 12011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see 12111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see 12211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see 12311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see 12411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see 12511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see 12611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see 12711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see 12811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see 12911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see 13011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see 13111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see 13211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see 13311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see 13411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see 13511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see 13611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see 13711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see 13811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see 13911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see 14011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see 14111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see 14211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see 14311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see 14411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see 14511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see 14611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see 14711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see 14811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see 14911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see 15011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 15111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 15211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 15311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 15411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 15511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 15611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 15711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 15811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 15911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 16011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 16111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 16211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 16311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 16411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 16511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 16611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 16711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 16811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 16911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 17011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 17111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 17211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 17311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 17411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 17511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 17611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 17711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 17811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 17911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 18011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 18111308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::samples 450 # Bytes accessed per row activation 18211308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::mean 221.297778 # Bytes accessed per row activation 18311308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::gmean 151.217299 # Bytes accessed per row activation 18411308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::stdev 224.192300 # Bytes accessed per row activation 18511308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::0-127 165 36.67% 36.67% # Bytes accessed per row activation 18611308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::128-255 148 32.89% 69.56% # Bytes accessed per row activation 18711308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::256-383 55 12.22% 81.78% # Bytes accessed per row activation 18811308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::384-511 28 6.22% 88.00% # Bytes accessed per row activation 18911308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::512-639 19 4.22% 92.22% # Bytes accessed per row activation 19011308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::640-767 11 2.44% 94.67% # Bytes accessed per row activation 19111308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::768-895 8 1.78% 96.44% # Bytes accessed per row activation 19211308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::896-1023 6 1.33% 97.78% # Bytes accessed per row activation 19311308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::1024-1151 10 2.22% 100.00% # Bytes accessed per row activation 19411308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::total 450 # Bytes accessed per row activation 19511308Santhony.gutierrez@amd.comsystem.mem_ctrls.totQLat 14130749 # Total ticks spent queuing 19611308Santhony.gutierrez@amd.comsystem.mem_ctrls.totMemAccLat 43436999 # Total ticks spent from burst creation until serviced by the DRAM 19711308Santhony.gutierrez@amd.comsystem.mem_ctrls.totBusLat 7815000 # Total ticks spent in databus transfers 19811308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgQLat 9040.79 # Average queueing delay per DRAM burst 19911308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst 20011308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgMemAccLat 27790.79 # Average memory access latency per DRAM burst 20111308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgRdBW 213.35 # Average DRAM read bandwidth in MiByte/s 20211308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 20311308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgRdBWSys 213.35 # Average system read bandwidth in MiByte/s 20411308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 20511308Santhony.gutierrez@amd.comsystem.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 20611308Santhony.gutierrez@amd.comsystem.mem_ctrls.busUtil 1.67 # Data bus utilization in percentage 20711308Santhony.gutierrez@amd.comsystem.mem_ctrls.busUtilRead 1.67 # Data bus utilization in percentage for reads 20811308Santhony.gutierrez@amd.comsystem.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes 20911308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgRdQLen 1.01 # Average read queue length when enqueuing 21011308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing 21111308Santhony.gutierrez@amd.comsystem.mem_ctrls.readRowHits 1109 # Number of row buffer hits during reads 21211308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes 21311308Santhony.gutierrez@amd.comsystem.mem_ctrls.readRowHitRate 70.95 # Row buffer hit rate for reads 21411308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes 21511308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgGap 299825.34 # Average gap between requests 21611308Santhony.gutierrez@amd.comsystem.mem_ctrls.pageHitRate 70.95 # Row buffer hit rate, read and write combined 21711308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.actEnergy 1300320 # Energy for activate commands per rank (pJ) 21811308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.preEnergy 709500 # Energy for precharge commands per rank (pJ) 21911308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.readEnergy 5335200 # Energy for read commands per rank (pJ) 22011308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22111308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.refreshEnergy 30513600 # Energy for refresh commands per rank (pJ) 22211308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.actBackEnergy 265391145 # Energy for active background per rank (pJ) 22311308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.preBackEnergy 47661750 # Energy for precharge background per rank (pJ) 22411308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.totalEnergy 350911515 # Total energy per rank (pJ) 22511308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.averagePower 750.717244 # Core power per rank (mW) 22611308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::IDLE 79008000 # Time in different power states 22711308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::REF 15600000 # Time in different power states 22811308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states 22911308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::ACT 374147000 # Time in different power states 23011308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23111308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.actEnergy 2101680 # Energy for activate commands per rank (pJ) 23211308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.preEnergy 1146750 # Energy for precharge commands per rank (pJ) 23311308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.readEnergy 6801600 # Energy for read commands per rank (pJ) 23411308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) 23511308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.refreshEnergy 30513600 # Energy for refresh commands per rank (pJ) 23611308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.actBackEnergy 276170130 # Energy for active background per rank (pJ) 23711308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.preBackEnergy 38206500 # Energy for precharge background per rank (pJ) 23811308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.totalEnergy 354940260 # Total energy per rank (pJ) 23911308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.averagePower 759.336079 # Core power per rank (mW) 24011308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::IDLE 61948750 # Time in different power states 24111308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::REF 15600000 # Time in different power states 24211308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states 24311308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::ACT 389900000 # Time in different power states 24411308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states 24511308Santhony.gutierrez@amd.comsystem.ruby.clk_domain.clock 500 # Clock period in ticks 24611308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory 24711308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory 24811308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory 24911308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory 25011308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory 25111308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory 25211308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory 25311308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory 25411308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory 25511308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory 25611308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory 25711308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory 25811308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory 25911308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory 26011308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory 26111308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory 26211308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory 26311308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory 26411308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory 26511308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory 26611308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory 26711308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory 26811308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_read::cpu0.inst 1486090034 # Total read bandwidth from this memory (bytes/s) 26911308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_read::cpu0.data 255584622 # Total read bandwidth from this memory (bytes/s) 27011308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 6995774 # Total read bandwidth from this memory (bytes/s) 27111308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 6995774 # Total read bandwidth from this memory (bytes/s) 27211308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_read::total 1755666203 # Total read bandwidth from this memory (bytes/s) 27311308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_inst_read::cpu0.inst 1486090034 # Instruction read bandwidth from this memory (bytes/s) 27411308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 4265716 # Instruction read bandwidth from this memory (bytes/s) 27511308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 4265716 # Instruction read bandwidth from this memory (bytes/s) 27611308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_inst_read::total 1494621466 # Instruction read bandwidth from this memory (bytes/s) 27711308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_write::cpu0.data 155201667 # Write bandwidth from this memory (bytes/s) 27811308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 546012 # Write bandwidth from this memory (bytes/s) 27911308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 546012 # Write bandwidth from this memory (bytes/s) 28011308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_write::total 156293690 # Write bandwidth from this memory (bytes/s) 28111308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_total::cpu0.inst 1486090034 # Total bandwidth to/from this memory (bytes/s) 28211308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_total::cpu0.data 410786289 # Total bandwidth to/from this memory (bytes/s) 28311308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 7541785 # Total bandwidth to/from this memory (bytes/s) 28411308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 7541785 # Total bandwidth to/from this memory (bytes/s) 28511308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_total::total 1911959894 # Total bandwidth to/from this memory (bytes/s) 28611308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist::bucket_size 1 28711308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist::max_bucket 9 28811308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist::samples 114203 28911308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist::mean 1.000035 29011308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist::gmean 1.000024 29111308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist::stdev 0.005918 29211308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 29311308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist::total 114203 29411308Santhony.gutierrez@amd.comsystem.ruby.latency_hist::bucket_size 64 29511308Santhony.gutierrez@amd.comsystem.ruby.latency_hist::max_bucket 639 29611308Santhony.gutierrez@amd.comsystem.ruby.latency_hist::samples 114203 29711308Santhony.gutierrez@amd.comsystem.ruby.latency_hist::mean 3.070988 29811308Santhony.gutierrez@amd.comsystem.ruby.latency_hist::gmean 1.072272 29911308Santhony.gutierrez@amd.comsystem.ruby.latency_hist::stdev 18.192328 30011308Santhony.gutierrez@amd.comsystem.ruby.latency_hist | 112654 98.64% 98.64% | 11 0.01% 98.65% | 1238 1.08% 99.74% | 266 0.23% 99.97% | 14 0.01% 99.98% | 12 0.01% 99.99% | 7 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 30111308Santhony.gutierrez@amd.comsystem.ruby.latency_hist::total 114203 30211308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist::bucket_size 64 30311308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist::max_bucket 639 30411308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist::samples 1549 30511308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist::mean 152.827631 30611308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist::gmean 149.009432 30711308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist::stdev 40.628532 30811308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist | 0 0.00% 0.00% | 11 0.71% 0.71% | 1238 79.92% 80.63% | 266 17.17% 97.81% | 14 0.90% 98.71% | 12 0.77% 99.48% | 7 0.45% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 30911308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist::total 1549 31011308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist::bucket_size 2 31111308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist::max_bucket 19 31211308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist::samples 112654 31311308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist::mean 1.011824 31411308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist::gmean 1.001936 31511308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist::stdev 0.461184 31611308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist | 112580 99.93% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 74 0.07% 100.00% 31711308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist::total 112654 31811308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.incomplete_times 112580 31911308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.incomplete_times 74 32011308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits 32111308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.demand_misses 1556 # Number of cache demand misses 32211308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.demand_accesses 1556 # Number of cache demand accesses 32311308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.num_data_array_reads 16142 # number of data array reads 32411308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.num_data_array_writes 11998 # number of data array writes 32511308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.num_tag_array_reads 27136 # number of tag array reads 32611308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.num_tag_array_writes 1431 # number of tag array writes 32711308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits 32811308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D1cache.demand_misses 0 # Number of cache demand misses 32911308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D1cache.demand_accesses 0 # Number of cache demand accesses 33011308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits 33111308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.demand_misses 1287 # Number of cache demand misses 33211308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.demand_accesses 1287 # Number of cache demand accesses 33311308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.num_data_array_reads 85994 # number of data array reads 33411308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.num_data_array_writes 67 # number of data array writes 33511308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.num_tag_array_reads 87697 # number of tag array reads 33611308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.num_tag_array_writes 67 # number of tag array writes 33711308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 33811308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.demand_misses 1549 # Number of cache demand misses 33911308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.demand_accesses 1549 # Number of cache demand accesses 34011308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.num_data_array_reads 167 # number of data array reads 34111308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.num_data_array_writes 11993 # number of data array writes 34211308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.num_tag_array_reads 12092 # number of tag array reads 34311308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.num_tag_array_writes 1694 # number of tag array writes 34411308Santhony.gutierrez@amd.comsystem.cpu0.clk_domain.clock 500 # Clock period in ticks 34511308Santhony.gutierrez@amd.comsystem.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks 34611955Sgabeblack@google.comsystem.cpu0.workload.numSyscalls 21 # Number of system calls 34711308Santhony.gutierrez@amd.comsystem.cpu0.numCycles 937709 # number of cpu cycles simulated 34811308Santhony.gutierrez@amd.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 34911308Santhony.gutierrez@amd.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 35011308Santhony.gutierrez@amd.comsystem.cpu0.committedInsts 66963 # Number of instructions committed 35111308Santhony.gutierrez@amd.comsystem.cpu0.committedOps 137705 # Number of ops (including micro ops) committed 35211308Santhony.gutierrez@amd.comsystem.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses 35311308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses 35411308Santhony.gutierrez@amd.comsystem.cpu0.num_func_calls 3196 # number of times a function call or return occured 35511308Santhony.gutierrez@amd.comsystem.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls 35611308Santhony.gutierrez@amd.comsystem.cpu0.num_int_insts 136380 # number of integer instructions 35711308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_insts 1279 # number of float instructions 35811308Santhony.gutierrez@amd.comsystem.cpu0.num_int_register_reads 257490 # number of times the integer registers were read 35911308Santhony.gutierrez@amd.comsystem.cpu0.num_int_register_writes 110039 # number of times the integer registers were written 36011308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read 36111308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_register_writes 981 # number of times the floating registers were written 36211308Santhony.gutierrez@amd.comsystem.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read 36311308Santhony.gutierrez@amd.comsystem.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written 36411308Santhony.gutierrez@amd.comsystem.cpu0.num_mem_refs 27198 # number of memory refs 36511308Santhony.gutierrez@amd.comsystem.cpu0.num_load_insts 16684 # Number of load instructions 36611308Santhony.gutierrez@amd.comsystem.cpu0.num_store_insts 10514 # Number of store instructions 36711308Santhony.gutierrez@amd.comsystem.cpu0.num_idle_cycles 7323.003984 # Number of idle cycles 36811308Santhony.gutierrez@amd.comsystem.cpu0.num_busy_cycles 930385.996016 # Number of busy cycles 36911308Santhony.gutierrez@amd.comsystem.cpu0.not_idle_fraction 0.992191 # Percentage of non-idle cycles 37011308Santhony.gutierrez@amd.comsystem.cpu0.idle_fraction 0.007809 # Percentage of idle cycles 37111308Santhony.gutierrez@amd.comsystem.cpu0.Branches 16199 # Number of branches fetched 37211308Santhony.gutierrez@amd.comsystem.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction 37311308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction 37411308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction 37511308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction 37611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction 37711308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction 37811308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction 37911308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatMult 0 0.00% 80.25% # Class of executed instruction 38011308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatDiv 0 0.00% 80.25% # Class of executed instruction 38111308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 80.25% # Class of executed instruction 38211308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdAdd 0 0.00% 80.25% # Class of executed instruction 38311308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 80.25% # Class of executed instruction 38411308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdAlu 0 0.00% 80.25% # Class of executed instruction 38511308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdCmp 0 0.00% 80.25% # Class of executed instruction 38611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdCvt 0 0.00% 80.25% # Class of executed instruction 38711308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdMisc 0 0.00% 80.25% # Class of executed instruction 38811308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdMult 0 0.00% 80.25% # Class of executed instruction 38911308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 80.25% # Class of executed instruction 39011308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdShift 0 0.00% 80.25% # Class of executed instruction 39111308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 80.25% # Class of executed instruction 39211308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 80.25% # Class of executed instruction 39311308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 80.25% # Class of executed instruction 39411308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 80.25% # Class of executed instruction 39511308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 80.25% # Class of executed instruction 39611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 80.25% # Class of executed instruction 39711308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 80.25% # Class of executed instruction 39811308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25% # Class of executed instruction 39911308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 80.25% # Class of executed instruction 40011308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25% # Class of executed instruction 40111308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction 40211308Santhony.gutierrez@amd.comsystem.cpu0.op_class::MemRead 16684 12.12% 92.36% # Class of executed instruction 40311308Santhony.gutierrez@amd.comsystem.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction 40411308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 40511308Santhony.gutierrez@amd.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 40611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::total 137705 # Class of executed instruction 40711308Santhony.gutierrez@amd.comsystem.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 40811308Santhony.gutierrez@amd.comsystem.cpu1.clk_domain.clock 1000 # Clock period in ticks 40911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 41011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 41111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 271 # number of times the wf's instructions are blocked due to RAW dependencies 41211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 41311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 41411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 41511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 41611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 41711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 41811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 41911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 42011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 42111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 42211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands 42311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands 42411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands 42511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands 42611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 42711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands 42811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 42911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 43011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 43111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 43211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands 43311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 43411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 43511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 43611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 43711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 43811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 43911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 44011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 44111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 44211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 44311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 44411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 44511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 44611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 44711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 44811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 44911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 45011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 45111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 45211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 45311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 45411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 45511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 45611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 45711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 45811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 45911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 46011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 46111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 46211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 46311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 46411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 46511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 46611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 46711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 46811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 46911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 47011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 47111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 47211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 47311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 47411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 47511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 47611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 47711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 47811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 47911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 48011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 48111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 48211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 48311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 48411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 48511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 48611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 48711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 48811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 48911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 49011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 49111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 49211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 49311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 49411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 49511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 49611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 49711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 49811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 49911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 50011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 50111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 50211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 50311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 50411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 50511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 50611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 50711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 50811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 50911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 51011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 51111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 51211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 51311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 51411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 51511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 51611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 51711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 51811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 51911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 52011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 52111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 52211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 52311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 52411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 52511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 52611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 52711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 52811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 52911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 53011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 53111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 53211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 53311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 53411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 53511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 53611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 53711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 53811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 53911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 54011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 54111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 54211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 54311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 54411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 54511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 54611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 54711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 54811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 54911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 55011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 55111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 55211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 55311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 55411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 55511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 55611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 55711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 55811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 55911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 56011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 56111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 56211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 56311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 56411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 56511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 56611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 56711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 56811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 56911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 57011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 57111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 57211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 57311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 57411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 57511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 57611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 57711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 57811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 57911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 58011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 58111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 58211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 58311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 58411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 58511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 58611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 58711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 58811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 58911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 59011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 59111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 59211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 59311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 59411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 59511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 59611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 59711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 59811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 59911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 60011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 60111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 60211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 60311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 252 # number of times the wf's instructions are blocked due to RAW dependencies 60411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 60511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 60611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 60711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 60811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 60911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 61011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 61111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 61211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 61311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 61411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 61511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 61611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 61711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 61811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 61911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 62011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 62111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 62211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 62311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 62411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 62511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 62611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 62711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 62811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 62911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 63011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 63111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 63211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 63311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 63411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 63511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 63611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 63711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 63811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 63911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 64011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 64111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 64211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 64311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 64411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 64511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 64611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 64711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 64811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 64911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 65011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 65111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 65211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 65311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 65411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 65511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 65611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 65711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 65811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 65911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 66011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 66111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 66211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 66311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 66411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 66511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 66611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 66711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 66811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 66911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 67011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 67111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 67211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 67311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 67411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 67511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 67611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 67711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 67811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 67911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 68011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 68111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 68211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 68311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 68411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 68511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 68611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 68711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 68811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 68911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 69011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 69111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 69211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 69311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 69411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 69511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 69611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 69711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 69811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 69911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 70011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 70111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 70211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 70311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 70411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 70511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 70611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 70711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 70811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 70911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 71011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 71111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 71211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 71311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 71411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 71511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 71611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 71711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 71811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 71911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 72011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 72111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 72211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 72311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 72411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 72511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 72611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 72711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 72811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 72911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 73011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 73111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 73211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 73311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 73411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 73511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 73611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 73711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 73811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 73911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 74011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 74111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 74211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 74311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 74411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 74511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 74611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 74711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 74811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 74911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 75011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 75111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 75211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 75311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 75411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 75511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 75611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 75711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 75811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 75911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 76011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 76111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 76211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 76311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 76411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 76511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 76611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 76711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 76811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 76911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 77011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 77111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 77211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 77311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 77411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 77511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 77611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 77711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 77811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 77911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 78011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 78111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 78211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 78311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 78411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 78511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 78611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 78711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 78811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 78911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 79011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 79111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 79211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 79311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 79411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 79511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 243 # number of times the wf's instructions are blocked due to RAW dependencies 79611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 79711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 79811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 79911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 80011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 80111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 80211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 80311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 80411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 80511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 80611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 80711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 80811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 80911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 81011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 81111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 81211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 81311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 81411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 81511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 81611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 81711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 81811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 81911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 82011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 82111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 82211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 82311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 82411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 82511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 82611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 82711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 82811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 82911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 83011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 83111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 83211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 83311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 83411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 83511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 83611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 83711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 83811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 83911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 84011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 84111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 84211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 84311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 84411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 84511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 84611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 84711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 84811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 84911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 85011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 85111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 85211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 85311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 85411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 85511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 85611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 85711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 85811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 85911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 86011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 86111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 86211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 86311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 86411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 86511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 86611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 86711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 86811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 86911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 87011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 87111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 87211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 87311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 87411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 87511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 87611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 87711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 87811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 87911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 88011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 88111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 88211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 88311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 88411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 88511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 88611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 88711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 88811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 88911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 89011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 89111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 89211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 89311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 89411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 89511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 89611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 89711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 89811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 89911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 90011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 90111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 90211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 90311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 90411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 90511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 90611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 90711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 90811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 90911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 91011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 91111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 91211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 91311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 91411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 91511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 91611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 91711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 91811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 91911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 92011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 92111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 92211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 92311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 92411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 92511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 92611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 92711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 92811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 92911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 93011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 93111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 93211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 93311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 93411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 93511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 93611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 93711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 93811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 93911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 94011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 94111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 94211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 94311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 94411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 94511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 94611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 94711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 94811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 94911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 95011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 95111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 95211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 95311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 95411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 95511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 95611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 95711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 95811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 95911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 96011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 96111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 96211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 96311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 96411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 96511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 96611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 96711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 96811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 96911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 97011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 97111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 97211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 97311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 97411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 97511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 97611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 97711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 97811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 97911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 98011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 98111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 98211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 98311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 98411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 98511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 98611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 98711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 228 # number of times the wf's instructions are blocked due to RAW dependencies 98811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 98911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 99011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 99111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 99211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 99311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 99411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 99511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 99611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 99711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 99811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 99911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 100011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 100111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 100211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 100311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 100411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 100511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 100611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 100711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 100811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 100911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 101011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 101111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 101211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 101311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 101411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 101511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 101611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 101711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 101811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 101911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 102011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 102111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 102211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 102311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 102411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 102511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 102611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 102711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 102811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 102911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 103011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 103111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 103211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 103311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 103411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 103511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 103611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 103711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 103811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 103911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 104011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 104111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 104211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 104311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 104411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 104511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 104611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 104711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 104811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 104911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 105011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 105111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 105211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 105311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 105411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 105511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 105611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 105711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 105811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 105911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 106011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 106111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 106211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 106311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 106411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 106511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 106611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 106711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 106811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 106911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 107011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 107111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 107211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 107311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 107411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 107511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 107611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 107711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 107811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 107911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 108011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 108111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 108211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 108311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 108411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 108511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 108611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 108711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 108811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 108911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 109011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 109111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 109211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 109311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 109411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 109511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 109611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 109711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 109811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 109911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 110011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 110111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 110211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 110311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 110411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 110511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 110611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 110711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 110811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 110911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 111011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 111111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 111211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 111311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 111411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 111511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 111611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 111711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 111811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 111911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 112011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 112111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 112211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 112311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 112411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 112511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 112611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 112711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 112811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 112911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 113011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 113111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 113211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 113311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 113411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 113511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 113611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 113711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 113811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 113911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 114011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 114111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 114211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 114311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 114411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 114511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 114611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 114711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 114811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 114911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 115011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 115111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 115211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 115311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 115411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 115511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 115611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 115711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 115811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 115911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 116011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 116111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 116211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 116311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 116411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 116511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 116611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 116711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 116811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 116911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 117011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 117111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 117211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 117311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 117411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 117511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 117611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 117711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 117811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 117911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it 118011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 118111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 118211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 118311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 118411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 118511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 118611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 118711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 118811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 118911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 119011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 119111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 119211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 119311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 119411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 119511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 119611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 119711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 119811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 119911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 120011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 120111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 120211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 120311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 120411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 120511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 120611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 120711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 120811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 120911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 121011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 121111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 121211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 121311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 121411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it 121511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it 121611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it 121711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 4103 # number of cycles the CU issues nothing 121811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 133 # number of cycles the CU issued at least one instruction 121911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 122011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 122111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 122211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 122311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 122411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued 122511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 1359 # Number of cycles no instruction of specific type issued 122611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 382 # Number of cycles no instruction of specific type issued 122711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 338 # Number of cycles no instruction of specific type issued 122811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 302 # Number of cycles no instruction of specific type issued 122911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 373 # Number of cycles no instruction of specific type issued 123011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 26 # Number of cycles no instruction of specific type issued 123111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::samples 4236 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 123211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::mean 0.033286 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 123311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::stdev 0.190882 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 123411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 123511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::0 4103 96.86% 96.86% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 123611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::1 126 2.97% 99.83% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 123711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::2 6 0.14% 99.98% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 123811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::3 1 0.02% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 123911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 124011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 124111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 124211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 124311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 124411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 124511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::total 4236 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 124611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 68 # number of CU transitions from active to idle 124711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 68 # duration of idle periods in cycles 124811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 53.455882 # duration of idle periods in cycles 124911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 203.558231 # duration of idle periods in cycles 125011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles 125111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 48 70.59% 70.59% # duration of idle periods in cycles 125211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 8 11.76% 82.35% # duration of idle periods in cycles 125311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.47% 83.82% # duration of idle periods in cycles 125411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.47% 85.29% # duration of idle periods in cycles 125511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.94% 88.24% # duration of idle periods in cycles 125611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.47% 89.71% # duration of idle periods in cycles 125711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 89.71% # duration of idle periods in cycles 125811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 89.71% # duration of idle periods in cycles 125911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 89.71% # duration of idle periods in cycles 126011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 89.71% # duration of idle periods in cycles 126111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 89.71% # duration of idle periods in cycles 126211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 89.71% # duration of idle periods in cycles 126311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 89.71% # duration of idle periods in cycles 126411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 89.71% # duration of idle periods in cycles 126511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 89.71% # duration of idle periods in cycles 126611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 89.71% # duration of idle periods in cycles 126711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 10.29% 100.00% # duration of idle periods in cycles 126811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 126911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1317 # duration of idle periods in cycles 127011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 68 # duration of idle periods in cycles 127111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 127211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF 127311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests 127411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.tlb_cycles -318202403000 # total number of cycles for all uncoalesced requests 127511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.avg_translation_latency -413787260.078023 # Avg. translation latency for data translations 127611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 127711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 127811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 127911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 128011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses 128111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 128211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet 128311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet 128411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet 128511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet 128611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 128711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 128811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 128911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 129011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::10-11 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 129111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::12-13 4 66.67% 100.00% # Number of bank conflicts per LDS memory packet 129211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 129311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 129411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 129511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 129611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 129711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 129811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 129911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 130011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 130111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 130211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 130311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 130411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 130511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 130611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 130711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 130811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 130911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 131011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 131111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 131211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 131311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 131411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 131511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 131611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 131711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 131811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 131911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet 132011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet 132111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet 132211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) 132311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) 132411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) 132511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) 132611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) 132711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 132811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 132911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 133011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 133111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 133211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 133311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 133411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 133511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 133611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 133711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 133811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 133911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 134011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 134111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 134211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 134311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 134411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 134511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 134611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count 134711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count 134811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 134911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_instr_executed 141 # number of instructions executed 135011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 135111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::mean 84.978723 # Instruction Execution Rate: Number of executed vector instructions per cycle 135211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::stdev 240.114362 # Instruction Execution Rate: Number of executed vector instructions per cycle 135311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 135411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle 135511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle 135611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::4-5 53 37.59% 46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle 135711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::6-7 31 21.99% 68.79% # Instruction Execution Rate: Number of executed vector instructions per cycle 135811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle 135911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::10 1 0.71% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle 136011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 136111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle 136211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::max_value 1320 # Instruction Execution Rate: Number of executed vector instructions per cycle 136311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 136411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. VSZ/inst) 136511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_total_cycles 4236 # number of cycles the CU ran for 136611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.vpc 1.597970 # Vector Operations per cycle (this CU only) 136711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ipc 0.033286 # Instructions per cycle (this CU only) 136811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 136911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions) 137011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions) 137111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 137211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 137311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 137411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 137511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions) 137611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 137711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 137811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 137911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 138011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 138111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 138211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 138311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 138411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) 138511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 138611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 138711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) 138811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) 138911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) 139011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) 139111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) 139211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction 139311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::mean 37.833333 # number of active lanes per global memory instruction 139411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::stdev 27.064737 # number of active lanes per global memory instruction 139511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction 139611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction 139711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction 139811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::9-12 0 0.00% 5.56% # number of active lanes per global memory instruction 139911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::13-16 8 44.44% 50.00% # number of active lanes per global memory instruction 140011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction 140111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction 140211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction 140311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction 140411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction 140511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction 140611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction 140711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction 140811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction 140911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction 141011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction 141111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction 141211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction 141311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction 141411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction 141511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction 141611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction 141711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::mean 19.500000 # number of active lanes per local memory instruction 141811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::stdev 22.322634 # number of active lanes per local memory instruction 141911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction 142011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction 142111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction 142211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::9-12 0 0.00% 16.67% # number of active lanes per local memory instruction 142311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::13-16 4 66.67% 83.33% # number of active lanes per local memory instruction 142411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction 142511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction 142611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction 142711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction 142811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction 142911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction 143011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction 143111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction 143211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction 143311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction 143411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction 143511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction 143611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction 143711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 143811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 143911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 144011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 144111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 144211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations 144311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed 144411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts 144511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 144611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 144711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 276 # number of times the wf's instructions are blocked due to RAW dependencies 144811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 144911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 145011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 145111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 145211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 145311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 145411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 145511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 145611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 145711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 145811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands 145911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands 146011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands 146111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands 146211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 146311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands 146411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 146511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 146611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 146711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 146811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands 146911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 147011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 147111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 147211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 147311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 147411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 147511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 147611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 147711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 147811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 147911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 148011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 148111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 148211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 148311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 148411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 148511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 148611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 148711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 148811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 148911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 149011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 149111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 149211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 149311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 149411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 149511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 149611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 149711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 149811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 149911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 150011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 150111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 150211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 150311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 150411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 150511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 150611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 150711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 150811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 150911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 151011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 151111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 151211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 151311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 151411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 151511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 151611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 151711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 151811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 151911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 152011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 152111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 152211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 152311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 152411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 152511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 152611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 152711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 152811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 152911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 153011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 153111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 153211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 153311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 153411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 153511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 153611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 153711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 153811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 153911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 154011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 154111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 154211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 154311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 154411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 154511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 154611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 154711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 154811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 154911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 155011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 155111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 155211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 155311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 155411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 155511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 155611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 155711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 155811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 155911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 156011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 156111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 156211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 156311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 156411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 156511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 156611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 156711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 156811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 156911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 157011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 157111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 157211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 157311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 157411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 157511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 157611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 157711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 157811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 157911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 158011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 158111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 158211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 158311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 158411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 158511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 158611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 158711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 158811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 158911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 159011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 159111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 159211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 159311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 159411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 159511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 159611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 159711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 159811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 159911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 160011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 160111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 160211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 160311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 160411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 160511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 160611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 160711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 160811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 160911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 161011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 161111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 161211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 161311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 161411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 161511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 161611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 161711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 161811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 161911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 162011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 162111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 162211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 162311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 162411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 162511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 162611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 162711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 162811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 162911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 163011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 163111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 163211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 163311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 163411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 163511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 163611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 163711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 163811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 163911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 254 # number of times the wf's instructions are blocked due to RAW dependencies 164011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 164111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 164211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 164311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 164411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 164511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 164611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 164711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 164811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 164911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 165011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 165111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 165211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 165311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 165411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 165511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 165611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 165711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 165811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 165911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 166011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 166111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 166211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 166311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 166411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 166511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 166611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 166711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 166811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 166911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 167011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 167111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 167211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 167311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 167411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 167511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 167611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 167711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 167811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 167911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 168011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 168111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 168211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 168311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 168411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 168511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 168611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 168711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 168811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 168911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 169011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 169111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 169211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 169311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 169411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 169511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 169611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 169711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 169811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 169911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 170011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 170111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 170211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 170311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 170411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 170511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 170611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 170711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 170811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 170911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 171011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 171111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 171211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 171311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 171411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 171511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 171611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 171711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 171811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 171911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 172011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 172111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 172211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 172311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 172411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 172511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 172611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 172711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 172811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 172911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 173011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 173111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 173211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 173311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 173411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 173511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 173611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 173711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 173811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 173911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 174011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 174111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 174211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 174311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 174411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 174511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 174611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 174711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 174811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 174911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 175011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 175111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 175211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 175311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 175411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 175511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 175611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 175711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 175811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 175911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 176011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 176111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 176211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 176311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 176411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 176511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 176611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 176711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 176811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 176911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 177011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 177111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 177211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 177311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 177411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 177511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 177611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 177711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 177811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 177911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 178011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 178111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 178211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 178311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 178411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 178511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 178611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 178711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 178811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 178911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 179011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 179111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 179211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 179311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 179411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 179511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 179611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 179711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 179811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 179911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 180011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 180111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 180211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 180311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 180411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 180511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 180611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 180711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 180811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 180911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 181011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 181111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 181211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 181311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 181411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 181511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 181611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 181711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 181811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 181911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 182011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 182111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 182211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 182311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 182411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 182511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 182611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 182711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 182811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 182911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 183011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 183111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 251 # number of times the wf's instructions are blocked due to RAW dependencies 183211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 183311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 183411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 183511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 183611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 183711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 183811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 183911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 184011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 184111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 184211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 184311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 184411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 184511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 184611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 184711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 184811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 184911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 185011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 185111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 185211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 185311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 185411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 185511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 185611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 185711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 185811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 185911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 186011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 186111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 186211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 186311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 186411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 186511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 186611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 186711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 186811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 186911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 187011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 187111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 187211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 187311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 187411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 187511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 187611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 187711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 187811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 187911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 188011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 188111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 188211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 188311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 188411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 188511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 188611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 188711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 188811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 188911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 189011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 189111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 189211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 189311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 189411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 189511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 189611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 189711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 189811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 189911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 190011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 190111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 190211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 190311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 190411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 190511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 190611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 190711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 190811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 190911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 191011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 191111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 191211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 191311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 191411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 191511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 191611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 191711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 191811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 191911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 192011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 192111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 192211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 192311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 192411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 192511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 192611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 192711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 192811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 192911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 193011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 193111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 193211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 193311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 193411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 193511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 193611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 193711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 193811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 193911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 194011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 194111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 194211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 194311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 194411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 194511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 194611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 194711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 194811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 194911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 195011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 195111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 195211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 195311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 195411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 195511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 195611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 195711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 195811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 195911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 196011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 196111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 196211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 196311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 196411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 196511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 196611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 196711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 196811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 196911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 197011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 197111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 197211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 197311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 197411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 197511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 197611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 197711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 197811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 197911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 198011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 198111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 198211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 198311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 198411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 198511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 198611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 198711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 198811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 198911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 199011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 199111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 199211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 199311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 199411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 199511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 199611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 199711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 199811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 199911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 200011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 200111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 200211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 200311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 200411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 200511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 200611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 200711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 200811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 200911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 201011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 201111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 201211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 201311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 201411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 201511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 201611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 201711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 201811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 201911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 202011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 202111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 202211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 202311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 236 # number of times the wf's instructions are blocked due to RAW dependencies 202411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 202511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 202611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 202711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 202811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 202911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 203011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 203111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 203211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 203311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 203411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 203511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 203611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 203711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 203811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 203911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 204011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 204111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 204211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 204311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 204411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 204511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 204611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 204711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 204811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 204911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 205011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 205111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 205211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 205311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 205411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 205511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 205611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 205711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 205811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 205911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 206011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 206111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 206211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 206311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 206411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 206511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 206611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 206711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 206811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 206911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 207011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 207111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 207211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 207311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 207411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 207511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 207611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 207711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 207811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 207911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 208011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 208111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 208211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 208311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 208411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 208511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 208611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 208711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 208811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 208911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 209011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 209111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 209211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 209311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 209411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 209511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 209611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 209711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 209811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 209911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 210011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 210111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 210211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 210311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 210411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 210511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 210611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 210711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 210811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 210911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 211011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 211111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 211211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 211311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 211411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 211511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 211611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 211711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 211811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 211911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 212011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 212111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 212211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 212311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 212411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 212511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 212611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 212711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 212811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 212911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 213011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 213111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 213211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 213311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 213411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 213511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 213611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 213711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 213811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 213911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 214011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 214111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 214211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 214311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 214411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 214511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 214611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 214711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 214811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 214911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 215011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 215111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 215211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 215311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 215411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 215511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 215611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 215711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 215811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 215911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 216011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 216111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 216211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 216311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 216411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 216511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 216611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 216711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 216811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 216911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 217011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 217111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 217211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 217311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 217411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 217511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 217611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 217711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 217811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 217911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 218011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 218111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 218211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 218311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 218411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 218511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 218611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 218711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 218811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 218911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 219011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 219111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 219211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 219311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 219411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 219511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 219611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 219711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 219811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 219911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 220011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 220111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 220211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 220311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 220411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 220511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 220611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 220711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 220811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 220911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 221011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 221111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 221211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 221311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 221411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 221511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it 221611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 221711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 221811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 221911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 222011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 222111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 222211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 222311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 222411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 222511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 222611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 222711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 222811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 222911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 223011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 223111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 223211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 223311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 223411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 223511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 223611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 223711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 223811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 223911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 224011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 224111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 224211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 224311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 224411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 224511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 224611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 224711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 224811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 224911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 225011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it 225111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it 225211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it 225311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 4105 # number of cycles the CU issues nothing 225411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 131 # number of cycles the CU issued at least one instruction 225511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 225611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 225711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 225811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 225911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 226011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued 226111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 1525 # Number of cycles no instruction of specific type issued 226211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 346 # Number of cycles no instruction of specific type issued 226311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 363 # Number of cycles no instruction of specific type issued 226411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 363 # Number of cycles no instruction of specific type issued 226511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 363 # Number of cycles no instruction of specific type issued 226611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 33 # Number of cycles no instruction of specific type issued 226711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::samples 4236 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 226811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::mean 0.033286 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 226911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::stdev 0.194558 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 227011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 227111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::0 4105 96.91% 96.91% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 227211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::1 123 2.90% 99.81% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 227311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::2 6 0.14% 99.95% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 227411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::3 2 0.05% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 227511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 227611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 227711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 227811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 227911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 228011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 228111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::total 4236 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 228211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 74 # number of CU transitions from active to idle 228311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 74 # duration of idle periods in cycles 228411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 51.891892 # duration of idle periods in cycles 228511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 210.095188 # duration of idle periods in cycles 228611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles 228711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 56 75.68% 75.68% # duration of idle periods in cycles 228811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 7 9.46% 85.14% # duration of idle periods in cycles 228911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 85.14% # duration of idle periods in cycles 229011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 2 2.70% 87.84% # duration of idle periods in cycles 229111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 1 1.35% 89.19% # duration of idle periods in cycles 229211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.35% 90.54% # duration of idle periods in cycles 229311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 90.54% # duration of idle periods in cycles 229411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 90.54% # duration of idle periods in cycles 229511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 90.54% # duration of idle periods in cycles 229611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 90.54% # duration of idle periods in cycles 229711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 90.54% # duration of idle periods in cycles 229811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 90.54% # duration of idle periods in cycles 229911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 90.54% # duration of idle periods in cycles 230011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 90.54% # duration of idle periods in cycles 230111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 90.54% # duration of idle periods in cycles 230211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 90.54% # duration of idle periods in cycles 230311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 9.46% 100.00% # duration of idle periods in cycles 230411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 230511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1321 # duration of idle periods in cycles 230611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 74 # duration of idle periods in cycles 230711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 230811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF 230911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests 231011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.tlb_cycles -318199598000 # total number of cycles for all uncoalesced requests 231111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.avg_translation_latency -413783612.483745 # Avg. translation latency for data translations 231211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 231311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 231411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 231511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 231611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses 231711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 231811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet 231911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet 232011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet 232111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet 232211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 232311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 232411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 232511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 232611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::10-11 1 16.67% 50.00% # Number of bank conflicts per LDS memory packet 232711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::12-13 3 50.00% 100.00% # Number of bank conflicts per LDS memory packet 232811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 232911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 233011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 233111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 233211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 233311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 233411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 233511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 233611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 233711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 233811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 233911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 234011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 234111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 234211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 234311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 234411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 234511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 234611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 234711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 234811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 234911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 235011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 235111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 235211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 235311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 235411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 235511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet 235611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet 235711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet 235811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) 235911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) 236011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) 236111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) 236211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) 236311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 236411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 236511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 236611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 236711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 236811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 236911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 237011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 237111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 237211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 237311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 237411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 237511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 237611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 237711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 237811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 237911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 238011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 238111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 238211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count 238311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count 238411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 238511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_instr_executed 141 # number of instructions executed 238611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 238711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::mean 86.326241 # Instruction Execution Rate: Number of executed vector instructions per cycle 238811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::stdev 246.713874 # Instruction Execution Rate: Number of executed vector instructions per cycle 238911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 239011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle 239111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle 239211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::4-5 53 37.59% 46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle 239311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::6-7 29 20.57% 67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle 239411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::8-9 5 3.55% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle 239511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::10 1 0.71% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle 239611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 239711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle 239811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::max_value 1324 # Instruction Execution Rate: Number of executed vector instructions per cycle 239911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 240011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. VSZ/inst) 240111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_total_cycles 4236 # number of cycles the CU ran for 240211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.vpc 1.596317 # Vector Operations per cycle (this CU only) 240311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ipc 0.033286 # Instructions per cycle (this CU only) 240411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 240511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions) 240611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions) 240711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 240811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 240911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 241011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions) 241111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions) 241211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 241311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 241411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 241511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 241611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 241711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 241811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 241911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 242011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) 242111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 242211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 242311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) 242411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) 242511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) 242611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) 242711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) 242811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction 242911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::mean 37.722222 # number of active lanes per global memory instruction 243011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::stdev 27.174394 # number of active lanes per global memory instruction 243111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction 243211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction 243311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction 243411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::9-12 2 11.11% 16.67% # number of active lanes per global memory instruction 243511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::13-16 6 33.33% 50.00% # number of active lanes per global memory instruction 243611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction 243711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction 243811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction 243911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction 244011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction 244111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction 244211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction 244311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction 244411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction 244511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction 244611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction 244711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction 244811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction 244911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction 245011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction 245111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction 245211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction 245311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::mean 19.333333 # number of active lanes per local memory instruction 245411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::stdev 22.384518 # number of active lanes per local memory instruction 245511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction 245611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction 245711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction 245811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::9-12 1 16.67% 33.33% # number of active lanes per local memory instruction 245911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::13-16 3 50.00% 83.33% # number of active lanes per local memory instruction 246011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction 246111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction 246211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction 246311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction 246411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction 246511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction 246611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction 246711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction 246811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction 246911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction 247011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction 247111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction 247211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction 247311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 247411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 247511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 247611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 247711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 247811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations 247911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed 248011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts 248111308Santhony.gutierrez@amd.comsystem.cpu2.num_kernel_launched 1 # number of kernel launched 248211308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits 248311308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses 248411308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses 248511308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.num_data_array_writes 1600 # number of data array writes 248611308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1602 # number of tag array reads 248711308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1572 # number of tag array writes 248811308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 248911308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks 249011308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses 249111308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses 249211308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue 249311308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 249411308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts 249511308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 249611308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks 249711308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses 249811308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits 249911308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses 250011308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate 250111308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses 250211308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits 250311308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses 250411308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate 250511308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level 250611308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table 250711308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.unique_pages 0 # Number of unique pages touched 250811308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 250911308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs 251011308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 251111308Santhony.gutierrez@amd.comsystem.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 251211308Santhony.gutierrez@amd.comsystem.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks 251311308Santhony.gutierrez@amd.comsystem.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses 251411308Santhony.gutierrez@amd.comsystem.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses 251511308Santhony.gutierrez@amd.comsystem.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue 251611308Santhony.gutierrez@amd.comsystem.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 251711308Santhony.gutierrez@amd.comsystem.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts 251811308Santhony.gutierrez@amd.comsystem.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 251911308Santhony.gutierrez@amd.comsystem.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks 252011308Santhony.gutierrez@amd.comsystem.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses 252111308Santhony.gutierrez@amd.comsystem.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses 252211308Santhony.gutierrez@amd.comsystem.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue 252311308Santhony.gutierrez@amd.comsystem.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 252411308Santhony.gutierrez@amd.comsystem.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts 252511308Santhony.gutierrez@amd.comsystem.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 252611308Santhony.gutierrez@amd.comsystem.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks 252711308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses 252811308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_hits 774 # Number of TLB hits 252911308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_misses 4 # Number of TLB misses 253011308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate 253111308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses 253211308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_hits 774 # Number of TLB hits 253311308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_misses 4 # Number of TLB misses 253411308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate 253511308Santhony.gutierrez@amd.comsystem.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level 253611308Santhony.gutierrez@amd.comsystem.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table 253711308Santhony.gutierrez@amd.comsystem.l1_tlb0.unique_pages 4 # Number of unique pages touched 253811308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 253911308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs 254011308Santhony.gutierrez@amd.comsystem.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 254111308Santhony.gutierrez@amd.comsystem.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 254211308Santhony.gutierrez@amd.comsystem.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks 254311308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses 254411308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_hits 766 # Number of TLB hits 254511308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_misses 3 # Number of TLB misses 254611308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate 254711308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses 254811308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_hits 766 # Number of TLB hits 254911308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_misses 3 # Number of TLB misses 255011308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate 255111308Santhony.gutierrez@amd.comsystem.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level 255211308Santhony.gutierrez@amd.comsystem.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table 255311308Santhony.gutierrez@amd.comsystem.l1_tlb1.unique_pages 3 # Number of unique pages touched 255411308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 255511308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs 255611308Santhony.gutierrez@amd.comsystem.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 255711308Santhony.gutierrez@amd.comsystem.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 255811308Santhony.gutierrez@amd.comsystem.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks 255911308Santhony.gutierrez@amd.comsystem.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses 256011308Santhony.gutierrez@amd.comsystem.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 256111308Santhony.gutierrez@amd.comsystem.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 256211308Santhony.gutierrez@amd.comsystem.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 256311308Santhony.gutierrez@amd.comsystem.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts 256411308Santhony.gutierrez@amd.comsystem.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 256511308Santhony.gutierrez@amd.comsystem.l2_tlb.clk_domain.clock 1000 # Clock period in ticks 256611308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses 256711308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_hits 3 # Number of TLB hits 256811308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_misses 5 # Number of TLB misses 256911308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate 257011308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses 257111308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_hits 3 # Number of TLB hits 257211308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_misses 12 # Number of TLB misses 257311308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate 257411308Santhony.gutierrez@amd.comsystem.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level 257511308Santhony.gutierrez@amd.comsystem.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table 257611308Santhony.gutierrez@amd.comsystem.l2_tlb.unique_pages 5 # Number of unique pages touched 257711308Santhony.gutierrez@amd.comsystem.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs 257811308Santhony.gutierrez@amd.comsystem.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs 257911308Santhony.gutierrez@amd.comsystem.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 258011308Santhony.gutierrez@amd.comsystem.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 258111308Santhony.gutierrez@amd.comsystem.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks 258211308Santhony.gutierrez@amd.comsystem.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses 258311308Santhony.gutierrez@amd.comsystem.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 258411308Santhony.gutierrez@amd.comsystem.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 258511308Santhony.gutierrez@amd.comsystem.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 258611308Santhony.gutierrez@amd.comsystem.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts 258711308Santhony.gutierrez@amd.comsystem.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 258811308Santhony.gutierrez@amd.comsystem.l3_tlb.clk_domain.clock 1000 # Clock period in ticks 258911308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses 259011308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_hits 0 # Number of TLB hits 259111308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_misses 5 # Number of TLB misses 259211308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate 259311308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses 259411308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_hits 0 # Number of TLB hits 259511308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_misses 12 # Number of TLB misses 259611308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate 259711308Santhony.gutierrez@amd.comsystem.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level 259811308Santhony.gutierrez@amd.comsystem.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table 259911308Santhony.gutierrez@amd.comsystem.l3_tlb.unique_pages 5 # Number of unique pages touched 260011308Santhony.gutierrez@amd.comsystem.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs 260111308Santhony.gutierrez@amd.comsystem.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs 260211308Santhony.gutierrez@amd.comsystem.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 260311308Santhony.gutierrez@amd.comsystem.piobus.trans_dist::WriteReq 94 # Transaction distribution 260411308Santhony.gutierrez@amd.comsystem.piobus.trans_dist::WriteResp 94 # Transaction distribution 260511308Santhony.gutierrez@amd.comsystem.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) 260611308Santhony.gutierrez@amd.comsystem.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes) 260711308Santhony.gutierrez@amd.comsystem.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes) 260811308Santhony.gutierrez@amd.comsystem.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes) 260911308Santhony.gutierrez@amd.comsystem.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks) 261011308Santhony.gutierrez@amd.comsystem.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) 261111308Santhony.gutierrez@amd.comsystem.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) 261211308Santhony.gutierrez@amd.comsystem.piobus.respLayer0.utilization 0.0 # Layer utilization (%) 261311308Santhony.gutierrez@amd.comsystem.rb_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits 261411308Santhony.gutierrez@amd.comsystem.rb_cntrl0.cacheMemory.demand_misses 0 # Number of cache demand misses 261511308Santhony.gutierrez@amd.comsystem.rb_cntrl0.cacheMemory.demand_accesses 0 # Number of cache demand accesses 261611308Santhony.gutierrez@amd.comsystem.rb_cntrl0.cacheMemory.num_tag_array_reads 1553 # number of tag array reads 261711308Santhony.gutierrez@amd.comsystem.rb_cntrl0.cacheMemory.num_tag_array_writes 3123 # number of tag array writes 261811308Santhony.gutierrez@amd.comsystem.reg_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits 261911308Santhony.gutierrez@amd.comsystem.reg_cntrl0.cacheMemory.demand_misses 0 # Number of cache demand misses 262011308Santhony.gutierrez@amd.comsystem.reg_cntrl0.cacheMemory.demand_accesses 0 # Number of cache demand accesses 262111308Santhony.gutierrez@amd.comsystem.reg_cntrl0.cacheMemory.num_tag_array_reads 279 # number of tag array reads 262211308Santhony.gutierrez@amd.comsystem.reg_cntrl0.cacheMemory.num_tag_array_writes 279 # number of tag array writes 262311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.percent_links_utilized 0.122493 262411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Data::0 16 262511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1558 262611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Request_Control::5 279 262711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Request_Control::7 279 262811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Request_Control::8 8 262911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1577 263011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 303 263111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Response_Control::4 34 263211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Writeback_Control::2 24 263311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1556 263411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Data::0 1152 263511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12464 263611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::5 2232 263711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::7 2232 263811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::8 64 263911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 113544 264011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 2424 264111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::4 272 264211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Writeback_Control::2 192 264311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12448 264411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.percent_links_utilized 0.185852 264511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Control::0 23 264611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 3098 264711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Request_Control::7 274 264811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Request_Control::8 4 264911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 1568 265011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 281 265111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Response_Control::4 23 265211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 3098 265311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Control::0 184 265411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 24784 265511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::7 2192 265611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::8 32 265711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 112896 265811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 2248 265911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::4 184 266011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 24784 266111308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 266211308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 266311308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 266411308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.num_data_array_reads 6 # number of data array reads 266511308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes 266611308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.num_tag_array_reads 1297 # number of tag array reads 266711308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.num_tag_array_writes 11 # number of tag array writes 266811308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.num_tag_array_stalls 1271 # number of stalls caused by tag array 266911308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array 267011308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP 267111308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers 267211308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 267311308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_ld_misses 5 # loads that miss in the GPU 267411308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP 267511308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers 267611308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 267711308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_st_misses 9 # stores that miss in the GPU 267811308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 267911308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 268011308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 268111308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU 268211308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 268311308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 268411308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 268511308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU 268611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.percent_links_utilized 0.003510 268711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_count.Control::0 11 268811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_count.Data::0 34 268911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_count.Data::1 18 269011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_count.Request_Control::0 16 269111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_count.Request_Control::1 9 269211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_count.Request_Control::7 5 269311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_count.Request_Control::8 4 269411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_count.Response_Data::2 9 269511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_count.Response_Data::3 11 269611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_count.Response_Control::2 22 269711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_count.Response_Control::4 11 269811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_count.Writeback_Control::2 16 269911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_count.Writeback_Control::3 16 270011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_count.Unblock_Control::4 32 270111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_bytes.Control::0 88 270211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_bytes.Data::0 2448 270311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_bytes.Data::1 1296 270411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::0 128 270511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::1 72 270611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::7 40 270711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::8 32 270811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_bytes.Response_Data::2 648 270911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_bytes.Response_Data::3 792 271011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_bytes.Response_Control::2 176 271111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_bytes.Response_Control::4 88 271211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_bytes.Writeback_Control::2 128 271311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_bytes.Writeback_Control::3 128 271411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.msg_bytes.Unblock_Control::4 256 271511308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits 271611308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 271711308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses 271811308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_data_array_reads 6 # number of data array reads 271911308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes 272011308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_tag_array_reads 1297 # number of tag array reads 272111308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_tag_array_writes 11 # number of tag array writes 272211308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_tag_array_stalls 1271 # number of stalls caused by tag array 272311308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array 272411308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP 272511308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers 272611308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 272711308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_ld_misses 5 # loads that miss in the GPU 272811308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP 272911308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers 273011308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 273111308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_st_misses 9 # stores that miss in the GPU 273211308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 273311308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 273411308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 273511308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU 273611308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 273711308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 273811308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 273911308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU 274011308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 274111308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 274211308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 274311308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads 274411308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.num_tag_array_reads 91 # number of tag array reads 274511308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.num_tag_array_writes 10 # number of tag array writes 274611308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.sequencer.load_waiting_on_load 98 # Number of times a load aliased with a pending load 274711308Santhony.gutierrez@amd.comsystem.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 274811308Santhony.gutierrez@amd.comsystem.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses 274911308Santhony.gutierrez@amd.comsystem.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses 275011308Santhony.gutierrez@amd.comsystem.tcc_cntrl0.L2cache.num_data_array_writes 9 # number of data array writes 275111308Santhony.gutierrez@amd.comsystem.tcc_cntrl0.L2cache.num_tag_array_reads 45 # number of tag array reads 275211308Santhony.gutierrez@amd.comsystem.tcc_cntrl0.L2cache.num_tag_array_writes 21 # number of tag array writes 275311308Santhony.gutierrez@amd.comsystem.tcc_rb_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits 275411308Santhony.gutierrez@amd.comsystem.tcc_rb_cntrl0.cacheMemory.demand_misses 0 # Number of cache demand misses 275511308Santhony.gutierrez@amd.comsystem.tcc_rb_cntrl0.cacheMemory.demand_accesses 0 # Number of cache demand accesses 275611308Santhony.gutierrez@amd.comsystem.tcc_rb_cntrl0.cacheMemory.num_tag_array_reads 29 # number of tag array reads 275711308Santhony.gutierrez@amd.comsystem.tcc_rb_cntrl0.cacheMemory.num_tag_array_writes 89 # number of tag array writes 275811308Santhony.gutierrez@amd.comsystem.tcc_rb_cntrl0.cacheMemory.num_tag_array_stalls 20 # number of stalls caused by tag array 275911308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Control 34 276011308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Data 68 276111308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Request_Control 5534 276211308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Response_Data 3165 276311308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Response_Control 674 276411308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Writeback_Control 56 276511308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Unblock_Control 4686 276611308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Control 272 276711308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Data 4896 276811308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Request_Control 44272 276911308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Response_Data 227880 277011308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Response_Control 5392 277111308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Writeback_Control 448 277211308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Unblock_Control 37488 277311308Santhony.gutierrez@amd.comsystem.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 277411308Santhony.gutierrez@amd.comsystem.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks 277511308Santhony.gutierrez@amd.comsystem.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses 277611308Santhony.gutierrez@amd.comsystem.sqc_coalescer.coalesced_accesses 66 # Number of coalesced TLB accesses 277711308Santhony.gutierrez@amd.comsystem.sqc_coalescer.queuing_cycles 288000 # Number of cycles spent in queue 277811308Santhony.gutierrez@amd.comsystem.sqc_coalescer.local_queuing_cycles 288000 # Number of cycles spent in queue for all incoming reqs 277911308Santhony.gutierrez@amd.comsystem.sqc_coalescer.local_latency 3348.837209 # Avg. latency over all incoming pkts 278011308Santhony.gutierrez@amd.comsystem.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 278111308Santhony.gutierrez@amd.comsystem.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks 278211308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_TLB_accesses 66 # Number of TLB accesses 278311308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_TLB_hits 65 # Number of TLB hits 278411308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_TLB_misses 1 # Number of TLB misses 278511308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_TLB_miss_rate 1.515152 # TLB miss rate 278611308Santhony.gutierrez@amd.comsystem.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses 278711308Santhony.gutierrez@amd.comsystem.sqc_tlb.global_TLB_hits 78 # Number of TLB hits 278811308Santhony.gutierrez@amd.comsystem.sqc_tlb.global_TLB_misses 8 # Number of TLB misses 278911308Santhony.gutierrez@amd.comsystem.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate 279011308Santhony.gutierrez@amd.comsystem.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level 279111308Santhony.gutierrez@amd.comsystem.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table 279211308Santhony.gutierrez@amd.comsystem.sqc_tlb.unique_pages 1 # Number of unique pages touched 279311308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_cycles 66001 # Number of cycles spent in queue for all incoming reqs 279411308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_latency 1000.015152 # Avg. latency over incoming coalesced reqs 279511308Santhony.gutierrez@amd.comsystem.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 279611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.091873 279711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Data::0 16 279811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1279 279911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::5 279 280011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 19 280111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 17 280211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1556 280311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Data::0 1152 280411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 10232 280511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::5 2232 280611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 1368 280711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 136 280811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12448 280911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.015277 281011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_count.Request_Control::0 279 281111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Control::2 286 281211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_count.Writeback_Control::2 8 281311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Request_Control::0 2232 281411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Control::2 2288 281511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Writeback_Control::2 64 281611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.379702 281711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_count.Request_Control::7 274 281811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_count.Request_Control::8 4 281911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 1549 282011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Control::4 23 282111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Request_Control::7 2192 282211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Request_Control::8 32 282311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 111528 282411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Control::4 184 282511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle3.link_utilization 0.003119 282611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle3.msg_count.Request_Control::7 5 282711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle3.msg_count.Request_Control::8 4 282811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle3.msg_count.Response_Data::2 9 282911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle3.msg_count.Response_Control::4 11 283011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle3.msg_count.Writeback_Control::2 16 283111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Request_Control::7 40 283211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Request_Control::8 32 283311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Response_Data::2 648 283411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Response_Control::4 88 283511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Writeback_Control::2 128 283611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.372290 283711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::0 23 283811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::2 1549 283911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Control::0 184 284011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::2 111528 284111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.link_utilization 0.090620 284211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_count.Request_Control::0 1549 284311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_count.Request_Control::7 274 284411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_count.Request_Control::8 4 284511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Control::4 23 284611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_count.Unblock_Control::4 1549 284711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Request_Control::0 12392 284811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Request_Control::7 2192 284911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Request_Control::8 32 285011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Control::4 184 285111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Unblock_Control::4 12392 285211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.link_utilization 0.094646 285311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_count.Request_Control::0 1549 285411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_count.Response_Data::2 19 285511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_count.Response_Control::2 281 285611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_count.Unblock_Control::4 1549 285711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Request_Control::0 12392 285811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Response_Data::2 1368 285911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Response_Control::2 2248 286011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Unblock_Control::4 12392 286111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle0.link_utilization 0.000933 286211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle0.msg_count.Response_Data::3 3 286311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle0.msg_count.Writeback_Control::3 8 286411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle0.msg_bytes.Response_Data::3 216 286511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle0.msg_bytes.Writeback_Control::3 64 286611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle1.link_utilization 0.000933 286711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle1.msg_count.Response_Data::3 3 286811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle1.msg_count.Writeback_Control::3 8 286911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle1.msg_bytes.Response_Data::3 216 287011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle1.msg_bytes.Writeback_Control::3 64 287111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle2.link_utilization 0.007438 287211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle2.msg_count.Control::0 11 287311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle2.msg_count.Data::1 18 287411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle2.msg_count.Request_Control::1 9 287511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle2.msg_count.Response_Data::2 9 287611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle2.msg_count.Writeback_Control::2 16 287711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Control::0 88 287811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Data::1 1296 287911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Request_Control::1 72 288011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Response_Data::2 648 288111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Writeback_Control::2 128 288211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle3.link_utilization 0.001200 288311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle3.msg_count.Response_Data::3 5 288411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle3.msg_bytes.Response_Data::3 360 288511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle4.link_utilization 0.005705 288611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle4.msg_count.Data::0 18 288711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle4.msg_count.Request_Control::0 7 288811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle4.msg_count.Request_Control::7 5 288911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle4.msg_count.Request_Control::8 4 289011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle4.msg_count.Response_Control::4 11 289111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle4.msg_count.Unblock_Control::4 25 289211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Data::0 1296 289311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Request_Control::0 56 289411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Request_Control::7 40 289511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Request_Control::8 32 289611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Response_Control::4 88 289711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Unblock_Control::4 200 289811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle5.link_utilization 0.004852 289911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle5.msg_count.Data::0 16 290011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle5.msg_count.Request_Control::0 9 290111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle5.msg_count.Response_Control::2 22 290211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle5.msg_count.Unblock_Control::4 7 290311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Data::0 1152 290411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Request_Control::0 72 290511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Response_Control::2 176 290611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Unblock_Control::4 56 290711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Load_L1miss 193 0.00% 0.00% 290811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Load_L1hit 16142 0.00% 0.00% 290911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.Ifetch0_L1hit 85994 0.00% 0.00% 291011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.Ifetch0_L1miss 1101 0.00% 0.00% 291111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Store_L1miss 327 0.00% 0.00% 291211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Store_L1hit 10446 0.00% 0.00% 291311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.NB_AckS 1047 0.00% 0.00% 291411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.NB_AckM 329 0.00% 0.00% 291511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.NB_AckE 173 0.00% 0.00% 291611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L1I_Repl 602 0.00% 0.00% 291711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L1D0_Repl 28 0.00% 0.00% 291811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L2_to_L1D0 7 0.00% 0.00% 291911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L2_to_L1I 67 0.00% 0.00% 292011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.PrbInvData 15 0.00% 0.00% 292111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.PrbInvDataDemand 2 0.00% 0.00% 292211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.PrbShrData 4 0.00% 0.00% 292311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.PrbShrDataDemand 2 0.00% 0.00% 292411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.C0_Load_L1miss 186 0.00% 0.00% 292511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00% 292611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00% 292711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.PrbInvDataDemand 1 0.00% 0.00% 292811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.C0_Load_L1hit 643 0.00% 0.00% 292911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.Ifetch0_L1hit 85994 0.00% 0.00% 293011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.Ifetch0_L1miss 67 0.00% 0.00% 293111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.C0_Store_L1hit 4 0.00% 0.00% 293211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.L1I_Repl 602 0.00% 0.00% 293311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.C0_Load_L1miss 2 0.00% 0.00% 293411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.C0_Load_L1hit 2728 0.00% 0.00% 293511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.C0_Store_L1hit 50 0.00% 0.00% 293611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.L1D0_Repl 16 0.00% 0.00% 293711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.PrbInvData 1 0.00% 0.00% 293811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.PrbShrData 1 0.00% 0.00% 293911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.PrbShrDataDemand 1 0.00% 0.00% 294011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.O.PrbInvData 4 0.00% 0.00% 294111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.C0_Load_L1miss 5 0.00% 0.00% 294211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.C0_Load_L1hit 12771 0.00% 0.00% 294311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.C0_Store_L1miss 2 0.00% 0.00% 294411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.C0_Store_L1hit 10392 0.00% 0.00% 294511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.L1D0_Repl 12 0.00% 0.00% 294611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.PrbInvData 10 0.00% 0.00% 294711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.PrbInvDataDemand 1 0.00% 0.00% 294811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.PrbShrData 3 0.00% 0.00% 294911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.PrbShrDataDemand 1 0.00% 0.00% 295011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_M0.NB_AckM 325 0.00% 0.00% 295111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_E0S.NB_AckS 13 0.00% 0.00% 295211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_E0S.NB_AckE 173 0.00% 0.00% 295311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.Si_F0.L2_to_L1I 67 0.00% 0.00% 295411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S_M0.NB_AckM 4 0.00% 0.00% 295511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00% 295611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00% 295711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0_F.L2_to_L1D0 5 0.00% 0.00% 295811308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.RdBlkS 190 0.00% 0.00% 295911308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.RdBlkM 31 0.00% 0.00% 296011308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.RdBlk 56 0.00% 0.00% 296111308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.WriteThrough 1 0.00% 0.00% 296211308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.Atomic 1 0.00% 0.00% 296311308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.RdBlkSP 844 0.00% 0.00% 296411308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.RdBlkMP 298 0.00% 0.00% 296511308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.RdBlkP 137 0.00% 0.00% 296611308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.WriteThroughP 15 0.00% 0.00% 296711308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.AtomicP 1 0.00% 0.00% 296811308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.CPUPrbResp 28 0.00% 0.00% 296911308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.LastCPUPrbResp 8 0.00% 0.00% 297011308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.ProbeAcksComplete 271 0.00% 0.00% 297111308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.L3Hit 11 0.00% 0.00% 297211308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.MemData 1563 0.00% 0.00% 297311308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.CoreUnblock 1556 0.00% 0.00% 297411308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.UnblockWriteThrough 18 0.00% 0.00% 297511308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.RdBlkS 190 0.00% 0.00% 297611308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.RdBlkM 31 0.00% 0.00% 297711308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.RdBlk 56 0.00% 0.00% 297811308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.WriteThrough 1 0.00% 0.00% 297911308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.Atomic 1 0.00% 0.00% 298011308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.RdBlkSP 844 0.00% 0.00% 298111308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.RdBlkMP 298 0.00% 0.00% 298211308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.RdBlkP 137 0.00% 0.00% 298311308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.WriteThroughP 15 0.00% 0.00% 298411308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.AtomicP 1 0.00% 0.00% 298511308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.CPUPrbResp 28 0.00% 0.00% 298611308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BS_M.MemData 1034 0.00% 0.00% 298711308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_M.MemData 347 0.00% 0.00% 298811308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_M.L3Hit 11 0.00% 0.00% 298911308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_M.MemData 180 0.00% 0.00% 299011308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 190 0.00% 0.00% 299111308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_PM.LastCPUPrbResp 4 0.00% 0.00% 299211308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 29 0.00% 0.00% 299311308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_PM.LastCPUPrbResp 2 0.00% 0.00% 299411308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_PM.ProbeAcksComplete 52 0.00% 0.00% 299511308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_PM.MemData 2 0.00% 0.00% 299611308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_Pm.LastCPUPrbResp 2 0.00% 0.00% 299711308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B.CoreUnblock 1556 0.00% 0.00% 299811308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B.UnblockWriteThrough 18 0.00% 0.00% 299911308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.CPURead | 1220 99.43% 99.43% | 7 0.57% 100.00% 300011308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.CPURead::total 1227 300111308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.CPUWrite | 331 89.95% 89.95% | 37 10.05% 100.00% 300211308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.CPUWrite::total 368 300311308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.PrivateNotify | 272 98.91% 98.91% | 3 1.09% 100.00% 300411308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.PrivateNotify::total 275 300511308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.SharedNotify | 2 50.00% 50.00% | 2 50.00% 100.00% 300611308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.SharedNotify::total 4 300711308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.InvRegion | 2 50.00% 50.00% | 2 50.00% 100.00% 300811308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.InvRegion::total 4 300911308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.DowngradeRegion | 2 50.00% 50.00% | 2 50.00% 100.00% 301011308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.DowngradeRegion::total 4 301111308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.InvAck | 23 67.65% 67.65% | 11 32.35% 100.00% 301211308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.InvAck::total 34 301311308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.DoneAck | 1572 96.26% 96.26% | 61 3.74% 100.00% 301411308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.DoneAck::total 1633 301511308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.AllOutstanding | 6 54.55% 54.55% | 5 45.45% 100.00% 301611308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.AllOutstanding::total 11 301711308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.Evict | 64 66.67% 66.67% | 32 33.33% 100.00% 301811308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.Evict::total 96 301911308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.LastAck_PrbResp | 4 50.00% 50.00% | 4 50.00% 100.00% 302011308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.LastAck_PrbResp::total 8 302111308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.StallAccess | 0 0.00% 0.00% | 16 100.00% 100.00% 302211308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.StallAccess::total 16 302311308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.NP.CPURead | 243 98.78% 98.78% | 3 1.22% 100.00% 302411308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.NP.CPURead::total 246 302511308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.NP.CPUWrite | 29 96.67% 96.67% | 1 3.33% 100.00% 302611308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.NP.CPUWrite::total 30 302711308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P.CPURead | 965 99.59% 99.59% | 4 0.41% 100.00% 302811308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P.CPURead::total 969 302911308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P.CPUWrite | 298 94.90% 94.90% | 16 5.10% 100.00% 303011308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P.CPUWrite::total 314 303111308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P.InvRegion | 1 100.00% 100.00% | 0 0.00% 100.00% 303211308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P.InvRegion::total 1 303311308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P.DowngradeRegion | 2 50.00% 50.00% | 2 50.00% 100.00% 303411308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P.DowngradeRegion::total 4 303511308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P.DoneAck | 1535 98.52% 98.52% | 23 1.48% 100.00% 303611308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P.DoneAck::total 1558 303711308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P.StallAccess | 0 0.00% 0.00% | 15 100.00% 100.00% 303811308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P.StallAccess::total 15 303911308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S.CPURead | 12 100.00% 100.00% | 0 0.00% 100.00% 304011308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S.CPURead::total 12 304111308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S.CPUWrite | 2 66.67% 66.67% | 1 33.33% 100.00% 304211308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S.CPUWrite::total 3 304311308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S.InvRegion | 1 33.33% 33.33% | 2 66.67% 100.00% 304411308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S.InvRegion::total 3 304511308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S.DoneAck | 14 87.50% 87.50% | 2 12.50% 100.00% 304611308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S.DoneAck::total 16 304711308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.NP_PS.PrivateNotify | 270 99.26% 99.26% | 2 0.74% 100.00% 304811308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.NP_PS.PrivateNotify::total 272 304911308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.NP_PS.SharedNotify | 2 50.00% 50.00% | 2 50.00% 100.00% 305011308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.NP_PS.SharedNotify::total 4 305111308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.NP_PS.DoneAck | 8 25.81% 25.81% | 23 74.19% 100.00% 305211308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.NP_PS.DoneAck::total 31 305311308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.NP_PS.StallAccess | 0 0.00% 0.00% | 1 100.00% 100.00% 305411308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.NP_PS.StallAccess::total 1 305511308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S_P.CPUWrite | 0 0.00% 0.00% | 18 100.00% 100.00% 305611308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S_P.CPUWrite::total 18 305711308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S_P.PrivateNotify | 2 66.67% 66.67% | 1 33.33% 100.00% 305811308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S_P.PrivateNotify::total 3 305911308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S_P.DoneAck | 15 53.57% 53.57% | 13 46.43% 100.00% 306011308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S_P.DoneAck::total 28 306111308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_NP.InvAck | 17 60.71% 60.71% | 11 39.29% 100.00% 306211308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_NP.InvAck::total 28 306311308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_NP.Evict | 32 50.00% 50.00% | 32 50.00% 100.00% 306411308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_NP.Evict::total 64 306511308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_NP.LastAck_PrbResp | 2 50.00% 50.00% | 2 50.00% 100.00% 306611308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_NP.LastAck_PrbResp::total 4 306711308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_S.InvAck | 6 100.00% 100.00% | 0 0.00% 100.00% 306811308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_S.InvAck::total 6 306911308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_S.Evict | 32 100.00% 100.00% | 0 0.00% 100.00% 307011308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_S.Evict::total 32 307111308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_S.LastAck_PrbResp | 2 50.00% 50.00% | 2 50.00% 100.00% 307211308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_S.LastAck_PrbResp::total 4 307311308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_NP_O.AllOutstanding | 2 50.00% 50.00% | 2 50.00% 100.00% 307411308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_NP_O.AllOutstanding::total 4 307511308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_S_O.AllOutstanding | 2 50.00% 50.00% | 2 50.00% 100.00% 307611308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.P_S_O.AllOutstanding::total 4 307711308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S_O.AllOutstanding | 2 66.67% 66.67% | 1 33.33% 100.00% 307811308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.S_O.AllOutstanding::total 3 307911308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.SS_P.CPUWrite | 2 66.67% 66.67% | 1 33.33% 100.00% 308011308Santhony.gutierrez@amd.comsystem.ruby.RegionBuffer_Controller.SS_P.CPUWrite::total 3 308111308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.SendInv 1 0.00% 0.00% 308211308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.SendUpgrade 3 0.00% 0.00% 308311308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.SendDowngrade 4 0.00% 0.00% 308411308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.PrivateRequest 271 0.00% 0.00% 308511308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.InvAckCore 4 0.00% 0.00% 308611308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.InvAckCoreNoShare 4 0.00% 0.00% 308711308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.CPUPrivateAck 278 0.00% 0.00% 308811308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.LastAck 8 0.00% 0.00% 308911308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.DirReadyAck 8 0.00% 0.00% 309011308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.TriggerInv 4 0.00% 0.00% 309111308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.TriggerDowngrade 4 0.00% 0.00% 309211308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.NP.PrivateRequest 271 0.00% 0.00% 309311308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.P.SendInv 1 0.00% 0.00% 309411308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.P.SendDowngrade 4 0.00% 0.00% 309511308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.S.SendUpgrade 3 0.00% 0.00% 309611308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.NP_P.CPUPrivateAck 270 0.00% 0.00% 309711308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.P_P.CPUPrivateAck 1 0.00% 0.00% 309811308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.P_S.CPUPrivateAck 4 0.00% 0.00% 309911308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.S_P.CPUPrivateAck 3 0.00% 0.00% 310011308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.P_AS.InvAckCore 4 0.00% 0.00% 310111308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.P_AS.LastAck 4 0.00% 0.00% 310211308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.S_AP.InvAckCoreNoShare 3 0.00% 0.00% 310311308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.S_AP.LastAck 3 0.00% 0.00% 310411308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.P_AP.InvAckCoreNoShare 1 0.00% 0.00% 310511308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.P_AP.LastAck 1 0.00% 0.00% 310611308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.P_AP_W.DirReadyAck 1 0.00% 0.00% 310711308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.P_AP_W.TriggerInv 1 0.00% 0.00% 310811308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.P_AS_W.DirReadyAck 4 0.00% 0.00% 310911308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.P_AS_W.TriggerDowngrade 4 0.00% 0.00% 311011308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.S_AP_W.DirReadyAck 3 0.00% 0.00% 311111308Santhony.gutierrez@amd.comsystem.ruby.RegionDir_Controller.S_AP_W.TriggerInv 3 0.00% 0.00% 311211308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist::bucket_size 64 311311308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist::max_bucket 639 311411308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist::samples 16335 311511308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist::mean 2.844751 311611308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist::gmean 1.060634 311711308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist::stdev 17.742972 311811308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist | 16149 98.86% 98.86% | 11 0.07% 98.93% | 119 0.73% 99.66% | 52 0.32% 99.98% | 2 0.01% 99.99% | 1 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 311911308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist::total 16335 312011308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist::bucket_size 64 312111308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist::max_bucket 639 312211308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist::samples 186 312311308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist::mean 162.333333 312411308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist::gmean 157.431876 312511308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist::stdev 43.755298 312611308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 11 5.91% 5.91% | 119 63.98% 69.89% | 52 27.96% 97.85% | 2 1.08% 98.92% | 1 0.54% 99.46% | 1 0.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 312711308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist::total 186 312811308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist::bucket_size 2 312911308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist::max_bucket 19 313011308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist::samples 16149 313111308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist::mean 1.007802 313211308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist::gmean 1.001277 313311308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist::stdev 0.374686 313411308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist | 16142 99.96% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 7 0.04% 100.00% 313511308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist::total 16149 313611308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist::bucket_size 64 313711308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist::max_bucket 639 313811308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist::samples 10412 313911308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist::mean 5.551287 314011308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist::gmean 1.167783 314111308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist::stdev 26.172531 314211308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist | 10087 96.88% 96.88% | 0 0.00% 96.88% | 289 2.78% 99.65% | 29 0.28% 99.93% | 4 0.04% 99.97% | 2 0.02% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 314311308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist::total 10412 314411308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist::bucket_size 64 314511308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist::max_bucket 639 314611308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist::samples 325 314711308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist::mean 146.809231 314811308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist::gmean 143.903653 314911308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist::stdev 36.751508 315011308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 289 88.92% 88.92% | 29 8.92% 97.85% | 4 1.23% 99.08% | 2 0.62% 99.69% | 0 0.00% 99.69% | 1 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 315111308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist::total 325 315211308Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist::bucket_size 1 315311308Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist::max_bucket 9 315411308Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist::samples 10087 315511308Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist::mean 1 315611308Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist::gmean 1 315711308Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 10087 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 315811308Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist::total 10087 315911308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist::bucket_size 64 316011308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist::max_bucket 639 316111308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist::samples 87095 316211308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist::mean 2.818945 316311308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist::gmean 1.063630 316411308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist::stdev 17.067789 316511308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist | 86061 98.81% 98.81% | 0 0.00% 98.81% | 826 0.95% 99.76% | 185 0.21% 99.97% | 8 0.01% 99.98% | 9 0.01% 99.99% | 6 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 316611308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist::total 87095 316711308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist::bucket_size 64 316811308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist::max_bucket 639 316911308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist::samples 1034 317011308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist::mean 153.045455 317111308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist::gmean 149.192268 317211308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist::stdev 40.969954 317311308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 826 79.88% 79.88% | 185 17.89% 97.78% | 8 0.77% 98.55% | 9 0.87% 99.42% | 6 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 317411308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist::total 1034 317511308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist::bucket_size 2 317611308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist::max_bucket 19 317711308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist::samples 86061 317811308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist::mean 1.014013 317911308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist::gmean 1.002295 318011308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist::stdev 0.502042 318111308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist | 85994 99.92% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 67 0.08% 100.00% 318211308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist::total 86061 318311308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist::bucket_size 32 318411308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist::max_bucket 319 318511308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist::samples 341 318611308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist::mean 2.671554 318711308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist::gmean 1.059947 318811308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist::stdev 15.416875 318911308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist | 337 98.83% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 3 0.88% 99.71% | 1 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 319011308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist::total 341 319111308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist::bucket_size 32 319211308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist::max_bucket 319 319311308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist::samples 4 319411308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist::mean 143.500000 319511308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist::gmean 143.041358 319611308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist::stdev 13.403980 319711308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 75.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 319811308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist::total 4 319911308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist::bucket_size 1 320011308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist::max_bucket 9 320111308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist::samples 337 320211308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist::mean 1 320311308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist::gmean 1 320411308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 320511308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist::total 337 320611308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist::bucket_size 1 320711308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist::max_bucket 9 320811308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist::samples 10 320911308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist::mean 1 321011308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist::gmean 1 321111308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 321211308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist::total 10 321311308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 1 321411308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 9 321511308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::samples 10 321611308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::mean 1 321711308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::gmean 1 321811308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 321911308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::total 10 322011308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 322111308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 322211308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist::samples 10 322311308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist::mean 1 322411308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist::gmean 1 322511308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 322611308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist::total 10 322711308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist::bucket_size 1 322811308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist::max_bucket 9 322911308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist::samples 10 323011308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist::mean 1 323111308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist::gmean 1 323211308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 323311308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist::total 10 323411308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist::bucket_size 1 323511308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist::max_bucket 9 323611308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist::samples 112580 323711308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist::mean 1 323811308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist::gmean 1 323911308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 112580 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 324011308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist::total 112580 324111308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist::bucket_size 2 324211308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist::max_bucket 19 324311308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist::samples 74 324411308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist::mean 19 324511308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist::gmean 19.000000 324611308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 74 100.00% 100.00% 324711308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist::total 74 324811308Santhony.gutierrez@amd.comsystem.ruby.L3Cache.hit_mach_latency_hist::bucket_size 16 324911308Santhony.gutierrez@amd.comsystem.ruby.L3Cache.hit_mach_latency_hist::max_bucket 159 325011308Santhony.gutierrez@amd.comsystem.ruby.L3Cache.hit_mach_latency_hist::samples 11 325111308Santhony.gutierrez@amd.comsystem.ruby.L3Cache.hit_mach_latency_hist::mean 107 325211308Santhony.gutierrez@amd.comsystem.ruby.L3Cache.hit_mach_latency_hist::gmean 107.000000 325311308Santhony.gutierrez@amd.comsystem.ruby.L3Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 325411308Santhony.gutierrez@amd.comsystem.ruby.L3Cache.hit_mach_latency_hist::total 11 325511308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist::bucket_size 64 325611308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist::max_bucket 639 325711308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist::samples 1538 325811308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist::mean 153.155397 325911308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist::gmean 149.362802 326011308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist::stdev 40.587599 326111308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1238 80.49% 80.49% | 266 17.30% 97.79% | 14 0.91% 98.70% | 12 0.78% 99.48% | 7 0.46% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 326211308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist::total 1538 326311308Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 1 326411308Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 9 326511308Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 16142 326611308Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1 326711308Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1 326811308Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 16142 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 326911308Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 16142 327011308Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist::bucket_size 2 327111308Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist::max_bucket 19 327211308Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist::samples 7 327311308Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist::mean 19 327411308Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist::gmean 19.000000 327511308Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% 327611308Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist::total 7 327711308Santhony.gutierrez@amd.comsystem.ruby.LD.L3Cache.hit_type_mach_latency_hist::bucket_size 16 327811308Santhony.gutierrez@amd.comsystem.ruby.LD.L3Cache.hit_type_mach_latency_hist::max_bucket 159 327911308Santhony.gutierrez@amd.comsystem.ruby.LD.L3Cache.hit_type_mach_latency_hist::samples 11 328011308Santhony.gutierrez@amd.comsystem.ruby.LD.L3Cache.hit_type_mach_latency_hist::mean 107 328111308Santhony.gutierrez@amd.comsystem.ruby.LD.L3Cache.hit_type_mach_latency_hist::gmean 107.000000 328211308Santhony.gutierrez@amd.comsystem.ruby.LD.L3Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 328311308Santhony.gutierrez@amd.comsystem.ruby.LD.L3Cache.hit_type_mach_latency_hist::total 11 328411308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist::bucket_size 64 328511308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist::max_bucket 639 328611308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist::samples 175 328711308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist::mean 165.811429 328811308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist::gmean 161.300002 328911308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist::stdev 42.776536 329011308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 119 68.00% 68.00% | 52 29.71% 97.71% | 2 1.14% 98.86% | 1 0.57% 99.43% | 1 0.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 329111308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist::total 175 329211308Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 1 329311308Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 9 329411308Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 10087 329511308Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1 329611308Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1 329711308Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10087 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 329811308Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 10087 329911308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist::bucket_size 64 330011308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist::max_bucket 639 330111308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist::samples 325 330211308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist::mean 146.809231 330311308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist::gmean 143.903653 330411308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist::stdev 36.751508 330511308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 289 88.92% 88.92% | 29 8.92% 97.85% | 4 1.23% 99.08% | 2 0.62% 99.69% | 0 0.00% 99.69% | 1 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 330611308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist::total 325 330711308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::bucket_size 1 330811308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::max_bucket 9 330911308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::samples 85994 331011308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::mean 1 331111308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::gmean 1 331211308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 85994 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 331311308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::total 85994 331411308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::bucket_size 2 331511308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::max_bucket 19 331611308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::samples 67 331711308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::mean 19 331811308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::gmean 19.000000 331911308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 67 100.00% 100.00% 332011308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::total 67 332111308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist::bucket_size 64 332211308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist::max_bucket 639 332311308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist::samples 1034 332411308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist::mean 153.045455 332511308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist::gmean 149.192268 332611308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist::stdev 40.969954 332711308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 826 79.88% 79.88% | 185 17.89% 97.78% | 8 0.77% 98.55% | 9 0.87% 99.42% | 6 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 332811308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist::total 1034 332911308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1 333011308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9 333111308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 337 333211308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 1 333311308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 1 333411308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 333511308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::total 337 333611308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::bucket_size 32 333711308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::max_bucket 319 333811308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::samples 4 333911308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::mean 143.500000 334011308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::gmean 143.041358 334111308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::stdev 13.403980 334211308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 75.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 334311308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::total 4 334411308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1 334511308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9 334611308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 10 334711308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 1 334811308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 1 334911308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 335011308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::total 10 335111308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::bucket_size 1 335211308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::max_bucket 9 335311308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::samples 10 335411308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::mean 1 335511308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::gmean 1 335611308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 335711308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::total 10 335811308Santhony.gutierrez@amd.comsystem.ruby.SQC_Controller.Fetch 86 0.00% 0.00% 335911308Santhony.gutierrez@amd.comsystem.ruby.SQC_Controller.Data 5 0.00% 0.00% 336011308Santhony.gutierrez@amd.comsystem.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00% 336111308Santhony.gutierrez@amd.comsystem.ruby.SQC_Controller.I.Data 5 0.00% 0.00% 336211308Santhony.gutierrez@amd.comsystem.ruby.SQC_Controller.V.Fetch 81 0.00% 0.00% 336311308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.RdBlk 9 0.00% 0.00% 336411308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.WrVicBlk 16 0.00% 0.00% 336511308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.Atomic 2 0.00% 0.00% 336611308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.AtomicDone 1 0.00% 0.00% 336711308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.Data 9 0.00% 0.00% 336811308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.PrbInv 11 0.00% 0.00% 336911308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.WBAck 16 0.00% 0.00% 337011308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.V.PrbInv 1 0.00% 0.00% 337111308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.I.RdBlk 7 0.00% 0.00% 337211308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.I.WrVicBlk 16 0.00% 0.00% 337311308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.I.Atomic 1 0.00% 0.00% 337411308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.I.PrbInv 10 0.00% 0.00% 337511308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.I.WBAck 16 0.00% 0.00% 337611308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.IV.RdBlk 2 0.00% 0.00% 337711308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.IV.Data 7 0.00% 0.00% 337811308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.A.Atomic 1 0.00% 0.00% 337911308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.A.AtomicDone 1 0.00% 0.00% 338011308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.A.Data 2 0.00% 0.00% 338111308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Load | 5 50.00% 50.00% | 5 50.00% 100.00% 338211308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Load::total 10 338311308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00% 338411308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.StoreThrough::total 16 338511308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00% 338611308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Atomic::total 2 338711308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Flush | 768 50.00% 50.00% | 768 50.00% 100.00% 338811308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Flush::total 1536 338911308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Evict | 512 50.00% 50.00% | 512 50.00% 100.00% 339011308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Evict::total 1024 339111308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_Ack | 3 50.00% 50.00% | 3 50.00% 100.00% 339211308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_Ack::total 6 339311308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00% 339411308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_AckWB::total 16 339511308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00% 339611308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Load::total 4 339711308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00% 339811308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.StoreThrough::total 16 339911308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00% 340011308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Atomic::total 2 340111308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Flush | 766 50.00% 50.00% | 766 50.00% 100.00% 340211308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Flush::total 1532 340311308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Evict | 510 50.00% 50.00% | 510 50.00% 100.00% 340411308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Evict::total 1020 340511308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.TCC_Ack | 2 50.00% 50.00% | 2 50.00% 100.00% 340611308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.TCC_Ack::total 4 340711308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00% 340811308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.TCC_AckWB::total 16 340911308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.V.Load | 3 50.00% 50.00% | 3 50.00% 100.00% 341011308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.V.Load::total 6 341111308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.V.Flush | 2 50.00% 50.00% | 2 50.00% 100.00% 341211308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.V.Flush::total 4 341311308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.V.Evict | 2 50.00% 50.00% | 2 50.00% 100.00% 341411308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.V.Evict::total 4 341511308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.A.TCC_Ack | 1 50.00% 50.00% | 1 50.00% 100.00% 341611308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.A.TCC_Ack::total 2 341711308Santhony.gutierrez@amd.com 341811308Santhony.gutierrez@amd.com---------- End Simulation Statistics ---------- 3419