stats.txt revision 11731
111308Santhony.gutierrez@amd.com 211308Santhony.gutierrez@amd.com---------- Begin Simulation Statistics ---------- 311731Sjason@lowepower.comsim_seconds 0.000667 # Number of seconds simulated 411731Sjason@lowepower.comsim_ticks 667407500 # Number of ticks simulated 511731Sjason@lowepower.comfinal_tick 667407500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611308Santhony.gutierrez@amd.comsim_freq 1000000000000 # Frequency of simulated ticks 711731Sjason@lowepower.comhost_inst_rate 72185 # Simulator instruction rate (inst/s) 811731Sjason@lowepower.comhost_op_rate 148440 # Simulator op (including micro ops) rate (op/s) 911731Sjason@lowepower.comhost_tick_rate 719412350 # Simulator tick rate (ticks/s) 1011731Sjason@lowepower.comhost_mem_usage 1308600 # Number of bytes of host memory used 1111731Sjason@lowepower.comhost_seconds 0.93 # Real time elapsed on the host 1211308Santhony.gutierrez@amd.comsim_insts 66963 # Number of instructions simulated 1311308Santhony.gutierrez@amd.comsim_ops 137705 # Number of ops (including micro ops) simulated 1411308Santhony.gutierrez@amd.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511308Santhony.gutierrez@amd.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611731Sjason@lowepower.comsystem.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 1711731Sjason@lowepower.comsystem.mem_ctrls.bytes_read::dir_cntrl0 99136 # Number of bytes read from this memory 1811731Sjason@lowepower.comsystem.mem_ctrls.bytes_read::total 99136 # Number of bytes read from this memory 1911731Sjason@lowepower.comsystem.mem_ctrls.num_reads::dir_cntrl0 1549 # Number of read requests responded to by this memory 2011731Sjason@lowepower.comsystem.mem_ctrls.num_reads::total 1549 # Number of read requests responded to by this memory 2111731Sjason@lowepower.comsystem.mem_ctrls.bw_read::dir_cntrl0 148538936 # Total read bandwidth from this memory (bytes/s) 2211731Sjason@lowepower.comsystem.mem_ctrls.bw_read::total 148538936 # Total read bandwidth from this memory (bytes/s) 2311731Sjason@lowepower.comsystem.mem_ctrls.bw_total::dir_cntrl0 148538936 # Total bandwidth to/from this memory (bytes/s) 2411731Sjason@lowepower.comsystem.mem_ctrls.bw_total::total 148538936 # Total bandwidth to/from this memory (bytes/s) 2511731Sjason@lowepower.comsystem.mem_ctrls.readReqs 1549 # Number of read requests accepted 2611308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeReqs 0 # Number of write requests accepted 2711731Sjason@lowepower.comsystem.mem_ctrls.readBursts 1549 # Number of DRAM read bursts, including those serviced by the write queue 2811308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 2911731Sjason@lowepower.comsystem.mem_ctrls.bytesReadDRAM 99136 # Total number of bytes read from DRAM 3011308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue 3111308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM 3211731Sjason@lowepower.comsystem.mem_ctrls.bytesReadSys 99136 # Total read bytes from the system interface side 3311308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side 3411308Santhony.gutierrez@amd.comsystem.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 3511308Santhony.gutierrez@amd.comsystem.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 3611308Santhony.gutierrez@amd.comsystem.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 3711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts 3811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts 3911731Sjason@lowepower.comsystem.mem_ctrls.perBankRdBursts::2 91 # Per bank write bursts 4011308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts 4111308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts 4211308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts 4311308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts 4411308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts 4511308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts 4611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts 4711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::10 174 # Per bank write bursts 4811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::11 90 # Per bank write bursts 4911308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::12 222 # Per bank write bursts 5011308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::13 125 # Per bank write bursts 5111308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::14 51 # Per bank write bursts 5211308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::15 94 # Per bank write bursts 5311308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts 5411308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts 5511308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts 5611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts 5711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts 5811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts 5911308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts 6011308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts 6111308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts 6211308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts 6311308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts 6411308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts 6511308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts 6611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts 6711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts 6811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts 6911308Santhony.gutierrez@amd.comsystem.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 7011308Santhony.gutierrez@amd.comsystem.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 7111731Sjason@lowepower.comsystem.mem_ctrls.totGap 667174000 # Total gap between requests 7211308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 7311308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 7411308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 7511308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 7611308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 7711308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 7811731Sjason@lowepower.comsystem.mem_ctrls.readPktSize::6 1549 # Read request sizes (log2) 7911308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 8011308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 8111308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 8211308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 8311308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 8411308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 8511308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) 8611731Sjason@lowepower.comsystem.mem_ctrls.rdQLenPdf::0 1540 # What read queue length does an incoming req see 8711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::1 2 # What read queue length does an incoming req see 8811308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see 8911308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see 9011731Sjason@lowepower.comsystem.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see 9111680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see 9211731Sjason@lowepower.comsystem.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see 9311680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see 9411308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 9511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 9611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 9711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 9811308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 9911308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 10011308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 10111308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 10211308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 10311308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 10411308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 10511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 10611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 10711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 10811308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 10911308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 11011308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 11111308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 11211308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 11311308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 11411308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 11511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 11611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 11711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 11811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see 11911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see 12011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see 12111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see 12211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see 12311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see 12411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see 12511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see 12611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see 12711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see 12811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see 12911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see 13011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see 13111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see 13211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see 13311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see 13411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see 13511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see 13611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see 13711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see 13811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see 13911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see 14011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see 14111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see 14211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see 14311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see 14411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see 14511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see 14611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see 14711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see 14811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see 14911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see 15011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see 15111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 15211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 15311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 15411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 15511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 15611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 15711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 15811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 15911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 16011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 16111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 16211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 16311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 16411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 16511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 16611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 16711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 16811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 16911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 17011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 17111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 17211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 17311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 17411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 17511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 17611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 17711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 17811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 17911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 18011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 18111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 18211680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::samples 484 # Bytes accessed per row activation 18311731Sjason@lowepower.comsystem.mem_ctrls.bytesPerActivate::mean 203.371901 # Bytes accessed per row activation 18411731Sjason@lowepower.comsystem.mem_ctrls.bytesPerActivate::gmean 144.930715 # Bytes accessed per row activation 18511731Sjason@lowepower.comsystem.mem_ctrls.bytesPerActivate::stdev 194.713066 # Bytes accessed per row activation 18611680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::0-127 177 36.57% 36.57% # Bytes accessed per row activation 18711731Sjason@lowepower.comsystem.mem_ctrls.bytesPerActivate::128-255 168 34.71% 71.28% # Bytes accessed per row activation 18811731Sjason@lowepower.comsystem.mem_ctrls.bytesPerActivate::256-383 63 13.02% 84.30% # Bytes accessed per row activation 18911680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::384-511 29 5.99% 90.29% # Bytes accessed per row activation 19011731Sjason@lowepower.comsystem.mem_ctrls.bytesPerActivate::512-639 19 3.93% 94.21% # Bytes accessed per row activation 19111731Sjason@lowepower.comsystem.mem_ctrls.bytesPerActivate::640-767 11 2.27% 96.49% # Bytes accessed per row activation 19211680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::768-895 10 2.07% 98.55% # Bytes accessed per row activation 19311308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::896-1023 2 0.41% 98.97% # Bytes accessed per row activation 19411308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::1024-1151 5 1.03% 100.00% # Bytes accessed per row activation 19511680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::total 484 # Bytes accessed per row activation 19611731Sjason@lowepower.comsystem.mem_ctrls.totQLat 31625750 # Total ticks spent queuing 19711731Sjason@lowepower.comsystem.mem_ctrls.totMemAccLat 60669500 # Total ticks spent from burst creation until serviced by the DRAM 19811731Sjason@lowepower.comsystem.mem_ctrls.totBusLat 7745000 # Total ticks spent in databus transfers 19911731Sjason@lowepower.comsystem.mem_ctrls.avgQLat 20416.88 # Average queueing delay per DRAM burst 20011308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst 20111731Sjason@lowepower.comsystem.mem_ctrls.avgMemAccLat 39166.88 # Average memory access latency per DRAM burst 20211731Sjason@lowepower.comsystem.mem_ctrls.avgRdBW 148.54 # Average DRAM read bandwidth in MiByte/s 20311308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 20411731Sjason@lowepower.comsystem.mem_ctrls.avgRdBWSys 148.54 # Average system read bandwidth in MiByte/s 20511308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 20611308Santhony.gutierrez@amd.comsystem.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 20711680SCurtis.Dunham@arm.comsystem.mem_ctrls.busUtil 1.16 # Data bus utilization in percentage 20811680SCurtis.Dunham@arm.comsystem.mem_ctrls.busUtilRead 1.16 # Data bus utilization in percentage for reads 20911308Santhony.gutierrez@amd.comsystem.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21011308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 21111308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing 21211731Sjason@lowepower.comsystem.mem_ctrls.readRowHits 1060 # Number of row buffer hits during reads 21311308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes 21411731Sjason@lowepower.comsystem.mem_ctrls.readRowHitRate 68.43 # Row buffer hit rate for reads 21511308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes 21611731Sjason@lowepower.comsystem.mem_ctrls.avgGap 430712.72 # Average gap between requests 21711731Sjason@lowepower.comsystem.mem_ctrls.pageHitRate 68.43 # Row buffer hit rate, read and write combined 21811680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.actEnergy 1320900 # Energy for activate commands per rank (pJ) 21911680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.preEnergy 694485 # Energy for precharge commands per rank (pJ) 22011731Sjason@lowepower.comsystem.mem_ctrls_0.readEnergy 4876620 # Energy for read commands per rank (pJ) 22111308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22211680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.refreshEnergy 51629760.000000 # Energy for refresh commands per rank (pJ) 22311731Sjason@lowepower.comsystem.mem_ctrls_0.actBackEnergy 18588840 # Energy for active background per rank (pJ) 22411680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.preBackEnergy 1670400 # Energy for precharge background per rank (pJ) 22511731Sjason@lowepower.comsystem.mem_ctrls_0.actPowerDownEnergy 210561990 # Energy for active power-down per rank (pJ) 22611731Sjason@lowepower.comsystem.mem_ctrls_0.prePowerDownEnergy 42231360 # Energy for precharge power-down per rank (pJ) 22711731Sjason@lowepower.comsystem.mem_ctrls_0.selfRefreshEnergy 15446940 # Energy for self refresh per rank (pJ) 22811731Sjason@lowepower.comsystem.mem_ctrls_0.totalEnergy 347021295 # Total energy per rank (pJ) 22911731Sjason@lowepower.comsystem.mem_ctrls_0.averagePower 519.954143 # Core power per rank (mW) 23011731Sjason@lowepower.comsystem.mem_ctrls_0.totalIdleTime 622134250 # Total Idle time Per DRAM Rank 23111680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::IDLE 2030000 # Time in different power states 23211680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::REF 21876000 # Time in different power states 23311731Sjason@lowepower.comsystem.mem_ctrls_0.memoryStateTime::SREF 50557000 # Time in different power states 23411731Sjason@lowepower.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN 109975750 # Time in different power states 23511731Sjason@lowepower.comsystem.mem_ctrls_0.memoryStateTime::ACT 21192250 # Time in different power states 23611731Sjason@lowepower.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN 461776500 # Time in different power states 23711680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.actEnergy 2170560 # Energy for activate commands per rank (pJ) 23811680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.preEnergy 1142295 # Energy for precharge commands per rank (pJ) 23911680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.readEnergy 6183240 # Energy for read commands per rank (pJ) 24011308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24111680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.refreshEnergy 52244400.000000 # Energy for refresh commands per rank (pJ) 24211731Sjason@lowepower.comsystem.mem_ctrls_1.actBackEnergy 21584190 # Energy for active background per rank (pJ) 24311680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.preBackEnergy 1299360 # Energy for precharge background per rank (pJ) 24411731Sjason@lowepower.comsystem.mem_ctrls_1.actPowerDownEnergy 243510840 # Energy for active power-down per rank (pJ) 24511731Sjason@lowepower.comsystem.mem_ctrls_1.prePowerDownEnergy 28002720 # Energy for precharge power-down per rank (pJ) 24611731Sjason@lowepower.comsystem.mem_ctrls_1.selfRefreshEnergy 2892540 # Energy for self refresh per rank (pJ) 24711731Sjason@lowepower.comsystem.mem_ctrls_1.totalEnergy 359030145 # Total energy per rank (pJ) 24811731Sjason@lowepower.comsystem.mem_ctrls_1.averagePower 537.947423 # Core power per rank (mW) 24911731Sjason@lowepower.comsystem.mem_ctrls_1.totalIdleTime 616133750 # Total Idle time Per DRAM Rank 25011680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::IDLE 980000 # Time in different power states 25111680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::REF 22106000 # Time in different power states 25211731Sjason@lowepower.comsystem.mem_ctrls_1.memoryStateTime::SREF 9751250 # Time in different power states 25311731Sjason@lowepower.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN 72913500 # Time in different power states 25411731Sjason@lowepower.comsystem.mem_ctrls_1.memoryStateTime::ACT 27618000 # Time in different power states 25511731Sjason@lowepower.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN 534038750 # Time in different power states 25611308Santhony.gutierrez@amd.comsystem.ruby.clk_domain.clock 500 # Clock period in ticks 25711731Sjason@lowepower.comsystem.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 25811308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory 25911308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory 26011731Sjason@lowepower.comsystem.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 2856 # Number of bytes read from this memory 26111731Sjason@lowepower.comsystem.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 2856 # Number of bytes read from this memory 26211731Sjason@lowepower.comsystem.ruby.phys_mem.bytes_read::total 822304 # Number of bytes read from this memory 26311308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory 26411731Sjason@lowepower.comsystem.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 1576 # Number of instructions bytes read from this memory 26511731Sjason@lowepower.comsystem.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 1576 # Number of instructions bytes read from this memory 26611731Sjason@lowepower.comsystem.ruby.phys_mem.bytes_inst_read::total 699912 # Number of instructions bytes read from this memory 26711308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory 26811308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory 26911308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory 27011308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory 27111308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory 27211308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory 27311731Sjason@lowepower.comsystem.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 547 # Number of read requests responded to by this memory 27411731Sjason@lowepower.comsystem.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 547 # Number of read requests responded to by this memory 27511731Sjason@lowepower.comsystem.ruby.phys_mem.num_reads::total 104875 # Number of read requests responded to by this memory 27611308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory 27711308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory 27811308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory 27911308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory 28011731Sjason@lowepower.comsystem.ruby.phys_mem.bw_read::cpu0.inst 1043979877 # Total read bandwidth from this memory (bytes/s) 28111731Sjason@lowepower.comsystem.ruby.phys_mem.bw_read::cpu0.data 179548477 # Total read bandwidth from this memory (bytes/s) 28211731Sjason@lowepower.comsystem.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4279245 # Total read bandwidth from this memory (bytes/s) 28311731Sjason@lowepower.comsystem.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4279245 # Total read bandwidth from this memory (bytes/s) 28411731Sjason@lowepower.comsystem.ruby.phys_mem.bw_read::total 1232086843 # Total read bandwidth from this memory (bytes/s) 28511731Sjason@lowepower.comsystem.ruby.phys_mem.bw_inst_read::cpu0.inst 1043979877 # Instruction read bandwidth from this memory (bytes/s) 28611731Sjason@lowepower.comsystem.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 2361376 # Instruction read bandwidth from this memory (bytes/s) 28711731Sjason@lowepower.comsystem.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 2361376 # Instruction read bandwidth from this memory (bytes/s) 28811731Sjason@lowepower.comsystem.ruby.phys_mem.bw_inst_read::total 1048702629 # Instruction read bandwidth from this memory (bytes/s) 28911731Sjason@lowepower.comsystem.ruby.phys_mem.bw_write::cpu0.data 109029341 # Write bandwidth from this memory (bytes/s) 29011731Sjason@lowepower.comsystem.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 383574 # Write bandwidth from this memory (bytes/s) 29111731Sjason@lowepower.comsystem.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 383574 # Write bandwidth from this memory (bytes/s) 29211731Sjason@lowepower.comsystem.ruby.phys_mem.bw_write::total 109796489 # Write bandwidth from this memory (bytes/s) 29311731Sjason@lowepower.comsystem.ruby.phys_mem.bw_total::cpu0.inst 1043979877 # Total bandwidth to/from this memory (bytes/s) 29411731Sjason@lowepower.comsystem.ruby.phys_mem.bw_total::cpu0.data 288577818 # Total bandwidth to/from this memory (bytes/s) 29511731Sjason@lowepower.comsystem.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 4662818 # Total bandwidth to/from this memory (bytes/s) 29611731Sjason@lowepower.comsystem.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 4662818 # Total bandwidth to/from this memory (bytes/s) 29711731Sjason@lowepower.comsystem.ruby.phys_mem.bw_total::total 1341883332 # Total bandwidth to/from this memory (bytes/s) 29811731Sjason@lowepower.comsystem.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 29911731Sjason@lowepower.comsystem.ruby.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 30011312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::bucket_size 1 30111312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::max_bucket 9 30211312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::samples 114203 30311312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::mean 1.000035 30411312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::gmean 1.000024 30511312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::stdev 0.005918 30611312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 30711312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::total 114203 30811312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_coalsr::bucket_size 1 30911312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_coalsr::max_bucket 9 31011369Ssteve.reinhardt@amd.comsystem.ruby.outstanding_req_hist_coalsr::samples 27 31111731Sjason@lowepower.comsystem.ruby.outstanding_req_hist_coalsr::mean 2.074074 31211731Sjason@lowepower.comsystem.ruby.outstanding_req_hist_coalsr::gmean 1.820631 31311731Sjason@lowepower.comsystem.ruby.outstanding_req_hist_coalsr::stdev 1.071517 31411731Sjason@lowepower.comsystem.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 10 37.04% 37.04% | 9 33.33% 70.37% | 4 14.81% 85.19% | 4 14.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 31511369Ssteve.reinhardt@amd.comsystem.ruby.outstanding_req_hist_coalsr::total 27 31611312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::bucket_size 64 31711312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::max_bucket 639 31811312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::samples 114203 31911680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr::mean 4.823332 32011680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr::gmean 2.131609 32111680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr::stdev 24.449444 32211680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr | 112668 98.66% 98.66% | 0 0.00% 98.66% | 0 0.00% 98.66% | 1490 1.30% 99.96% | 18 0.02% 99.98% | 18 0.02% 99.99% | 2 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 7 0.01% 100.00% 32311312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::total 114203 32411312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_coalsr::bucket_size 64 32511312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_coalsr::max_bucket 639 32611369Ssteve.reinhardt@amd.comsystem.ruby.latency_hist_coalsr::samples 27 32711731Sjason@lowepower.comsystem.ruby.latency_hist_coalsr::mean 175.777778 32811731Sjason@lowepower.comsystem.ruby.latency_hist_coalsr::gmean 29.086037 32911731Sjason@lowepower.comsystem.ruby.latency_hist_coalsr::stdev 175.084668 33011731Sjason@lowepower.comsystem.ruby.latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 1 3.70% 51.85% | 2 7.41% 59.26% | 7 25.93% 85.19% | 4 14.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 33111369Ssteve.reinhardt@amd.comsystem.ruby.latency_hist_coalsr::total 27 33211312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::bucket_size 64 33311312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::max_bucket 639 33411312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::samples 1535 33511680SCurtis.Dunham@arm.comsystem.ruby.hit_latency_hist_seqr::mean 211.362215 33611680SCurtis.Dunham@arm.comsystem.ruby.hit_latency_hist_seqr::gmean 209.793806 33711680SCurtis.Dunham@arm.comsystem.ruby.hit_latency_hist_seqr::stdev 34.965177 33811680SCurtis.Dunham@arm.comsystem.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1490 97.07% 97.07% | 18 1.17% 98.24% | 18 1.17% 99.41% | 2 0.13% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 7 0.46% 100.00% 33911312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::total 1535 34011312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::bucket_size 4 34111312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::max_bucket 39 34211312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::samples 112668 34311312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::mean 2.009426 34411312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::gmean 2.002413 34511312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::stdev 0.411800 34611312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr | 112609 99.95% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 59 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 34711312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::total 112668 34811312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_coalsr::bucket_size 64 34911312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_coalsr::max_bucket 639 35011369Ssteve.reinhardt@amd.comsystem.ruby.miss_latency_hist_coalsr::samples 27 35111731Sjason@lowepower.comsystem.ruby.miss_latency_hist_coalsr::mean 175.777778 35211731Sjason@lowepower.comsystem.ruby.miss_latency_hist_coalsr::gmean 29.086037 35311731Sjason@lowepower.comsystem.ruby.miss_latency_hist_coalsr::stdev 175.084668 35411731Sjason@lowepower.comsystem.ruby.miss_latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 1 3.70% 51.85% | 2 7.41% 59.26% | 7 25.93% 85.19% | 4 14.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 35511369Ssteve.reinhardt@amd.comsystem.ruby.miss_latency_hist_coalsr::total 27 35611312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.incomplete_times_seqr 112609 35711312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.incomplete_times_seqr 59 35811308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits 35911308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses 36011308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses 36111308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.num_data_array_reads 16155 # number of data array reads 36211308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.num_data_array_writes 11985 # number of data array writes 36311308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.num_tag_array_reads 27132 # number of tag array reads 36411308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.num_tag_array_writes 1584 # number of tag array writes 36511308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits 36611308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D1cache.demand_misses 0 # Number of cache demand misses 36711308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D1cache.demand_accesses 0 # Number of cache demand accesses 36811308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits 36911308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.demand_misses 1088 # Number of cache demand misses 37011308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.demand_accesses 1088 # Number of cache demand accesses 37111308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.num_data_array_reads 86007 # number of data array reads 37211308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.num_data_array_writes 54 # number of data array writes 37311308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.num_tag_array_reads 87684 # number of tag array reads 37411308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes 37511308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 37611308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses 37711308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses 37811308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads 37911308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes 38011731Sjason@lowepower.comsystem.cp_cntrl0.L2cache.num_tag_array_reads 12057 # number of tag array reads 38111308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes 38211731Sjason@lowepower.comsystem.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 38311731Sjason@lowepower.comsystem.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 38411731Sjason@lowepower.comsystem.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 38511308Santhony.gutierrez@amd.comsystem.cpu0.clk_domain.clock 500 # Clock period in ticks 38611731Sjason@lowepower.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 38711308Santhony.gutierrez@amd.comsystem.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks 38811731Sjason@lowepower.comsystem.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 38911731Sjason@lowepower.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 39011308Santhony.gutierrez@amd.comsystem.cpu0.workload.num_syscalls 21 # Number of system calls 39111530Sandreas.sandberg@arm.comsystem.cpu0.numPwrStateTransitions 2 # Number of power state transitions 39211530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::samples 1 # Distribution of time spent in the clock gated state 39311731Sjason@lowepower.comsystem.cpu0.pwrStateClkGateDist::mean 2095501 # Distribution of time spent in the clock gated state 39411530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 1 100.00% 100.00% # Distribution of time spent in the clock gated state 39511731Sjason@lowepower.comsystem.cpu0.pwrStateClkGateDist::min_value 2095501 # Distribution of time spent in the clock gated state 39611731Sjason@lowepower.comsystem.cpu0.pwrStateClkGateDist::max_value 2095501 # Distribution of time spent in the clock gated state 39711530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::total 1 # Distribution of time spent in the clock gated state 39811680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 665311999 # Cumulative time (in ticks) in various power states 39911731Sjason@lowepower.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 2095501 # Cumulative time (in ticks) in various power states 40011731Sjason@lowepower.comsystem.cpu0.numCycles 1334815 # number of cpu cycles simulated 40111308Santhony.gutierrez@amd.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 40211308Santhony.gutierrez@amd.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 40311308Santhony.gutierrez@amd.comsystem.cpu0.committedInsts 66963 # Number of instructions committed 40411308Santhony.gutierrez@amd.comsystem.cpu0.committedOps 137705 # Number of ops (including micro ops) committed 40511308Santhony.gutierrez@amd.comsystem.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses 40611308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses 40711308Santhony.gutierrez@amd.comsystem.cpu0.num_func_calls 3196 # number of times a function call or return occured 40811308Santhony.gutierrez@amd.comsystem.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls 40911308Santhony.gutierrez@amd.comsystem.cpu0.num_int_insts 136380 # number of integer instructions 41011308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_insts 1279 # number of float instructions 41111308Santhony.gutierrez@amd.comsystem.cpu0.num_int_register_reads 257490 # number of times the integer registers were read 41211308Santhony.gutierrez@amd.comsystem.cpu0.num_int_register_writes 110039 # number of times the integer registers were written 41311308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read 41411308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_register_writes 981 # number of times the floating registers were written 41511308Santhony.gutierrez@amd.comsystem.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read 41611308Santhony.gutierrez@amd.comsystem.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written 41711308Santhony.gutierrez@amd.comsystem.cpu0.num_mem_refs 27198 # number of memory refs 41811308Santhony.gutierrez@amd.comsystem.cpu0.num_load_insts 16684 # Number of load instructions 41911308Santhony.gutierrez@amd.comsystem.cpu0.num_store_insts 10514 # Number of store instructions 42011731Sjason@lowepower.comsystem.cpu0.num_idle_cycles 4191.003994 # Number of idle cycles 42111731Sjason@lowepower.comsystem.cpu0.num_busy_cycles 1330623.996006 # Number of busy cycles 42211731Sjason@lowepower.comsystem.cpu0.not_idle_fraction 0.996860 # Percentage of non-idle cycles 42311731Sjason@lowepower.comsystem.cpu0.idle_fraction 0.003140 # Percentage of idle cycles 42411308Santhony.gutierrez@amd.comsystem.cpu0.Branches 16199 # Number of branches fetched 42511308Santhony.gutierrez@amd.comsystem.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction 42611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction 42711308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction 42811308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction 42911308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction 43011308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction 43111308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction 43211308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatMult 0 0.00% 80.25% # Class of executed instruction 43311687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMultAcc 0 0.00% 80.25% # Class of executed instruction 43411308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatDiv 0 0.00% 80.25% # Class of executed instruction 43511687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMisc 0 0.00% 80.25% # Class of executed instruction 43611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 80.25% # Class of executed instruction 43711308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdAdd 0 0.00% 80.25% # Class of executed instruction 43811308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 80.25% # Class of executed instruction 43911308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdAlu 0 0.00% 80.25% # Class of executed instruction 44011308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdCmp 0 0.00% 80.25% # Class of executed instruction 44111308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdCvt 0 0.00% 80.25% # Class of executed instruction 44211308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdMisc 0 0.00% 80.25% # Class of executed instruction 44311308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdMult 0 0.00% 80.25% # Class of executed instruction 44411308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 80.25% # Class of executed instruction 44511308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdShift 0 0.00% 80.25% # Class of executed instruction 44611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 80.25% # Class of executed instruction 44711308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 80.25% # Class of executed instruction 44811308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 80.25% # Class of executed instruction 44911308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 80.25% # Class of executed instruction 45011308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 80.25% # Class of executed instruction 45111308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 80.25% # Class of executed instruction 45211308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 80.25% # Class of executed instruction 45311308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25% # Class of executed instruction 45411308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 80.25% # Class of executed instruction 45511308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25% # Class of executed instruction 45611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction 45711687Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 16382 11.90% 92.15% # Class of executed instruction 45811687Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 10514 7.64% 99.78% # Class of executed instruction 45911687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemRead 302 0.22% 100.00% # Class of executed instruction 46011687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 46111308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 46211308Santhony.gutierrez@amd.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 46311308Santhony.gutierrez@amd.comsystem.cpu0.op_class::total 137705 # Class of executed instruction 46411308Santhony.gutierrez@amd.comsystem.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 46511308Santhony.gutierrez@amd.comsystem.cpu1.clk_domain.clock 1000 # Clock period in ticks 46611731Sjason@lowepower.comsystem.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 46711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 46811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 46911731Sjason@lowepower.comsystem.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 309 # number of times the wf's instructions are blocked due to RAW dependencies 47011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 47111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 47211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 47311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 47411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 47511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 47611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 47711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 47811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 47911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 48011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands 48111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands 48211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands 48311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands 48411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 48511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands 48611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 48711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 48811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 48911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 49011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands 49111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 49211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 49311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 49411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 49511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 49611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 49711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 49811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 49911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 50011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 50111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 50211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 50311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 50411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 50511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 50611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 50711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 50811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 50911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 51011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 51111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 51211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 51311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 51411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 51511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 51611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 51711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 51811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 51911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 52011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 52111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 52211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 52311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 52411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 52511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 52611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 52711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 52811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 52911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 53011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 53111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 53211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 53311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 53411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 53511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 53611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 53711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 53811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 53911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 54011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 54111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 54211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 54311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 54411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 54511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 54611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 54711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 54811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 54911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 55011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 55111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 55211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 55311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 55411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 55511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 55611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 55711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 55811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 55911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 56011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 56111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 56211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 56311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 56411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 56511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 56611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 56711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 56811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 56911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 57011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 57111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 57211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 57311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 57411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 57511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 57611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 57711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 57811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 57911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 58011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 58111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 58211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 58311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 58411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 58511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 58611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 58711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 58811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 58911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 59011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 59111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 59211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 59311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 59411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 59511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 59611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 59711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 59811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 59911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 60011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 60111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 60211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 60311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 60411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 60511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 60611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 60711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 60811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 60911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 61011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 61111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 61211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 61311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 61411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 61511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 61611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 61711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 61811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 61911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 62011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 62111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 62211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 62311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 62411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 62511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 62611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 62711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 62811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 62911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 63011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 63111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 63211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 63311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 63411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 63511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 63611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 63711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 63811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 63911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 64011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 64111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 64211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 64311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 64411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 64511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 64611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 64711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 64811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 64911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 65011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 65111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 65211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 65311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 65411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 65511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 65611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 65711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 65811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 65911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 66011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 66111731Sjason@lowepower.comsystem.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 284 # number of times the wf's instructions are blocked due to RAW dependencies 66211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 66311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 66411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 66511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 66611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 66711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 66811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 66911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 67011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 67111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 67211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 67311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 67411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 67511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 67611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 67711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 67811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 67911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 68011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 68111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 68211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 68311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 68411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 68511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 68611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 68711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 68811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 68911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 69011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 69111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 69211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 69311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 69411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 69511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 69611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 69711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 69811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 69911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 70011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 70111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 70211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 70311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 70411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 70511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 70611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 70711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 70811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 70911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 71011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 71111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 71211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 71311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 71411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 71511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 71611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 71711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 71811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 71911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 72011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 72111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 72211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 72311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 72411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 72511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 72611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 72711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 72811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 72911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 73011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 73111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 73211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 73311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 73411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 73511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 73611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 73711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 73811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 73911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 74011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 74111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 74211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 74311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 74411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 74511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 74611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 74711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 74811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 74911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 75011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 75111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 75211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 75311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 75411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 75511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 75611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 75711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 75811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 75911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 76011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 76111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 76211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 76311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 76411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 76511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 76611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 76711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 76811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 76911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 77011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 77111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 77211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 77311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 77411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 77511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 77611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 77711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 77811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 77911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 78011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 78111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 78211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 78311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 78411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 78511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 78611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 78711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 78811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 78911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 79011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 79111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 79211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 79311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 79411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 79511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 79611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 79711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 79811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 79911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 80011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 80111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 80211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 80311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 80411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 80511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 80611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 80711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 80811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 80911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 81011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 81111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 81211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 81311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 81411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 81511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 81611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 81711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 81811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 81911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 82011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 82111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 82211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 82311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 82411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 82511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 82611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 82711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 82811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 82911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 83011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 83111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 83211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 83311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 83411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 83511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 83611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 83711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 83811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 83911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 84011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 84111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 84211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 84311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 84411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 84511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 84611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 84711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 84811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 84911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 85011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 85111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 85211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 85311731Sjason@lowepower.comsystem.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 279 # number of times the wf's instructions are blocked due to RAW dependencies 85411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 85511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 85611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 85711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 85811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 85911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 86011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 86111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 86211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 86311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 86411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 86511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 86611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 86711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 86811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 86911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 87011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 87111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 87211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 87311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 87411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 87511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 87611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 87711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 87811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 87911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 88011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 88111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 88211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 88311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 88411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 88511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 88611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 88711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 88811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 88911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 89011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 89111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 89211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 89311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 89411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 89511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 89611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 89711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 89811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 89911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 90011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 90111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 90211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 90311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 90411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 90511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 90611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 90711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 90811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 90911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 91011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 91111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 91211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 91311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 91411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 91511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 91611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 91711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 91811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 91911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 92011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 92111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 92211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 92311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 92411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 92511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 92611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 92711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 92811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 92911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 93011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 93111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 93211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 93311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 93411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 93511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 93611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 93711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 93811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 93911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 94011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 94111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 94211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 94311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 94411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 94511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 94611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 94711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 94811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 94911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 95011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 95111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 95211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 95311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 95411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 95511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 95611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 95711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 95811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 95911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 96011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 96111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 96211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 96311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 96411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 96511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 96611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 96711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 96811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 96911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 97011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 97111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 97211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 97311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 97411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 97511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 97611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 97711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 97811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 97911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 98011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 98111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 98211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 98311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 98411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 98511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 98611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 98711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 98811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 98911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 99011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 99111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 99211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 99311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 99411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 99511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 99611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 99711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 99811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 99911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 100011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 100111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 100211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 100311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 100411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 100511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 100611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 100711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 100811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 100911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 101011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 101111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 101211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 101311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 101411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 101511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 101611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 101711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 101811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 101911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 102011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 102111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 102211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 102311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 102411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 102511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 102611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 102711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 102811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 102911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 103011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 103111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 103211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 103311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 103411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 103511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 103611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 103711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 103811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 103911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 104011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 104111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 104211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 104311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 104411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 104511731Sjason@lowepower.comsystem.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 274 # number of times the wf's instructions are blocked due to RAW dependencies 104611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 104711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 104811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 104911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 105011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 105111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 105211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 105311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 105411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 105511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 105611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 105711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 105811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 105911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 106011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 106111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 106211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 106311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 106411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 106511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 106611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 106711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 106811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 106911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 107011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 107111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 107211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 107311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 107411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 107511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 107611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 107711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 107811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 107911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 108011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 108111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 108211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 108311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 108411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 108511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 108611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 108711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 108811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 108911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 109011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 109111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 109211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 109311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 109411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 109511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 109611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 109711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 109811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 109911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 110011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 110111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 110211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 110311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 110411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 110511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 110611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 110711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 110811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 110911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 111011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 111111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 111211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 111311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 111411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 111511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 111611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 111711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 111811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 111911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 112011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 112111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 112211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 112311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 112411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 112511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 112611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 112711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 112811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 112911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 113011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 113111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 113211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 113311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 113411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 113511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 113611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 113711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 113811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 113911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 114011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 114111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 114211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 114311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 114411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 114511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 114611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 114711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 114811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 114911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 115011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 115111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 115211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 115311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 115411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 115511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 115611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 115711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 115811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 115911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 116011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 116111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 116211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 116311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 116411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 116511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 116611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 116711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 116811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 116911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 117011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 117111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 117211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 117311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 117411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 117511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 117611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 117711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 117811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 117911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 118011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 118111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 118211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 118311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 118411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 118511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 118611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 118711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 118811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 118911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 119011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 119111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 119211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 119311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 119411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 119511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 119611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 119711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 119811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 119911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 120011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 120111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 120211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 120311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 120411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 120511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 120611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 120711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 120811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 120911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 121011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 121111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 121211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 121311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 121411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 121511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 121611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 121711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 121811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 121911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 122011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 122111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 122211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 122311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 122411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 122511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 122611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 122711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 122811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 122911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 123011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 123111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 123211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 123311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 123411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 123511731Sjason@lowepower.comsystem.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 123611731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 35 # For each instruction fetch request recieved record how many instructions you got from it 123711731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 11.257143 # For each instruction fetch request recieved record how many instructions you got from it 123811731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 5.595917 # For each instruction fetch request recieved record how many instructions you got from it 123911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 124011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 124111731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 4 11.43% 11.43% # For each instruction fetch request recieved record how many instructions you got from it 124211731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 4 11.43% 22.86% # For each instruction fetch request recieved record how many instructions you got from it 124311731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.86% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 124411731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 124511731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 124611731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 124711731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 124811731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 124911731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 4 11.43% 37.14% # For each instruction fetch request recieved record how many instructions you got from it 125011731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 4 11.43% 48.57% # For each instruction fetch request recieved record how many instructions you got from it 125111731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it 125211731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it 125311731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 1 2.86% 51.43% # For each instruction fetch request recieved record how many instructions you got from it 125411731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 51.43% # For each instruction fetch request recieved record how many instructions you got from it 125511731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 17 48.57% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 125611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 125711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 125811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 125911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 126011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 126111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 126211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 126311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 126411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 126511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 126611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 126711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 126811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 126911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 127011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 127111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 127211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 127311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it 127411731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 16 # For each instruction fetch request recieved record how many instructions you got from it 127511731Sjason@lowepower.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 35 # For each instruction fetch request recieved record how many instructions you got from it 127611731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 2741 # number of cycles the CU issues nothing 127711369Ssteve.reinhardt@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction 127811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 127911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 128011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 128111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 128211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 128311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued 128411731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 625 # Number of cycles no instruction of specific type issued 128511731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 340 # Number of cycles no instruction of specific type issued 128611731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 338 # Number of cycles no instruction of specific type issued 128711731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 335 # Number of cycles no instruction of specific type issued 128811731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued 128911369Ssteve.reinhardt@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued 129011731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.spc::samples 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 129111731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.spc::mean 0.049648 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 129211731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.spc::stdev 0.277106 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 129311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 129411731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.spc::0 2741 96.51% 96.51% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 129511731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.spc::1 57 2.01% 98.52% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 129611731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.spc::2 42 1.48% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 129711731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.spc::3 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 129811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 129911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 130011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 130111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 130211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 130311731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.spc::max_value 2 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 130411731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.spc::total 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 130511731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 90 # number of CU transitions from active to idle 130611731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 90 # duration of idle periods in cycles 130711731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 29.322222 # duration of idle periods in cycles 130811731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 145.995831 # duration of idle periods in cycles 130911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles 131011731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 76 84.44% 84.44% # duration of idle periods in cycles 131111731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.78% 92.22% # duration of idle periods in cycles 131211731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 92.22% # duration of idle periods in cycles 131311731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 92.22% # duration of idle periods in cycles 131411731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 0 0.00% 92.22% # duration of idle periods in cycles 131511731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.11% 93.33% # duration of idle periods in cycles 131611731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 93.33% # duration of idle periods in cycles 131711731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 93.33% # duration of idle periods in cycles 131811731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 93.33% # duration of idle periods in cycles 131911731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 93.33% # duration of idle periods in cycles 132011731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 93.33% # duration of idle periods in cycles 132111731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 93.33% # duration of idle periods in cycles 132211731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 93.33% # duration of idle periods in cycles 132311731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 93.33% # duration of idle periods in cycles 132411731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 93.33% # duration of idle periods in cycles 132511731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 93.33% # duration of idle periods in cycles 132611731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 6 6.67% 100.00% # duration of idle periods in cycles 132711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 132811680SCurtis.Dunham@arm.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1291 # duration of idle periods in cycles 132911731Sjason@lowepower.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 90 # duration of idle periods in cycles 133011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 133111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF 133211731Sjason@lowepower.comsystem.cpu1.CUs0.valu_insts 68 # Number of vector ALU insts issued. 133311731Sjason@lowepower.comsystem.cpu1.CUs0.valu_insts_per_wf 17 # The avg. number of vector ALU insts issued per-wavefront. 133411731Sjason@lowepower.comsystem.cpu1.CUs0.salu_insts 0 # Number of scalar ALU insts issued. 133511731Sjason@lowepower.comsystem.cpu1.CUs0.salu_insts_per_wf 0 # The avg. number of scalar ALU insts issued per-wavefront. 133611731Sjason@lowepower.comsystem.cpu1.CUs0.inst_cycles_valu 68 # Number of cycles needed to execute VALU insts. 133711731Sjason@lowepower.comsystem.cpu1.CUs0.inst_cycles_salu 0 # Number of cycles needed to execute SALU insts. 133811731Sjason@lowepower.comsystem.cpu1.CUs0.thread_cycles_valu 3076 # Number of thread cycles used to execute vector ALU ops. Similar to instCyclesVALU but multiplied by the number of active threads. 133911731Sjason@lowepower.comsystem.cpu1.CUs0.valu_utilization 70.680147 # Percentage of active vector ALU threads in a wave. 134011731Sjason@lowepower.comsystem.cpu1.CUs0.lds_no_flat_insts 6 # Number of LDS insts issued, not including FLAT accesses that resolve to LDS. 134111731Sjason@lowepower.comsystem.cpu1.CUs0.lds_no_flat_insts_per_wf 1.500000 # The avg. number of LDS insts (not including FLAT accesses that resolve to LDS) per-wavefront. 134211731Sjason@lowepower.comsystem.cpu1.CUs0.flat_vmem_insts 0 # The number of FLAT insts that resolve to vmem issued. 134311731Sjason@lowepower.comsystem.cpu1.CUs0.flat_vmem_insts_per_wf 0 # The average number of FLAT insts that resolve to vmem issued per-wavefront. 134411731Sjason@lowepower.comsystem.cpu1.CUs0.flat_lds_insts 0 # The number of FLAT insts that resolve to LDS issued. 134511731Sjason@lowepower.comsystem.cpu1.CUs0.flat_lds_insts_per_wf 0 # The average number of FLAT insts that resolve to LDS issued per-wavefront. 134611731Sjason@lowepower.comsystem.cpu1.CUs0.vector_mem_writes 8 # Number of vector mem write insts (excluding FLAT insts). 134711731Sjason@lowepower.comsystem.cpu1.CUs0.vector_mem_writes_per_wf 2 # The average number of vector mem write insts (excluding FLAT insts) per-wavefront. 134811731Sjason@lowepower.comsystem.cpu1.CUs0.vector_mem_reads 29 # Number of vector mem read insts (excluding FLAT insts). 134911731Sjason@lowepower.comsystem.cpu1.CUs0.vector_mem_reads_per_wf 7.250000 # The avg. number of vector mem read insts (excluding FLAT insts) per-wavefront. 135011731Sjason@lowepower.comsystem.cpu1.CUs0.scalar_mem_writes 0 # Number of scalar mem write insts. 135111731Sjason@lowepower.comsystem.cpu1.CUs0.scalar_mem_writes_per_wf 0 # The average number of scalar mem write insts per-wavefront. 135211731Sjason@lowepower.comsystem.cpu1.CUs0.scalar_mem_reads 0 # Number of scalar mem read insts. 135311731Sjason@lowepower.comsystem.cpu1.CUs0.scalar_mem_reads_per_wf 0 # The average number of scalar mem read insts per-wavefront. 135411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests 135511731Sjason@lowepower.comsystem.cpu1.CUs0.tlb_cycles -454892896000 # total number of cycles for all uncoalesced requests 135611731Sjason@lowepower.comsystem.cpu1.CUs0.avg_translation_latency -591538226.267880 # Avg. translation latency for data translations 135711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 135811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 135911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 136011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 136111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses 136211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 136311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet 136411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet 136511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet 136611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet 136711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 136811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 136911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 137011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 137111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::10-11 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 137211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::12-13 4 66.67% 100.00% # Number of bank conflicts per LDS memory packet 137311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 137411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 137511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 137611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 137711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 137811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 137911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 138011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 138111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 138211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 138311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 138411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 138511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 138611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 138711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 138811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 138911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 139011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 139111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 139211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 139311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 139411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 139511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 139611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 139711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 139811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 139911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 140011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet 140111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet 140211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet 140311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) 140411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) 140511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) 140611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) 140711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) 140811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 140911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 141011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 141111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 141211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 141311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 141411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 141511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 141611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 141711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 141811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 141911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 142011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 142111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 142211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 142311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 142411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 142511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 142611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 142711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count 142811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count 142911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 143011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_instr_executed 141 # number of instructions executed 143111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 143211731Sjason@lowepower.comsystem.cpu1.CUs0.inst_exec_rate::mean 71.028369 # Instruction Execution Rate: Number of executed vector instructions per cycle 143311731Sjason@lowepower.comsystem.cpu1.CUs0.inst_exec_rate::stdev 225.061514 # Instruction Execution Rate: Number of executed vector instructions per cycle 143411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 143511369Ssteve.reinhardt@amd.comsystem.cpu1.CUs0.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 143611369Ssteve.reinhardt@amd.comsystem.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 8.51% # Instruction Execution Rate: Number of executed vector instructions per cycle 143711731Sjason@lowepower.comsystem.cpu1.CUs0.inst_exec_rate::4-5 61 43.26% 51.77% # Instruction Execution Rate: Number of executed vector instructions per cycle 143811731Sjason@lowepower.comsystem.cpu1.CUs0.inst_exec_rate::6-7 32 22.70% 74.47% # Instruction Execution Rate: Number of executed vector instructions per cycle 143911731Sjason@lowepower.comsystem.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 76.60% # Instruction Execution Rate: Number of executed vector instructions per cycle 144011731Sjason@lowepower.comsystem.cpu1.CUs0.inst_exec_rate::10 3 2.13% 78.72% # Instruction Execution Rate: Number of executed vector instructions per cycle 144111731Sjason@lowepower.comsystem.cpu1.CUs0.inst_exec_rate::overflows 30 21.28% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 144211369Ssteve.reinhardt@amd.comsystem.cpu1.CUs0.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle 144311680SCurtis.Dunham@arm.comsystem.cpu1.CUs0.inst_exec_rate::max_value 1297 # Instruction Execution Rate: Number of executed vector instructions per cycle 144411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 144511680SCurtis.Dunham@arm.comsystem.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. WF size/inst) 144611731Sjason@lowepower.comsystem.cpu1.CUs0.num_total_cycles 2840 # number of cycles the CU ran for 144711731Sjason@lowepower.comsystem.cpu1.CUs0.vpc 2.383451 # Vector Operations per cycle (this CU only) 144811731Sjason@lowepower.comsystem.cpu1.CUs0.ipc 0.049648 # Instructions per cycle (this CU only) 144911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 145011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions) 145111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions) 145211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 145311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 145411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 145511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 145611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions) 145711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 145811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 145911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 146011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 146111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 146211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 146311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 146411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 146511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) 146611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 146711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 146811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) 146911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) 147011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) 147111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) 147211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) 147311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction 147411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::mean 37.833333 # number of active lanes per global memory instruction 147511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::stdev 27.064737 # number of active lanes per global memory instruction 147611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction 147711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction 147811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction 147911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::9-12 0 0.00% 5.56% # number of active lanes per global memory instruction 148011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::13-16 8 44.44% 50.00% # number of active lanes per global memory instruction 148111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction 148211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction 148311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction 148411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction 148511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction 148611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction 148711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction 148811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction 148911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction 149011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction 149111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction 149211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction 149311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction 149411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction 149511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction 149611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction 149711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction 149811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::mean 19.500000 # number of active lanes per local memory instruction 149911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::stdev 22.322634 # number of active lanes per local memory instruction 150011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction 150111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction 150211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction 150311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::9-12 0 0.00% 16.67% # number of active lanes per local memory instruction 150411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::13-16 4 66.67% 83.33% # number of active lanes per local memory instruction 150511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction 150611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction 150711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction 150811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction 150911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction 151011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction 151111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction 151211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction 151311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction 151411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction 151511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction 151611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction 151711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction 151811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 151911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 152011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 152111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 152211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 152311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations 152411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed 152511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts 152611731Sjason@lowepower.comsystem.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 152711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 152811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 152911731Sjason@lowepower.comsystem.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 406 # number of times the wf's instructions are blocked due to RAW dependencies 153011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 153111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 153211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 153311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 153411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 153511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 153611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 153711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 153811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 153911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 154011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands 154111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands 154211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands 154311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands 154411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 154511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands 154611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 154711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 154811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 154911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 155011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands 155111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 155211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 155311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 155411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 155511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 155611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 155711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 155811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 155911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 156011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 156111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 156211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 156311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 156411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 156511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 156611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 156711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 156811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 156911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 157011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 157111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 157211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 157311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 157411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 157511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 157611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 157711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 157811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 157911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 158011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 158111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 158211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 158311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 158411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 158511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 158611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 158711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 158811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 158911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 159011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 159111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 159211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 159311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 159411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 159511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 159611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 159711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 159811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 159911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 160011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 160111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 160211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 160311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 160411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 160511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 160611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 160711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 160811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 160911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 161011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 161111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 161211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 161311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 161411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 161511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 161611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 161711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 161811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 161911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 162011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 162111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 162211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 162311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 162411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 162511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 162611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 162711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 162811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 162911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 163011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 163111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 163211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 163311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 163411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 163511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 163611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 163711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 163811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 163911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 164011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 164111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 164211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 164311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 164411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 164511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 164611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 164711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 164811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 164911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 165011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 165111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 165211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 165311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 165411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 165511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 165611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 165711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 165811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 165911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 166011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 166111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 166211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 166311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 166411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 166511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 166611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 166711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 166811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 166911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 167011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 167111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 167211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 167311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 167411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 167511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 167611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 167711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 167811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 167911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 168011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 168111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 168211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 168311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 168411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 168511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 168611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 168711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 168811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 168911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 169011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 169111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 169211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 169311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 169411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 169511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 169611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 169711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 169811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 169911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 170011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 170111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 170211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 170311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 170411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 170511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 170611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 170711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 170811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 170911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 171011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 171111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 171211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 171311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 171411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 171511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 171611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 171711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 171811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 171911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 172011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 172111731Sjason@lowepower.comsystem.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 381 # number of times the wf's instructions are blocked due to RAW dependencies 172211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 172311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 172411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 172511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 172611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 172711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 172811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 172911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 173011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 173111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 173211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 173311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 173411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 173511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 173611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 173711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 173811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 173911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 174011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 174111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 174211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 174311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 174411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 174511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 174611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 174711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 174811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 174911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 175011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 175111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 175211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 175311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 175411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 175511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 175611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 175711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 175811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 175911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 176011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 176111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 176211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 176311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 176411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 176511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 176611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 176711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 176811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 176911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 177011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 177111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 177211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 177311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 177411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 177511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 177611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 177711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 177811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 177911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 178011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 178111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 178211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 178311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 178411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 178511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 178611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 178711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 178811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 178911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 179011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 179111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 179211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 179311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 179411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 179511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 179611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 179711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 179811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 179911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 180011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 180111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 180211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 180311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 180411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 180511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 180611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 180711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 180811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 180911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 181011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 181111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 181211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 181311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 181411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 181511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 181611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 181711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 181811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 181911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 182011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 182111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 182211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 182311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 182411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 182511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 182611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 182711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 182811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 182911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 183011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 183111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 183211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 183311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 183411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 183511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 183611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 183711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 183811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 183911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 184011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 184111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 184211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 184311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 184411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 184511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 184611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 184711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 184811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 184911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 185011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 185111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 185211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 185311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 185411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 185511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 185611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 185711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 185811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 185911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 186011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 186111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 186211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 186311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 186411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 186511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 186611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 186711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 186811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 186911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 187011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 187111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 187211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 187311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 187411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 187511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 187611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 187711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 187811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 187911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 188011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 188111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 188211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 188311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 188411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 188511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 188611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 188711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 188811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 188911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 189011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 189111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 189211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 189311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 189411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 189511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 189611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 189711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 189811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 189911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 190011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 190111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 190211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 190311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 190411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 190511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 190611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 190711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 190811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 190911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 191011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 191111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 191211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 191311731Sjason@lowepower.comsystem.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 372 # number of times the wf's instructions are blocked due to RAW dependencies 191411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 191511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 191611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 191711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 191811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 191911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 192011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 192111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 192211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 192311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 192411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 192511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 192611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 192711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 192811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 192911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 193011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 193111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 193211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 193311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 193411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 193511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 193611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 193711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 193811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 193911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 194011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 194111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 194211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 194311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 194411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 194511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 194611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 194711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 194811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 194911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 195011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 195111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 195211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 195311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 195411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 195511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 195611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 195711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 195811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 195911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 196011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 196111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 196211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 196311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 196411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 196511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 196611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 196711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 196811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 196911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 197011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 197111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 197211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 197311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 197411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 197511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 197611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 197711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 197811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 197911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 198011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 198111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 198211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 198311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 198411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 198511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 198611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 198711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 198811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 198911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 199011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 199111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 199211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 199311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 199411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 199511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 199611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 199711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 199811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 199911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 200011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 200111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 200211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 200311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 200411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 200511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 200611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 200711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 200811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 200911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 201011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 201111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 201211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 201311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 201411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 201511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 201611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 201711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 201811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 201911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 202011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 202111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 202211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 202311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 202411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 202511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 202611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 202711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 202811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 202911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 203011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 203111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 203211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 203311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 203411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 203511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 203611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 203711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 203811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 203911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 204011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 204111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 204211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 204311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 204411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 204511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 204611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 204711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 204811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 204911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 205011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 205111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 205211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 205311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 205411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 205511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 205611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 205711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 205811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 205911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 206011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 206111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 206211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 206311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 206411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 206511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 206611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 206711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 206811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 206911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 207011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 207111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 207211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 207311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 207411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 207511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 207611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 207711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 207811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 207911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 208011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 208111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 208211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 208311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 208411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 208511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 208611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 208711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 208811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 208911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 209011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 209111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 209211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 209311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 209411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 209511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 209611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 209711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 209811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 209911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 210011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 210111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 210211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 210311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 210411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 210511731Sjason@lowepower.comsystem.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 364 # number of times the wf's instructions are blocked due to RAW dependencies 210611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 210711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 210811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 210911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 211011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 211111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 211211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 211311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 211411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 211511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 211611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 211711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 211811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 211911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 212011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 212111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 212211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 212311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 212411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 212511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 212611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 212711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 212811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 212911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 213011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 213111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 213211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 213311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 213411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 213511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 213611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 213711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 213811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 213911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 214011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 214111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 214211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 214311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 214411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 214511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 214611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 214711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 214811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 214911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 215011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 215111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 215211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 215311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 215411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 215511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 215611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 215711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 215811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 215911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 216011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 216111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 216211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 216311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 216411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 216511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 216611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 216711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 216811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 216911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 217011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 217111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 217211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 217311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 217411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 217511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 217611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 217711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 217811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 217911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 218011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 218111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 218211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 218311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 218411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 218511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 218611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 218711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 218811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 218911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 219011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 219111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 219211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 219311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 219411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 219511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 219611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 219711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 219811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 219911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 220011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 220111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 220211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 220311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 220411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 220511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 220611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 220711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 220811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 220911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 221011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 221111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 221211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 221311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 221411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 221511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 221611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 221711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 221811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 221911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 222011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 222111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 222211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 222311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 222411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 222511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 222611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 222711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 222811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 222911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 223011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 223111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 223211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 223311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 223411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 223511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 223611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 223711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 223811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 223911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 224011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 224111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 224211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 224311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 224411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 224511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 224611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 224711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 224811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 224911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 225011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 225111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 225211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 225311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 225411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 225511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 225611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 225711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 225811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 225911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 226011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 226111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 226211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 226311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 226411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 226511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 226611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 226711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 226811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 226911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 227011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 227111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 227211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 227311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 227411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 227511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 227611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 227711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 227811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 227911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 228011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 228111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 228211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 228311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 228411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 228511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 228611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 228711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 228811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 228911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 229011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 229111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 229211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 229311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 229411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 229511731Sjason@lowepower.comsystem.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 229611731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 35 # For each instruction fetch request recieved record how many instructions you got from it 229711731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 11.257143 # For each instruction fetch request recieved record how many instructions you got from it 229811731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 5.595917 # For each instruction fetch request recieved record how many instructions you got from it 229911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 230011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 230111731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 4 11.43% 11.43% # For each instruction fetch request recieved record how many instructions you got from it 230211731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 4 11.43% 22.86% # For each instruction fetch request recieved record how many instructions you got from it 230311731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.86% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 230411731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 230511731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 230611731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 230711731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 230811731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it 230911731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 4 11.43% 37.14% # For each instruction fetch request recieved record how many instructions you got from it 231011731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 4 11.43% 48.57% # For each instruction fetch request recieved record how many instructions you got from it 231111731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it 231211731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it 231311731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 1 2.86% 51.43% # For each instruction fetch request recieved record how many instructions you got from it 231411731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 51.43% # For each instruction fetch request recieved record how many instructions you got from it 231511731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 17 48.57% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 231611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 231711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 231811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 231911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 232011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 232111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 232211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 232311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 232411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 232511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 232611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 232711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 232811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 232911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 233011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 233111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 233211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 233311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it 233411731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 16 # For each instruction fetch request recieved record how many instructions you got from it 233511731Sjason@lowepower.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 35 # For each instruction fetch request recieved record how many instructions you got from it 233611731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 2740 # number of cycles the CU issues nothing 233711731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 100 # number of cycles the CU issued at least one instruction 233811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 233911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 234011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 234111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 234211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 234311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued 234411731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 795 # Number of cycles no instruction of specific type issued 234511731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 437 # Number of cycles no instruction of specific type issued 234611731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 431 # Number of cycles no instruction of specific type issued 234711731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 422 # Number of cycles no instruction of specific type issued 234811731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 408 # Number of cycles no instruction of specific type issued 234911369Ssteve.reinhardt@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued 235011731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.spc::samples 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 235111731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.spc::mean 0.049648 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 235211731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.spc::stdev 0.275831 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 235311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 235411731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.spc::0 2740 96.48% 96.48% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 235511731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.spc::1 59 2.08% 98.56% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 235611731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.spc::2 41 1.44% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 235711731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.spc::3 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 235811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 235911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 236011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 236111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 236211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 236311731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.spc::max_value 2 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 236411731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.spc::total 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 236511731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 91 # number of CU transitions from active to idle 236611731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 91 # duration of idle periods in cycles 236711731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 30.010989 # duration of idle periods in cycles 236811731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 148.108031 # duration of idle periods in cycles 236911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles 237011731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 76 83.52% 83.52% # duration of idle periods in cycles 237111731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.79% 92.31% # duration of idle periods in cycles 237211731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 92.31% # duration of idle periods in cycles 237311731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 92.31% # duration of idle periods in cycles 237411731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 0 0.00% 92.31% # duration of idle periods in cycles 237511731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.10% 93.41% # duration of idle periods in cycles 237611731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 93.41% # duration of idle periods in cycles 237711731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 93.41% # duration of idle periods in cycles 237811731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 93.41% # duration of idle periods in cycles 237911731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 93.41% # duration of idle periods in cycles 238011731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 93.41% # duration of idle periods in cycles 238111731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 93.41% # duration of idle periods in cycles 238211731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 93.41% # duration of idle periods in cycles 238311731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 93.41% # duration of idle periods in cycles 238411731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 93.41% # duration of idle periods in cycles 238511731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 93.41% # duration of idle periods in cycles 238611731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 6 6.59% 100.00% # duration of idle periods in cycles 238711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 238811680SCurtis.Dunham@arm.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1299 # duration of idle periods in cycles 238911731Sjason@lowepower.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 91 # duration of idle periods in cycles 239011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 239111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF 239211731Sjason@lowepower.comsystem.cpu1.CUs1.valu_insts 68 # Number of vector ALU insts issued. 239311731Sjason@lowepower.comsystem.cpu1.CUs1.valu_insts_per_wf 17 # The avg. number of vector ALU insts issued per-wavefront. 239411731Sjason@lowepower.comsystem.cpu1.CUs1.salu_insts 0 # Number of scalar ALU insts issued. 239511731Sjason@lowepower.comsystem.cpu1.CUs1.salu_insts_per_wf 0 # The avg. number of scalar ALU insts issued per-wavefront. 239611731Sjason@lowepower.comsystem.cpu1.CUs1.inst_cycles_valu 68 # Number of cycles needed to execute VALU insts. 239711731Sjason@lowepower.comsystem.cpu1.CUs1.inst_cycles_salu 0 # Number of cycles needed to execute SALU insts. 239811731Sjason@lowepower.comsystem.cpu1.CUs1.thread_cycles_valu 3071 # Number of thread cycles used to execute vector ALU ops. Similar to instCyclesVALU but multiplied by the number of active threads. 239911731Sjason@lowepower.comsystem.cpu1.CUs1.valu_utilization 70.565257 # Percentage of active vector ALU threads in a wave. 240011731Sjason@lowepower.comsystem.cpu1.CUs1.lds_no_flat_insts 6 # Number of LDS insts issued, not including FLAT accesses that resolve to LDS. 240111731Sjason@lowepower.comsystem.cpu1.CUs1.lds_no_flat_insts_per_wf 1.500000 # The avg. number of LDS insts (not including FLAT accesses that resolve to LDS) per-wavefront. 240211731Sjason@lowepower.comsystem.cpu1.CUs1.flat_vmem_insts 0 # The number of FLAT insts that resolve to vmem issued. 240311731Sjason@lowepower.comsystem.cpu1.CUs1.flat_vmem_insts_per_wf 0 # The average number of FLAT insts that resolve to vmem issued per-wavefront. 240411731Sjason@lowepower.comsystem.cpu1.CUs1.flat_lds_insts 0 # The number of FLAT insts that resolve to LDS issued. 240511731Sjason@lowepower.comsystem.cpu1.CUs1.flat_lds_insts_per_wf 0 # The average number of FLAT insts that resolve to LDS issued per-wavefront. 240611731Sjason@lowepower.comsystem.cpu1.CUs1.vector_mem_writes 8 # Number of vector mem write insts (excluding FLAT insts). 240711731Sjason@lowepower.comsystem.cpu1.CUs1.vector_mem_writes_per_wf 2 # The average number of vector mem write insts (excluding FLAT insts) per-wavefront. 240811731Sjason@lowepower.comsystem.cpu1.CUs1.vector_mem_reads 29 # Number of vector mem read insts (excluding FLAT insts). 240911731Sjason@lowepower.comsystem.cpu1.CUs1.vector_mem_reads_per_wf 7.250000 # The avg. number of vector mem read insts (excluding FLAT insts) per-wavefront. 241011731Sjason@lowepower.comsystem.cpu1.CUs1.scalar_mem_writes 0 # Number of scalar mem write insts. 241111731Sjason@lowepower.comsystem.cpu1.CUs1.scalar_mem_writes_per_wf 0 # The average number of scalar mem write insts per-wavefront. 241211731Sjason@lowepower.comsystem.cpu1.CUs1.scalar_mem_reads 0 # Number of scalar mem read insts. 241311731Sjason@lowepower.comsystem.cpu1.CUs1.scalar_mem_reads_per_wf 0 # The average number of scalar mem read insts per-wavefront. 241411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests 241511731Sjason@lowepower.comsystem.cpu1.CUs1.tlb_cycles -454919630000 # total number of cycles for all uncoalesced requests 241611731Sjason@lowepower.comsystem.cpu1.CUs1.avg_translation_latency -591572990.897269 # Avg. translation latency for data translations 241711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 241811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 241911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 242011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 242111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses 242211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 242311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet 242411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet 242511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet 242611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet 242711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 242811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 242911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 243011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 243111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::10-11 1 16.67% 50.00% # Number of bank conflicts per LDS memory packet 243211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::12-13 3 50.00% 100.00% # Number of bank conflicts per LDS memory packet 243311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 243411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 243511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 243611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 243711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 243811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 243911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 244011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 244111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 244211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 244311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 244411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 244511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 244611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 244711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 244811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 244911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 245011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 245111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 245211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 245311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 245411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 245511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 245611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 245711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 245811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 245911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 246011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet 246111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet 246211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet 246311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) 246411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) 246511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) 246611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) 246711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) 246811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 246911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 247011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 247111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 247211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 247311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 247411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 247511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 247611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 247711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 247811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 247911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 248011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 248111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 248211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 248311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 248411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 248511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 248611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 248711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count 248811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count 248911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 249011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_instr_executed 141 # number of instructions executed 249111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 249211731Sjason@lowepower.comsystem.cpu1.CUs1.inst_exec_rate::mean 72.113475 # Instruction Execution Rate: Number of executed vector instructions per cycle 249311731Sjason@lowepower.comsystem.cpu1.CUs1.inst_exec_rate::stdev 228.065470 # Instruction Execution Rate: Number of executed vector instructions per cycle 249411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 249511369Ssteve.reinhardt@amd.comsystem.cpu1.CUs1.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 249611369Ssteve.reinhardt@amd.comsystem.cpu1.CUs1.inst_exec_rate::2-3 13 9.22% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle 249711731Sjason@lowepower.comsystem.cpu1.CUs1.inst_exec_rate::4-5 60 42.55% 51.77% # Instruction Execution Rate: Number of executed vector instructions per cycle 249811731Sjason@lowepower.comsystem.cpu1.CUs1.inst_exec_rate::6-7 34 24.11% 75.89% # Instruction Execution Rate: Number of executed vector instructions per cycle 249911731Sjason@lowepower.comsystem.cpu1.CUs1.inst_exec_rate::8-9 3 2.13% 78.01% # Instruction Execution Rate: Number of executed vector instructions per cycle 250011731Sjason@lowepower.comsystem.cpu1.CUs1.inst_exec_rate::10 1 0.71% 78.72% # Instruction Execution Rate: Number of executed vector instructions per cycle 250111731Sjason@lowepower.comsystem.cpu1.CUs1.inst_exec_rate::overflows 30 21.28% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 250211369Ssteve.reinhardt@amd.comsystem.cpu1.CUs1.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle 250311680SCurtis.Dunham@arm.comsystem.cpu1.CUs1.inst_exec_rate::max_value 1305 # Instruction Execution Rate: Number of executed vector instructions per cycle 250411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 250511680SCurtis.Dunham@arm.comsystem.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. WF size/inst) 250611731Sjason@lowepower.comsystem.cpu1.CUs1.num_total_cycles 2840 # number of cycles the CU ran for 250711731Sjason@lowepower.comsystem.cpu1.CUs1.vpc 2.380986 # Vector Operations per cycle (this CU only) 250811731Sjason@lowepower.comsystem.cpu1.CUs1.ipc 0.049648 # Instructions per cycle (this CU only) 250911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 251011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions) 251111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions) 251211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 251311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 251411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 251511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions) 251611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions) 251711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 251811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 251911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 252011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 252111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 252211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 252311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 252411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 252511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) 252611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 252711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 252811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) 252911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) 253011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) 253111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) 253211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) 253311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction 253411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::mean 37.722222 # number of active lanes per global memory instruction 253511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::stdev 27.174394 # number of active lanes per global memory instruction 253611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction 253711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction 253811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction 253911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::9-12 2 11.11% 16.67% # number of active lanes per global memory instruction 254011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::13-16 6 33.33% 50.00% # number of active lanes per global memory instruction 254111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction 254211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction 254311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction 254411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction 254511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction 254611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction 254711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction 254811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction 254911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction 255011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction 255111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction 255211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction 255311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction 255411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction 255511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction 255611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction 255711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction 255811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::mean 19.333333 # number of active lanes per local memory instruction 255911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::stdev 22.384518 # number of active lanes per local memory instruction 256011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction 256111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction 256211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction 256311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::9-12 1 16.67% 33.33% # number of active lanes per local memory instruction 256411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::13-16 3 50.00% 83.33% # number of active lanes per local memory instruction 256511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction 256611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction 256711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction 256811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction 256911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction 257011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction 257111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction 257211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction 257311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction 257411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction 257511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction 257611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction 257711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction 257811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 257911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 258011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 258111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 258211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 258311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations 258411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed 258511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts 258611731Sjason@lowepower.comsystem.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 258711731Sjason@lowepower.comsystem.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 258811731Sjason@lowepower.comsystem.cpu2.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 258911308Santhony.gutierrez@amd.comsystem.cpu2.num_kernel_launched 1 # number of kernel launched 259011308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits 259111308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses 259211308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses 259311731Sjason@lowepower.comsystem.dir_cntrl0.L3CacheMemory.num_data_array_writes 1549 # number of data array writes 259411731Sjason@lowepower.comsystem.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1549 # number of tag array reads 259511731Sjason@lowepower.comsystem.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1549 # number of tag array writes 259611731Sjason@lowepower.comsystem.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 259711308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 259811308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks 259911731Sjason@lowepower.comsystem.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 260011308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses 260111308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses 260211308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue 260311308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 260411308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts 260511308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 260611308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks 260711731Sjason@lowepower.comsystem.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 260811308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses 260911308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits 261011308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses 261111308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate 261211308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses 261311308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits 261411308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses 261511308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate 261611308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level 261711308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table 261811308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.unique_pages 0 # Number of unique pages touched 261911308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 262011308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs 262111308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 262211308Santhony.gutierrez@amd.comsystem.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 262311308Santhony.gutierrez@amd.comsystem.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks 262411731Sjason@lowepower.comsystem.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 262511308Santhony.gutierrez@amd.comsystem.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses 262611308Santhony.gutierrez@amd.comsystem.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses 262711308Santhony.gutierrez@amd.comsystem.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue 262811308Santhony.gutierrez@amd.comsystem.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 262911308Santhony.gutierrez@amd.comsystem.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts 263011308Santhony.gutierrez@amd.comsystem.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 263111308Santhony.gutierrez@amd.comsystem.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks 263211731Sjason@lowepower.comsystem.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 263311308Santhony.gutierrez@amd.comsystem.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses 263411308Santhony.gutierrez@amd.comsystem.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses 263511308Santhony.gutierrez@amd.comsystem.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue 263611308Santhony.gutierrez@amd.comsystem.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 263711308Santhony.gutierrez@amd.comsystem.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts 263811308Santhony.gutierrez@amd.comsystem.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 263911308Santhony.gutierrez@amd.comsystem.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks 264011731Sjason@lowepower.comsystem.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 264111308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses 264211308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_hits 774 # Number of TLB hits 264311308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_misses 4 # Number of TLB misses 264411308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate 264511308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses 264611308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_hits 774 # Number of TLB hits 264711308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_misses 4 # Number of TLB misses 264811308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate 264911308Santhony.gutierrez@amd.comsystem.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level 265011308Santhony.gutierrez@amd.comsystem.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table 265111308Santhony.gutierrez@amd.comsystem.l1_tlb0.unique_pages 4 # Number of unique pages touched 265211308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 265311308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs 265411308Santhony.gutierrez@amd.comsystem.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 265511308Santhony.gutierrez@amd.comsystem.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 265611308Santhony.gutierrez@amd.comsystem.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks 265711731Sjason@lowepower.comsystem.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 265811308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses 265911308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_hits 766 # Number of TLB hits 266011308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_misses 3 # Number of TLB misses 266111308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate 266211308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses 266311308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_hits 766 # Number of TLB hits 266411308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_misses 3 # Number of TLB misses 266511308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate 266611308Santhony.gutierrez@amd.comsystem.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level 266711308Santhony.gutierrez@amd.comsystem.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table 266811308Santhony.gutierrez@amd.comsystem.l1_tlb1.unique_pages 3 # Number of unique pages touched 266911308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 267011308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs 267111308Santhony.gutierrez@amd.comsystem.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 267211308Santhony.gutierrez@amd.comsystem.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 267311308Santhony.gutierrez@amd.comsystem.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks 267411731Sjason@lowepower.comsystem.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 267511308Santhony.gutierrez@amd.comsystem.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses 267611308Santhony.gutierrez@amd.comsystem.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 267711308Santhony.gutierrez@amd.comsystem.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 267811308Santhony.gutierrez@amd.comsystem.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 267911308Santhony.gutierrez@amd.comsystem.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts 268011308Santhony.gutierrez@amd.comsystem.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 268111308Santhony.gutierrez@amd.comsystem.l2_tlb.clk_domain.clock 1000 # Clock period in ticks 268211731Sjason@lowepower.comsystem.l2_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 268311308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses 268411308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_hits 3 # Number of TLB hits 268511308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_misses 5 # Number of TLB misses 268611308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate 268711308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses 268811308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_hits 3 # Number of TLB hits 268911308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_misses 12 # Number of TLB misses 269011308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate 269111308Santhony.gutierrez@amd.comsystem.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level 269211308Santhony.gutierrez@amd.comsystem.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table 269311308Santhony.gutierrez@amd.comsystem.l2_tlb.unique_pages 5 # Number of unique pages touched 269411308Santhony.gutierrez@amd.comsystem.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs 269511308Santhony.gutierrez@amd.comsystem.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs 269611308Santhony.gutierrez@amd.comsystem.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 269711308Santhony.gutierrez@amd.comsystem.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 269811308Santhony.gutierrez@amd.comsystem.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks 269911731Sjason@lowepower.comsystem.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 270011308Santhony.gutierrez@amd.comsystem.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses 270111308Santhony.gutierrez@amd.comsystem.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 270211308Santhony.gutierrez@amd.comsystem.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 270311308Santhony.gutierrez@amd.comsystem.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 270411308Santhony.gutierrez@amd.comsystem.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts 270511308Santhony.gutierrez@amd.comsystem.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 270611308Santhony.gutierrez@amd.comsystem.l3_tlb.clk_domain.clock 1000 # Clock period in ticks 270711731Sjason@lowepower.comsystem.l3_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 270811308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses 270911308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_hits 0 # Number of TLB hits 271011308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_misses 5 # Number of TLB misses 271111308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate 271211308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses 271311308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_hits 0 # Number of TLB hits 271411308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_misses 12 # Number of TLB misses 271511308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate 271611308Santhony.gutierrez@amd.comsystem.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level 271711308Santhony.gutierrez@amd.comsystem.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table 271811308Santhony.gutierrez@amd.comsystem.l3_tlb.unique_pages 5 # Number of unique pages touched 271911308Santhony.gutierrez@amd.comsystem.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs 272011308Santhony.gutierrez@amd.comsystem.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs 272111308Santhony.gutierrez@amd.comsystem.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 272211731Sjason@lowepower.comsystem.piobus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 272311308Santhony.gutierrez@amd.comsystem.piobus.trans_dist::WriteReq 94 # Transaction distribution 272411308Santhony.gutierrez@amd.comsystem.piobus.trans_dist::WriteResp 94 # Transaction distribution 272511308Santhony.gutierrez@amd.comsystem.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) 272611308Santhony.gutierrez@amd.comsystem.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes) 272711308Santhony.gutierrez@amd.comsystem.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes) 272811308Santhony.gutierrez@amd.comsystem.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes) 272911308Santhony.gutierrez@amd.comsystem.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks) 273011308Santhony.gutierrez@amd.comsystem.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) 273111308Santhony.gutierrez@amd.comsystem.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) 273211308Santhony.gutierrez@amd.comsystem.piobus.respLayer0.utilization 0.0 # Layer utilization (%) 273311731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 273411731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.percent_links_utilized 0.007895 273511731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.msg_count.Control::0 1549 273611731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1549 273711731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1561 273811731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1537 273911731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1549 274011731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12392 274111731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12392 274211731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112392 274311731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12296 274411731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12392 274511731Sjason@lowepower.comsystem.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 274611731Sjason@lowepower.comsystem.ruby.network.ext_links1.int_node.percent_links_utilized 0.009908 274711731Sjason@lowepower.comsystem.ruby.network.ext_links1.int_node.msg_count.Control::0 14 274811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 274911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537 275011731Sjason@lowepower.comsystem.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 12 275111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1535 275211731Sjason@lowepower.comsystem.ruby.network.ext_links1.int_node.msg_bytes.Control::0 112 275311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280 275411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664 275511731Sjason@lowepower.comsystem.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 96 275611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12280 275711308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 275811308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 275911308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 276011731Sjason@lowepower.comsystem.tcp_cntrl0.L1cache.num_data_array_reads 8 # number of data array reads 276111308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes 276211369Ssteve.reinhardt@amd.comsystem.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads 276311308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes 276411731Sjason@lowepower.comsystem.tcp_cntrl0.L1cache.num_data_array_stalls 6 # number of stalls caused by data array 276511731Sjason@lowepower.comsystem.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 276611369Ssteve.reinhardt@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP 276711308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers 276811308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 276911308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_ld_misses 2 # loads that miss in the GPU 277011308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP 277111731Sjason@lowepower.comsystem.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers 277211308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 277311731Sjason@lowepower.comsystem.tcp_cntrl0.coalescer.gpu_st_misses 5 # stores that miss in the GPU 277411308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 277511308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 277611308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 277711308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU 277811308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 277911308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 278011308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 278111308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU 278211731Sjason@lowepower.comsystem.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 278311731Sjason@lowepower.comsystem.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 278411731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 278511731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.percent_links_utilized 0.000708 278611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Control::0 1535 278711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Control::1 14 278811731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 14 278911731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 17 279011731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 24 279111731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 31 279211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1525 279311731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 14 279411731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::5 17 279511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Control::0 12280 279611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Control::1 112 279711731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 112 279811731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 136 279911731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 1728 280011731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 2232 280111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 12200 280211731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 112 280311731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::5 136 280411308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits 280511308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 280611308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses 280711731Sjason@lowepower.comsystem.tcp_cntrl1.L1cache.num_data_array_reads 8 # number of data array reads 280811308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes 280911308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_tag_array_reads 25 # number of tag array reads 281011308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes 281111308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array 281211731Sjason@lowepower.comsystem.tcp_cntrl1.L1cache.num_data_array_stalls 6 # number of stalls caused by data array 281311731Sjason@lowepower.comsystem.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 281411308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP 281511308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers 281611308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 281711308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 281811308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP 281911731Sjason@lowepower.comsystem.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers 282011308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 282111731Sjason@lowepower.comsystem.tcp_cntrl1.coalescer.gpu_st_misses 4 # stores that miss in the GPU 282211308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 282311308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 282411308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 282511308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU 282611308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 282711308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 282811308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 282911308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU 283011731Sjason@lowepower.comsystem.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 283111731Sjason@lowepower.comsystem.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 283211308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 283311308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 283411308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 283511731Sjason@lowepower.comsystem.sqc_cntrl0.L1cache.num_data_array_reads 70 # number of data array reads 283611731Sjason@lowepower.comsystem.sqc_cntrl0.L1cache.num_data_array_writes 3 # number of data array writes 283711731Sjason@lowepower.comsystem.sqc_cntrl0.L1cache.num_tag_array_reads 70 # number of tag array reads 283811731Sjason@lowepower.comsystem.sqc_cntrl0.L1cache.num_tag_array_writes 3 # number of tag array writes 283911731Sjason@lowepower.comsystem.sqc_cntrl0.L1cache.num_data_array_stalls 28 # number of stalls caused by data array 284011731Sjason@lowepower.comsystem.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 284111731Sjason@lowepower.comsystem.sqc_cntrl0.sequencer.load_waiting_on_load 75 # Number of times a load aliased with a pending load 284211731Sjason@lowepower.comsystem.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 284311308Santhony.gutierrez@amd.comsystem.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 284411308Santhony.gutierrez@amd.comsystem.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses 284511308Santhony.gutierrez@amd.comsystem.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses 284611731Sjason@lowepower.comsystem.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 284711308Santhony.gutierrez@amd.comsystem.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits 284811308Santhony.gutierrez@amd.comsystem.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses 284911308Santhony.gutierrez@amd.comsystem.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses 285011731Sjason@lowepower.comsystem.tccdir_cntrl0.directory.num_tag_array_reads 1552 # number of tag array reads 285111731Sjason@lowepower.comsystem.tccdir_cntrl0.directory.num_tag_array_writes 25 # number of tag array writes 285211731Sjason@lowepower.comsystem.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 285311731Sjason@lowepower.comsystem.ruby.network.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 285411731Sjason@lowepower.comsystem.ruby.network.msg_count.Control 3112 285511731Sjason@lowepower.comsystem.ruby.network.msg_count.Request_Control 3115 285611731Sjason@lowepower.comsystem.ruby.network.msg_count.Response_Data 3153 285711731Sjason@lowepower.comsystem.ruby.network.msg_count.Response_Control 3074 285811731Sjason@lowepower.comsystem.ruby.network.msg_count.Unblock_Control 3115 285911731Sjason@lowepower.comsystem.ruby.network.msg_byte.Control 24896 286011731Sjason@lowepower.comsystem.ruby.network.msg_byte.Request_Control 24920 286111731Sjason@lowepower.comsystem.ruby.network.msg_byte.Response_Data 227016 286211731Sjason@lowepower.comsystem.ruby.network.msg_byte.Response_Control 24592 286311731Sjason@lowepower.comsystem.ruby.network.msg_byte.Unblock_Control 24920 286411308Santhony.gutierrez@amd.comsystem.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 286511308Santhony.gutierrez@amd.comsystem.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks 286611731Sjason@lowepower.comsystem.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 286711731Sjason@lowepower.comsystem.sqc_coalescer.uncoalesced_accesses 70 # Number of uncoalesced TLB accesses 286811731Sjason@lowepower.comsystem.sqc_coalescer.coalesced_accesses 50 # Number of coalesced TLB accesses 286911731Sjason@lowepower.comsystem.sqc_coalescer.queuing_cycles 100000 # Number of cycles spent in queue 287011731Sjason@lowepower.comsystem.sqc_coalescer.local_queuing_cycles 100000 # Number of cycles spent in queue for all incoming reqs 287111731Sjason@lowepower.comsystem.sqc_coalescer.local_latency 1428.571429 # Avg. latency over all incoming pkts 287211308Santhony.gutierrez@amd.comsystem.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 287311308Santhony.gutierrez@amd.comsystem.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks 287411731Sjason@lowepower.comsystem.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 287511731Sjason@lowepower.comsystem.sqc_tlb.local_TLB_accesses 50 # Number of TLB accesses 287611731Sjason@lowepower.comsystem.sqc_tlb.local_TLB_hits 49 # Number of TLB hits 287711308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_TLB_misses 1 # Number of TLB misses 287811731Sjason@lowepower.comsystem.sqc_tlb.local_TLB_miss_rate 2 # TLB miss rate 287911731Sjason@lowepower.comsystem.sqc_tlb.global_TLB_accesses 70 # Number of TLB accesses 288011731Sjason@lowepower.comsystem.sqc_tlb.global_TLB_hits 62 # Number of TLB hits 288111308Santhony.gutierrez@amd.comsystem.sqc_tlb.global_TLB_misses 8 # Number of TLB misses 288211731Sjason@lowepower.comsystem.sqc_tlb.global_TLB_miss_rate 11.428571 # TLB miss rate 288311731Sjason@lowepower.comsystem.sqc_tlb.access_cycles 70008 # Cycles spent accessing this TLB level 288411308Santhony.gutierrez@amd.comsystem.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table 288511308Santhony.gutierrez@amd.comsystem.sqc_tlb.unique_pages 1 # Number of unique pages touched 288611731Sjason@lowepower.comsystem.sqc_tlb.local_cycles 50001 # Number of cycles spent in queue for all incoming reqs 288711731Sjason@lowepower.comsystem.sqc_tlb.local_latency 1000.020000 # Avg. latency over incoming coalesced reqs 288811308Santhony.gutierrez@amd.comsystem.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 288911731Sjason@lowepower.comsystem.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states 289011731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005552 289111731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1549 289211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12 289311731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1537 289411731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1549 289511731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12392 289611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 864 289711731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12296 289811731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12392 289911731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016188 290011731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 14 290111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2 1535 290211731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 112 290311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2 110520 290411731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001944 290511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0 1535 290611731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 14 290711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0 12280 290811731Sjason@lowepower.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 1008 290911731Sjason@lowepower.comsystem.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016188 291011731Sjason@lowepower.comsystem.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 14 291111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2 1535 291211731Sjason@lowepower.comsystem.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 112 291311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2 110520 291411731Sjason@lowepower.comsystem.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003629 291511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0 1535 291611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2 2 291711731Sjason@lowepower.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 12 291811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_count.Unblock_Control::4 1535 291911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0 12280 292011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2 144 292111731Sjason@lowepower.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 96 292211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4 12280 292311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.000083 292411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::1 8 292511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::3 7 292611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Control::1 64 292711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::3 504 292811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.link_utilization 0.000081 292911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_count.Control::1 6 293011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3 7 293111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Control::1 48 293211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3 504 293311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.link_utilization 0 293411731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.002132 293511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_count.Control::0 1535 293611731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_count.Request_Control::1 17 293711731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::2 14 293811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::3 14 293911731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_count.Unblock_Control::5 17 294011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Control::0 12280 294111731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Request_Control::1 136 294211731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::2 1008 294311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::3 1008 294411731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Unblock_Control::5 136 294511731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.000032 294611731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Data::3 3 294711731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Data::3 216 294811731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.throttle5.link_utilization 0.001923 294911731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_count.Request_Control::0 14 295011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Data::2 10 295111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Control::2 1525 295211731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_count.Unblock_Control::4 14 295311731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Request_Control::0 112 295411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Data::2 720 295511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Control::2 12200 295611731Sjason@lowepower.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Unblock_Control::4 112 295711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Load_L1miss 180 0.00% 0.00% 295811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Load_L1hit 16155 0.00% 0.00% 295911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.Ifetch0_L1hit 86007 0.00% 0.00% 296011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.Ifetch0_L1miss 1088 0.00% 0.00% 296111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Store_L1miss 325 0.00% 0.00% 296211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Store_L1hit 10448 0.00% 0.00% 296311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.NB_AckS 1043 0.00% 0.00% 296411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.NB_AckM 326 0.00% 0.00% 296511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.NB_AckE 166 0.00% 0.00% 296611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L1I_Repl 589 0.00% 0.00% 296711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L1D0_Repl 24 0.00% 0.00% 296811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L2_to_L1D0 5 0.00% 0.00% 296911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L2_to_L1I 54 0.00% 0.00% 297011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.PrbInvData 9 0.00% 0.00% 297111731Sjason@lowepower.comsystem.ruby.CorePair_Controller.PrbShrData 5 0.00% 0.00% 297211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.C0_Load_L1miss 175 0.00% 0.00% 297311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00% 297411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00% 297511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.PrbInvData 8 0.00% 0.00% 297611731Sjason@lowepower.comsystem.ruby.CorePair_Controller.I.PrbShrData 3 0.00% 0.00% 297711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.C0_Load_L1hit 635 0.00% 0.00% 297811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.Ifetch0_L1hit 86007 0.00% 0.00% 297911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.Ifetch0_L1miss 54 0.00% 0.00% 298011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.L1I_Repl 589 0.00% 0.00% 298111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.C0_Load_L1miss 2 0.00% 0.00% 298211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.C0_Load_L1hit 2721 0.00% 0.00% 298311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.C0_Store_L1hit 46 0.00% 0.00% 298411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.L1D0_Repl 16 0.00% 0.00% 298511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.PrbShrData 1 0.00% 0.00% 298611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.O.C0_Load_L1hit 3 0.00% 0.00% 298711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.O.C0_Store_L1hit 1 0.00% 0.00% 298811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.C0_Load_L1miss 3 0.00% 0.00% 298911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.C0_Load_L1hit 12796 0.00% 0.00% 299011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.C0_Store_L1hit 10401 0.00% 0.00% 299111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.L1D0_Repl 8 0.00% 0.00% 299211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.PrbInvData 1 0.00% 0.00% 299311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.PrbShrData 1 0.00% 0.00% 299411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_M0.NB_AckM 325 0.00% 0.00% 299511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_E0S.NB_AckS 9 0.00% 0.00% 299611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_E0S.NB_AckE 166 0.00% 0.00% 299711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.Si_F0.L2_to_L1I 54 0.00% 0.00% 299811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.O_M0.NB_AckM 1 0.00% 0.00% 299911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00% 300011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00% 300111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0_F.L2_to_L1D0 3 0.00% 0.00% 300211731Sjason@lowepower.comsystem.ruby.Directory_Controller.RdBlkS 1037 0.00% 0.00% 300311308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.RdBlkM 335 0.00% 0.00% 300411308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.RdBlk 177 0.00% 0.00% 300511731Sjason@lowepower.comsystem.ruby.Directory_Controller.CPUPrbResp 1549 0.00% 0.00% 300611731Sjason@lowepower.comsystem.ruby.Directory_Controller.ProbeAcksComplete 1549 0.00% 0.00% 300711731Sjason@lowepower.comsystem.ruby.Directory_Controller.MemData 1549 0.00% 0.00% 300811731Sjason@lowepower.comsystem.ruby.Directory_Controller.CoreUnblock 1549 0.00% 0.00% 300911731Sjason@lowepower.comsystem.ruby.Directory_Controller.U.RdBlkS 1037 0.00% 0.00% 301011308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.RdBlkM 335 0.00% 0.00% 301111308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.RdBlk 177 0.00% 0.00% 301211731Sjason@lowepower.comsystem.ruby.Directory_Controller.BS_M.MemData 35 0.00% 0.00% 301311731Sjason@lowepower.comsystem.ruby.Directory_Controller.BM_M.MemData 18 0.00% 0.00% 301411731Sjason@lowepower.comsystem.ruby.Directory_Controller.B_M.MemData 11 0.00% 0.00% 301511731Sjason@lowepower.comsystem.ruby.Directory_Controller.BS_PM.CPUPrbResp 35 0.00% 0.00% 301611731Sjason@lowepower.comsystem.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 35 0.00% 0.00% 301711731Sjason@lowepower.comsystem.ruby.Directory_Controller.BS_PM.MemData 1002 0.00% 0.00% 301811731Sjason@lowepower.comsystem.ruby.Directory_Controller.BM_PM.CPUPrbResp 18 0.00% 0.00% 301911731Sjason@lowepower.comsystem.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 18 0.00% 0.00% 302011731Sjason@lowepower.comsystem.ruby.Directory_Controller.BM_PM.MemData 317 0.00% 0.00% 302111731Sjason@lowepower.comsystem.ruby.Directory_Controller.B_PM.CPUPrbResp 11 0.00% 0.00% 302211731Sjason@lowepower.comsystem.ruby.Directory_Controller.B_PM.ProbeAcksComplete 11 0.00% 0.00% 302311731Sjason@lowepower.comsystem.ruby.Directory_Controller.B_PM.MemData 166 0.00% 0.00% 302411731Sjason@lowepower.comsystem.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1002 0.00% 0.00% 302511731Sjason@lowepower.comsystem.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1002 0.00% 0.00% 302611731Sjason@lowepower.comsystem.ruby.Directory_Controller.BM_Pm.CPUPrbResp 317 0.00% 0.00% 302711731Sjason@lowepower.comsystem.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 317 0.00% 0.00% 302811731Sjason@lowepower.comsystem.ruby.Directory_Controller.B_Pm.CPUPrbResp 166 0.00% 0.00% 302911731Sjason@lowepower.comsystem.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 166 0.00% 0.00% 303011731Sjason@lowepower.comsystem.ruby.Directory_Controller.B.CoreUnblock 1549 0.00% 0.00% 303111680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::bucket_size 64 303211680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::max_bucket 639 303311312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::samples 16335 303411680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::mean 4.314539 303511680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::gmean 2.104196 303611680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::stdev 22.794494 303711680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr | 16160 98.93% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 166 1.02% 99.94% | 6 0.04% 99.98% | 1 0.01% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 2 0.01% 100.00% 303811312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::total 16335 303911312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_coalsr::bucket_size 64 304011312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_coalsr::max_bucket 639 304111369Ssteve.reinhardt@amd.comsystem.ruby.LD.latency_hist_coalsr::samples 9 304211731Sjason@lowepower.comsystem.ruby.LD.latency_hist_coalsr::mean 133.666667 304311731Sjason@lowepower.comsystem.ruby.LD.latency_hist_coalsr::gmean 19.860866 304411731Sjason@lowepower.comsystem.ruby.LD.latency_hist_coalsr::stdev 158.801763 304511731Sjason@lowepower.comsystem.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 304611369Ssteve.reinhardt@amd.comsystem.ruby.LD.latency_hist_coalsr::total 9 304711680SCurtis.Dunham@arm.comsystem.ruby.LD.hit_latency_hist_seqr::bucket_size 64 304811680SCurtis.Dunham@arm.comsystem.ruby.LD.hit_latency_hist_seqr::max_bucket 639 304911312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::samples 175 305011680SCurtis.Dunham@arm.comsystem.ruby.LD.hit_latency_hist_seqr::mean 217.531429 305111680SCurtis.Dunham@arm.comsystem.ruby.LD.hit_latency_hist_seqr::gmean 214.409561 305211680SCurtis.Dunham@arm.comsystem.ruby.LD.hit_latency_hist_seqr::stdev 50.482703 305311680SCurtis.Dunham@arm.comsystem.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 6 3.43% 98.29% | 1 0.57% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 2 1.14% 100.00% 305411312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::total 175 305511312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::bucket_size 4 305611312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::max_bucket 39 305711312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::samples 16160 305811312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::mean 2.005569 305911312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::gmean 2.001425 306011312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::stdev 0.316580 306111312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 306211312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::total 16160 306311312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_coalsr::bucket_size 64 306411312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_coalsr::max_bucket 639 306511369Ssteve.reinhardt@amd.comsystem.ruby.LD.miss_latency_hist_coalsr::samples 9 306611731Sjason@lowepower.comsystem.ruby.LD.miss_latency_hist_coalsr::mean 133.666667 306711731Sjason@lowepower.comsystem.ruby.LD.miss_latency_hist_coalsr::gmean 19.860866 306811731Sjason@lowepower.comsystem.ruby.LD.miss_latency_hist_coalsr::stdev 158.801763 306911731Sjason@lowepower.comsystem.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 307011369Ssteve.reinhardt@amd.comsystem.ruby.LD.miss_latency_hist_coalsr::total 9 307111312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::bucket_size 64 307211312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::max_bucket 639 307311312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::samples 10412 307411680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::mean 8.469939 307511680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::gmean 2.309412 307611680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::stdev 36.833690 307711680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 314 3.02% 99.92% | 1 0.01% 99.93% | 5 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% 307811312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::total 10412 307911731Sjason@lowepower.comsystem.ruby.ST.latency_hist_coalsr::bucket_size 64 308011731Sjason@lowepower.comsystem.ruby.ST.latency_hist_coalsr::max_bucket 639 308111312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_coalsr::samples 16 308211731Sjason@lowepower.comsystem.ruby.ST.latency_hist_coalsr::mean 184.500000 308311731Sjason@lowepower.comsystem.ruby.ST.latency_hist_coalsr::gmean 27.004823 308411731Sjason@lowepower.comsystem.ruby.ST.latency_hist_coalsr::stdev 190.921974 308511731Sjason@lowepower.comsystem.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 4 25.00% 75.00% | 4 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 308611312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_coalsr::total 16 308711312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::bucket_size 64 308811312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::max_bucket 639 308911312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::samples 322 309011680SCurtis.Dunham@arm.comsystem.ruby.ST.hit_latency_hist_seqr::mean 211.208075 309111680SCurtis.Dunham@arm.comsystem.ruby.ST.hit_latency_hist_seqr::gmean 209.444324 309211680SCurtis.Dunham@arm.comsystem.ruby.ST.hit_latency_hist_seqr::stdev 38.157121 309311680SCurtis.Dunham@arm.comsystem.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 314 97.52% 97.52% | 1 0.31% 97.83% | 5 1.55% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 2 0.62% 100.00% 309411312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::total 322 309511312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::bucket_size 1 309611312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::max_bucket 9 309711312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::samples 10090 309811312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::mean 2 309911312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::gmean 2.000000 310011312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 310111312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::total 10090 310211731Sjason@lowepower.comsystem.ruby.ST.miss_latency_hist_coalsr::bucket_size 64 310311731Sjason@lowepower.comsystem.ruby.ST.miss_latency_hist_coalsr::max_bucket 639 310411312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_coalsr::samples 16 310511731Sjason@lowepower.comsystem.ruby.ST.miss_latency_hist_coalsr::mean 184.500000 310611731Sjason@lowepower.comsystem.ruby.ST.miss_latency_hist_coalsr::gmean 27.004823 310711731Sjason@lowepower.comsystem.ruby.ST.miss_latency_hist_coalsr::stdev 190.921974 310811731Sjason@lowepower.comsystem.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 4 25.00% 75.00% | 4 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 310911312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_coalsr::total 16 311011312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.latency_hist_coalsr::bucket_size 64 311111312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.latency_hist_coalsr::max_bucket 639 311211312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.latency_hist_coalsr::samples 2 311311731Sjason@lowepower.comsystem.ruby.ATOMIC.latency_hist_coalsr::mean 295.500000 311411731Sjason@lowepower.comsystem.ruby.ATOMIC.latency_hist_coalsr::gmean 293.237105 311511731Sjason@lowepower.comsystem.ruby.ATOMIC.latency_hist_coalsr::stdev 51.618795 311611312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 311711312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.latency_hist_coalsr::total 2 311811312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr::bucket_size 64 311911312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr::max_bucket 639 312011312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr::samples 2 312111731Sjason@lowepower.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr::mean 295.500000 312211731Sjason@lowepower.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 293.237105 312311731Sjason@lowepower.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 51.618795 312411312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 312511312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr::total 2 312611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::bucket_size 64 312711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::max_bucket 639 312811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::samples 87095 312911680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr::mean 4.485148 313011680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr::gmean 2.116532 313111680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr::stdev 22.815865 313211680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr | 86061 98.81% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1006 1.16% 99.97% | 11 0.01% 99.98% | 12 0.01% 99.99% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% 313311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::total 87095 313411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 64 313511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 639 313611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::samples 1034 313711680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.hit_latency_hist_seqr::mean 210.386847 313811680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.hit_latency_hist_seqr::gmean 209.145816 313911680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.hit_latency_hist_seqr::stdev 30.434753 314011680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1006 97.29% 97.29% | 11 1.06% 98.36% | 12 1.16% 99.52% | 2 0.19% 99.71% | 0 0.00% 99.71% | 0 0.00% 99.71% | 3 0.29% 100.00% 314111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::total 1034 314211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 4 314311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 39 314411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::samples 86061 314511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::mean 2.011294 314611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::gmean 2.002892 314711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::stdev 0.450747 314811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr | 86007 99.94% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 54 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 314911312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::total 86061 315011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::bucket_size 32 315111312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::max_bucket 319 315211312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::samples 341 315311312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::mean 4.392962 315411312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::gmean 2.111743 315511312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::stdev 21.996747 315611312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr | 337 98.83% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 4 1.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 315711312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::total 341 315811312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::bucket_size 32 315911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::max_bucket 319 316011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::samples 4 316111312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::mean 206 316211312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::gmean 206.000000 316311312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 316411312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::total 4 316511312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::bucket_size 1 316611312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::max_bucket 9 316711312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::samples 337 316811312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::mean 2 316911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::gmean 2.000000 317011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 317111312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::total 337 317211312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::bucket_size 1 317311312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::max_bucket 9 317411312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::samples 10 317511312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::mean 2 317611312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::gmean 2 317711312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 317811312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::total 10 317911312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::bucket_size 1 318011312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::max_bucket 9 318111312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::samples 10 318211312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::mean 2 318311312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::gmean 2 318411312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 318511312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::total 10 318611312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::bucket_size 1 318711312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::max_bucket 9 318811312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::samples 10 318911312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::mean 2 319011312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::gmean 2 319111312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 319211312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::total 10 319311312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist_seqr::bucket_size 1 319411312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist_seqr::max_bucket 9 319511312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist_seqr::samples 10 319611312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist_seqr::mean 2 319711312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist_seqr::gmean 2 319811312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 319911312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist_seqr::total 10 320011312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size 1 320111312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket 9 320211312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::samples 112609 320311312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 2 320411312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 2.000000 320511312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 112609 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 320611312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::total 112609 320711312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist_seqr::bucket_size 4 320811312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist_seqr::max_bucket 39 320911312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist_seqr::samples 59 321011312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist_seqr::mean 20 321111312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist_seqr::gmean 20.000000 321211312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 59 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 321311312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist_seqr::total 59 321411312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size 64 321511312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket 639 321611312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::samples 1535 321711680SCurtis.Dunham@arm.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::mean 211.362215 321811680SCurtis.Dunham@arm.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::gmean 209.793806 321911680SCurtis.Dunham@arm.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::stdev 34.965177 322011680SCurtis.Dunham@arm.comsystem.ruby.Directory.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1490 97.07% 97.07% | 18 1.17% 98.24% | 18 1.17% 99.41% | 2 0.13% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 7 0.46% 100.00% 322111312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::total 1535 322211312Santhony.gutierrez@amd.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 64 322311312Santhony.gutierrez@amd.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 639 322411312Santhony.gutierrez@amd.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 3 322511731Sjason@lowepower.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 338.666667 322611731Sjason@lowepower.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 338.633640 322711731Sjason@lowepower.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 5.773503 322811731Sjason@lowepower.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 322911312Santhony.gutierrez@amd.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 3 323011312Santhony.gutierrez@amd.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1 323111312Santhony.gutierrez@amd.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9 323211369Ssteve.reinhardt@amd.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::samples 13 323311731Sjason@lowepower.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::mean 2.153846 323411731Sjason@lowepower.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 2.109532 323511731Sjason@lowepower.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.554700 323611731Sjason@lowepower.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 12 92.31% 92.31% | 0 0.00% 92.31% | 1 7.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 323711369Ssteve.reinhardt@amd.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::total 13 323811680SCurtis.Dunham@arm.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 64 323911680SCurtis.Dunham@arm.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 639 324011312Santhony.gutierrez@amd.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 11 324111731Sjason@lowepower.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 336.545455 324211731Sjason@lowepower.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 330.845159 324311731Sjason@lowepower.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 64.151950 324411731Sjason@lowepower.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 9.09% 9.09% | 2 18.18% 27.27% | 4 36.36% 63.64% | 4 36.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 324511312Santhony.gutierrez@amd.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 11 324611312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 324711312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 324811312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::samples 16155 324911312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 325011312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 325111312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 16155 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 325211312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::total 16155 325311312Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::bucket_size 4 325411312Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::max_bucket 39 325511312Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::samples 5 325611312Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::mean 20 325711312Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::gmean 20.000000 325811312Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 325911312Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::total 5 326011680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 326111680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 326211312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::samples 175 326311680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 217.531429 326411680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 214.409561 326511680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev 50.482703 326611680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 6 3.43% 98.29% | 1 0.57% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 2 1.14% 100.00% 326711312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 175 326811312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 326911312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 327011312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 2 327111731Sjason@lowepower.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 342 327211731Sjason@lowepower.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 342.000000 327311731Sjason@lowepower.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 327411312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 2 327511312Santhony.gutierrez@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 327611312Santhony.gutierrez@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 327711369Ssteve.reinhardt@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 5 327811369Ssteve.reinhardt@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 2.400000 327911369Ssteve.reinhardt@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.297397 328011369Ssteve.reinhardt@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.894427 328111369Ssteve.reinhardt@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 80.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 328211369Ssteve.reinhardt@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 5 328311731Sjason@lowepower.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 328411731Sjason@lowepower.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 328511312Santhony.gutierrez@amd.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 2 328611731Sjason@lowepower.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 253.500000 328711731Sjason@lowepower.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 253.440328 328811731Sjason@lowepower.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 7.778175 328911731Sjason@lowepower.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% 329011312Santhony.gutierrez@amd.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 2 329111312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 329211312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 329311312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 10090 329411312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 329511312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 329611312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 329711312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 10090 329811312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 329911312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 330011312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 322 330111680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 211.208075 330211680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 209.444324 330311680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 38.157121 330411680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 314 97.52% 97.52% | 1 0.31% 97.83% | 5 1.55% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 2 0.62% 100.00% 330511312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 322 330611312Santhony.gutierrez@amd.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 330711312Santhony.gutierrez@amd.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 330811312Santhony.gutierrez@amd.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 8 330911731Sjason@lowepower.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 2 331011731Sjason@lowepower.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 2 331111731Sjason@lowepower.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 331211312Santhony.gutierrez@amd.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 8 331311731Sjason@lowepower.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64 331411731Sjason@lowepower.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639 331511312Santhony.gutierrez@amd.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 8 331611731Sjason@lowepower.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 367 331711731Sjason@lowepower.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 364.630235 331811731Sjason@lowepower.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 44.510031 331911731Sjason@lowepower.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 50.00% 50.00% | 4 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 332011312Santhony.gutierrez@amd.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 8 332111312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 332211312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 332311312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 1 332411731Sjason@lowepower.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 332 332511731Sjason@lowepower.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 332.000000 332611312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev nan 332711312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 332811312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 1 332911312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 333011312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 333111312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::samples 1 333211731Sjason@lowepower.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 259 333311731Sjason@lowepower.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 259.000000 333411312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::stdev nan 333511312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 333611312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::total 1 333711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 333811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 333911312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::samples 86007 334011312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 334111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 334211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 86007 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 334311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::total 86007 334411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::bucket_size 4 334511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::max_bucket 39 334611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::samples 54 334711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::mean 20 334811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::gmean 20.000000 334911312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 54 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 335011312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::total 54 335111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 335211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 335311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1034 335411680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 210.386847 335511680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 209.145816 335611680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev 30.434753 335711680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1006 97.29% 97.29% | 11 1.06% 98.36% | 12 1.16% 99.52% | 2 0.19% 99.71% | 0 0.00% 99.71% | 0 0.00% 99.71% | 3 0.29% 100.00% 335811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1034 335911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 336011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 336111312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::samples 337 336211312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 336311312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 336411312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 336511312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::total 337 336611312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::bucket_size 32 336711312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::max_bucket 319 336811312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::samples 4 336911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::mean 206 337011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::gmean 206.000000 337111312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 337211312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::total 4 337311312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 337411312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 337511312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::samples 10 337611312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 337711312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2 337811312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 337911312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::total 10 338011312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 338111312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 338211312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::samples 10 338311312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 338411312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2 338511312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 338611312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::total 10 338711731Sjason@lowepower.comsystem.ruby.SQC_Controller.Fetch 70 0.00% 0.00% 338811731Sjason@lowepower.comsystem.ruby.SQC_Controller.TCC_AckS 3 0.00% 0.00% 338911731Sjason@lowepower.comsystem.ruby.SQC_Controller.I.Fetch 3 0.00% 0.00% 339011731Sjason@lowepower.comsystem.ruby.SQC_Controller.S.Fetch 67 0.00% 0.00% 339111731Sjason@lowepower.comsystem.ruby.SQC_Controller.I_S.TCC_AckS 3 0.00% 0.00% 339211731Sjason@lowepower.comsystem.ruby.TCCdir_Controller.RdBlk 54 0.00% 0.00% 339311731Sjason@lowepower.comsystem.ruby.TCCdir_Controller.RdBlkM 34 0.00% 0.00% 339411731Sjason@lowepower.comsystem.ruby.TCCdir_Controller.RdBlkS 3 0.00% 0.00% 339511308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.CPUPrbResp 14 0.00% 0.00% 339611308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.ProbeAcksComplete 13 0.00% 0.00% 339711731Sjason@lowepower.comsystem.ruby.TCCdir_Controller.CoreUnblock 15 0.00% 0.00% 339811308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00% 339911731Sjason@lowepower.comsystem.ruby.TCCdir_Controller.NB_AckS 5 0.00% 0.00% 340011308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.NB_AckM 9 0.00% 0.00% 340111308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.PrbInvData 326 0.00% 0.00% 340211308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.PrbShrData 1209 0.00% 0.00% 340311308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I.RdBlk 2 0.00% 0.00% 340411308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I.RdBlkM 9 0.00% 0.00% 340511731Sjason@lowepower.comsystem.ruby.TCCdir_Controller.I.RdBlkS 3 0.00% 0.00% 340611308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I.PrbInvData 325 0.00% 0.00% 340711308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I.PrbShrData 1200 0.00% 0.00% 340811308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.S.RdBlk 2 0.00% 0.00% 340911308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.S.PrbInvData 1 0.00% 0.00% 341011308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.M.RdBlkM 1 0.00% 0.00% 341111308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.M.PrbShrData 9 0.00% 0.00% 341211308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.CP_I.CPUPrbResp 2 0.00% 0.00% 341311308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 1 0.00% 0.00% 341411308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.CP_O.CPUPrbResp 9 0.00% 0.00% 341511308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 9 0.00% 0.00% 341611731Sjason@lowepower.comsystem.ruby.TCCdir_Controller.I_M.RdBlkM 20 0.00% 0.00% 341711308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I_M.NB_AckM 9 0.00% 0.00% 341811731Sjason@lowepower.comsystem.ruby.TCCdir_Controller.I_ES.RdBlk 41 0.00% 0.00% 341911308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I_ES.NB_AckS 2 0.00% 0.00% 342011731Sjason@lowepower.comsystem.ruby.TCCdir_Controller.I_S.NB_AckS 3 0.00% 0.00% 342111308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BBS_S.CPUPrbResp 2 0.00% 0.00% 342211308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BBS_S.ProbeAcksComplete 2 0.00% 0.00% 342311308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 1 0.00% 0.00% 342411308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 1 0.00% 0.00% 342511308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BB_M.CoreUnblock 1 0.00% 0.00% 342611308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BB_S.LastCoreUnblock 2 0.00% 0.00% 342711731Sjason@lowepower.comsystem.ruby.TCCdir_Controller.BBB_S.RdBlk 9 0.00% 0.00% 342811731Sjason@lowepower.comsystem.ruby.TCCdir_Controller.BBB_S.CoreUnblock 5 0.00% 0.00% 342911731Sjason@lowepower.comsystem.ruby.TCCdir_Controller.BBB_M.RdBlkM 4 0.00% 0.00% 343011308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BBB_M.CoreUnblock 9 0.00% 0.00% 343111369Ssteve.reinhardt@amd.comsystem.ruby.TCP_Controller.Load | 4 44.44% 44.44% | 5 55.56% 100.00% 343211369Ssteve.reinhardt@amd.comsystem.ruby.TCP_Controller.Load::total 9 343311308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Store | 9 50.00% 50.00% | 9 50.00% 100.00% 343411308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Store::total 18 343511308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_AckS | 2 50.00% 50.00% | 2 50.00% 100.00% 343611308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_AckS::total 4 343711308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00% 343811308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_AckM::total 10 343911731Sjason@lowepower.comsystem.ruby.TCP_Controller.PrbInvData | 2 66.67% 66.67% | 1 33.33% 100.00% 344011308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.PrbInvData::total 3 344111731Sjason@lowepower.comsystem.ruby.TCP_Controller.PrbShrData | 6 54.55% 54.55% | 5 45.45% 100.00% 344211308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.PrbShrData::total 11 344311308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00% 344411308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Load::total 4 344511308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Store | 5 50.00% 50.00% | 5 50.00% 100.00% 344611308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Store::total 10 344711369Ssteve.reinhardt@amd.comsystem.ruby.TCP_Controller.S.Load | 2 40.00% 40.00% | 3 60.00% 100.00% 344811369Ssteve.reinhardt@amd.comsystem.ruby.TCP_Controller.S.Load::total 5 344911308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.S.PrbInvData | 1 50.00% 50.00% | 1 50.00% 100.00% 345011308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.S.PrbInvData::total 2 345111308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.S.PrbShrData | 2 100.00% 100.00% | 0 0.00% 100.00% 345211308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.S.PrbShrData::total 2 345311308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.M.Store | 4 50.00% 50.00% | 4 50.00% 100.00% 345411308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.M.Store::total 8 345511731Sjason@lowepower.comsystem.ruby.TCP_Controller.M.PrbInvData | 1 100.00% 100.00% | 0 0.00% 100.00% 345611308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.M.PrbInvData::total 1 345711731Sjason@lowepower.comsystem.ruby.TCP_Controller.M.PrbShrData | 4 44.44% 44.44% | 5 55.56% 100.00% 345811308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.M.PrbShrData::total 9 345911308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I_M.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00% 346011308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I_M.TCC_AckM::total 10 346111308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I_ES.TCC_AckS | 2 50.00% 50.00% | 2 50.00% 100.00% 346211308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I_ES.TCC_AckS::total 4 346311308Santhony.gutierrez@amd.com 346411308Santhony.gutierrez@amd.com---------- End Simulation Statistics ---------- 3465