stats.txt revision 11312
111308Santhony.gutierrez@amd.com 211308Santhony.gutierrez@amd.com---------- Begin Simulation Statistics ---------- 311308Santhony.gutierrez@amd.comsim_seconds 0.000663 # Number of seconds simulated 411308Santhony.gutierrez@amd.comsim_ticks 663454500 # Number of ticks simulated 511308Santhony.gutierrez@amd.comfinal_tick 663454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611308Santhony.gutierrez@amd.comsim_freq 1000000000000 # Frequency of simulated ticks 711312Santhony.gutierrez@amd.comhost_inst_rate 74039 # Simulator instruction rate (inst/s) 811312Santhony.gutierrez@amd.comhost_op_rate 152254 # Simulator op (including micro ops) rate (op/s) 911312Santhony.gutierrez@amd.comhost_tick_rate 733530611 # Simulator tick rate (ticks/s) 1011312Santhony.gutierrez@amd.comhost_mem_usage 1301780 # Number of bytes of host memory used 1111312Santhony.gutierrez@amd.comhost_seconds 0.90 # Real time elapsed on the host 1211308Santhony.gutierrez@amd.comsim_insts 66963 # Number of instructions simulated 1311308Santhony.gutierrez@amd.comsim_ops 137705 # Number of ops (including micro ops) simulated 1411308Santhony.gutierrez@amd.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511308Santhony.gutierrez@amd.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytes_read::dir_cntrl0 99264 # Number of bytes read from this memory 1711308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytes_read::total 99264 # Number of bytes read from this memory 1811308Santhony.gutierrez@amd.comsystem.mem_ctrls.num_reads::dir_cntrl0 1551 # Number of read requests responded to by this memory 1911308Santhony.gutierrez@amd.comsystem.mem_ctrls.num_reads::total 1551 # Number of read requests responded to by this memory 2011308Santhony.gutierrez@amd.comsystem.mem_ctrls.bw_read::dir_cntrl0 149616892 # Total read bandwidth from this memory (bytes/s) 2111308Santhony.gutierrez@amd.comsystem.mem_ctrls.bw_read::total 149616892 # Total read bandwidth from this memory (bytes/s) 2211308Santhony.gutierrez@amd.comsystem.mem_ctrls.bw_total::dir_cntrl0 149616892 # Total bandwidth to/from this memory (bytes/s) 2311308Santhony.gutierrez@amd.comsystem.mem_ctrls.bw_total::total 149616892 # Total bandwidth to/from this memory (bytes/s) 2411308Santhony.gutierrez@amd.comsystem.mem_ctrls.readReqs 1551 # Number of read requests accepted 2511308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeReqs 0 # Number of write requests accepted 2611308Santhony.gutierrez@amd.comsystem.mem_ctrls.readBursts 1551 # Number of DRAM read bursts, including those serviced by the write queue 2711308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 2811308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesReadDRAM 99264 # Total number of bytes read from DRAM 2911308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue 3011308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM 3111308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesReadSys 99264 # Total read bytes from the system interface side 3211308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side 3311308Santhony.gutierrez@amd.comsystem.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 3411308Santhony.gutierrez@amd.comsystem.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 3511308Santhony.gutierrez@amd.comsystem.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 3611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts 3711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts 3811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts 3911308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts 4011308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts 4111308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts 4211308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts 4311308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts 4411308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts 4511308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts 4611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::10 174 # Per bank write bursts 4711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::11 90 # Per bank write bursts 4811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::12 222 # Per bank write bursts 4911308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::13 125 # Per bank write bursts 5011308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::14 51 # Per bank write bursts 5111308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::15 94 # Per bank write bursts 5211308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts 5311308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts 5411308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts 5511308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts 5611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts 5711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts 5811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts 5911308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts 6011308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts 6111308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts 6211308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts 6311308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts 6411308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts 6511308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts 6611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts 6711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts 6811308Santhony.gutierrez@amd.comsystem.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 6911308Santhony.gutierrez@amd.comsystem.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 7011308Santhony.gutierrez@amd.comsystem.mem_ctrls.totGap 663221000 # Total gap between requests 7111308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 7211308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 7311308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 7411308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 7511308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 7611308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 7711308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::6 1551 # Read request sizes (log2) 7811308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 7911308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 8011308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 8111308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 8211308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 8311308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 8411308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) 8511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::0 1542 # What read queue length does an incoming req see 8611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::1 2 # What read queue length does an incoming req see 8711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see 8811308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see 8911308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see 9011308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see 9111308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 9211308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 9311308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 9411308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 9511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 9611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 9711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 9811308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 9911308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 10011308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 10111308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 10211308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 10311308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 10411308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 10511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 10611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 10711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 10811308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 10911308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 11011308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 11111308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 11211308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 11311308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 11411308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 11511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 11611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 11711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see 11811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see 11911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see 12011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see 12111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see 12211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see 12311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see 12411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see 12511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see 12611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see 12711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see 12811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see 12911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see 13011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see 13111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see 13211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see 13311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see 13411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see 13511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see 13611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see 13711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see 13811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see 13911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see 14011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see 14111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see 14211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see 14311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see 14411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see 14511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see 14611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see 14711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see 14811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see 14911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see 15011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 15111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 15211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 15311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 15411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 15511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 15611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 15711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 15811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 15911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 16011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 16111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 16211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 16311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 16411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 16511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 16611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 16711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 16811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 16911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 17011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 17111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 17211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 17311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 17411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 17511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 17611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 17711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 17811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 17911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 18011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 18111308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::samples 485 # Bytes accessed per row activation 18211308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::mean 204.008247 # Bytes accessed per row activation 18311308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::gmean 145.772769 # Bytes accessed per row activation 18411308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::stdev 192.306659 # Bytes accessed per row activation 18511308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::0-127 178 36.70% 36.70% # Bytes accessed per row activation 18611308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::128-255 156 32.16% 68.87% # Bytes accessed per row activation 18711308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::256-383 70 14.43% 83.30% # Bytes accessed per row activation 18811308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::384-511 40 8.25% 91.55% # Bytes accessed per row activation 18911308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::512-639 15 3.09% 94.64% # Bytes accessed per row activation 19011308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::640-767 10 2.06% 96.70% # Bytes accessed per row activation 19111308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::768-895 9 1.86% 98.56% # Bytes accessed per row activation 19211308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::896-1023 2 0.41% 98.97% # Bytes accessed per row activation 19311308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::1024-1151 5 1.03% 100.00% # Bytes accessed per row activation 19411308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::total 485 # Bytes accessed per row activation 19511308Santhony.gutierrez@amd.comsystem.mem_ctrls.totQLat 15500500 # Total ticks spent queuing 19611308Santhony.gutierrez@amd.comsystem.mem_ctrls.totMemAccLat 44581750 # Total ticks spent from burst creation until serviced by the DRAM 19711308Santhony.gutierrez@amd.comsystem.mem_ctrls.totBusLat 7755000 # Total ticks spent in databus transfers 19811308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgQLat 9993.87 # Average queueing delay per DRAM burst 19911308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst 20011308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgMemAccLat 28743.87 # Average memory access latency per DRAM burst 20111308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgRdBW 149.62 # Average DRAM read bandwidth in MiByte/s 20211308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 20311308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgRdBWSys 149.62 # Average system read bandwidth in MiByte/s 20411308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 20511308Santhony.gutierrez@amd.comsystem.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 20611308Santhony.gutierrez@amd.comsystem.mem_ctrls.busUtil 1.17 # Data bus utilization in percentage 20711308Santhony.gutierrez@amd.comsystem.mem_ctrls.busUtilRead 1.17 # Data bus utilization in percentage for reads 20811308Santhony.gutierrez@amd.comsystem.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes 20911308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 21011308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing 21111308Santhony.gutierrez@amd.comsystem.mem_ctrls.readRowHits 1062 # Number of row buffer hits during reads 21211308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes 21311308Santhony.gutierrez@amd.comsystem.mem_ctrls.readRowHitRate 68.47 # Row buffer hit rate for reads 21411308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes 21511308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgGap 427608.64 # Average gap between requests 21611308Santhony.gutierrez@amd.comsystem.mem_ctrls.pageHitRate 68.47 # Row buffer hit rate, read and write combined 21711308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.actEnergy 1391040 # Energy for activate commands per rank (pJ) 21811308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.preEnergy 759000 # Energy for precharge commands per rank (pJ) 21911308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.readEnergy 5335200 # Energy for read commands per rank (pJ) 22011308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22111308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.refreshEnergy 43227600 # Energy for refresh commands per rank (pJ) 22211308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.actBackEnergy 335485755 # Energy for active background per rank (pJ) 22311308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.preBackEnergy 102969000 # Energy for precharge background per rank (pJ) 22411308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.totalEnergy 489167595 # Total energy per rank (pJ) 22511308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.averagePower 738.822020 # Core power per rank (mW) 22611308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::IDLE 170399250 # Time in different power states 22711308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::REF 22100000 # Time in different power states 22811308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states 22911308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::ACT 470741750 # Time in different power states 23011308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23111308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.actEnergy 2275560 # Energy for activate commands per rank (pJ) 23211308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.preEnergy 1241625 # Energy for precharge commands per rank (pJ) 23311308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.readEnergy 6723600 # Energy for read commands per rank (pJ) 23411308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) 23511308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.refreshEnergy 43227600 # Energy for refresh commands per rank (pJ) 23611308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.actBackEnergy 371983995 # Energy for active background per rank (pJ) 23711308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.preBackEnergy 70953000 # Energy for precharge background per rank (pJ) 23811308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.totalEnergy 496405380 # Total energy per rank (pJ) 23911308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.averagePower 749.753724 # Core power per rank (mW) 24011308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::IDLE 115859750 # Time in different power states 24111308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::REF 22100000 # Time in different power states 24211308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states 24311308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::ACT 524145250 # Time in different power states 24411308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states 24511308Santhony.gutierrez@amd.comsystem.ruby.clk_domain.clock 500 # Clock period in ticks 24611308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory 24711308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory 24811308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory 24911308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory 25011308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory 25111308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory 25211308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory 25311308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory 25411308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory 25511308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory 25611308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory 25711308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory 25811308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory 25911308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory 26011308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory 26111308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory 26211308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory 26311308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory 26411308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory 26511308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory 26611308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory 26711308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory 26811308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_read::cpu0.inst 1050200127 # Total read bandwidth from this memory (bytes/s) 26911308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_read::cpu0.data 180618264 # Total read bandwidth from this memory (bytes/s) 27011308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4943821 # Total read bandwidth from this memory (bytes/s) 27111308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4943821 # Total read bandwidth from this memory (bytes/s) 27211308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_read::total 1240706032 # Total read bandwidth from this memory (bytes/s) 27311308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_inst_read::cpu0.inst 1050200127 # Instruction read bandwidth from this memory (bytes/s) 27411308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 3014525 # Instruction read bandwidth from this memory (bytes/s) 27511308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 3014525 # Instruction read bandwidth from this memory (bytes/s) 27611308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_inst_read::total 1056229176 # Instruction read bandwidth from this memory (bytes/s) 27711308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_write::cpu0.data 109678961 # Write bandwidth from this memory (bytes/s) 27811308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 385859 # Write bandwidth from this memory (bytes/s) 27911308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 385859 # Write bandwidth from this memory (bytes/s) 28011308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_write::total 110450679 # Write bandwidth from this memory (bytes/s) 28111308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_total::cpu0.inst 1050200127 # Total bandwidth to/from this memory (bytes/s) 28211308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_total::cpu0.data 290297225 # Total bandwidth to/from this memory (bytes/s) 28311308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s) 28411308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s) 28511308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_total::total 1351156711 # Total bandwidth to/from this memory (bytes/s) 28611312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::bucket_size 1 28711312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::max_bucket 9 28811312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::samples 114203 28911312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::mean 1.000035 29011312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::gmean 1.000024 29111312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::stdev 0.005918 29211312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 29311312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::total 114203 29411312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_coalsr::bucket_size 1 29511312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_coalsr::max_bucket 9 29611312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_coalsr::samples 28 29711312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_coalsr::mean 1.642857 29811312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_coalsr::gmean 1.455771 29911312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_coalsr::stdev 0.911421 30011312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 16 57.14% 57.14% | 8 28.57% 85.71% | 2 7.14% 92.86% | 2 7.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 30111312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_coalsr::total 28 30211312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::bucket_size 64 30311312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::max_bucket 639 30411312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::samples 114203 30511312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::mean 4.784183 30611312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::gmean 2.131364 30711312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::stdev 23.846744 30811312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr | 112668 98.66% 98.66% | 0 0.00% 98.66% | 0 0.00% 98.66% | 1506 1.32% 99.97% | 19 0.02% 99.99% | 10 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 30911312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::total 114203 31011312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_coalsr::bucket_size 64 31111312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_coalsr::max_bucket 639 31211312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_coalsr::samples 28 31311312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_coalsr::mean 136.285714 31411312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_coalsr::gmean 19.975449 31511312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_coalsr::stdev 139.699905 31611312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_coalsr | 14 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 10 35.71% 85.71% | 1 3.57% 89.29% | 3 10.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 31711312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_coalsr::total 28 31811312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::bucket_size 64 31911312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::max_bucket 639 32011312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::samples 1535 32111312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::mean 208.449511 32211312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::gmean 208.002927 32311312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::stdev 15.847049 32411312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1506 98.11% 98.11% | 19 1.24% 99.35% | 10 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 32511312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::total 1535 32611312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::bucket_size 4 32711312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::max_bucket 39 32811312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::samples 112668 32911312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::mean 2.009426 33011312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::gmean 2.002413 33111312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::stdev 0.411800 33211312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr | 112609 99.95% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 59 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 33311312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::total 112668 33411312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_coalsr::bucket_size 64 33511312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_coalsr::max_bucket 639 33611312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_coalsr::samples 28 33711312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_coalsr::mean 136.285714 33811312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_coalsr::gmean 19.975449 33911312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_coalsr::stdev 139.699905 34011312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_coalsr | 14 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 10 35.71% 85.71% | 1 3.57% 89.29% | 3 10.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 34111312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_coalsr::total 28 34211312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.incomplete_times_seqr 112609 34311312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.incomplete_times_seqr 59 34411308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits 34511308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses 34611308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses 34711308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.num_data_array_reads 16155 # number of data array reads 34811308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.num_data_array_writes 11985 # number of data array writes 34911308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.num_tag_array_reads 27132 # number of tag array reads 35011308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.num_tag_array_writes 1584 # number of tag array writes 35111308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits 35211308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D1cache.demand_misses 0 # Number of cache demand misses 35311308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D1cache.demand_accesses 0 # Number of cache demand accesses 35411308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits 35511308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.demand_misses 1088 # Number of cache demand misses 35611308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.demand_accesses 1088 # Number of cache demand accesses 35711308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.num_data_array_reads 86007 # number of data array reads 35811308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.num_data_array_writes 54 # number of data array writes 35911308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.num_tag_array_reads 87684 # number of tag array reads 36011308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes 36111308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 36211308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses 36311308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses 36411308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads 36511308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes 36611308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.num_tag_array_reads 12059 # number of tag array reads 36711308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes 36811308Santhony.gutierrez@amd.comsystem.cpu0.clk_domain.clock 500 # Clock period in ticks 36911308Santhony.gutierrez@amd.comsystem.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks 37011308Santhony.gutierrez@amd.comsystem.cpu0.workload.num_syscalls 21 # Number of system calls 37111308Santhony.gutierrez@amd.comsystem.cpu0.numCycles 1326909 # number of cpu cycles simulated 37211308Santhony.gutierrez@amd.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 37311308Santhony.gutierrez@amd.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 37411308Santhony.gutierrez@amd.comsystem.cpu0.committedInsts 66963 # Number of instructions committed 37511308Santhony.gutierrez@amd.comsystem.cpu0.committedOps 137705 # Number of ops (including micro ops) committed 37611308Santhony.gutierrez@amd.comsystem.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses 37711308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses 37811308Santhony.gutierrez@amd.comsystem.cpu0.num_func_calls 3196 # number of times a function call or return occured 37911308Santhony.gutierrez@amd.comsystem.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls 38011308Santhony.gutierrez@amd.comsystem.cpu0.num_int_insts 136380 # number of integer instructions 38111308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_insts 1279 # number of float instructions 38211308Santhony.gutierrez@amd.comsystem.cpu0.num_int_register_reads 257490 # number of times the integer registers were read 38311308Santhony.gutierrez@amd.comsystem.cpu0.num_int_register_writes 110039 # number of times the integer registers were written 38411308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read 38511308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_register_writes 981 # number of times the floating registers were written 38611308Santhony.gutierrez@amd.comsystem.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read 38711308Santhony.gutierrez@amd.comsystem.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written 38811308Santhony.gutierrez@amd.comsystem.cpu0.num_mem_refs 27198 # number of memory refs 38911308Santhony.gutierrez@amd.comsystem.cpu0.num_load_insts 16684 # Number of load instructions 39011308Santhony.gutierrez@amd.comsystem.cpu0.num_store_insts 10514 # Number of store instructions 39111308Santhony.gutierrez@amd.comsystem.cpu0.num_idle_cycles 5227.003992 # Number of idle cycles 39211308Santhony.gutierrez@amd.comsystem.cpu0.num_busy_cycles 1321681.996008 # Number of busy cycles 39311308Santhony.gutierrez@amd.comsystem.cpu0.not_idle_fraction 0.996061 # Percentage of non-idle cycles 39411308Santhony.gutierrez@amd.comsystem.cpu0.idle_fraction 0.003939 # Percentage of idle cycles 39511308Santhony.gutierrez@amd.comsystem.cpu0.Branches 16199 # Number of branches fetched 39611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction 39711308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction 39811308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction 39911308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction 40011308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction 40111308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction 40211308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction 40311308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatMult 0 0.00% 80.25% # Class of executed instruction 40411308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatDiv 0 0.00% 80.25% # Class of executed instruction 40511308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 80.25% # Class of executed instruction 40611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdAdd 0 0.00% 80.25% # Class of executed instruction 40711308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 80.25% # Class of executed instruction 40811308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdAlu 0 0.00% 80.25% # Class of executed instruction 40911308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdCmp 0 0.00% 80.25% # Class of executed instruction 41011308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdCvt 0 0.00% 80.25% # Class of executed instruction 41111308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdMisc 0 0.00% 80.25% # Class of executed instruction 41211308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdMult 0 0.00% 80.25% # Class of executed instruction 41311308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 80.25% # Class of executed instruction 41411308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdShift 0 0.00% 80.25% # Class of executed instruction 41511308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 80.25% # Class of executed instruction 41611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 80.25% # Class of executed instruction 41711308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 80.25% # Class of executed instruction 41811308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 80.25% # Class of executed instruction 41911308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 80.25% # Class of executed instruction 42011308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 80.25% # Class of executed instruction 42111308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 80.25% # Class of executed instruction 42211308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25% # Class of executed instruction 42311308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 80.25% # Class of executed instruction 42411308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25% # Class of executed instruction 42511308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction 42611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::MemRead 16684 12.12% 92.36% # Class of executed instruction 42711308Santhony.gutierrez@amd.comsystem.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction 42811308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 42911308Santhony.gutierrez@amd.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 43011308Santhony.gutierrez@amd.comsystem.cpu0.op_class::total 137705 # Class of executed instruction 43111308Santhony.gutierrez@amd.comsystem.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 43211308Santhony.gutierrez@amd.comsystem.cpu1.clk_domain.clock 1000 # Clock period in ticks 43311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 43411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 43511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 297 # number of times the wf's instructions are blocked due to RAW dependencies 43611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 43711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 43811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 43911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 44011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 44111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 44211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 44311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 44411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 44511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 44611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands 44711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands 44811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands 44911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands 45011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 45111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands 45211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 45311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 45411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 45511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 45611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands 45711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 45811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 45911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 46011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 46111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 46211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 46311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 46411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 46511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 46611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 46711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 46811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 46911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 47011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 47111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 47211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 47311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 47411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 47511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 47611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 47711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 47811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 47911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 48011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 48111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 48211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 48311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 48411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 48511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 48611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 48711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 48811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 48911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 49011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 49111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 49211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 49311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 49411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 49511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 49611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 49711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 49811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 49911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 50011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 50111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 50211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 50311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 50411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 50511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 50611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 50711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 50811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 50911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 51011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 51111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 51211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 51311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 51411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 51511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 51611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 51711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 51811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 51911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 52011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 52111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 52211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 52311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 52411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 52511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 52611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 52711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 52811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 52911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 53011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 53111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 53211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 53311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 53411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 53511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 53611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 53711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 53811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 53911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 54011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 54111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 54211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 54311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 54411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 54511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 54611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 54711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 54811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 54911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 55011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 55111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 55211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 55311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 55411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 55511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 55611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 55711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 55811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 55911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 56011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 56111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 56211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 56311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 56411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 56511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 56611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 56711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 56811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 56911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 57011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 57111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 57211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 57311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 57411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 57511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 57611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 57711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 57811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 57911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 58011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 58111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 58211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 58311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 58411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 58511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 58611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 58711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 58811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 58911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 59011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 59111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 59211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 59311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 59411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 59511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 59611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 59711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 59811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 59911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 60011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 60111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 60211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 60311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 60411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 60511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 60611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 60711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 60811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 60911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 61011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 61111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 61211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 61311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 61411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 61511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 61611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 61711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 61811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 61911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 62011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 62111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 62211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 62311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 62411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 62511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 62611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 62711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 273 # number of times the wf's instructions are blocked due to RAW dependencies 62811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 62911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 63011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 63111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 63211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 63311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 63411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 63511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 63611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 63711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 63811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 63911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 64011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 64111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 64211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 64311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 64411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 64511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 64611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 64711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 64811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 64911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 65011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 65111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 65211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 65311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 65411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 65511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 65611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 65711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 65811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 65911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 66011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 66111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 66211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 66311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 66411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 66511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 66611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 66711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 66811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 66911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 67011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 67111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 67211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 67311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 67411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 67511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 67611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 67711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 67811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 67911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 68011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 68111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 68211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 68311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 68411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 68511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 68611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 68711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 68811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 68911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 69011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 69111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 69211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 69311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 69411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 69511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 69611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 69711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 69811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 69911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 70011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 70111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 70211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 70311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 70411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 70511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 70611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 70711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 70811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 70911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 71011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 71111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 71211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 71311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 71411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 71511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 71611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 71711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 71811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 71911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 72011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 72111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 72211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 72311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 72411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 72511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 72611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 72711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 72811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 72911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 73011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 73111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 73211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 73311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 73411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 73511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 73611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 73711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 73811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 73911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 74011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 74111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 74211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 74311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 74411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 74511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 74611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 74711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 74811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 74911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 75011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 75111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 75211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 75311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 75411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 75511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 75611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 75711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 75811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 75911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 76011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 76111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 76211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 76311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 76411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 76511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 76611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 76711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 76811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 76911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 77011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 77111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 77211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 77311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 77411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 77511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 77611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 77711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 77811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 77911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 78011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 78111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 78211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 78311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 78411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 78511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 78611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 78711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 78811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 78911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 79011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 79111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 79211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 79311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 79411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 79511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 79611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 79711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 79811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 79911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 80011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 80111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 80211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 80311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 80411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 80511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 80611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 80711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 80811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 80911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 81011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 81111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 81211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 81311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 81411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 81511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 81611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 81711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 81811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 81911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 272 # number of times the wf's instructions are blocked due to RAW dependencies 82011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 82111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 82211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 82311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 82411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 82511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 82611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 82711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 82811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 82911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 83011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 83111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 83211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 83311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 83411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 83511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 83611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 83711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 83811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 83911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 84011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 84111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 84211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 84311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 84411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 84511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 84611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 84711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 84811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 84911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 85011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 85111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 85211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 85311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 85411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 85511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 85611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 85711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 85811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 85911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 86011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 86111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 86211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 86311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 86411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 86511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 86611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 86711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 86811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 86911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 87011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 87111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 87211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 87311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 87411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 87511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 87611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 87711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 87811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 87911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 88011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 88111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 88211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 88311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 88411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 88511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 88611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 88711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 88811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 88911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 89011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 89111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 89211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 89311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 89411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 89511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 89611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 89711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 89811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 89911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 90011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 90111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 90211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 90311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 90411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 90511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 90611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 90711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 90811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 90911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 91011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 91111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 91211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 91311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 91411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 91511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 91611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 91711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 91811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 91911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 92011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 92111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 92211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 92311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 92411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 92511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 92611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 92711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 92811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 92911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 93011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 93111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 93211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 93311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 93411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 93511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 93611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 93711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 93811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 93911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 94011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 94111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 94211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 94311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 94411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 94511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 94611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 94711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 94811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 94911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 95011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 95111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 95211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 95311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 95411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 95511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 95611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 95711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 95811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 95911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 96011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 96111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 96211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 96311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 96411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 96511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 96611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 96711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 96811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 96911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 97011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 97111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 97211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 97311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 97411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 97511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 97611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 97711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 97811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 97911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 98011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 98111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 98211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 98311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 98411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 98511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 98611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 98711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 98811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 98911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 99011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 99111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 99211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 99311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 99411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 99511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 99611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 99711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 99811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 99911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 100011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 100111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 100211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 100311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 100411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 100511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 100611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 100711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 100811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 100911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 101011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 101111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 256 # number of times the wf's instructions are blocked due to RAW dependencies 101211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 101311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 101411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 101511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 101611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 101711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 101811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 101911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 102011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 102111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 102211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 102311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 102411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 102511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 102611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 102711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 102811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 102911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 103011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 103111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 103211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 103311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 103411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 103511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 103611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 103711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 103811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 103911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 104011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 104111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 104211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 104311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 104411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 104511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 104611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 104711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 104811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 104911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 105011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 105111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 105211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 105311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 105411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 105511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 105611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 105711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 105811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 105911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 106011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 106111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 106211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 106311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 106411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 106511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 106611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 106711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 106811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 106911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 107011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 107111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 107211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 107311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 107411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 107511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 107611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 107711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 107811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 107911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 108011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 108111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 108211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 108311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 108411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 108511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 108611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 108711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 108811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 108911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 109011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 109111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 109211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 109311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 109411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 109511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 109611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 109711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 109811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 109911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 110011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 110111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 110211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 110311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 110411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 110511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 110611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 110711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 110811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 110911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 111011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 111111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 111211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 111311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 111411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 111511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 111611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 111711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 111811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 111911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 112011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 112111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 112211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 112311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 112411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 112511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 112611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 112711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 112811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 112911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 113011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 113111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 113211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 113311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 113411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 113511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 113611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 113711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 113811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 113911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 114011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 114111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 114211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 114311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 114411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 114511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 114611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 114711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 114811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 114911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 115011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 115111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 115211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 115311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 115411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 115511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 115611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 115711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 115811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 115911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 116011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 116111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 116211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 116311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 116411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 116511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 116611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 116711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 116811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 116911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 117011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 117111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 117211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 117311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 117411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 117511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 117611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 117711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 117811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 117911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 118011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 118111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 118211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 118311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 118411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 118511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 118611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 118711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 118811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 118911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 119011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 119111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 119211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 119311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 119411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 119511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 119611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 119711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 119811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 119911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 120011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 120111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 120211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 120311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it 120411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 120511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 120611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 120711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 120811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 120911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 121011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 121111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 121211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 121311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 121411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 121511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 121611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 121711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 121811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 121911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 122011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 122111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 122211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 122311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 122411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 122511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 122611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 122711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 122811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 122911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 123011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 123111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 123211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 123311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 123411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 123511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 123611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 123711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 123811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it 123911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it 124011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it 124111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3230 # number of cycles the CU issues nothing 124211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 128 # number of cycles the CU issued at least one instruction 124311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 124411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 124511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 124611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 124711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 124811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued 124911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 780 # Number of cycles no instruction of specific type issued 125011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 367 # Number of cycles no instruction of specific type issued 125111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 384 # Number of cycles no instruction of specific type issued 125211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 327 # Number of cycles no instruction of specific type issued 125311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 414 # Number of cycles no instruction of specific type issued 125411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 30 # Number of cycles no instruction of specific type issued 125511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::samples 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 125611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::mean 0.041989 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 125711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::stdev 0.220406 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 125811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 125911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::0 3230 96.19% 96.19% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 126011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::1 116 3.45% 99.64% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 126111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::2 11 0.33% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 126211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 126311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 126411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 126511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 126611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 126711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 126811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 126911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::total 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 127011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 82 # number of CU transitions from active to idle 127111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 82 # duration of idle periods in cycles 127211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 39.280488 # duration of idle periods in cycles 127311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 158.161058 # duration of idle periods in cycles 127411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles 127511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 62 75.61% 75.61% # duration of idle periods in cycles 127611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 9 10.98% 86.59% # duration of idle periods in cycles 127711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.22% 87.80% # duration of idle periods in cycles 127811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 87.80% # duration of idle periods in cycles 127911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.44% 90.24% # duration of idle periods in cycles 128011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.22% 91.46% # duration of idle periods in cycles 128111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 91.46% # duration of idle periods in cycles 128211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 91.46% # duration of idle periods in cycles 128311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 91.46% # duration of idle periods in cycles 128411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 91.46% # duration of idle periods in cycles 128511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 91.46% # duration of idle periods in cycles 128611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 91.46% # duration of idle periods in cycles 128711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 91.46% # duration of idle periods in cycles 128811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 91.46% # duration of idle periods in cycles 128911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 91.46% # duration of idle periods in cycles 129011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 91.46% # duration of idle periods in cycles 129111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 8.54% 100.00% # duration of idle periods in cycles 129211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 129311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1285 # duration of idle periods in cycles 129411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 82 # duration of idle periods in cycles 129511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 129611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF 129711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests 129811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.tlb_cycles -452460956000 # total number of cycles for all uncoalesced requests 129911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.avg_translation_latency -588375755.526658 # Avg. translation latency for data translations 130011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 130111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 130211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 130311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 130411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses 130511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 130611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet 130711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet 130811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet 130911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet 131011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 131111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 131211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 131311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 131411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::10-11 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 131511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::12-13 4 66.67% 100.00% # Number of bank conflicts per LDS memory packet 131611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 131711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 131811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 131911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 132011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 132111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 132211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 132311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 132411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 132511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 132611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 132711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 132811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 132911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 133011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 133111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 133211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 133311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 133411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 133511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 133611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 133711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 133811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 133911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 134011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 134111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 134211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 134311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet 134411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet 134511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet 134611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) 134711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) 134811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) 134911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) 135011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) 135111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 135211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 135311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 135411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 135511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 135611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 135711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 135811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 135911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 136011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 136111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 136211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 136311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 136411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 136511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 136611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 136711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 136811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 136911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 137011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count 137111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count 137211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 137311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_instr_executed 141 # number of instructions executed 137411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 137511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::mean 86.382979 # Instruction Execution Rate: Number of executed vector instructions per cycle 137611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::stdev 229.391669 # Instruction Execution Rate: Number of executed vector instructions per cycle 137711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 137811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle 137911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle 138011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::4-5 51 36.17% 45.39% # Instruction Execution Rate: Number of executed vector instructions per cycle 138111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::6-7 32 22.70% 68.09% # Instruction Execution Rate: Number of executed vector instructions per cycle 138211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::8-9 2 1.42% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle 138311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::10 2 1.42% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle 138411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::overflows 41 29.08% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 138511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle 138611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::max_value 1291 # Instruction Execution Rate: Number of executed vector instructions per cycle 138711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 138811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. VSZ/inst) 138911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_total_cycles 3358 # number of cycles the CU ran for 139011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.vpc 2.015783 # Vector Operations per cycle (this CU only) 139111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ipc 0.041989 # Instructions per cycle (this CU only) 139211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 139311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions) 139411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions) 139511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 139611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 139711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 139811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 139911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions) 140011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 140111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 140211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 140311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 140411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 140511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 140611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 140711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 140811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) 140911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 141011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 141111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) 141211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) 141311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) 141411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) 141511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) 141611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction 141711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::mean 37.833333 # number of active lanes per global memory instruction 141811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::stdev 27.064737 # number of active lanes per global memory instruction 141911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction 142011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction 142111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction 142211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::9-12 0 0.00% 5.56% # number of active lanes per global memory instruction 142311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::13-16 8 44.44% 50.00% # number of active lanes per global memory instruction 142411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction 142511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction 142611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction 142711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction 142811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction 142911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction 143011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction 143111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction 143211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction 143311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction 143411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction 143511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction 143611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction 143711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction 143811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction 143911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction 144011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction 144111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::mean 19.500000 # number of active lanes per local memory instruction 144211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::stdev 22.322634 # number of active lanes per local memory instruction 144311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction 144411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction 144511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction 144611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::9-12 0 0.00% 16.67% # number of active lanes per local memory instruction 144711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::13-16 4 66.67% 83.33% # number of active lanes per local memory instruction 144811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction 144911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction 145011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction 145111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction 145211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction 145311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction 145411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction 145511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction 145611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction 145711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction 145811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction 145911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction 146011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction 146111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 146211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 146311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 146411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 146511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 146611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations 146711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed 146811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts 146911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 147011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 147111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 381 # number of times the wf's instructions are blocked due to RAW dependencies 147211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 147311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 147411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 147511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 147611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 147711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 147811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 147911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 148011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 148111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 148211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands 148311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands 148411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands 148511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands 148611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 148711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands 148811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 148911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 149011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 149111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 149211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands 149311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 149411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 149511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 149611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 149711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 149811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 149911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 150011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 150111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 150211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 150311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 150411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 150511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 150611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 150711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 150811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 150911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 151011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 151111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 151211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 151311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 151411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 151511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 151611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 151711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 151811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 151911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 152011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 152111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 152211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 152311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 152411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 152511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 152611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 152711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 152811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 152911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 153011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 153111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 153211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 153311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 153411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 153511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 153611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 153711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 153811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 153911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 154011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 154111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 154211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 154311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 154411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 154511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 154611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 154711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 154811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 154911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 155011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 155111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 155211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 155311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 155411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 155511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 155611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 155711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 155811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 155911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 156011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 156111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 156211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 156311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 156411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 156511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 156611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 156711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 156811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 156911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 157011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 157111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 157211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 157311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 157411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 157511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 157611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 157711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 157811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 157911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 158011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 158111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 158211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 158311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 158411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 158511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 158611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 158711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 158811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 158911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 159011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 159111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 159211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 159311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 159411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 159511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 159611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 159711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 159811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 159911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 160011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 160111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 160211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 160311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 160411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 160511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 160611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 160711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 160811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 160911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 161011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 161111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 161211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 161311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 161411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 161511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 161611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 161711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 161811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 161911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 162011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 162111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 162211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 162311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 162411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 162511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 162611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 162711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 162811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 162911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 163011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 163111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 163211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 163311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 163411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 163511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 163611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 163711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 163811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 163911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 164011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 164111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 164211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 164311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 164411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 164511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 164611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 164711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 164811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 164911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 165011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 165111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 165211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 165311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 165411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 165511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 165611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 165711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 165811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 165911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 166011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 166111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 166211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 166311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 356 # number of times the wf's instructions are blocked due to RAW dependencies 166411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 166511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 166611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 166711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 166811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 166911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 167011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 167111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 167211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 167311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 167411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 167511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 167611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 167711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 167811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 167911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 168011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 168111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 168211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 168311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 168411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 168511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 168611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 168711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 168811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 168911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 169011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 169111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 169211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 169311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 169411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 169511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 169611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 169711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 169811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 169911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 170011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 170111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 170211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 170311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 170411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 170511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 170611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 170711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 170811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 170911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 171011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 171111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 171211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 171311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 171411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 171511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 171611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 171711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 171811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 171911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 172011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 172111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 172211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 172311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 172411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 172511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 172611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 172711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 172811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 172911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 173011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 173111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 173211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 173311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 173411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 173511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 173611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 173711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 173811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 173911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 174011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 174111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 174211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 174311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 174411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 174511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 174611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 174711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 174811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 174911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 175011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 175111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 175211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 175311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 175411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 175511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 175611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 175711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 175811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 175911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 176011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 176111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 176211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 176311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 176411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 176511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 176611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 176711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 176811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 176911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 177011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 177111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 177211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 177311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 177411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 177511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 177611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 177711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 177811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 177911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 178011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 178111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 178211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 178311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 178411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 178511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 178611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 178711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 178811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 178911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 179011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 179111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 179211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 179311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 179411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 179511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 179611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 179711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 179811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 179911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 180011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 180111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 180211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 180311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 180411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 180511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 180611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 180711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 180811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 180911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 181011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 181111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 181211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 181311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 181411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 181511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 181611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 181711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 181811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 181911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 182011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 182111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 182211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 182311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 182411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 182511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 182611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 182711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 182811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 182911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 183011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 183111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 183211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 183311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 183411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 183511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 183611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 183711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 183811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 183911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 184011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 184111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 184211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 184311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 184411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 184511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 184611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 184711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 184811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 184911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 185011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 185111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 185211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 185311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 185411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 185511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 356 # number of times the wf's instructions are blocked due to RAW dependencies 185611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 185711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 185811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 185911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 186011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 186111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 186211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 186311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 186411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 186511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 186611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 186711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 186811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 186911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 187011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 187111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 187211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 187311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 187411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 187511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 187611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 187711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 187811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 187911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 188011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 188111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 188211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 188311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 188411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 188511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 188611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 188711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 188811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 188911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 189011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 189111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 189211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 189311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 189411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 189511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 189611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 189711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 189811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 189911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 190011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 190111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 190211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 190311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 190411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 190511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 190611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 190711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 190811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 190911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 191011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 191111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 191211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 191311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 191411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 191511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 191611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 191711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 191811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 191911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 192011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 192111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 192211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 192311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 192411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 192511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 192611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 192711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 192811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 192911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 193011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 193111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 193211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 193311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 193411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 193511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 193611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 193711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 193811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 193911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 194011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 194111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 194211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 194311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 194411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 194511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 194611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 194711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 194811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 194911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 195011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 195111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 195211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 195311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 195411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 195511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 195611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 195711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 195811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 195911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 196011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 196111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 196211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 196311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 196411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 196511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 196611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 196711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 196811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 196911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 197011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 197111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 197211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 197311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 197411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 197511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 197611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 197711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 197811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 197911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 198011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 198111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 198211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 198311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 198411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 198511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 198611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 198711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 198811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 198911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 199011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 199111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 199211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 199311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 199411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 199511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 199611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 199711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 199811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 199911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 200011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 200111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 200211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 200311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 200411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 200511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 200611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 200711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 200811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 200911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 201011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 201111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 201211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 201311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 201411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 201511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 201611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 201711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 201811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 201911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 202011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 202111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 202211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 202311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 202411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 202511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 202611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 202711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 202811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 202911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 203011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 203111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 203211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 203311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 203411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 203511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 203611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 203711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 203811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 203911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 204011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 204111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 204211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 204311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 204411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 204511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 204611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 204711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 339 # number of times the wf's instructions are blocked due to RAW dependencies 204811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 204911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 205011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 205111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 205211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 205311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 205411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 205511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 205611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 205711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 205811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 205911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 206011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 206111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 206211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 206311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 206411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 206511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 206611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 206711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 206811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 206911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 207011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 207111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 207211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 207311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 207411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 207511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 207611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 207711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 207811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 207911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 208011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 208111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 208211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 208311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 208411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 208511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 208611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 208711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 208811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 208911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 209011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 209111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 209211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 209311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 209411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 209511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 209611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 209711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 209811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 209911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 210011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 210111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 210211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 210311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 210411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 210511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 210611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 210711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 210811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 210911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 211011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 211111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 211211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 211311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 211411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 211511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 211611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 211711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 211811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 211911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 212011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 212111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 212211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 212311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 212411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 212511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 212611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 212711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 212811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 212911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 213011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 213111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 213211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 213311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 213411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 213511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 213611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 213711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 213811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 213911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 214011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 214111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 214211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 214311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 214411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 214511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 214611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 214711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 214811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 214911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 215011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 215111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 215211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 215311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 215411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 215511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 215611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 215711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 215811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 215911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 216011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 216111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 216211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 216311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 216411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 216511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 216611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 216711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 216811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 216911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 217011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 217111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 217211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 217311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 217411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 217511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 217611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 217711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 217811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 217911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 218011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 218111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 218211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 218311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 218411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 218511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 218611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 218711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 218811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 218911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 219011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 219111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 219211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 219311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 219411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 219511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 219611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 219711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 219811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 219911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 220011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 220111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 220211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 220311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 220411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 220511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 220611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 220711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 220811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 220911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 221011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 221111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 221211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 221311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 221411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 221511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 221611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 221711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 221811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 221911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 222011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 222111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 222211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 222311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 222411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 222511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 222611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 222711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 222811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 222911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 223011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 223111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 223211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 223311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 223411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 223511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 223611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 223711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 223811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 223911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it 224011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 224111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 224211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 224311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 224411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 224511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 224611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 224711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 224811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 224911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 225011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 225111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 225211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 225311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 225411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 225511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 225611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 225711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 225811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 225911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 226011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 226111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 226211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 226311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 226411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 226511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 226611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 226711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 226811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 226911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 227011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 227111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 227211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 227311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 227411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it 227511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it 227611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it 227711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3228 # number of cycles the CU issues nothing 227811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 130 # number of cycles the CU issued at least one instruction 227911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 228011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 228111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 228211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 228311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 228411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued 228511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 778 # Number of cycles no instruction of specific type issued 228611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 472 # Number of cycles no instruction of specific type issued 228711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 447 # Number of cycles no instruction of specific type issued 228811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 411 # Number of cycles no instruction of specific type issued 228911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 417 # Number of cycles no instruction of specific type issued 229011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 26 # Number of cycles no instruction of specific type issued 229111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::samples 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 229211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::mean 0.041989 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 229311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::stdev 0.217686 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 229411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 229511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::0 3228 96.13% 96.13% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 229611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::1 120 3.57% 99.70% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 229711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::2 9 0.27% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 229811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 229911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 230011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 230111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 230211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 230311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 230411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 230511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::total 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 230611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 81 # number of CU transitions from active to idle 230711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 81 # duration of idle periods in cycles 230811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 38.617284 # duration of idle periods in cycles 230911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 158.076213 # duration of idle periods in cycles 231011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles 231111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 60 74.07% 74.07% # duration of idle periods in cycles 231211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 10 12.35% 86.42% # duration of idle periods in cycles 231311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 86.42% # duration of idle periods in cycles 231411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 2 2.47% 88.89% # duration of idle periods in cycles 231511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 2 2.47% 91.36% # duration of idle periods in cycles 231611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 0 0.00% 91.36% # duration of idle periods in cycles 231711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 91.36% # duration of idle periods in cycles 231811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 91.36% # duration of idle periods in cycles 231911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 91.36% # duration of idle periods in cycles 232011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 91.36% # duration of idle periods in cycles 232111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 91.36% # duration of idle periods in cycles 232211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 91.36% # duration of idle periods in cycles 232311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 91.36% # duration of idle periods in cycles 232411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 91.36% # duration of idle periods in cycles 232511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 91.36% # duration of idle periods in cycles 232611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 91.36% # duration of idle periods in cycles 232711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 8.64% 100.00% # duration of idle periods in cycles 232811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 232911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1293 # duration of idle periods in cycles 233011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 81 # duration of idle periods in cycles 233111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 233211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF 233311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests 233411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.tlb_cycles -452466433000 # total number of cycles for all uncoalesced requests 233511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.avg_translation_latency -588382877.763329 # Avg. translation latency for data translations 233611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 233711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 233811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 233911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 234011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses 234111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 234211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet 234311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet 234411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet 234511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet 234611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 234711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 234811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 234911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 235011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::10-11 1 16.67% 50.00% # Number of bank conflicts per LDS memory packet 235111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::12-13 3 50.00% 100.00% # Number of bank conflicts per LDS memory packet 235211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 235311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 235411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 235511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 235611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 235711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 235811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 235911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 236011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 236111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 236211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 236311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 236411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 236511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 236611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 236711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 236811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 236911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 237011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 237111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 237211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 237311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 237411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 237511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 237611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 237711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 237811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 237911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet 238011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet 238111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet 238211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) 238311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) 238411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) 238511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) 238611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) 238711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 238811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 238911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 239011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 239111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 239211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 239311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 239411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 239511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 239611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 239711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 239811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 239911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 240011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 240111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 240211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 240311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 240411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 240511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 240611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count 240711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count 240811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 240911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_instr_executed 141 # number of instructions executed 241011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 241111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::mean 85.666667 # Instruction Execution Rate: Number of executed vector instructions per cycle 241211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::stdev 230.212531 # Instruction Execution Rate: Number of executed vector instructions per cycle 241311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 241411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle 241511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle 241611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::4-5 52 36.88% 46.10% # Instruction Execution Rate: Number of executed vector instructions per cycle 241711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::6-7 33 23.40% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle 241811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::8-9 4 2.84% 72.34% # Instruction Execution Rate: Number of executed vector instructions per cycle 241911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::10 1 0.71% 73.05% # Instruction Execution Rate: Number of executed vector instructions per cycle 242011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::overflows 38 26.95% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 242111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle 242211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::max_value 1299 # Instruction Execution Rate: Number of executed vector instructions per cycle 242311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 242411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. VSZ/inst) 242511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_total_cycles 3358 # number of cycles the CU ran for 242611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.vpc 2.013699 # Vector Operations per cycle (this CU only) 242711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ipc 0.041989 # Instructions per cycle (this CU only) 242811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 242911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions) 243011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions) 243111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 243211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 243311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 243411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions) 243511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions) 243611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 243711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 243811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 243911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 244011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 244111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 244211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 244311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 244411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) 244511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 244611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 244711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) 244811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) 244911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) 245011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) 245111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) 245211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction 245311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::mean 37.722222 # number of active lanes per global memory instruction 245411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::stdev 27.174394 # number of active lanes per global memory instruction 245511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction 245611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction 245711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction 245811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::9-12 2 11.11% 16.67% # number of active lanes per global memory instruction 245911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::13-16 6 33.33% 50.00% # number of active lanes per global memory instruction 246011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction 246111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction 246211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction 246311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction 246411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction 246511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction 246611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction 246711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction 246811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction 246911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction 247011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction 247111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction 247211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction 247311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction 247411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction 247511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction 247611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction 247711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::mean 19.333333 # number of active lanes per local memory instruction 247811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::stdev 22.384518 # number of active lanes per local memory instruction 247911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction 248011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction 248111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction 248211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::9-12 1 16.67% 33.33% # number of active lanes per local memory instruction 248311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::13-16 3 50.00% 83.33% # number of active lanes per local memory instruction 248411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction 248511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction 248611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction 248711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction 248811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction 248911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction 249011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction 249111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction 249211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction 249311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction 249411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction 249511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction 249611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction 249711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 249811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 249911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 250011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 250111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 250211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations 250311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed 250411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts 250511308Santhony.gutierrez@amd.comsystem.cpu2.num_kernel_launched 1 # number of kernel launched 250611308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits 250711308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses 250811308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses 250911308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.num_data_array_writes 1551 # number of data array writes 251011308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1551 # number of tag array reads 251111308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1551 # number of tag array writes 251211308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 251311308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks 251411308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses 251511308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses 251611308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue 251711308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 251811308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts 251911308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 252011308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks 252111308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses 252211308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits 252311308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses 252411308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate 252511308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses 252611308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits 252711308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses 252811308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate 252911308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level 253011308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table 253111308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.unique_pages 0 # Number of unique pages touched 253211308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 253311308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs 253411308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 253511308Santhony.gutierrez@amd.comsystem.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 253611308Santhony.gutierrez@amd.comsystem.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks 253711308Santhony.gutierrez@amd.comsystem.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses 253811308Santhony.gutierrez@amd.comsystem.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses 253911308Santhony.gutierrez@amd.comsystem.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue 254011308Santhony.gutierrez@amd.comsystem.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 254111308Santhony.gutierrez@amd.comsystem.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts 254211308Santhony.gutierrez@amd.comsystem.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 254311308Santhony.gutierrez@amd.comsystem.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks 254411308Santhony.gutierrez@amd.comsystem.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses 254511308Santhony.gutierrez@amd.comsystem.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses 254611308Santhony.gutierrez@amd.comsystem.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue 254711308Santhony.gutierrez@amd.comsystem.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 254811308Santhony.gutierrez@amd.comsystem.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts 254911308Santhony.gutierrez@amd.comsystem.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 255011308Santhony.gutierrez@amd.comsystem.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks 255111308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses 255211308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_hits 774 # Number of TLB hits 255311308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_misses 4 # Number of TLB misses 255411308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate 255511308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses 255611308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_hits 774 # Number of TLB hits 255711308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_misses 4 # Number of TLB misses 255811308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate 255911308Santhony.gutierrez@amd.comsystem.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level 256011308Santhony.gutierrez@amd.comsystem.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table 256111308Santhony.gutierrez@amd.comsystem.l1_tlb0.unique_pages 4 # Number of unique pages touched 256211308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 256311308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs 256411308Santhony.gutierrez@amd.comsystem.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 256511308Santhony.gutierrez@amd.comsystem.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 256611308Santhony.gutierrez@amd.comsystem.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks 256711308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses 256811308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_hits 766 # Number of TLB hits 256911308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_misses 3 # Number of TLB misses 257011308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate 257111308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses 257211308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_hits 766 # Number of TLB hits 257311308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_misses 3 # Number of TLB misses 257411308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate 257511308Santhony.gutierrez@amd.comsystem.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level 257611308Santhony.gutierrez@amd.comsystem.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table 257711308Santhony.gutierrez@amd.comsystem.l1_tlb1.unique_pages 3 # Number of unique pages touched 257811308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 257911308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs 258011308Santhony.gutierrez@amd.comsystem.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 258111308Santhony.gutierrez@amd.comsystem.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 258211308Santhony.gutierrez@amd.comsystem.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks 258311308Santhony.gutierrez@amd.comsystem.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses 258411308Santhony.gutierrez@amd.comsystem.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 258511308Santhony.gutierrez@amd.comsystem.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 258611308Santhony.gutierrez@amd.comsystem.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 258711308Santhony.gutierrez@amd.comsystem.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts 258811308Santhony.gutierrez@amd.comsystem.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 258911308Santhony.gutierrez@amd.comsystem.l2_tlb.clk_domain.clock 1000 # Clock period in ticks 259011308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses 259111308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_hits 3 # Number of TLB hits 259211308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_misses 5 # Number of TLB misses 259311308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate 259411308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses 259511308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_hits 3 # Number of TLB hits 259611308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_misses 12 # Number of TLB misses 259711308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate 259811308Santhony.gutierrez@amd.comsystem.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level 259911308Santhony.gutierrez@amd.comsystem.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table 260011308Santhony.gutierrez@amd.comsystem.l2_tlb.unique_pages 5 # Number of unique pages touched 260111308Santhony.gutierrez@amd.comsystem.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs 260211308Santhony.gutierrez@amd.comsystem.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs 260311308Santhony.gutierrez@amd.comsystem.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 260411308Santhony.gutierrez@amd.comsystem.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 260511308Santhony.gutierrez@amd.comsystem.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks 260611308Santhony.gutierrez@amd.comsystem.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses 260711308Santhony.gutierrez@amd.comsystem.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 260811308Santhony.gutierrez@amd.comsystem.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 260911308Santhony.gutierrez@amd.comsystem.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 261011308Santhony.gutierrez@amd.comsystem.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts 261111308Santhony.gutierrez@amd.comsystem.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 261211308Santhony.gutierrez@amd.comsystem.l3_tlb.clk_domain.clock 1000 # Clock period in ticks 261311308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses 261411308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_hits 0 # Number of TLB hits 261511308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_misses 5 # Number of TLB misses 261611308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate 261711308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses 261811308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_hits 0 # Number of TLB hits 261911308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_misses 12 # Number of TLB misses 262011308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate 262111308Santhony.gutierrez@amd.comsystem.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level 262211308Santhony.gutierrez@amd.comsystem.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table 262311308Santhony.gutierrez@amd.comsystem.l3_tlb.unique_pages 5 # Number of unique pages touched 262411308Santhony.gutierrez@amd.comsystem.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs 262511308Santhony.gutierrez@amd.comsystem.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs 262611308Santhony.gutierrez@amd.comsystem.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 262711308Santhony.gutierrez@amd.comsystem.piobus.trans_dist::WriteReq 94 # Transaction distribution 262811308Santhony.gutierrez@amd.comsystem.piobus.trans_dist::WriteResp 94 # Transaction distribution 262911308Santhony.gutierrez@amd.comsystem.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) 263011308Santhony.gutierrez@amd.comsystem.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes) 263111308Santhony.gutierrez@amd.comsystem.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes) 263211308Santhony.gutierrez@amd.comsystem.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes) 263311308Santhony.gutierrez@amd.comsystem.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks) 263411308Santhony.gutierrez@amd.comsystem.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) 263511308Santhony.gutierrez@amd.comsystem.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) 263611308Santhony.gutierrez@amd.comsystem.piobus.respLayer0.utilization 0.0 # Layer utilization (%) 263711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.percent_links_utilized 0.007952 263811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Control::0 1551 263911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1551 264011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1563 264111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1539 264211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1551 264311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12408 264411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12408 264511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112536 264611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12312 264711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12408 264811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.percent_links_utilized 0.009970 264911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_count.Control::0 16 265011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 265111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537 265211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 14 265311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1535 265411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_bytes.Control::0 128 265511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280 265611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664 265711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 112 265811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12280 265911308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 266011308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 266111308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 266211308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.num_data_array_reads 10 # number of data array reads 266311308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes 266411308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.num_tag_array_reads 27 # number of tag array reads 266511308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes 266611308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array 266711308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array 266811308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP 266911308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers 267011308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 267111308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_ld_misses 2 # loads that miss in the GPU 267211308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP 267311308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers 267411308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 267511308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_st_misses 4 # stores that miss in the GPU 267611308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 267711308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 267811308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 267911308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU 268011308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 268111308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 268211308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 268311308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU 268411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.percent_links_utilized 0.000721 268511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Control::0 1535 268611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Control::1 14 268711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 16 268811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 19 268911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 26 269011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 33 269111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1525 269211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 16 269311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::5 19 269411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Control::0 12280 269511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Control::1 112 269611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 128 269711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 152 269811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 1872 269911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 2376 270011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 12200 270111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 128 270211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::5 152 270311308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits 270411308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 270511308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses 270611308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_data_array_reads 7 # number of data array reads 270711308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes 270811308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_tag_array_reads 25 # number of tag array reads 270911308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes 271011308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array 271111308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array 271211308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP 271311308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers 271411308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 271511308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 271611308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP 271711308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers 271811308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 271911308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_st_misses 5 # stores that miss in the GPU 272011308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 272111308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 272211308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 272311308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU 272411308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 272511308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 272611308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 272711308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU 272811308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 272911308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 273011308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 273111308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads 273211308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.num_data_array_writes 5 # number of data array writes 273311308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads 273411308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes 273511308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.num_data_array_stalls 44 # number of stalls caused by data array 273611308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load 273711308Santhony.gutierrez@amd.comsystem.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 273811308Santhony.gutierrez@amd.comsystem.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses 273911308Santhony.gutierrez@amd.comsystem.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses 274011308Santhony.gutierrez@amd.comsystem.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits 274111308Santhony.gutierrez@amd.comsystem.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses 274211308Santhony.gutierrez@amd.comsystem.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses 274311308Santhony.gutierrez@amd.comsystem.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads 274411308Santhony.gutierrez@amd.comsystem.tccdir_cntrl0.directory.num_tag_array_writes 27 # number of tag array writes 274511308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Control 3116 274611308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Request_Control 3121 274711308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Response_Data 3159 274811308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Response_Control 3078 274911308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Unblock_Control 3121 275011308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Control 24928 275111308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Request_Control 24968 275211308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Response_Data 227448 275311308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Response_Control 24624 275411308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Unblock_Control 24968 275511308Santhony.gutierrez@amd.comsystem.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 275611308Santhony.gutierrez@amd.comsystem.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks 275711308Santhony.gutierrez@amd.comsystem.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses 275811308Santhony.gutierrez@amd.comsystem.sqc_coalescer.coalesced_accesses 63 # Number of coalesced TLB accesses 275911308Santhony.gutierrez@amd.comsystem.sqc_coalescer.queuing_cycles 100000 # Number of cycles spent in queue 276011308Santhony.gutierrez@amd.comsystem.sqc_coalescer.local_queuing_cycles 100000 # Number of cycles spent in queue for all incoming reqs 276111308Santhony.gutierrez@amd.comsystem.sqc_coalescer.local_latency 1162.790698 # Avg. latency over all incoming pkts 276211308Santhony.gutierrez@amd.comsystem.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 276311308Santhony.gutierrez@amd.comsystem.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks 276411308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_TLB_accesses 63 # Number of TLB accesses 276511308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_TLB_hits 62 # Number of TLB hits 276611308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_TLB_misses 1 # Number of TLB misses 276711308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_TLB_miss_rate 1.587302 # TLB miss rate 276811308Santhony.gutierrez@amd.comsystem.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses 276911308Santhony.gutierrez@amd.comsystem.sqc_tlb.global_TLB_hits 78 # Number of TLB hits 277011308Santhony.gutierrez@amd.comsystem.sqc_tlb.global_TLB_misses 8 # Number of TLB misses 277111308Santhony.gutierrez@amd.comsystem.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate 277211308Santhony.gutierrez@amd.comsystem.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level 277311308Santhony.gutierrez@amd.comsystem.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table 277411308Santhony.gutierrez@amd.comsystem.sqc_tlb.unique_pages 1 # Number of unique pages touched 277511308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_cycles 63001 # Number of cycles spent in queue for all incoming reqs 277611308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_latency 1000.015873 # Avg. latency over incoming coalesced reqs 277711308Santhony.gutierrez@amd.comsystem.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 277811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005592 277911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551 278011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12 278111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1539 278211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1551 278311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12408 278411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 864 278511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12312 278611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12408 278711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016287 278811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 16 278911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2 1535 279011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 128 279111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2 110520 279211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001977 279311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0 1535 279411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 16 279511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0 12280 279611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 1152 279711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016287 279811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 16 279911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2 1535 280011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 128 280111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2 110520 280211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003653 280311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0 1535 280411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2 2 280511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 14 280611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_count.Unblock_Control::4 1535 280711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0 12280 280811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2 144 280911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 112 281011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4 12280 281111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.000084 281211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::1 8 281311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::3 7 281411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Control::1 64 281511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::3 504 281611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.link_utilization 0.000081 281711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_count.Control::1 6 281811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3 7 281911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Control::1 48 282011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3 504 282111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.link_utilization 0 282211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.002170 282311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_count.Control::0 1535 282411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_count.Request_Control::1 19 282511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::2 16 282611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::3 14 282711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_count.Unblock_Control::5 19 282811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Control::0 12280 282911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Request_Control::1 152 283011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::2 1152 283111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::3 1008 283211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Unblock_Control::5 152 283311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.000053 283411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Data::3 5 283511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Data::3 360 283611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle5.link_utilization 0.001939 283711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_count.Request_Control::0 16 283811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Data::2 10 283911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Control::2 1525 284011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_count.Unblock_Control::4 16 284111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Request_Control::0 128 284211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Data::2 720 284311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Control::2 12200 284411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Unblock_Control::4 128 284511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Load_L1miss 180 0.00% 0.00% 284611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Load_L1hit 16155 0.00% 0.00% 284711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.Ifetch0_L1hit 86007 0.00% 0.00% 284811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.Ifetch0_L1miss 1088 0.00% 0.00% 284911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Store_L1miss 325 0.00% 0.00% 285011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Store_L1hit 10448 0.00% 0.00% 285111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.NB_AckS 1043 0.00% 0.00% 285211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.NB_AckM 326 0.00% 0.00% 285311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.NB_AckE 166 0.00% 0.00% 285411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L1I_Repl 589 0.00% 0.00% 285511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L1D0_Repl 24 0.00% 0.00% 285611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L2_to_L1D0 5 0.00% 0.00% 285711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L2_to_L1I 54 0.00% 0.00% 285811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.PrbInvData 9 0.00% 0.00% 285911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.PrbShrData 7 0.00% 0.00% 286011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.C0_Load_L1miss 175 0.00% 0.00% 286111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00% 286211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00% 286311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.PrbInvData 8 0.00% 0.00% 286411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.PrbShrData 5 0.00% 0.00% 286511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.C0_Load_L1hit 635 0.00% 0.00% 286611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.Ifetch0_L1hit 86007 0.00% 0.00% 286711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.Ifetch0_L1miss 54 0.00% 0.00% 286811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.L1I_Repl 589 0.00% 0.00% 286911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.C0_Load_L1miss 2 0.00% 0.00% 287011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.C0_Load_L1hit 2721 0.00% 0.00% 287111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.C0_Store_L1hit 46 0.00% 0.00% 287211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.L1D0_Repl 16 0.00% 0.00% 287311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.PrbShrData 1 0.00% 0.00% 287411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.O.C0_Load_L1hit 3 0.00% 0.00% 287511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.O.C0_Store_L1hit 1 0.00% 0.00% 287611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.C0_Load_L1miss 3 0.00% 0.00% 287711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.C0_Load_L1hit 12796 0.00% 0.00% 287811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.C0_Store_L1hit 10401 0.00% 0.00% 287911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.L1D0_Repl 8 0.00% 0.00% 288011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.PrbInvData 1 0.00% 0.00% 288111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.PrbShrData 1 0.00% 0.00% 288211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_M0.NB_AckM 325 0.00% 0.00% 288311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_E0S.NB_AckS 9 0.00% 0.00% 288411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_E0S.NB_AckE 166 0.00% 0.00% 288511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.Si_F0.L2_to_L1I 54 0.00% 0.00% 288611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.O_M0.NB_AckM 1 0.00% 0.00% 288711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00% 288811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00% 288911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0_F.L2_to_L1D0 3 0.00% 0.00% 289011308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.RdBlkS 1039 0.00% 0.00% 289111308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.RdBlkM 335 0.00% 0.00% 289211308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.RdBlk 177 0.00% 0.00% 289311308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.CPUPrbResp 1551 0.00% 0.00% 289411308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.ProbeAcksComplete 1551 0.00% 0.00% 289511308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.MemData 1551 0.00% 0.00% 289611308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.CoreUnblock 1551 0.00% 0.00% 289711308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.RdBlkS 1039 0.00% 0.00% 289811308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.RdBlkM 335 0.00% 0.00% 289911308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.RdBlk 177 0.00% 0.00% 290011308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BS_M.MemData 29 0.00% 0.00% 290111308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_M.MemData 12 0.00% 0.00% 290211308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_M.MemData 1 0.00% 0.00% 290311308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BS_PM.CPUPrbResp 29 0.00% 0.00% 290411308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 29 0.00% 0.00% 290511308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BS_PM.MemData 1010 0.00% 0.00% 290611308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_PM.CPUPrbResp 12 0.00% 0.00% 290711308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 12 0.00% 0.00% 290811308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_PM.MemData 323 0.00% 0.00% 290911308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_PM.CPUPrbResp 1 0.00% 0.00% 291011308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_PM.ProbeAcksComplete 1 0.00% 0.00% 291111308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_PM.MemData 176 0.00% 0.00% 291211308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1010 0.00% 0.00% 291311308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1010 0.00% 0.00% 291411308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_Pm.CPUPrbResp 323 0.00% 0.00% 291511308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 323 0.00% 0.00% 291611308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_Pm.CPUPrbResp 176 0.00% 0.00% 291711308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 176 0.00% 0.00% 291811308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B.CoreUnblock 1551 0.00% 0.00% 291911312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::bucket_size 32 292011312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::max_bucket 319 292111312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::samples 16335 292211312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::mean 4.217447 292311312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::gmean 2.103537 292411312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::stdev 21.286370 292511312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr | 16160 98.93% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 166 1.02% 99.94% | 9 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 292611312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::total 16335 292711312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_coalsr::bucket_size 64 292811312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_coalsr::max_bucket 639 292911312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_coalsr::samples 10 293011312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_coalsr::mean 119.100000 293111312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_coalsr::gmean 16.830524 293211312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_coalsr::stdev 153.079827 293311312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_coalsr | 6 60.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 20.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 293411312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_coalsr::total 10 293511312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::bucket_size 32 293611312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::max_bucket 319 293711312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::samples 175 293811312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::mean 208.468571 293911312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::gmean 208.231054 294011312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::stdev 10.632194 294111312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 9 5.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 294211312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::total 175 294311312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::bucket_size 4 294411312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::max_bucket 39 294511312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::samples 16160 294611312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::mean 2.005569 294711312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::gmean 2.001425 294811312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::stdev 0.316580 294911312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 295011312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::total 16160 295111312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_coalsr::bucket_size 64 295211312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_coalsr::max_bucket 639 295311312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_coalsr::samples 10 295411312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_coalsr::mean 119.100000 295511312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_coalsr::gmean 16.830524 295611312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_coalsr::stdev 153.079827 295711312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_coalsr | 6 60.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 20.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 295811312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_coalsr::total 10 295911312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::bucket_size 64 296011312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::max_bucket 639 296111312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::samples 10412 296211312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::mean 8.385709 296311312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::gmean 2.308923 296411312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::stdev 35.862445 296511312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 316 3.03% 99.94% | 3 0.03% 99.97% | 3 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 296611312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::total 10412 296711312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_coalsr::bucket_size 32 296811312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_coalsr::max_bucket 319 296911312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_coalsr::samples 16 297011312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_coalsr::mean 125.375000 297111312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_coalsr::gmean 15.803091 297211312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_coalsr::stdev 128.466792 297311312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 8 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 297411312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_coalsr::total 16 297511312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::bucket_size 64 297611312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::max_bucket 639 297711312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::samples 322 297811312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::mean 208.484472 297911312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::gmean 208.014366 298011312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::stdev 16.327683 298111312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 316 98.14% 98.14% | 3 0.93% 99.07% | 3 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 298211312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::total 322 298311312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::bucket_size 1 298411312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::max_bucket 9 298511312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::samples 10090 298611312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::mean 2 298711312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::gmean 2.000000 298811312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 298911312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::total 10090 299011312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_coalsr::bucket_size 32 299111312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_coalsr::max_bucket 319 299211312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_coalsr::samples 16 299311312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_coalsr::mean 125.375000 299411312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_coalsr::gmean 15.803091 299511312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_coalsr::stdev 128.466792 299611312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 8 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 299711312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_coalsr::total 16 299811312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.latency_hist_coalsr::bucket_size 64 299911312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.latency_hist_coalsr::max_bucket 639 300011312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.latency_hist_coalsr::samples 2 300111312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.latency_hist_coalsr::mean 309.500000 300211312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.latency_hist_coalsr::gmean 306.568100 300311312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.latency_hist_coalsr::stdev 60.104076 300411312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 300511312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.latency_hist_coalsr::total 2 300611312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr::bucket_size 64 300711312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr::max_bucket 639 300811312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr::samples 2 300911312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr::mean 309.500000 301011312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 306.568100 301111312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 60.104076 301211312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 301311312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.miss_latency_hist_coalsr::total 2 301411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::bucket_size 64 301511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::max_bucket 639 301611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::samples 87095 301711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::mean 4.462093 301811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::gmean 2.116390 301911312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::stdev 22.435279 302011312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr | 86061 98.81% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1011 1.16% 99.97% | 16 0.02% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 302111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::total 87095 302211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 64 302311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 639 302411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::samples 1034 302511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::mean 208.444874 302611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::gmean 207.968565 302711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::stdev 16.462617 302811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 302911312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::total 1034 303011312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 4 303111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 39 303211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::samples 86061 303311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::mean 2.011294 303411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::gmean 2.002892 303511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::stdev 0.450747 303611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr | 86007 99.94% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 54 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 303711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::total 86061 303811312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::bucket_size 32 303911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::max_bucket 319 304011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::samples 341 304111312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::mean 4.392962 304211312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::gmean 2.111743 304311312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::stdev 21.996747 304411312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr | 337 98.83% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 4 1.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 304511312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::total 341 304611312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::bucket_size 32 304711312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::max_bucket 319 304811312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::samples 4 304911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::mean 206 305011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::gmean 206.000000 305111312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 305211312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::total 4 305311312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::bucket_size 1 305411312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::max_bucket 9 305511312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::samples 337 305611312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::mean 2 305711312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::gmean 2.000000 305811312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 305911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::total 337 306011312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::bucket_size 1 306111312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::max_bucket 9 306211312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::samples 10 306311312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::mean 2 306411312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::gmean 2 306511312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 306611312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::total 10 306711312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::bucket_size 1 306811312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::max_bucket 9 306911312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::samples 10 307011312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::mean 2 307111312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::gmean 2 307211312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 307311312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::total 10 307411312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::bucket_size 1 307511312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::max_bucket 9 307611312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::samples 10 307711312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::mean 2 307811312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::gmean 2 307911312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 308011312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::total 10 308111312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist_seqr::bucket_size 1 308211312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist_seqr::max_bucket 9 308311312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist_seqr::samples 10 308411312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist_seqr::mean 2 308511312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist_seqr::gmean 2 308611312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 308711312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist_seqr::total 10 308811312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size 1 308911312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket 9 309011312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::samples 112609 309111312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 2 309211312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 2.000000 309311312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 112609 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 309411312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::total 112609 309511312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist_seqr::bucket_size 4 309611312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist_seqr::max_bucket 39 309711312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist_seqr::samples 59 309811312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist_seqr::mean 20 309911312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist_seqr::gmean 20.000000 310011312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 59 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 310111312Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist_seqr::total 59 310211312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size 64 310311312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket 639 310411312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::samples 1535 310511312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::mean 208.449511 310611312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::gmean 208.002927 310711312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::stdev 15.847049 310811312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1506 98.11% 98.11% | 19 1.24% 99.35% | 10 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 310911312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::total 1535 311011312Santhony.gutierrez@amd.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 64 311111312Santhony.gutierrez@amd.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 639 311211312Santhony.gutierrez@amd.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 3 311311312Santhony.gutierrez@amd.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 342 311411312Santhony.gutierrez@amd.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 341.902506 311511312Santhony.gutierrez@amd.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 10 311611312Santhony.gutierrez@amd.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 311711312Santhony.gutierrez@amd.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 3 311811312Santhony.gutierrez@amd.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1 311911312Santhony.gutierrez@amd.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9 312011312Santhony.gutierrez@amd.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::samples 14 312111312Santhony.gutierrez@amd.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.714286 312211312Santhony.gutierrez@amd.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.485994 312311312Santhony.gutierrez@amd.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 1.069045 312411312Santhony.gutierrez@amd.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 57.14% 57.14% | 4 28.57% 85.71% | 0 0.00% 85.71% | 2 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 312511312Santhony.gutierrez@amd.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::total 14 312611312Santhony.gutierrez@amd.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 32 312711312Santhony.gutierrez@amd.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 319 312811312Santhony.gutierrez@amd.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 11 312911312Santhony.gutierrez@amd.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 251.454545 313011312Santhony.gutierrez@amd.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 251.396753 313111312Santhony.gutierrez@amd.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 5.733474 313211312Santhony.gutierrez@amd.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 90.91% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00% 313311312Santhony.gutierrez@amd.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 11 313411312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 313511312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 313611312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::samples 16155 313711312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 313811312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 313911312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 16155 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 314011312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::total 16155 314111312Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::bucket_size 4 314211312Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::max_bucket 39 314311312Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::samples 5 314411312Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::mean 20 314511312Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::gmean 20.000000 314611312Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 314711312Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::total 5 314811312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size 32 314911312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket 319 315011312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::samples 175 315111312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 208.468571 315211312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 208.231054 315311312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev 10.632194 315411312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 9 5.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 315511312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 175 315611312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 315711312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 315811312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 2 315911312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 337 316011312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 336.962906 316111312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 7.071068 316211312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 316311312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 2 316411312Santhony.gutierrez@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 316511312Santhony.gutierrez@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 316611312Santhony.gutierrez@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 6 316711312Santhony.gutierrez@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 2.666667 316811312Santhony.gutierrez@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.519842 316911312Santhony.gutierrez@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 1.032796 317011312Santhony.gutierrez@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 66.67% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 317111312Santhony.gutierrez@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 6 317211312Santhony.gutierrez@amd.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 317311312Santhony.gutierrez@amd.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 317411312Santhony.gutierrez@amd.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 2 317511312Santhony.gutierrez@amd.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 250.500000 317611312Santhony.gutierrez@amd.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 250.487525 317711312Santhony.gutierrez@amd.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 3.535534 317811312Santhony.gutierrez@amd.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 317911312Santhony.gutierrez@amd.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 2 318011312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 318111312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 318211312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 10090 318311312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 318411312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 318511312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 318611312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 10090 318711312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 318811312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 318911312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 322 319011312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 208.484472 319111312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 208.014366 319211312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 16.327683 319311312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 316 98.14% 98.14% | 3 0.93% 99.07% | 3 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 319411312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 322 319511312Santhony.gutierrez@amd.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 319611312Santhony.gutierrez@amd.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 319711312Santhony.gutierrez@amd.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 8 319811312Santhony.gutierrez@amd.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1 319911312Santhony.gutierrez@amd.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1 320011312Santhony.gutierrez@amd.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 320111312Santhony.gutierrez@amd.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 8 320211312Santhony.gutierrez@amd.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 320311312Santhony.gutierrez@amd.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 320411312Santhony.gutierrez@amd.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 8 320511312Santhony.gutierrez@amd.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 249.750000 320611312Santhony.gutierrez@amd.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 249.737699 320711312Santhony.gutierrez@amd.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 2.659216 320811312Santhony.gutierrez@amd.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 320911312Santhony.gutierrez@amd.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 8 321011312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 321111312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 321211312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 1 321311312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 352 321411312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 352.000000 321511312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev nan 321611312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 321711312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 1 321811312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 321911312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 322011312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::samples 1 322111312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 267 322211312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 267.000000 322311312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::stdev nan 322411312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 322511312Santhony.gutierrez@amd.comsystem.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::total 1 322611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 322711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 322811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::samples 86007 322911312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 323011312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 323111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 86007 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 323211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::total 86007 323311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::bucket_size 4 323411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::max_bucket 39 323511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::samples 54 323611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::mean 20 323711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::gmean 20.000000 323811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 54 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 323911312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::total 54 324011312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 324111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 324211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1034 324311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 208.444874 324411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 207.968565 324511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev 16.462617 324611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 324711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1034 324811312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 324911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 325011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::samples 337 325111312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 325211312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 325311312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 325411312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::total 337 325511312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::bucket_size 32 325611312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::max_bucket 319 325711312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::samples 4 325811312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::mean 206 325911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::gmean 206.000000 326011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 326111312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::total 4 326211312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 326311312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 326411312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::samples 10 326511312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 326611312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2 326711312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 326811312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::total 10 326911312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 327011312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 327111312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::samples 10 327211312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 327311312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2 327411312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 327511312Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::total 10 327611308Santhony.gutierrez@amd.comsystem.ruby.SQC_Controller.Fetch 86 0.00% 0.00% 327711308Santhony.gutierrez@amd.comsystem.ruby.SQC_Controller.TCC_AckS 5 0.00% 0.00% 327811308Santhony.gutierrez@amd.comsystem.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00% 327911308Santhony.gutierrez@amd.comsystem.ruby.SQC_Controller.S.Fetch 81 0.00% 0.00% 328011308Santhony.gutierrez@amd.comsystem.ruby.SQC_Controller.I_S.TCC_AckS 5 0.00% 0.00% 328111308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.RdBlk 53 0.00% 0.00% 328211308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.RdBlkM 36 0.00% 0.00% 328311308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.RdBlkS 5 0.00% 0.00% 328411308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.CPUPrbResp 14 0.00% 0.00% 328511308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.ProbeAcksComplete 13 0.00% 0.00% 328611308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.CoreUnblock 17 0.00% 0.00% 328711308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00% 328811308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.NB_AckS 7 0.00% 0.00% 328911308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.NB_AckM 9 0.00% 0.00% 329011308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.PrbInvData 326 0.00% 0.00% 329111308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.PrbShrData 1209 0.00% 0.00% 329211308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I.RdBlk 2 0.00% 0.00% 329311308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I.RdBlkM 9 0.00% 0.00% 329411308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I.RdBlkS 5 0.00% 0.00% 329511308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I.PrbInvData 325 0.00% 0.00% 329611308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I.PrbShrData 1200 0.00% 0.00% 329711308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.S.RdBlk 2 0.00% 0.00% 329811308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.S.PrbInvData 1 0.00% 0.00% 329911308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.M.RdBlkM 1 0.00% 0.00% 330011308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.M.PrbShrData 9 0.00% 0.00% 330111308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.CP_I.CPUPrbResp 2 0.00% 0.00% 330211308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 1 0.00% 0.00% 330311308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.CP_O.CPUPrbResp 9 0.00% 0.00% 330411308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 9 0.00% 0.00% 330511308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I_M.RdBlkM 22 0.00% 0.00% 330611308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I_M.NB_AckM 9 0.00% 0.00% 330711308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I_ES.RdBlk 41 0.00% 0.00% 330811308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I_ES.NB_AckS 2 0.00% 0.00% 330911308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I_S.NB_AckS 5 0.00% 0.00% 331011308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BBS_S.CPUPrbResp 2 0.00% 0.00% 331111308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BBS_S.ProbeAcksComplete 2 0.00% 0.00% 331211308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 1 0.00% 0.00% 331311308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 1 0.00% 0.00% 331411308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BB_M.CoreUnblock 1 0.00% 0.00% 331511308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BB_S.LastCoreUnblock 2 0.00% 0.00% 331611308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BBB_S.RdBlk 8 0.00% 0.00% 331711308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BBB_S.CoreUnblock 7 0.00% 0.00% 331811308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BBB_M.RdBlkM 4 0.00% 0.00% 331911308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BBB_M.CoreUnblock 9 0.00% 0.00% 332011308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Load | 5 50.00% 50.00% | 5 50.00% 100.00% 332111308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Load::total 10 332211308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Store | 9 50.00% 50.00% | 9 50.00% 100.00% 332311308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Store::total 18 332411308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_AckS | 2 50.00% 50.00% | 2 50.00% 100.00% 332511308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_AckS::total 4 332611308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00% 332711308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_AckM::total 10 332811308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.PrbInvData | 1 33.33% 33.33% | 2 66.67% 100.00% 332911308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.PrbInvData::total 3 333011308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.PrbShrData | 7 63.64% 63.64% | 4 36.36% 100.00% 333111308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.PrbShrData::total 11 333211308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00% 333311308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Load::total 4 333411308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Store | 5 50.00% 50.00% | 5 50.00% 100.00% 333511308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Store::total 10 333611308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.S.Load | 3 50.00% 50.00% | 3 50.00% 100.00% 333711308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.S.Load::total 6 333811308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.S.PrbInvData | 1 50.00% 50.00% | 1 50.00% 100.00% 333911308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.S.PrbInvData::total 2 334011308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.S.PrbShrData | 2 100.00% 100.00% | 0 0.00% 100.00% 334111308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.S.PrbShrData::total 2 334211308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.M.Store | 4 50.00% 50.00% | 4 50.00% 100.00% 334311308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.M.Store::total 8 334411308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.M.PrbInvData | 0 0.00% 0.00% | 1 100.00% 100.00% 334511308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.M.PrbInvData::total 1 334611308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.M.PrbShrData | 5 55.56% 55.56% | 4 44.44% 100.00% 334711308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.M.PrbShrData::total 9 334811308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I_M.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00% 334911308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I_M.TCC_AckM::total 10 335011308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I_ES.TCC_AckS | 2 50.00% 50.00% | 2 50.00% 100.00% 335111308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I_ES.TCC_AckS::total 4 335211308Santhony.gutierrez@amd.com 335311308Santhony.gutierrez@amd.com---------- End Simulation Statistics ---------- 3354