xref: /gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini

[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000

[system]
type=System
children=clk_domain cp_cntrl0 cpu0 cpu1 cpu2 dir_cntrl0 dispatcher_coalescer dispatcher_tlb dvfs_handler l1_coalescer0 l1_coalescer1 l1_tlb0 l1_tlb1 l2_coalescer l2_tlb l3_coalescer l3_tlb mem_ctrls piobus ruby sqc_cntrl0 sqc_coalescer sqc_tlb sys_port_proxy tcc_cntrl0 tccdir_cntrl0 tcp_cntrl0 tcp_cntrl1 voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:536870911:0:0:0:0
memories=system.mem_ctrls system.ruby.phys_mem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.sys_port_proxy.slave[0]

[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain

[system.cp_cntrl0]
type=CorePair_Controller
children=L1D0cache L1D1cache L1Icache L2cache mandatoryQueue probeToCore requestFromCore responseFromCore responseToCore sequencer sequencer1 triggerQueue unblockFromCore
L1D0cache=system.cp_cntrl0.L1D0cache
L1D1cache=system.cp_cntrl0.L1D1cache
L1Icache=system.cp_cntrl0.L1Icache
L2cache=system.cp_cntrl0.L2cache
buffer_size=0
clk_domain=system.clk_domain
cluster_id=0
default_p_state=UNDEFINED
eventq_index=0
issue_latency=15
l2_hit_latency=18
mandatoryQueue=system.cp_cntrl0.mandatoryQueue
number_of_TBEs=256
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
probeToCore=system.cp_cntrl0.probeToCore
recycle_latency=10
requestFromCore=system.cp_cntrl0.requestFromCore
responseFromCore=system.cp_cntrl0.responseFromCore
responseToCore=system.cp_cntrl0.responseToCore
ruby_system=system.ruby
send_evictions=true
sequencer=system.cp_cntrl0.sequencer
sequencer1=system.cp_cntrl0.sequencer1
system=system
transitions_per_cycle=32
triggerQueue=system.cp_cntrl0.triggerQueue
unblockFromCore=system.cp_cntrl0.unblockFromCore
version=0

[system.cp_cntrl0.L1D0cache]
type=RubyCache
children=replacement_policy
assoc=2
block_size=0
dataAccessLatency=1
dataArrayBanks=1
eventq_index=0
is_icache=false
replacement_policy=system.cp_cntrl0.L1D0cache.replacement_policy
resourceStalls=false
ruby_system=system.ruby
size=65536
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1

[system.cp_cntrl0.L1D0cache.replacement_policy]
type=PseudoLRUReplacementPolicy
assoc=2
block_size=64
eventq_index=0
size=65536

[system.cp_cntrl0.L1D1cache]
type=RubyCache
children=replacement_policy
assoc=2
block_size=0
dataAccessLatency=1
dataArrayBanks=1
eventq_index=0
is_icache=false
replacement_policy=system.cp_cntrl0.L1D1cache.replacement_policy
resourceStalls=false
ruby_system=system.ruby
size=65536
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1

[system.cp_cntrl0.L1D1cache.replacement_policy]
type=PseudoLRUReplacementPolicy
assoc=2
block_size=64
eventq_index=0
size=65536

[system.cp_cntrl0.L1Icache]
type=RubyCache
children=replacement_policy
assoc=2
block_size=0
dataAccessLatency=1
dataArrayBanks=1
eventq_index=0
is_icache=false
replacement_policy=system.cp_cntrl0.L1Icache.replacement_policy
resourceStalls=false
ruby_system=system.ruby
size=32768
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1

[system.cp_cntrl0.L1Icache.replacement_policy]
type=PseudoLRUReplacementPolicy
assoc=2
block_size=64
eventq_index=0
size=32768

[system.cp_cntrl0.L2cache]
type=RubyCache
children=replacement_policy
assoc=8
block_size=0
dataAccessLatency=1
dataArrayBanks=1
eventq_index=0
is_icache=false
replacement_policy=system.cp_cntrl0.L2cache.replacement_policy
resourceStalls=false
ruby_system=system.ruby
size=2097152
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1

[system.cp_cntrl0.L2cache.replacement_policy]
type=PseudoLRUReplacementPolicy
assoc=8
block_size=64
eventq_index=0
size=2097152

[system.cp_cntrl0.mandatoryQueue]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false

[system.cp_cntrl0.probeToCore]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false
slave=system.ruby.network.master[3]

[system.cp_cntrl0.requestFromCore]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false
master=system.ruby.network.slave[2]

[system.cp_cntrl0.responseFromCore]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false
master=system.ruby.network.slave[3]

[system.cp_cntrl0.responseToCore]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false
slave=system.ruby.network.master[4]

[system.cp_cntrl0.sequencer]
type=RubySequencer
clk_domain=system.clk_domain
coreid=0
dcache=system.cp_cntrl0.L1D0cache
dcache_hit_latency=2
deadlock_threshold=500000
default_p_state=UNDEFINED
eventq_index=0
garnet_standalone=false
icache=system.cp_cntrl0.L1Icache
icache_hit_latency=2
is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_ruby_tester=false
version=0
master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave
mem_master_port=system.piobus.slave[0]
slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master

[system.cp_cntrl0.sequencer1]
type=RubySequencer
clk_domain=system.clk_domain
coreid=1
dcache=system.cp_cntrl0.L1D1cache
dcache_hit_latency=2
deadlock_threshold=500000
default_p_state=UNDEFINED
eventq_index=0
garnet_standalone=false
icache=system.cp_cntrl0.L1Icache
icache_hit_latency=2
is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_ruby_tester=false
version=1

[system.cp_cntrl0.triggerQueue]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false

[system.cp_cntrl0.unblockFromCore]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false
master=system.ruby.network.slave[4]

[system.cpu0]
type=TimingSimpleCPU
children=apic_clk_domain clk_domain dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu0.clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu0.tracer
workload=system.cpu0.workload
dcache_port=system.cp_cntrl0.sequencer.slave[1]
icache_port=system.cp_cntrl0.sequencer.slave[0]

[system.cpu0.apic_clk_domain]
type=DerivedClockDomain
clk_divider=16
clk_domain=system.cpu0.clk_domain
eventq_index=0

[system.cpu0.clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain

[system.cpu0.dtb]
type=X86TLB
children=walker
eventq_index=0
size=64
walker=system.cpu0.dtb.walker

[system.cpu0.dtb.walker]
type=X86PagetableWalker
clk_domain=system.cpu0.clk_domain
default_p_state=UNDEFINED
eventq_index=0
num_squash_per_cycle=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
system=system
port=system.cp_cntrl0.sequencer.slave[3]

[system.cpu0.interrupts]
type=X86LocalApic
clk_domain=system.cpu0.apic_clk_domain
default_p_state=UNDEFINED
eventq_index=0
int_latency=1000
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=2305843009213693952
pio_latency=100000
power_model=Null
system=system
int_master=system.cp_cntrl0.sequencer.slave[4]
int_slave=system.cp_cntrl0.sequencer.master[1]
pio=system.cp_cntrl0.sequencer.master[0]

[system.cpu0.isa]
type=X86ISA
eventq_index=0

[system.cpu0.itb]
type=X86TLB
children=walker
eventq_index=0
size=64
walker=system.cpu0.itb.walker

[system.cpu0.itb.walker]
type=X86PagetableWalker
clk_domain=system.cpu0.clk_domain
default_p_state=UNDEFINED
eventq_index=0
num_squash_per_cycle=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
system=system
port=system.cp_cntrl0.sequencer.slave[2]

[system.cpu0.tracer]
type=ExeTracer
eventq_index=0

[system.cpu0.workload]
type=Process
cmd=gpu-hello
cwd=
drivers=system.cpu2.cl_driver
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
simpoint=0
system=system
uid=100
useArchPT=false

[system.cpu1]
type=Shader
children=CUs0 CUs1 clk_domain
CUs=system.cpu1.CUs0 system.cpu1.CUs1
clk_domain=system.cpu1.clk_domain
cpu_pointer=system.cpu0
default_p_state=UNDEFINED
eventq_index=0
globalmem=65536
impl_kern_boundary_sync=false
n_wf=8
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
separate_acquire_release=false
timing=true
translation=false

[system.cpu1.CUs0]
type=ComputeUnit
children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31
clk_domain=system.cpu1.clk_domain
coalescer_to_vrf_bus_width=32
countPages=false
cu_id=0
debugSegFault=false
default_p_state=UNDEFINED
dpbypass_pipe_length=4
eventq_index=0
execPolicy=OLDEST-FIRST
functionalTLB=true
global_mem_queue_size=256
issue_period=4
localDataStore=system.cpu1.CUs0.localDataStore
localMemBarrier=false
local_mem_queue_size=256
mem_req_latency=9
mem_resp_latency=9
n_wf=8
num_SIMDs=4
num_global_mem_pipes=1
num_shared_mem_pipes=1
out_of_order_data_delivery=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
perLaneTLB=false
power_model=Null
prefetch_depth=0
prefetch_prev_type=PF_PHASE
prefetch_stride=1
spbypass_pipe_length=4
system=system
vector_register_file=system.cpu1.CUs0.vector_register_file0 system.cpu1.CUs0.vector_register_file1 system.cpu1.CUs0.vector_register_file2 system.cpu1.CUs0.vector_register_file3
vrf_to_coalescer_bus_width=32
wavefronts=system.cpu1.CUs0.wavefronts00 system.cpu1.CUs0.wavefronts01 system.cpu1.CUs0.wavefronts02 system.cpu1.CUs0.wavefronts03 system.cpu1.CUs0.wavefronts04 system.cpu1.CUs0.wavefronts05 system.cpu1.CUs0.wavefronts06 system.cpu1.CUs0.wavefronts07 system.cpu1.CUs0.wavefronts08 system.cpu1.CUs0.wavefronts09 system.cpu1.CUs0.wavefronts10 system.cpu1.CUs0.wavefronts11 system.cpu1.CUs0.wavefronts12 system.cpu1.CUs0.wavefronts13 system.cpu1.CUs0.wavefronts14 system.cpu1.CUs0.wavefronts15 system.cpu1.CUs0.wavefronts16 system.cpu1.CUs0.wavefronts17 system.cpu1.CUs0.wavefronts18 system.cpu1.CUs0.wavefronts19 system.cpu1.CUs0.wavefronts20 system.cpu1.CUs0.wavefronts21 system.cpu1.CUs0.wavefronts22 system.cpu1.CUs0.wavefronts23 system.cpu1.CUs0.wavefronts24 system.cpu1.CUs0.wavefronts25 system.cpu1.CUs0.wavefronts26 system.cpu1.CUs0.wavefronts27 system.cpu1.CUs0.wavefronts28 system.cpu1.CUs0.wavefronts29 system.cpu1.CUs0.wavefronts30 system.cpu1.CUs0.wavefronts31
wfSize=64
xactCasMode=false
ldsPort=system.cpu1.CUs0.ldsBus.slave
memory_port=system.tcp_cntrl0.coalescer.slave[0] system.tcp_cntrl0.coalescer.slave[1] system.tcp_cntrl0.coalescer.slave[2] system.tcp_cntrl0.coalescer.slave[3] system.tcp_cntrl0.coalescer.slave[4] system.tcp_cntrl0.coalescer.slave[5] system.tcp_cntrl0.coalescer.slave[6] system.tcp_cntrl0.coalescer.slave[7] system.tcp_cntrl0.coalescer.slave[8] system.tcp_cntrl0.coalescer.slave[9] system.tcp_cntrl0.coalescer.slave[10] system.tcp_cntrl0.coalescer.slave[11] system.tcp_cntrl0.coalescer.slave[12] system.tcp_cntrl0.coalescer.slave[13] system.tcp_cntrl0.coalescer.slave[14] system.tcp_cntrl0.coalescer.slave[15] system.tcp_cntrl0.coalescer.slave[16] system.tcp_cntrl0.coalescer.slave[17] system.tcp_cntrl0.coalescer.slave[18] system.tcp_cntrl0.coalescer.slave[19] system.tcp_cntrl0.coalescer.slave[20] system.tcp_cntrl0.coalescer.slave[21] system.tcp_cntrl0.coalescer.slave[22] system.tcp_cntrl0.coalescer.slave[23] system.tcp_cntrl0.coalescer.slave[24] system.tcp_cntrl0.coalescer.slave[25] system.tcp_cntrl0.coalescer.slave[26] system.tcp_cntrl0.coalescer.slave[27] system.tcp_cntrl0.coalescer.slave[28] system.tcp_cntrl0.coalescer.slave[29] system.tcp_cntrl0.coalescer.slave[30] system.tcp_cntrl0.coalescer.slave[31] system.tcp_cntrl0.coalescer.slave[32] system.tcp_cntrl0.coalescer.slave[33] system.tcp_cntrl0.coalescer.slave[34] system.tcp_cntrl0.coalescer.slave[35] system.tcp_cntrl0.coalescer.slave[36] system.tcp_cntrl0.coalescer.slave[37] system.tcp_cntrl0.coalescer.slave[38] system.tcp_cntrl0.coalescer.slave[39] system.tcp_cntrl0.coalescer.slave[40] system.tcp_cntrl0.coalescer.slave[41] system.tcp_cntrl0.coalescer.slave[42] system.tcp_cntrl0.coalescer.slave[43] system.tcp_cntrl0.coalescer.slave[44] system.tcp_cntrl0.coalescer.slave[45] system.tcp_cntrl0.coalescer.slave[46] system.tcp_cntrl0.coalescer.slave[47] system.tcp_cntrl0.coalescer.slave[48] system.tcp_cntrl0.coalescer.slave[49] system.tcp_cntrl0.coalescer.slave[50] system.tcp_cntrl0.coalescer.slave[51] system.tcp_cntrl0.coalescer.slave[52] system.tcp_cntrl0.coalescer.slave[53] system.tcp_cntrl0.coalescer.slave[54] system.tcp_cntrl0.coalescer.slave[55] system.tcp_cntrl0.coalescer.slave[56] system.tcp_cntrl0.coalescer.slave[57] system.tcp_cntrl0.coalescer.slave[58] system.tcp_cntrl0.coalescer.slave[59] system.tcp_cntrl0.coalescer.slave[60] system.tcp_cntrl0.coalescer.slave[61] system.tcp_cntrl0.coalescer.slave[62] system.tcp_cntrl0.coalescer.slave[63]
sqc_port=system.sqc_cntrl0.sequencer.slave[0]
sqc_tlb_port=system.sqc_coalescer.slave[0]
translation_port=system.l1_coalescer0.slave[0]

[system.cpu1.CUs0.ldsBus]
type=Bridge
clk_domain=system.cpu1.clk_domain
default_p_state=UNDEFINED
delay=0
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ranges=0:18446744073709551615:0:0:0:0
req_size=16
resp_size=16
master=system.cpu1.CUs0.localDataStore.cuPort
slave=system.cpu1.CUs0.ldsPort

[system.cpu1.CUs0.localDataStore]
type=LdsState
bankConflictPenalty=1
banks=32
clk_domain=system.cpu1.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:65535:0:0:0:0
size=65536
cuPort=system.cpu1.CUs0.ldsBus.master

[system.cpu1.CUs0.vector_register_file0]
type=VectorRegisterFile
eventq_index=0
min_alloc=4
num_regs_per_simd=2048
simd_id=0
wfSize=64

[system.cpu1.CUs0.vector_register_file1]
type=VectorRegisterFile
eventq_index=0
min_alloc=4
num_regs_per_simd=2048
simd_id=1
wfSize=64

[system.cpu1.CUs0.vector_register_file2]
type=VectorRegisterFile
eventq_index=0
min_alloc=4
num_regs_per_simd=2048
simd_id=2
wfSize=64

[system.cpu1.CUs0.vector_register_file3]
type=VectorRegisterFile
eventq_index=0
min_alloc=4
num_regs_per_simd=2048
simd_id=3
wfSize=64

[system.cpu1.CUs0.wavefronts00]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=0

[system.cpu1.CUs0.wavefronts01]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=1

[system.cpu1.CUs0.wavefronts02]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=2

[system.cpu1.CUs0.wavefronts03]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=3

[system.cpu1.CUs0.wavefronts04]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=4

[system.cpu1.CUs0.wavefronts05]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=5

[system.cpu1.CUs0.wavefronts06]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=6

[system.cpu1.CUs0.wavefronts07]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=7

[system.cpu1.CUs0.wavefronts08]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=0

[system.cpu1.CUs0.wavefronts09]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=1

[system.cpu1.CUs0.wavefronts10]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=2

[system.cpu1.CUs0.wavefronts11]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=3

[system.cpu1.CUs0.wavefronts12]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=4

[system.cpu1.CUs0.wavefronts13]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=5

[system.cpu1.CUs0.wavefronts14]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=6

[system.cpu1.CUs0.wavefronts15]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=7

[system.cpu1.CUs0.wavefronts16]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=0

[system.cpu1.CUs0.wavefronts17]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=1

[system.cpu1.CUs0.wavefronts18]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=2

[system.cpu1.CUs0.wavefronts19]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=3

[system.cpu1.CUs0.wavefronts20]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=4

[system.cpu1.CUs0.wavefronts21]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=5

[system.cpu1.CUs0.wavefronts22]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=6

[system.cpu1.CUs0.wavefronts23]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=7

[system.cpu1.CUs0.wavefronts24]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=0

[system.cpu1.CUs0.wavefronts25]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=1

[system.cpu1.CUs0.wavefronts26]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=2

[system.cpu1.CUs0.wavefronts27]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=3

[system.cpu1.CUs0.wavefronts28]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=4

[system.cpu1.CUs0.wavefronts29]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=5

[system.cpu1.CUs0.wavefronts30]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=6

[system.cpu1.CUs0.wavefronts31]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=7

[system.cpu1.CUs1]
type=ComputeUnit
children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31
clk_domain=system.cpu1.clk_domain
coalescer_to_vrf_bus_width=32
countPages=false
cu_id=1
debugSegFault=false
default_p_state=UNDEFINED
dpbypass_pipe_length=4
eventq_index=0
execPolicy=OLDEST-FIRST
functionalTLB=true
global_mem_queue_size=256
issue_period=4
localDataStore=system.cpu1.CUs1.localDataStore
localMemBarrier=false
local_mem_queue_size=256
mem_req_latency=9
mem_resp_latency=9
n_wf=8
num_SIMDs=4
num_global_mem_pipes=1
num_shared_mem_pipes=1
out_of_order_data_delivery=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
perLaneTLB=false
power_model=Null
prefetch_depth=0
prefetch_prev_type=PF_PHASE
prefetch_stride=1
spbypass_pipe_length=4
system=system
vector_register_file=system.cpu1.CUs1.vector_register_file0 system.cpu1.CUs1.vector_register_file1 system.cpu1.CUs1.vector_register_file2 system.cpu1.CUs1.vector_register_file3
vrf_to_coalescer_bus_width=32
wavefronts=system.cpu1.CUs1.wavefronts00 system.cpu1.CUs1.wavefronts01 system.cpu1.CUs1.wavefronts02 system.cpu1.CUs1.wavefronts03 system.cpu1.CUs1.wavefronts04 system.cpu1.CUs1.wavefronts05 system.cpu1.CUs1.wavefronts06 system.cpu1.CUs1.wavefronts07 system.cpu1.CUs1.wavefronts08 system.cpu1.CUs1.wavefronts09 system.cpu1.CUs1.wavefronts10 system.cpu1.CUs1.wavefronts11 system.cpu1.CUs1.wavefronts12 system.cpu1.CUs1.wavefronts13 system.cpu1.CUs1.wavefronts14 system.cpu1.CUs1.wavefronts15 system.cpu1.CUs1.wavefronts16 system.cpu1.CUs1.wavefronts17 system.cpu1.CUs1.wavefronts18 system.cpu1.CUs1.wavefronts19 system.cpu1.CUs1.wavefronts20 system.cpu1.CUs1.wavefronts21 system.cpu1.CUs1.wavefronts22 system.cpu1.CUs1.wavefronts23 system.cpu1.CUs1.wavefronts24 system.cpu1.CUs1.wavefronts25 system.cpu1.CUs1.wavefronts26 system.cpu1.CUs1.wavefronts27 system.cpu1.CUs1.wavefronts28 system.cpu1.CUs1.wavefronts29 system.cpu1.CUs1.wavefronts30 system.cpu1.CUs1.wavefronts31
wfSize=64
xactCasMode=false
ldsPort=system.cpu1.CUs1.ldsBus.slave
memory_port=system.tcp_cntrl1.coalescer.slave[0] system.tcp_cntrl1.coalescer.slave[1] system.tcp_cntrl1.coalescer.slave[2] system.tcp_cntrl1.coalescer.slave[3] system.tcp_cntrl1.coalescer.slave[4] system.tcp_cntrl1.coalescer.slave[5] system.tcp_cntrl1.coalescer.slave[6] system.tcp_cntrl1.coalescer.slave[7] system.tcp_cntrl1.coalescer.slave[8] system.tcp_cntrl1.coalescer.slave[9] system.tcp_cntrl1.coalescer.slave[10] system.tcp_cntrl1.coalescer.slave[11] system.tcp_cntrl1.coalescer.slave[12] system.tcp_cntrl1.coalescer.slave[13] system.tcp_cntrl1.coalescer.slave[14] system.tcp_cntrl1.coalescer.slave[15] system.tcp_cntrl1.coalescer.slave[16] system.tcp_cntrl1.coalescer.slave[17] system.tcp_cntrl1.coalescer.slave[18] system.tcp_cntrl1.coalescer.slave[19] system.tcp_cntrl1.coalescer.slave[20] system.tcp_cntrl1.coalescer.slave[21] system.tcp_cntrl1.coalescer.slave[22] system.tcp_cntrl1.coalescer.slave[23] system.tcp_cntrl1.coalescer.slave[24] system.tcp_cntrl1.coalescer.slave[25] system.tcp_cntrl1.coalescer.slave[26] system.tcp_cntrl1.coalescer.slave[27] system.tcp_cntrl1.coalescer.slave[28] system.tcp_cntrl1.coalescer.slave[29] system.tcp_cntrl1.coalescer.slave[30] system.tcp_cntrl1.coalescer.slave[31] system.tcp_cntrl1.coalescer.slave[32] system.tcp_cntrl1.coalescer.slave[33] system.tcp_cntrl1.coalescer.slave[34] system.tcp_cntrl1.coalescer.slave[35] system.tcp_cntrl1.coalescer.slave[36] system.tcp_cntrl1.coalescer.slave[37] system.tcp_cntrl1.coalescer.slave[38] system.tcp_cntrl1.coalescer.slave[39] system.tcp_cntrl1.coalescer.slave[40] system.tcp_cntrl1.coalescer.slave[41] system.tcp_cntrl1.coalescer.slave[42] system.tcp_cntrl1.coalescer.slave[43] system.tcp_cntrl1.coalescer.slave[44] system.tcp_cntrl1.coalescer.slave[45] system.tcp_cntrl1.coalescer.slave[46] system.tcp_cntrl1.coalescer.slave[47] system.tcp_cntrl1.coalescer.slave[48] system.tcp_cntrl1.coalescer.slave[49] system.tcp_cntrl1.coalescer.slave[50] system.tcp_cntrl1.coalescer.slave[51] system.tcp_cntrl1.coalescer.slave[52] system.tcp_cntrl1.coalescer.slave[53] system.tcp_cntrl1.coalescer.slave[54] system.tcp_cntrl1.coalescer.slave[55] system.tcp_cntrl1.coalescer.slave[56] system.tcp_cntrl1.coalescer.slave[57] system.tcp_cntrl1.coalescer.slave[58] system.tcp_cntrl1.coalescer.slave[59] system.tcp_cntrl1.coalescer.slave[60] system.tcp_cntrl1.coalescer.slave[61] system.tcp_cntrl1.coalescer.slave[62] system.tcp_cntrl1.coalescer.slave[63]
sqc_port=system.sqc_cntrl0.sequencer.slave[1]
sqc_tlb_port=system.sqc_coalescer.slave[1]
translation_port=system.l1_coalescer1.slave[0]

[system.cpu1.CUs1.ldsBus]
type=Bridge
clk_domain=system.cpu1.clk_domain
default_p_state=UNDEFINED
delay=0
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ranges=0:18446744073709551615:0:0:0:0
req_size=16
resp_size=16
master=system.cpu1.CUs1.localDataStore.cuPort
slave=system.cpu1.CUs1.ldsPort

[system.cpu1.CUs1.localDataStore]
type=LdsState
bankConflictPenalty=1
banks=32
clk_domain=system.cpu1.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:65535:0:0:0:0
size=65536
cuPort=system.cpu1.CUs1.ldsBus.master

[system.cpu1.CUs1.vector_register_file0]
type=VectorRegisterFile
eventq_index=0
min_alloc=4
num_regs_per_simd=2048
simd_id=0
wfSize=64

[system.cpu1.CUs1.vector_register_file1]
type=VectorRegisterFile
eventq_index=0
min_alloc=4
num_regs_per_simd=2048
simd_id=1
wfSize=64

[system.cpu1.CUs1.vector_register_file2]
type=VectorRegisterFile
eventq_index=0
min_alloc=4
num_regs_per_simd=2048
simd_id=2
wfSize=64

[system.cpu1.CUs1.vector_register_file3]
type=VectorRegisterFile
eventq_index=0
min_alloc=4
num_regs_per_simd=2048
simd_id=3
wfSize=64

[system.cpu1.CUs1.wavefronts00]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=0

[system.cpu1.CUs1.wavefronts01]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=1

[system.cpu1.CUs1.wavefronts02]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=2

[system.cpu1.CUs1.wavefronts03]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=3

[system.cpu1.CUs1.wavefronts04]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=4

[system.cpu1.CUs1.wavefronts05]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=5

[system.cpu1.CUs1.wavefronts06]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=6

[system.cpu1.CUs1.wavefronts07]
type=Wavefront
eventq_index=0
simdId=0
wfSize=64
wf_slot_id=7

[system.cpu1.CUs1.wavefronts08]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=0

[system.cpu1.CUs1.wavefronts09]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=1

[system.cpu1.CUs1.wavefronts10]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=2

[system.cpu1.CUs1.wavefronts11]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=3

[system.cpu1.CUs1.wavefronts12]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=4

[system.cpu1.CUs1.wavefronts13]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=5

[system.cpu1.CUs1.wavefronts14]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=6

[system.cpu1.CUs1.wavefronts15]
type=Wavefront
eventq_index=0
simdId=1
wfSize=64
wf_slot_id=7

[system.cpu1.CUs1.wavefronts16]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=0

[system.cpu1.CUs1.wavefronts17]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=1

[system.cpu1.CUs1.wavefronts18]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=2

[system.cpu1.CUs1.wavefronts19]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=3

[system.cpu1.CUs1.wavefronts20]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=4

[system.cpu1.CUs1.wavefronts21]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=5

[system.cpu1.CUs1.wavefronts22]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=6

[system.cpu1.CUs1.wavefronts23]
type=Wavefront
eventq_index=0
simdId=2
wfSize=64
wf_slot_id=7

[system.cpu1.CUs1.wavefronts24]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=0

[system.cpu1.CUs1.wavefronts25]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=1

[system.cpu1.CUs1.wavefronts26]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=2

[system.cpu1.CUs1.wavefronts27]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=3

[system.cpu1.CUs1.wavefronts28]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=4

[system.cpu1.CUs1.wavefronts29]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=5

[system.cpu1.CUs1.wavefronts30]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=6

[system.cpu1.CUs1.wavefronts31]
type=Wavefront
eventq_index=0
simdId=3
wfSize=64
wf_slot_id=7

[system.cpu1.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.cpu1.clk_domain.voltage_domain

[system.cpu1.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

[system.cpu2]
type=GpuDispatcher
children=cl_driver
cl_driver=system.cpu2.cl_driver
clk_domain=system.clk_domain
cpu=system.cpu0
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=8589934592
pio_latency=1000
power_model=Null
shader_pointer=system.cpu1
system=system
dma=system.piobus.slave[1]
pio=system.piobus.master[0]
translation_port=system.dispatcher_coalescer.slave[0]

[system.cpu2.cl_driver]
type=ClDriver
codefile=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
eventq_index=0
filename=hsa

[system.dir_cntrl0]
type=Directory_Controller
children=L3CacheMemory L3triggerQueue directory probeToCore requestFromCores responseFromCores responseFromMemory responseToCore triggerQueue unblockFromCores
CPUonly=false
L3CacheMemory=system.dir_cntrl0.L3CacheMemory
L3triggerQueue=system.dir_cntrl0.L3triggerQueue
TCC_select_num_bits=0
buffer_size=0
clk_domain=system.clk_domain
cluster_id=0
default_p_state=UNDEFINED
directory=system.dir_cntrl0.directory
eventq_index=0
l3_hit_latency=15
noTCCdir=false
number_of_TBEs=5120
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
probeToCore=system.dir_cntrl0.probeToCore
recycle_latency=10
requestFromCores=system.dir_cntrl0.requestFromCores
responseFromCores=system.dir_cntrl0.responseFromCores
responseFromMemory=system.dir_cntrl0.responseFromMemory
responseToCore=system.dir_cntrl0.responseToCore
response_latency=30
ruby_system=system.ruby
system=system
to_memory_controller_latency=1
transitions_per_cycle=32
triggerQueue=system.dir_cntrl0.triggerQueue
unblockFromCores=system.dir_cntrl0.unblockFromCores
useL3OnWT=false
version=0
memory=system.mem_ctrls.port

[system.dir_cntrl0.L3CacheMemory]
type=RubyCache
children=replacement_policy
assoc=8
block_size=0
dataAccessLatency=20
dataArrayBanks=256.0
eventq_index=0
is_icache=false
replacement_policy=system.dir_cntrl0.L3CacheMemory.replacement_policy
resourceStalls=true
ruby_system=system.ruby
size=16777216
start_index_bit=6
tagAccessLatency=15
tagArrayBanks=256.0

[system.dir_cntrl0.L3CacheMemory.replacement_policy]
type=PseudoLRUReplacementPolicy
assoc=8
block_size=64
eventq_index=0
size=16777216

[system.dir_cntrl0.L3triggerQueue]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false

[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
eventq_index=0
numa_high_bit=5
size=536870912
system=system
version=0

[system.dir_cntrl0.probeToCore]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false
master=system.ruby.network.slave[0]

[system.dir_cntrl0.requestFromCores]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
slave=system.ruby.network.master[0]

[system.dir_cntrl0.responseFromCores]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false
slave=system.ruby.network.master[1]

[system.dir_cntrl0.responseFromMemory]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false

[system.dir_cntrl0.responseToCore]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false
master=system.ruby.network.slave[1]

[system.dir_cntrl0.triggerQueue]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false

[system.dir_cntrl0.unblockFromCores]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false
slave=system.ruby.network.master[2]

[system.dispatcher_coalescer]
type=TLBCoalescer
children=clk_domain
clk_domain=system.dispatcher_coalescer.clk_domain
coalescingWindow=1
default_p_state=UNDEFINED
disableCoalescing=false
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
probesPerCycle=2
master=system.dispatcher_tlb.slave[0]
slave=system.cpu2.translation_port

[system.dispatcher_coalescer.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.dispatcher_coalescer.clk_domain.voltage_domain

[system.dispatcher_coalescer.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

[system.dispatcher_tlb]
type=X86GPUTLB
children=clk_domain
accessDistance=false
allocationPolicy=true
assoc=32
clk_domain=system.dispatcher_tlb.clk_domain
default_p_state=UNDEFINED
eventq_index=0
hitLatency=1
maxOutstandingReqs=64
missLatency1=5
missLatency2=750
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
size=32
master=system.l2_coalescer.slave[1]
slave=system.dispatcher_coalescer.master[0]

[system.dispatcher_tlb.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.dispatcher_tlb.clk_domain.voltage_domain

[system.dispatcher_tlb.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000

[system.l1_coalescer0]
type=TLBCoalescer
children=clk_domain
clk_domain=system.l1_coalescer0.clk_domain
coalescingWindow=1
default_p_state=UNDEFINED
disableCoalescing=false
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
probesPerCycle=2
master=system.l1_tlb0.slave[0]
slave=system.cpu1.CUs0.translation_port[0]

[system.l1_coalescer0.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.l1_coalescer0.clk_domain.voltage_domain

[system.l1_coalescer0.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

[system.l1_coalescer1]
type=TLBCoalescer
children=clk_domain
clk_domain=system.l1_coalescer1.clk_domain
coalescingWindow=1
default_p_state=UNDEFINED
disableCoalescing=false
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
probesPerCycle=2
master=system.l1_tlb1.slave[0]
slave=system.cpu1.CUs1.translation_port[0]

[system.l1_coalescer1.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.l1_coalescer1.clk_domain.voltage_domain

[system.l1_coalescer1.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

[system.l1_tlb0]
type=X86GPUTLB
children=clk_domain
accessDistance=false
allocationPolicy=true
assoc=32
clk_domain=system.l1_tlb0.clk_domain
default_p_state=UNDEFINED
eventq_index=0
hitLatency=1
maxOutstandingReqs=64
missLatency1=5
missLatency2=750
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
size=32
master=system.l2_coalescer.slave[2]
slave=system.l1_coalescer0.master[0]

[system.l1_tlb0.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.l1_tlb0.clk_domain.voltage_domain

[system.l1_tlb0.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

[system.l1_tlb1]
type=X86GPUTLB
children=clk_domain
accessDistance=false
allocationPolicy=true
assoc=32
clk_domain=system.l1_tlb1.clk_domain
default_p_state=UNDEFINED
eventq_index=0
hitLatency=1
maxOutstandingReqs=64
missLatency1=5
missLatency2=750
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
size=32
master=system.l2_coalescer.slave[3]
slave=system.l1_coalescer1.master[0]

[system.l1_tlb1.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.l1_tlb1.clk_domain.voltage_domain

[system.l1_tlb1.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

[system.l2_coalescer]
type=TLBCoalescer
children=clk_domain
clk_domain=system.l2_coalescer.clk_domain
coalescingWindow=1
default_p_state=UNDEFINED
disableCoalescing=false
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
probesPerCycle=2
master=system.l2_tlb.slave[0]
slave=system.sqc_tlb.master[0] system.dispatcher_tlb.master[0] system.l1_tlb0.master[0] system.l1_tlb1.master[0]

[system.l2_coalescer.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.l2_coalescer.clk_domain.voltage_domain

[system.l2_coalescer.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

[system.l2_tlb]
type=X86GPUTLB
children=clk_domain
accessDistance=false
allocationPolicy=true
assoc=32
clk_domain=system.l2_tlb.clk_domain
default_p_state=UNDEFINED
eventq_index=0
hitLatency=69
maxOutstandingReqs=64
missLatency1=5
missLatency2=750
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
size=4096
master=system.l3_coalescer.slave[0]
slave=system.l2_coalescer.master[0]

[system.l2_tlb.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.l2_tlb.clk_domain.voltage_domain

[system.l2_tlb.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

[system.l3_coalescer]
type=TLBCoalescer
children=clk_domain
clk_domain=system.l3_coalescer.clk_domain
coalescingWindow=1
default_p_state=UNDEFINED
disableCoalescing=false
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
probesPerCycle=2
master=system.l3_tlb.slave[0]
slave=system.l2_tlb.master[0]

[system.l3_coalescer.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.l3_coalescer.clk_domain.voltage_domain

[system.l3_coalescer.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

[system.l3_tlb]
type=X86GPUTLB
children=clk_domain
accessDistance=false
allocationPolicy=true
assoc=32
clk_domain=system.l3_tlb.clk_domain
default_p_state=UNDEFINED
eventq_index=0
hitLatency=150
maxOutstandingReqs=64
missLatency1=5
missLatency2=750
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
size=8192
slave=system.l3_coalescer.master[0]

[system.l3_tlb.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.l3_tlb.clk_domain.voltage_domain

[system.l3_tlb.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

[system.mem_ctrls]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=false
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:536870911:5:19:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.dir_cntrl0.memory

[system.piobus]
type=NoncoherentXBar
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
response_latency=0
use_default_range=false
width=32
master=system.cpu2.pio
slave=system.cp_cntrl0.sequencer.mem_master_port system.cpu2.dma

[system.ruby]
type=RubySystem
children=clk_domain network phys_mem
access_backing_store=true
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
default_p_state=UNDEFINED
eventq_index=0
hot_lines=false
memory_size_bits=48
num_of_sequencers=5
number_of_virtual_networks=10
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
phys_mem=system.ruby.phys_mem
power_model=Null
randomization=false

[system.ruby.clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain

[system.ruby.network]
type=SimpleNetwork
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_link_buffers72 int_link_buffers73 int_link_buffers74 int_link_buffers75 int_link_buffers76 int_link_buffers77 int_link_buffers78 int_link_buffers79 int_links0 int_links1 int_links2 int_links3
adaptive_routing=false
buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
default_p_state=UNDEFINED
endpoint_bandwidth=1000
eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6
int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 system.ruby.network.int_link_buffers72 system.ruby.network.int_link_buffers73 system.ruby.network.int_link_buffers74 system.ruby.network.int_link_buffers75 system.ruby.network.int_link_buffers76 system.ruby.network.int_link_buffers77 system.ruby.network.int_link_buffers78 system.ruby.network.int_link_buffers79
int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
netifs=
number_of_virtual_networks=10
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
routers=system.ruby.network.ext_links0.int_node system.ruby.network.ext_links1.int_node system.ruby.network.ext_links2.int_node
ruby_system=system.ruby
topology=Crossbar
master=system.dir_cntrl0.requestFromCores.slave system.dir_cntrl0.responseFromCores.slave system.dir_cntrl0.unblockFromCores.slave system.cp_cntrl0.probeToCore.slave system.cp_cntrl0.responseToCore.slave system.tcp_cntrl0.probeToTCP.slave system.tcp_cntrl0.responseToTCP.slave system.tcp_cntrl1.probeToTCP.slave system.tcp_cntrl1.responseToTCP.slave system.sqc_cntrl0.probeToSQC.slave system.sqc_cntrl0.responseToSQC.slave system.tcc_cntrl0.responseToTCC.slave system.tccdir_cntrl0.requestFromTCP.slave system.tccdir_cntrl0.responseFromTCP.slave system.tccdir_cntrl0.unblockFromTCP.slave system.tccdir_cntrl0.probeFromNB.slave system.tccdir_cntrl0.responseFromNB.slave
slave=system.dir_cntrl0.probeToCore.master system.dir_cntrl0.responseToCore.master system.cp_cntrl0.requestFromCore.master system.cp_cntrl0.responseFromCore.master system.cp_cntrl0.unblockFromCore.master system.tcp_cntrl0.requestFromTCP.master system.tcp_cntrl0.responseFromTCP.master system.tcp_cntrl0.unblockFromCore.master system.tcp_cntrl1.requestFromTCP.master system.tcp_cntrl1.responseFromTCP.master system.tcp_cntrl1.unblockFromCore.master system.sqc_cntrl0.requestFromSQC.master system.sqc_cntrl0.responseFromSQC.master system.sqc_cntrl0.unblockFromCore.master system.tcc_cntrl0.responseFromTCC.master system.tccdir_cntrl0.probeToCore.master system.tccdir_cntrl0.responseToCore.master system.tccdir_cntrl0.requestToNB.master system.tccdir_cntrl0.responseToNB.master system.tccdir_cntrl0.unblockToNB.master

[system.ruby.network.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=512
eventq_index=0
ext_node=system.dir_cntrl0
int_node=system.ruby.network.ext_links0.int_node
latency=1
link_id=0
weight=1

[system.ruby.network.ext_links0.int_node]
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 port_buffers36 port_buffers37 port_buffers38 port_buffers39 port_buffers40 port_buffers41 port_buffers42 port_buffers43 port_buffers44 port_buffers45 port_buffers46 port_buffers47 port_buffers48 port_buffers49 port_buffers50 port_buffers51 port_buffers52 port_buffers53 port_buffers54 port_buffers55 port_buffers56 port_buffers57 port_buffers58 port_buffers59 port_buffers60 port_buffers61 port_buffers62 port_buffers63 port_buffers64 port_buffers65 port_buffers66 port_buffers67 port_buffers68 port_buffers69 port_buffers70 port_buffers71 port_buffers72 port_buffers73 port_buffers74 port_buffers75 port_buffers76 port_buffers77 port_buffers78 port_buffers79 port_buffers80 port_buffers81 port_buffers82 port_buffers83 port_buffers84 port_buffers85 port_buffers86 port_buffers87 port_buffers88 port_buffers89
clk_domain=system.ruby.clk_domain
default_p_state=UNDEFINED
eventq_index=0
latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
port_buffers=system.ruby.network.ext_links0.int_node.port_buffers00 system.ruby.network.ext_links0.int_node.port_buffers01 system.ruby.network.ext_links0.int_node.port_buffers02 system.ruby.network.ext_links0.int_node.port_buffers03 system.ruby.network.ext_links0.int_node.port_buffers04 system.ruby.network.ext_links0.int_node.port_buffers05 system.ruby.network.ext_links0.int_node.port_buffers06 system.ruby.network.ext_links0.int_node.port_buffers07 system.ruby.network.ext_links0.int_node.port_buffers08 system.ruby.network.ext_links0.int_node.port_buffers09 system.ruby.network.ext_links0.int_node.port_buffers10 system.ruby.network.ext_links0.int_node.port_buffers11 system.ruby.network.ext_links0.int_node.port_buffers12 system.ruby.network.ext_links0.int_node.port_buffers13 system.ruby.network.ext_links0.int_node.port_buffers14 system.ruby.network.ext_links0.int_node.port_buffers15 system.ruby.network.ext_links0.int_node.port_buffers16 system.ruby.network.ext_links0.int_node.port_buffers17 system.ruby.network.ext_links0.int_node.port_buffers18 system.ruby.network.ext_links0.int_node.port_buffers19 system.ruby.network.ext_links0.int_node.port_buffers20 system.ruby.network.ext_links0.int_node.port_buffers21 system.ruby.network.ext_links0.int_node.port_buffers22 system.ruby.network.ext_links0.int_node.port_buffers23 system.ruby.network.ext_links0.int_node.port_buffers24 system.ruby.network.ext_links0.int_node.port_buffers25 system.ruby.network.ext_links0.int_node.port_buffers26 system.ruby.network.ext_links0.int_node.port_buffers27 system.ruby.network.ext_links0.int_node.port_buffers28 system.ruby.network.ext_links0.int_node.port_buffers29 system.ruby.network.ext_links0.int_node.port_buffers30 system.ruby.network.ext_links0.int_node.port_buffers31 system.ruby.network.ext_links0.int_node.port_buffers32 system.ruby.network.ext_links0.int_node.port_buffers33 system.ruby.network.ext_links0.int_node.port_buffers34 system.ruby.network.ext_links0.int_node.port_buffers35 system.ruby.network.ext_links0.int_node.port_buffers36 system.ruby.network.ext_links0.int_node.port_buffers37 system.ruby.network.ext_links0.int_node.port_buffers38 system.ruby.network.ext_links0.int_node.port_buffers39 system.ruby.network.ext_links0.int_node.port_buffers40 system.ruby.network.ext_links0.int_node.port_buffers41 system.ruby.network.ext_links0.int_node.port_buffers42 system.ruby.network.ext_links0.int_node.port_buffers43 system.ruby.network.ext_links0.int_node.port_buffers44 system.ruby.network.ext_links0.int_node.port_buffers45 system.ruby.network.ext_links0.int_node.port_buffers46 system.ruby.network.ext_links0.int_node.port_buffers47 system.ruby.network.ext_links0.int_node.port_buffers48 system.ruby.network.ext_links0.int_node.port_buffers49 system.ruby.network.ext_links0.int_node.port_buffers50 system.ruby.network.ext_links0.int_node.port_buffers51 system.ruby.network.ext_links0.int_node.port_buffers52 system.ruby.network.ext_links0.int_node.port_buffers53 system.ruby.network.ext_links0.int_node.port_buffers54 system.ruby.network.ext_links0.int_node.port_buffers55 system.ruby.network.ext_links0.int_node.port_buffers56 system.ruby.network.ext_links0.int_node.port_buffers57 system.ruby.network.ext_links0.int_node.port_buffers58 system.ruby.network.ext_links0.int_node.port_buffers59 system.ruby.network.ext_links0.int_node.port_buffers60 system.ruby.network.ext_links0.int_node.port_buffers61 system.ruby.network.ext_links0.int_node.port_buffers62 system.ruby.network.ext_links0.int_node.port_buffers63 system.ruby.network.ext_links0.int_node.port_buffers64 system.ruby.network.ext_links0.int_node.port_buffers65 system.ruby.network.ext_links0.int_node.port_buffers66 system.ruby.network.ext_links0.int_node.port_buffers67 system.ruby.network.ext_links0.int_node.port_buffers68 system.ruby.network.ext_links0.int_node.port_buffers69 system.ruby.network.ext_links0.int_node.port_buffers70 system.ruby.network.ext_links0.int_node.port_buffers71 system.ruby.network.ext_links0.int_node.port_buffers72 system.ruby.network.ext_links0.int_node.port_buffers73 system.ruby.network.ext_links0.int_node.port_buffers74 system.ruby.network.ext_links0.int_node.port_buffers75 system.ruby.network.ext_links0.int_node.port_buffers76 system.ruby.network.ext_links0.int_node.port_buffers77 system.ruby.network.ext_links0.int_node.port_buffers78 system.ruby.network.ext_links0.int_node.port_buffers79 system.ruby.network.ext_links0.int_node.port_buffers80 system.ruby.network.ext_links0.int_node.port_buffers81 system.ruby.network.ext_links0.int_node.port_buffers82 system.ruby.network.ext_links0.int_node.port_buffers83 system.ruby.network.ext_links0.int_node.port_buffers84 system.ruby.network.ext_links0.int_node.port_buffers85 system.ruby.network.ext_links0.int_node.port_buffers86 system.ruby.network.ext_links0.int_node.port_buffers87 system.ruby.network.ext_links0.int_node.port_buffers88 system.ruby.network.ext_links0.int_node.port_buffers89
power_model=Null
router_id=0
virt_nets=10

[system.ruby.network.ext_links0.int_node.port_buffers00]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false

[system.ruby.network.ext_links0.int_node.port_buffers01]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false

[system.ruby.network.ext_links0.int_node.port_buffers02]
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[system.ruby.network.ext_links5]
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[system.ruby.network.ext_links6]
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type=MessageBuffer
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type=MessageBuffer
buffer_size=0
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ordered=true
randomization=false

[system.ruby.network.int_link_buffers76]
type=MessageBuffer
buffer_size=0
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ordered=true
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[system.ruby.network.int_link_buffers77]
type=MessageBuffer
buffer_size=0
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ordered=true
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[system.ruby.network.int_link_buffers78]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false

[system.ruby.network.int_link_buffers79]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false

[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=512
dst_inport=
dst_node=system.ruby.network.ext_links1.int_node
eventq_index=0
latency=1
link_id=0
src_node=system.ruby.network.ext_links0.int_node
src_outport=
weight=1

[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=512
dst_inport=
dst_node=system.ruby.network.ext_links0.int_node
eventq_index=0
latency=1
link_id=1
src_node=system.ruby.network.ext_links1.int_node
src_outport=
weight=1

[system.ruby.network.int_links2]
type=SimpleIntLink
bandwidth_factor=512
dst_inport=
dst_node=system.ruby.network.ext_links2.int_node
eventq_index=0
latency=1
link_id=2
src_node=system.ruby.network.ext_links0.int_node
src_outport=
weight=1

[system.ruby.network.int_links3]
type=SimpleIntLink
bandwidth_factor=512
dst_inport=
dst_node=system.ruby.network.ext_links0.int_node
eventq_index=0
latency=1
link_id=3
src_node=system.ruby.network.ext_links2.int_node
src_outport=
weight=1

[system.ruby.phys_mem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.ruby.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=false
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:536870911:0:0:0:0

[system.sqc_cntrl0]
type=SQC_Controller
children=L1cache mandatoryQueue probeToSQC requestFromSQC responseFromSQC responseToSQC sequencer unblockFromCore
L1cache=system.sqc_cntrl0.L1cache
TCC_select_num_bits=0
buffer_size=0
clk_domain=system.clk_domain
cluster_id=0
default_p_state=UNDEFINED
eventq_index=0
issue_latency=80
l2_hit_latency=18
mandatoryQueue=system.sqc_cntrl0.mandatoryQueue
number_of_TBEs=256
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
probeToSQC=system.sqc_cntrl0.probeToSQC
recycle_latency=10
requestFromSQC=system.sqc_cntrl0.requestFromSQC
responseFromSQC=system.sqc_cntrl0.responseFromSQC
responseToSQC=system.sqc_cntrl0.responseToSQC
ruby_system=system.ruby
sequencer=system.sqc_cntrl0.sequencer
system=system
transitions_per_cycle=32
unblockFromCore=system.sqc_cntrl0.unblockFromCore
version=0

[system.sqc_cntrl0.L1cache]
type=RubyCache
children=replacement_policy
assoc=8
block_size=0
dataAccessLatency=4
dataArrayBanks=16
eventq_index=0
is_icache=false
replacement_policy=system.sqc_cntrl0.L1cache.replacement_policy
resourceStalls=true
ruby_system=system.ruby
size=32768
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=4

[system.sqc_cntrl0.L1cache.replacement_policy]
type=PseudoLRUReplacementPolicy
assoc=8
block_size=64
eventq_index=0
size=32768

[system.sqc_cntrl0.mandatoryQueue]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false

[system.sqc_cntrl0.probeToSQC]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
slave=system.ruby.network.master[9]

[system.sqc_cntrl0.requestFromSQC]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
master=system.ruby.network.slave[11]

[system.sqc_cntrl0.responseFromSQC]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
master=system.ruby.network.slave[12]

[system.sqc_cntrl0.responseToSQC]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
slave=system.ruby.network.master[10]

[system.sqc_cntrl0.sequencer]
type=RubySequencer
clk_domain=system.clk_domain
coreid=99
dcache=system.sqc_cntrl0.L1cache
dcache_hit_latency=1
deadlock_threshold=500000
default_p_state=UNDEFINED
eventq_index=0
garnet_standalone=false
icache=system.sqc_cntrl0.L1cache
icache_hit_latency=1
is_cpu_sequencer=false
max_outstanding_requests=16
no_retry_on_stall=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ruby_system=system.ruby
support_data_reqs=false
support_inst_reqs=true
system=system
using_ruby_tester=false
version=6
slave=system.cpu1.CUs0.sqc_port system.cpu1.CUs1.sqc_port

[system.sqc_cntrl0.unblockFromCore]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
master=system.ruby.network.slave[13]

[system.sqc_coalescer]
type=TLBCoalescer
children=clk_domain
clk_domain=system.sqc_coalescer.clk_domain
coalescingWindow=1
default_p_state=UNDEFINED
disableCoalescing=false
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
probesPerCycle=2
master=system.sqc_tlb.slave[0]
slave=system.cpu1.CUs0.sqc_tlb_port system.cpu1.CUs1.sqc_tlb_port

[system.sqc_coalescer.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.sqc_coalescer.clk_domain.voltage_domain

[system.sqc_coalescer.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

[system.sqc_tlb]
type=X86GPUTLB
children=clk_domain
accessDistance=false
allocationPolicy=true
assoc=32
clk_domain=system.sqc_tlb.clk_domain
default_p_state=UNDEFINED
eventq_index=0
hitLatency=1
maxOutstandingReqs=64
missLatency1=5
missLatency2=750
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
size=32
master=system.l2_coalescer.slave[0]
slave=system.sqc_coalescer.master[0]

[system.sqc_tlb.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.sqc_tlb.clk_domain.voltage_domain

[system.sqc_tlb.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

[system.sys_port_proxy]
type=RubyPortProxy
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_cpu_sequencer=true
no_retry_on_stall=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_ruby_tester=false
version=0
slave=system.system_port

[system.tcc_cntrl0]
type=TCC_Controller
children=L2cache responseFromTCC responseToTCC w_TCCUnblockToTCCDir w_probeToTCC w_reqToTCC w_reqToTCCDir w_respToTCC w_respToTCCDir
L2cache=system.tcc_cntrl0.L2cache
TCC_select_num_bits=0
buffer_size=0
clk_domain=system.clk_domain
cluster_id=0
default_p_state=UNDEFINED
eventq_index=0
l2_request_latency=1
l2_response_latency=16
number_of_TBEs=2048
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
recycle_latency=10
responseFromTCC=system.tcc_cntrl0.responseFromTCC
responseToTCC=system.tcc_cntrl0.responseToTCC
ruby_system=system.ruby
system=system
transitions_per_cycle=32
version=0
w_TCCUnblockToTCCDir=system.tcc_cntrl0.w_TCCUnblockToTCCDir
w_probeToTCC=system.tcc_cntrl0.w_probeToTCC
w_reqToTCC=system.tcc_cntrl0.w_reqToTCC
w_reqToTCCDir=system.tcc_cntrl0.w_reqToTCCDir
w_respToTCC=system.tcc_cntrl0.w_respToTCC
w_respToTCCDir=system.tcc_cntrl0.w_respToTCCDir

[system.tcc_cntrl0.L2cache]
type=RubyCache
children=replacement_policy
assoc=16
block_size=0
dataAccessLatency=8
dataArrayBanks=256
eventq_index=0
is_icache=false
replacement_policy=system.tcc_cntrl0.L2cache.replacement_policy
resourceStalls=true
ruby_system=system.ruby
size=262144.0
start_index_bit=6
tagAccessLatency=2
tagArrayBanks=256

[system.tcc_cntrl0.L2cache.replacement_policy]
type=PseudoLRUReplacementPolicy
assoc=16
block_size=64
eventq_index=0
size=262144.0

[system.tcc_cntrl0.responseFromTCC]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
master=system.ruby.network.slave[14]

[system.tcc_cntrl0.responseToTCC]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
slave=system.ruby.network.master[11]

[system.tcc_cntrl0.w_TCCUnblockToTCCDir]
type=RubyWireBuffer
eventq_index=0
ruby_system=system.ruby

[system.tcc_cntrl0.w_probeToTCC]
type=RubyWireBuffer
eventq_index=0
ruby_system=system.ruby

[system.tcc_cntrl0.w_reqToTCC]
type=RubyWireBuffer
eventq_index=0
ruby_system=system.ruby

[system.tcc_cntrl0.w_reqToTCCDir]
type=RubyWireBuffer
eventq_index=0
ruby_system=system.ruby

[system.tcc_cntrl0.w_respToTCC]
type=RubyWireBuffer
eventq_index=0
ruby_system=system.ruby

[system.tcc_cntrl0.w_respToTCCDir]
type=RubyWireBuffer
eventq_index=0
ruby_system=system.ruby

[system.tccdir_cntrl0]
type=TCCdir_Controller
children=directory probeFromNB probeToCore requestFromTCP requestToNB responseFromNB responseFromTCP responseToCore responseToNB triggerQueue unblockFromTCP unblockToNB
TCC_select_num_bits=0
buffer_size=0
clk_domain=system.clk_domain
cluster_id=0
default_p_state=UNDEFINED
directory=system.tccdir_cntrl0.directory
directory_latency=6
eventq_index=0
issue_latency=120
number_of_TBEs=1024
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
probeFromNB=system.tccdir_cntrl0.probeFromNB
probeToCore=system.tccdir_cntrl0.probeToCore
recycle_latency=10
requestFromTCP=system.tccdir_cntrl0.requestFromTCP
requestToNB=system.tccdir_cntrl0.requestToNB
responseFromNB=system.tccdir_cntrl0.responseFromNB
responseFromTCP=system.tccdir_cntrl0.responseFromTCP
responseToCore=system.tccdir_cntrl0.responseToCore
responseToNB=system.tccdir_cntrl0.responseToNB
response_latency=5
ruby_system=system.ruby
system=system
transitions_per_cycle=32
triggerQueue=system.tccdir_cntrl0.triggerQueue
unblockFromTCP=system.tccdir_cntrl0.unblockFromTCP
unblockToNB=system.tccdir_cntrl0.unblockToNB
version=0
w_TCCUnblockToTCCDir=system.tcc_cntrl0.w_TCCUnblockToTCCDir
w_probeToTCC=system.tcc_cntrl0.w_probeToTCC
w_reqToTCC=system.tcc_cntrl0.w_reqToTCC
w_reqToTCCDir=system.tcc_cntrl0.w_reqToTCCDir
w_respToTCC=system.tcc_cntrl0.w_respToTCC
w_respToTCCDir=system.tcc_cntrl0.w_respToTCCDir

[system.tccdir_cntrl0.directory]
type=RubyCache
children=replacement_policy
assoc=16
block_size=0
dataAccessLatency=1
dataArrayBanks=1
eventq_index=0
is_icache=false
replacement_policy=system.tccdir_cntrl0.directory.replacement_policy
resourceStalls=false
ruby_system=system.ruby
size=393216
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1

[system.tccdir_cntrl0.directory.replacement_policy]
type=PseudoLRUReplacementPolicy
assoc=16
block_size=64
eventq_index=0
size=393216

[system.tccdir_cntrl0.probeFromNB]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false
slave=system.ruby.network.master[15]

[system.tccdir_cntrl0.probeToCore]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
master=system.ruby.network.slave[15]

[system.tccdir_cntrl0.requestFromTCP]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
slave=system.ruby.network.master[12]

[system.tccdir_cntrl0.requestToNB]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false
master=system.ruby.network.slave[17]

[system.tccdir_cntrl0.responseFromNB]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false
slave=system.ruby.network.master[16]

[system.tccdir_cntrl0.responseFromTCP]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
slave=system.ruby.network.master[13]

[system.tccdir_cntrl0.responseToCore]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
master=system.ruby.network.slave[16]

[system.tccdir_cntrl0.responseToNB]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false
master=system.ruby.network.slave[18]

[system.tccdir_cntrl0.triggerQueue]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false

[system.tccdir_cntrl0.unblockFromTCP]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
slave=system.ruby.network.master[14]

[system.tccdir_cntrl0.unblockToNB]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false
master=system.ruby.network.slave[19]

[system.tcp_cntrl0]
type=TCP_Controller
children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
L1cache=system.tcp_cntrl0.L1cache
TCC_select_num_bits=0
buffer_size=0
clk_domain=system.clk_domain
cluster_id=0
coalescer=system.tcp_cntrl0.coalescer
default_p_state=UNDEFINED
eventq_index=0
issue_latency=40
l2_hit_latency=18
mandatoryQueue=system.tcp_cntrl0.mandatoryQueue
number_of_TBEs=2560
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
probeToTCP=system.tcp_cntrl0.probeToTCP
recycle_latency=10
requestFromTCP=system.tcp_cntrl0.requestFromTCP
responseFromTCP=system.tcp_cntrl0.responseFromTCP
responseToTCP=system.tcp_cntrl0.responseToTCP
ruby_system=system.ruby
sequencer=system.tcp_cntrl0.sequencer
system=system
transitions_per_cycle=32
unblockFromCore=system.tcp_cntrl0.unblockFromCore
use_seq_not_coal=false
version=0

[system.tcp_cntrl0.L1cache]
type=RubyCache
children=replacement_policy
assoc=8
block_size=0
dataAccessLatency=4
dataArrayBanks=16
eventq_index=0
is_icache=false
replacement_policy=system.tcp_cntrl0.L1cache.replacement_policy
resourceStalls=true
ruby_system=system.ruby
size=16384
start_index_bit=6
tagAccessLatency=4
tagArrayBanks=4

[system.tcp_cntrl0.L1cache.replacement_policy]
type=PseudoLRUReplacementPolicy
assoc=8
block_size=64
eventq_index=0
size=16384

[system.tcp_cntrl0.coalescer]
type=RubyGPUCoalescer
assume_rfo=true
clk_domain=system.clk_domain
dcache=system.tcp_cntrl0.L1cache
dcache_hit_latency=1
deadlock_threshold=500000
default_p_state=UNDEFINED
eventq_index=0
garnet_standalone=false
icache=system.tcp_cntrl0.L1cache
is_cpu_sequencer=false
max_outstanding_requests=2048
no_retry_on_stall=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=false
system=system
using_ruby_tester=false
version=2
slave=system.cpu1.CUs0.memory_port[0] system.cpu1.CUs0.memory_port[1] system.cpu1.CUs0.memory_port[2] system.cpu1.CUs0.memory_port[3] system.cpu1.CUs0.memory_port[4] system.cpu1.CUs0.memory_port[5] system.cpu1.CUs0.memory_port[6] system.cpu1.CUs0.memory_port[7] system.cpu1.CUs0.memory_port[8] system.cpu1.CUs0.memory_port[9] system.cpu1.CUs0.memory_port[10] system.cpu1.CUs0.memory_port[11] system.cpu1.CUs0.memory_port[12] system.cpu1.CUs0.memory_port[13] system.cpu1.CUs0.memory_port[14] system.cpu1.CUs0.memory_port[15] system.cpu1.CUs0.memory_port[16] system.cpu1.CUs0.memory_port[17] system.cpu1.CUs0.memory_port[18] system.cpu1.CUs0.memory_port[19] system.cpu1.CUs0.memory_port[20] system.cpu1.CUs0.memory_port[21] system.cpu1.CUs0.memory_port[22] system.cpu1.CUs0.memory_port[23] system.cpu1.CUs0.memory_port[24] system.cpu1.CUs0.memory_port[25] system.cpu1.CUs0.memory_port[26] system.cpu1.CUs0.memory_port[27] system.cpu1.CUs0.memory_port[28] system.cpu1.CUs0.memory_port[29] system.cpu1.CUs0.memory_port[30] system.cpu1.CUs0.memory_port[31] system.cpu1.CUs0.memory_port[32] system.cpu1.CUs0.memory_port[33] system.cpu1.CUs0.memory_port[34] system.cpu1.CUs0.memory_port[35] system.cpu1.CUs0.memory_port[36] system.cpu1.CUs0.memory_port[37] system.cpu1.CUs0.memory_port[38] system.cpu1.CUs0.memory_port[39] system.cpu1.CUs0.memory_port[40] system.cpu1.CUs0.memory_port[41] system.cpu1.CUs0.memory_port[42] system.cpu1.CUs0.memory_port[43] system.cpu1.CUs0.memory_port[44] system.cpu1.CUs0.memory_port[45] system.cpu1.CUs0.memory_port[46] system.cpu1.CUs0.memory_port[47] system.cpu1.CUs0.memory_port[48] system.cpu1.CUs0.memory_port[49] system.cpu1.CUs0.memory_port[50] system.cpu1.CUs0.memory_port[51] system.cpu1.CUs0.memory_port[52] system.cpu1.CUs0.memory_port[53] system.cpu1.CUs0.memory_port[54] system.cpu1.CUs0.memory_port[55] system.cpu1.CUs0.memory_port[56] system.cpu1.CUs0.memory_port[57] system.cpu1.CUs0.memory_port[58] system.cpu1.CUs0.memory_port[59] system.cpu1.CUs0.memory_port[60] system.cpu1.CUs0.memory_port[61] system.cpu1.CUs0.memory_port[62] system.cpu1.CUs0.memory_port[63]

[system.tcp_cntrl0.mandatoryQueue]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false

[system.tcp_cntrl0.probeToTCP]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
slave=system.ruby.network.master[5]

[system.tcp_cntrl0.requestFromTCP]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
master=system.ruby.network.slave[5]

[system.tcp_cntrl0.responseFromTCP]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
master=system.ruby.network.slave[6]

[system.tcp_cntrl0.responseToTCP]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
slave=system.ruby.network.master[6]

[system.tcp_cntrl0.sequencer]
type=RubySequencer
clk_domain=system.clk_domain
coreid=99
dcache=system.tcp_cntrl0.L1cache
dcache_hit_latency=1
deadlock_threshold=500000
default_p_state=UNDEFINED
eventq_index=0
garnet_standalone=false
icache=system.tcp_cntrl0.L1cache
icache_hit_latency=1
is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_ruby_tester=false
version=3

[system.tcp_cntrl0.unblockFromCore]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
master=system.ruby.network.slave[7]

[system.tcp_cntrl1]
type=TCP_Controller
children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
L1cache=system.tcp_cntrl1.L1cache
TCC_select_num_bits=0
buffer_size=0
clk_domain=system.clk_domain
cluster_id=0
coalescer=system.tcp_cntrl1.coalescer
default_p_state=UNDEFINED
eventq_index=0
issue_latency=40
l2_hit_latency=18
mandatoryQueue=system.tcp_cntrl1.mandatoryQueue
number_of_TBEs=2560
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
probeToTCP=system.tcp_cntrl1.probeToTCP
recycle_latency=10
requestFromTCP=system.tcp_cntrl1.requestFromTCP
responseFromTCP=system.tcp_cntrl1.responseFromTCP
responseToTCP=system.tcp_cntrl1.responseToTCP
ruby_system=system.ruby
sequencer=system.tcp_cntrl1.sequencer
system=system
transitions_per_cycle=32
unblockFromCore=system.tcp_cntrl1.unblockFromCore
use_seq_not_coal=false
version=1

[system.tcp_cntrl1.L1cache]
type=RubyCache
children=replacement_policy
assoc=8
block_size=0
dataAccessLatency=4
dataArrayBanks=16
eventq_index=0
is_icache=false
replacement_policy=system.tcp_cntrl1.L1cache.replacement_policy
resourceStalls=true
ruby_system=system.ruby
size=16384
start_index_bit=6
tagAccessLatency=4
tagArrayBanks=4

[system.tcp_cntrl1.L1cache.replacement_policy]
type=PseudoLRUReplacementPolicy
assoc=8
block_size=64
eventq_index=0
size=16384

[system.tcp_cntrl1.coalescer]
type=RubyGPUCoalescer
assume_rfo=true
clk_domain=system.clk_domain
dcache=system.tcp_cntrl1.L1cache
dcache_hit_latency=1
deadlock_threshold=500000
default_p_state=UNDEFINED
eventq_index=0
garnet_standalone=false
icache=system.tcp_cntrl1.L1cache
is_cpu_sequencer=false
max_outstanding_requests=2048
no_retry_on_stall=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=false
system=system
using_ruby_tester=false
version=4
slave=system.cpu1.CUs1.memory_port[0] system.cpu1.CUs1.memory_port[1] system.cpu1.CUs1.memory_port[2] system.cpu1.CUs1.memory_port[3] system.cpu1.CUs1.memory_port[4] system.cpu1.CUs1.memory_port[5] system.cpu1.CUs1.memory_port[6] system.cpu1.CUs1.memory_port[7] system.cpu1.CUs1.memory_port[8] system.cpu1.CUs1.memory_port[9] system.cpu1.CUs1.memory_port[10] system.cpu1.CUs1.memory_port[11] system.cpu1.CUs1.memory_port[12] system.cpu1.CUs1.memory_port[13] system.cpu1.CUs1.memory_port[14] system.cpu1.CUs1.memory_port[15] system.cpu1.CUs1.memory_port[16] system.cpu1.CUs1.memory_port[17] system.cpu1.CUs1.memory_port[18] system.cpu1.CUs1.memory_port[19] system.cpu1.CUs1.memory_port[20] system.cpu1.CUs1.memory_port[21] system.cpu1.CUs1.memory_port[22] system.cpu1.CUs1.memory_port[23] system.cpu1.CUs1.memory_port[24] system.cpu1.CUs1.memory_port[25] system.cpu1.CUs1.memory_port[26] system.cpu1.CUs1.memory_port[27] system.cpu1.CUs1.memory_port[28] system.cpu1.CUs1.memory_port[29] system.cpu1.CUs1.memory_port[30] system.cpu1.CUs1.memory_port[31] system.cpu1.CUs1.memory_port[32] system.cpu1.CUs1.memory_port[33] system.cpu1.CUs1.memory_port[34] system.cpu1.CUs1.memory_port[35] system.cpu1.CUs1.memory_port[36] system.cpu1.CUs1.memory_port[37] system.cpu1.CUs1.memory_port[38] system.cpu1.CUs1.memory_port[39] system.cpu1.CUs1.memory_port[40] system.cpu1.CUs1.memory_port[41] system.cpu1.CUs1.memory_port[42] system.cpu1.CUs1.memory_port[43] system.cpu1.CUs1.memory_port[44] system.cpu1.CUs1.memory_port[45] system.cpu1.CUs1.memory_port[46] system.cpu1.CUs1.memory_port[47] system.cpu1.CUs1.memory_port[48] system.cpu1.CUs1.memory_port[49] system.cpu1.CUs1.memory_port[50] system.cpu1.CUs1.memory_port[51] system.cpu1.CUs1.memory_port[52] system.cpu1.CUs1.memory_port[53] system.cpu1.CUs1.memory_port[54] system.cpu1.CUs1.memory_port[55] system.cpu1.CUs1.memory_port[56] system.cpu1.CUs1.memory_port[57] system.cpu1.CUs1.memory_port[58] system.cpu1.CUs1.memory_port[59] system.cpu1.CUs1.memory_port[60] system.cpu1.CUs1.memory_port[61] system.cpu1.CUs1.memory_port[62] system.cpu1.CUs1.memory_port[63]

[system.tcp_cntrl1.mandatoryQueue]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=false
randomization=false

[system.tcp_cntrl1.probeToTCP]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
slave=system.ruby.network.master[7]

[system.tcp_cntrl1.requestFromTCP]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
master=system.ruby.network.slave[8]

[system.tcp_cntrl1.responseFromTCP]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
master=system.ruby.network.slave[9]

[system.tcp_cntrl1.responseToTCP]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
slave=system.ruby.network.master[8]

[system.tcp_cntrl1.sequencer]
type=RubySequencer
clk_domain=system.clk_domain
coreid=99
dcache=system.tcp_cntrl1.L1cache
dcache_hit_latency=1
deadlock_threshold=500000
default_p_state=UNDEFINED
eventq_index=0
garnet_standalone=false
icache=system.tcp_cntrl1.L1cache
icache_hit_latency=1
is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_ruby_tester=false
version=5

[system.tcp_cntrl1.unblockFromCore]
type=MessageBuffer
buffer_size=0
eventq_index=0
ordered=true
randomization=false
master=system.ruby.network.slave[10]

[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000