config.ini revision 11570
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges=0:536870911 27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[2] 47 48[system.clk_domain] 49type=SrcClockDomain 50children=voltage_domain 51clock=1000 52domain_id=-1 53eventq_index=0 54init_perf_level=0 55voltage_domain=system.clk_domain.voltage_domain 56 57[system.clk_domain.voltage_domain] 58type=VoltageDomain 59eventq_index=0 60voltage=1.000000 61 62[system.cpu] 63type=TimingSimpleCPU 64children=apic_clk_domain dcache dtb icache interrupts isa itb tracer workload 65branchPred=Null 66checker=Null 67clk_domain=system.clk_domain 68cpu_id=-1 69default_p_state=UNDEFINED 70do_checkpoint_insts=true 71do_quiesce=true 72do_statistics_insts=true 73dtb=system.cpu.dtb 74eventq_index=0 75function_trace=false 76function_trace_start=0 77interrupts=system.cpu.interrupts 78isa=system.cpu.isa 79itb=system.cpu.itb 80max_insts_all_threads=0 81max_insts_any_thread=0 82max_loads_all_threads=0 83max_loads_any_thread=0 84numThreads=1 85p_state_clk_gate_bins=20 86p_state_clk_gate_max=1000000000000 87p_state_clk_gate_min=1000 88power_model=Null 89profile=0 90progress_interval=0 91simpoint_start_insts= 92socket_id=0 93switched_out=false 94system=system 95tracer=system.cpu.tracer 96workload=system.cpu.workload 97dcache_port=system.cpu.dcache.cpu_side 98icache_port=system.cpu.icache.cpu_side 99 100[system.cpu.apic_clk_domain] 101type=DerivedClockDomain 102clk_divider=16 103clk_domain=system.clk_domain 104eventq_index=0 105 106[system.cpu.dcache] 107type=Cache 108children=tags 109addr_ranges=0:18446744073709551615 110assoc=2 111clk_domain=system.clk_domain 112clusivity=mostly_incl 113default_p_state=UNDEFINED 114demand_mshr_reserve=1 115eventq_index=0 116hit_latency=2 117is_read_only=false 118max_miss_count=0 119mshrs=4 120p_state_clk_gate_bins=20 121p_state_clk_gate_max=1000000000000 122p_state_clk_gate_min=1000 123power_model=Null 124prefetch_on_access=false 125prefetcher=Null 126response_latency=2 127sequential_access=false 128size=65536 129system=system 130tags=system.cpu.dcache.tags 131tgts_per_mshr=20 132write_buffers=8 133writeback_clean=false 134cpu_side=system.cpu.dcache_port 135mem_side=system.l2bus.slave[1] 136 137[system.cpu.dcache.tags] 138type=LRU 139assoc=2 140block_size=64 141clk_domain=system.clk_domain 142default_p_state=UNDEFINED 143eventq_index=0 144hit_latency=2 145p_state_clk_gate_bins=20 146p_state_clk_gate_max=1000000000000 147p_state_clk_gate_min=1000 148power_model=Null 149sequential_access=false 150size=65536 151 152[system.cpu.dtb] 153type=X86TLB 154children=walker 155eventq_index=0 156size=64 157walker=system.cpu.dtb.walker 158 159[system.cpu.dtb.walker] 160type=X86PagetableWalker 161clk_domain=system.clk_domain 162default_p_state=UNDEFINED 163eventq_index=0 164num_squash_per_cycle=4 165p_state_clk_gate_bins=20 166p_state_clk_gate_max=1000000000000 167p_state_clk_gate_min=1000 168power_model=Null 169system=system 170 171[system.cpu.icache] 172type=Cache 173children=tags 174addr_ranges=0:18446744073709551615 175assoc=2 176clk_domain=system.clk_domain 177clusivity=mostly_incl 178default_p_state=UNDEFINED 179demand_mshr_reserve=1 180eventq_index=0 181hit_latency=2 182is_read_only=false 183max_miss_count=0 184mshrs=4 185p_state_clk_gate_bins=20 186p_state_clk_gate_max=1000000000000 187p_state_clk_gate_min=1000 188power_model=Null 189prefetch_on_access=false 190prefetcher=Null 191response_latency=2 192sequential_access=false 193size=16384 194system=system 195tags=system.cpu.icache.tags 196tgts_per_mshr=20 197write_buffers=8 198writeback_clean=false 199cpu_side=system.cpu.icache_port 200mem_side=system.l2bus.slave[0] 201 202[system.cpu.icache.tags] 203type=LRU 204assoc=2 205block_size=64 206clk_domain=system.clk_domain 207default_p_state=UNDEFINED 208eventq_index=0 209hit_latency=2 210p_state_clk_gate_bins=20 211p_state_clk_gate_max=1000000000000 212p_state_clk_gate_min=1000 213power_model=Null 214sequential_access=false 215size=16384 216 217[system.cpu.interrupts] 218type=X86LocalApic 219clk_domain=system.cpu.apic_clk_domain 220default_p_state=UNDEFINED 221eventq_index=0 222int_latency=1000 223p_state_clk_gate_bins=20 224p_state_clk_gate_max=1000000000000 225p_state_clk_gate_min=1000 226pio_addr=2305843009213693952 227pio_latency=100000 228power_model=Null 229system=system 230int_master=system.membus.slave[1] 231int_slave=system.membus.master[1] 232pio=system.membus.master[0] 233 234[system.cpu.isa] 235type=X86ISA 236eventq_index=0 237 238[system.cpu.itb] 239type=X86TLB 240children=walker 241eventq_index=0 242size=64 243walker=system.cpu.itb.walker 244 245[system.cpu.itb.walker] 246type=X86PagetableWalker 247clk_domain=system.clk_domain 248default_p_state=UNDEFINED 249eventq_index=0 250num_squash_per_cycle=4 251p_state_clk_gate_bins=20 252p_state_clk_gate_max=1000000000000 253p_state_clk_gate_min=1000 254power_model=Null 255system=system 256 257[system.cpu.tracer] 258type=ExeTracer 259eventq_index=0 260 261[system.cpu.workload] 262type=LiveProcess 263cmd=tests/test-progs/hello/bin/x86/linux/hello 264cwd= 265drivers= 266egid=100 267env= 268errout=cerr 269euid=100 270eventq_index=0 271executable= 272gid=100 273input=cin 274kvmInSE=false 275max_stack_size=67108864 276output=cout 277pid=100 278ppid=99 279simpoint=0 280system=system 281uid=100 282useArchPT=false 283 284[system.dvfs_handler] 285type=DVFSHandler 286domains= 287enable=false 288eventq_index=0 289sys_clk_domain=system.clk_domain 290transition_latency=100000000 291 292[system.l2bus] 293type=CoherentXBar 294children=snoop_filter 295clk_domain=system.clk_domain 296default_p_state=UNDEFINED 297eventq_index=0 298forward_latency=0 299frontend_latency=1 300p_state_clk_gate_bins=20 301p_state_clk_gate_max=1000000000000 302p_state_clk_gate_min=1000 303point_of_coherency=false 304power_model=Null 305response_latency=1 306snoop_filter=system.l2bus.snoop_filter 307snoop_response_latency=1 308system=system 309use_default_range=false 310width=32 311master=system.l2cache.cpu_side 312slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 313 314[system.l2bus.snoop_filter] 315type=SnoopFilter 316eventq_index=0 317lookup_latency=0 318max_capacity=8388608 319system=system 320 321[system.l2cache] 322type=Cache 323children=tags 324addr_ranges=0:18446744073709551615 325assoc=8 326clk_domain=system.clk_domain 327clusivity=mostly_incl 328default_p_state=UNDEFINED 329demand_mshr_reserve=1 330eventq_index=0 331hit_latency=20 332is_read_only=false 333max_miss_count=0 334mshrs=20 335p_state_clk_gate_bins=20 336p_state_clk_gate_max=1000000000000 337p_state_clk_gate_min=1000 338power_model=Null 339prefetch_on_access=false 340prefetcher=Null 341response_latency=20 342sequential_access=false 343size=262144 344system=system 345tags=system.l2cache.tags 346tgts_per_mshr=12 347write_buffers=8 348writeback_clean=false 349cpu_side=system.l2bus.master[0] 350mem_side=system.membus.slave[0] 351 352[system.l2cache.tags] 353type=LRU 354assoc=8 355block_size=64 356clk_domain=system.clk_domain 357default_p_state=UNDEFINED 358eventq_index=0 359hit_latency=20 360p_state_clk_gate_bins=20 361p_state_clk_gate_max=1000000000000 362p_state_clk_gate_min=1000 363power_model=Null 364sequential_access=false 365size=262144 366 367[system.mem_ctrl] 368type=DRAMCtrl 369IDD0=0.075000 370IDD02=0.000000 371IDD2N=0.050000 372IDD2N2=0.000000 373IDD2P0=0.000000 374IDD2P02=0.000000 375IDD2P1=0.000000 376IDD2P12=0.000000 377IDD3N=0.057000 378IDD3N2=0.000000 379IDD3P0=0.000000 380IDD3P02=0.000000 381IDD3P1=0.000000 382IDD3P12=0.000000 383IDD4R=0.187000 384IDD4R2=0.000000 385IDD4W=0.165000 386IDD4W2=0.000000 387IDD5=0.220000 388IDD52=0.000000 389IDD6=0.000000 390IDD62=0.000000 391VDD=1.500000 392VDD2=0.000000 393activation_limit=4 394addr_mapping=RoRaBaCoCh 395bank_groups_per_rank=0 396banks_per_rank=8 397burst_length=8 398channels=1 399clk_domain=system.clk_domain 400conf_table_reported=true 401default_p_state=UNDEFINED 402device_bus_width=8 403device_rowbuffer_size=1024 404device_size=536870912 405devices_per_rank=8 406dll=true 407eventq_index=0 408in_addr_map=true 409max_accesses_per_row=16 410mem_sched_policy=frfcfs 411min_writes_per_switch=16 412null=false 413p_state_clk_gate_bins=20 414p_state_clk_gate_max=1000000000000 415p_state_clk_gate_min=1000 416page_policy=open_adaptive 417power_model=Null 418range=0:536870911 419ranks_per_channel=2 420read_buffer_size=32 421static_backend_latency=10000 422static_frontend_latency=10000 423tBURST=5000 424tCCD_L=0 425tCK=1250 426tCL=13750 427tCS=2500 428tRAS=35000 429tRCD=13750 430tREFI=7800000 431tRFC=260000 432tRP=13750 433tRRD=6000 434tRRD_L=0 435tRTP=7500 436tRTW=2500 437tWR=15000 438tWTR=7500 439tXAW=30000 440tXP=0 441tXPDLL=0 442tXS=0 443tXSDLL=0 444write_buffer_size=64 445write_high_thresh_perc=85 446write_low_thresh_perc=50 447port=system.membus.master[2] 448 449[system.membus] 450type=CoherentXBar 451clk_domain=system.clk_domain 452default_p_state=UNDEFINED 453eventq_index=0 454forward_latency=4 455frontend_latency=3 456p_state_clk_gate_bins=20 457p_state_clk_gate_max=1000000000000 458p_state_clk_gate_min=1000 459point_of_coherency=true 460power_model=Null 461response_latency=2 462snoop_filter=Null 463snoop_response_latency=4 464system=system 465use_default_range=false 466width=16 467master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port 468slave=system.l2cache.mem_side system.cpu.interrupts.int_master system.system_port 469 470