stats.txt revision 11515:c48c7cc5a522
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000050 # Number of seconds simulated 4sim_ticks 49855000 # Number of ticks simulated 5final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 372227 # Simulator instruction rate (inst/s) 8host_op_rate 430264 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3715181399 # Simulator tick rate (ticks/s) 10host_mem_usage 693900 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 20system.mem_ctrl.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 21system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 22system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory 24system.mem_ctrl.bw_read::cpu.inst 288837629 # Total read bandwidth from this memory (bytes/s) 25system.mem_ctrl.bw_read::cpu.data 161749072 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::total 450586701 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_inst_read::cpu.inst 288837629 # Instruction read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::total 288837629 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_total::cpu.inst 288837629 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.data 161749072 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::total 450586701 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.readReqs 351 # Number of read requests accepted 33system.mem_ctrl.writeReqs 0 # Number of write requests accepted 34system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue 35system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.mem_ctrl.bytesReadDRAM 22464 # Total number of bytes read from DRAM 37system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 39system.mem_ctrl.bytesReadSys 22464 # Total read bytes from the system interface side 40system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.mem_ctrl.perBankRdBursts::0 78 # Per bank write bursts 45system.mem_ctrl.perBankRdBursts::1 42 # Per bank write bursts 46system.mem_ctrl.perBankRdBursts::2 13 # Per bank write bursts 47system.mem_ctrl.perBankRdBursts::3 33 # Per bank write bursts 48system.mem_ctrl.perBankRdBursts::4 14 # Per bank write bursts 49system.mem_ctrl.perBankRdBursts::5 31 # Per bank write bursts 50system.mem_ctrl.perBankRdBursts::6 34 # Per bank write bursts 51system.mem_ctrl.perBankRdBursts::7 9 # Per bank write bursts 52system.mem_ctrl.perBankRdBursts::8 4 # Per bank write bursts 53system.mem_ctrl.perBankRdBursts::9 6 # Per bank write bursts 54system.mem_ctrl.perBankRdBursts::10 25 # Per bank write bursts 55system.mem_ctrl.perBankRdBursts::11 43 # Per bank write bursts 56system.mem_ctrl.perBankRdBursts::12 8 # Per bank write bursts 57system.mem_ctrl.perBankRdBursts::13 5 # Per bank write bursts 58system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts 59system.mem_ctrl.perBankRdBursts::15 6 # Per bank write bursts 60system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts 61system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts 62system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts 63system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts 64system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts 65system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts 66system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts 67system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts 68system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts 69system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts 70system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 71system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 76system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 77system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry 78system.mem_ctrl.totGap 49757000 # Total gap between requests 79system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 80system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::6 351 # Read request sizes (log2) 86system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) 87system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) 88system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) 89system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) 90system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) 91system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) 92system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) 93system.mem_ctrl.rdQLenPdf::0 351 # What read queue length does an incoming req see 94system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see 95system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see 96system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.mem_ctrl.bytesPerActivate::samples 73 # Bytes accessed per row activation 190system.mem_ctrl.bytesPerActivate::mean 300.712329 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::gmean 214.051474 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::stdev 262.513782 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::0-127 14 19.18% 19.18% # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::128-255 25 34.25% 53.42% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::256-383 13 17.81% 71.23% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::384-511 6 8.22% 79.45% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::512-639 7 9.59% 89.04% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation 202system.mem_ctrl.totQLat 2474000 # Total ticks spent queuing 203system.mem_ctrl.totMemAccLat 9055250 # Total ticks spent from burst creation until serviced by the DRAM 204system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers 205system.mem_ctrl.avgQLat 7048.43 # Average queueing delay per DRAM burst 206system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst 207system.mem_ctrl.avgMemAccLat 25798.43 # Average memory access latency per DRAM burst 208system.mem_ctrl.avgRdBW 450.59 # Average DRAM read bandwidth in MiByte/s 209system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.mem_ctrl.avgRdBWSys 450.59 # Average system read bandwidth in MiByte/s 211system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.mem_ctrl.busUtil 3.52 # Data bus utilization in percentage 214system.mem_ctrl.busUtilRead 3.52 # Data bus utilization in percentage for reads 215system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 216system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 217system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing 218system.mem_ctrl.readRowHits 274 # Number of row buffer hits during reads 219system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes 220system.mem_ctrl.readRowHitRate 78.06 # Row buffer hit rate for reads 221system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes 222system.mem_ctrl.avgGap 141757.83 # Average gap between requests 223system.mem_ctrl.pageHitRate 78.06 # Row buffer hit rate, read and write combined 224system.mem_ctrl_0.actEnergy 347760 # Energy for activate commands per rank (pJ) 225system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) 226system.mem_ctrl_0.readEnergy 1825200 # Energy for read commands per rank (pJ) 227system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 228system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) 229system.mem_ctrl_0.actBackEnergy 31479390 # Energy for active background per rank (pJ) 230system.mem_ctrl_0.preBackEnergy 573750 # Energy for precharge background per rank (pJ) 231system.mem_ctrl_0.totalEnergy 37467210 # Total energy per rank (pJ) 232system.mem_ctrl_0.averagePower 797.535269 # Core power per rank (mW) 233system.mem_ctrl_0.memoryStateTime::IDLE 1052000 # Time in different power states 234system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states 235system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states 236system.mem_ctrl_0.memoryStateTime::ACT 44629000 # Time in different power states 237system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 238system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ) 239system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) 240system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ) 241system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 242system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) 243system.mem_ctrl_1.actBackEnergy 30267855 # Energy for active background per rank (pJ) 244system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ) 245system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ) 246system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW) 247system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states 248system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 249system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states 251system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states 252system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 253system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 254system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 255system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 256system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 257system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 258system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 259system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 260system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 261system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 262system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 263system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 264system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 265system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 266system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 267system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 268system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 269system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 270system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 271system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 272system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 273system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 274system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 275system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 276system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 277system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 278system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 279system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 280system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 281system.cpu.dtb.walker.walks 0 # Table walker walks requested 282system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 283system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 284system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 285system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 286system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 287system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 288system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 289system.cpu.dtb.inst_hits 0 # ITB inst hits 290system.cpu.dtb.inst_misses 0 # ITB inst misses 291system.cpu.dtb.read_hits 0 # DTB read hits 292system.cpu.dtb.read_misses 0 # DTB read misses 293system.cpu.dtb.write_hits 0 # DTB write hits 294system.cpu.dtb.write_misses 0 # DTB write misses 295system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 296system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 297system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 298system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 299system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 300system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 301system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 302system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 303system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 304system.cpu.dtb.read_accesses 0 # DTB read accesses 305system.cpu.dtb.write_accesses 0 # DTB write accesses 306system.cpu.dtb.inst_accesses 0 # ITB inst accesses 307system.cpu.dtb.hits 0 # DTB hits 308system.cpu.dtb.misses 0 # DTB misses 309system.cpu.dtb.accesses 0 # DTB accesses 310system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 311system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 312system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 313system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 314system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 317system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 318system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 319system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 320system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 321system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 322system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 323system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 324system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 325system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 326system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 327system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 328system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 329system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 330system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 331system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 334system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 335system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 336system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 337system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 338system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 339system.cpu.itb.walker.walks 0 # Table walker walks requested 340system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 341system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 342system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 343system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 344system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 345system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 346system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 347system.cpu.itb.inst_hits 0 # ITB inst hits 348system.cpu.itb.inst_misses 0 # ITB inst misses 349system.cpu.itb.read_hits 0 # DTB read hits 350system.cpu.itb.read_misses 0 # DTB read misses 351system.cpu.itb.write_hits 0 # DTB write hits 352system.cpu.itb.write_misses 0 # DTB write misses 353system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 354system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 355system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 356system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 357system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 358system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 359system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 360system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 361system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 362system.cpu.itb.read_accesses 0 # DTB read accesses 363system.cpu.itb.write_accesses 0 # DTB write accesses 364system.cpu.itb.inst_accesses 0 # ITB inst accesses 365system.cpu.itb.hits 0 # DTB hits 366system.cpu.itb.misses 0 # DTB misses 367system.cpu.itb.accesses 0 # DTB accesses 368system.cpu.workload.num_syscalls 13 # Number of system calls 369system.cpu.numCycles 49855 # number of cpu cycles simulated 370system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 371system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 372system.cpu.committedInsts 4988 # Number of instructions committed 373system.cpu.committedOps 5770 # Number of ops (including micro ops) committed 374system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses 375system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 376system.cpu.num_func_calls 215 # number of times a function call or return occured 377system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls 378system.cpu.num_int_insts 4977 # number of integer instructions 379system.cpu.num_fp_insts 16 # number of float instructions 380system.cpu.num_int_register_reads 8049 # number of times the integer registers were read 381system.cpu.num_int_register_writes 2992 # number of times the integer registers were written 382system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 383system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 384system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read 385system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written 386system.cpu.num_mem_refs 2035 # number of memory refs 387system.cpu.num_load_insts 1085 # Number of load instructions 388system.cpu.num_store_insts 950 # Number of store instructions 389system.cpu.num_idle_cycles 0.001000 # Number of idle cycles 390system.cpu.num_busy_cycles 49854.999000 # Number of busy cycles 391system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 392system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 393system.cpu.Branches 1107 # Number of branches fetched 394system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 395system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction 396system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction 397system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction 398system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction 399system.cpu.op_class::FloatCmp 0 0.00% 65.05% # Class of executed instruction 400system.cpu.op_class::FloatCvt 0 0.00% 65.05% # Class of executed instruction 401system.cpu.op_class::FloatMult 0 0.00% 65.05% # Class of executed instruction 402system.cpu.op_class::FloatDiv 0 0.00% 65.05% # Class of executed instruction 403system.cpu.op_class::FloatSqrt 0 0.00% 65.05% # Class of executed instruction 404system.cpu.op_class::SimdAdd 0 0.00% 65.05% # Class of executed instruction 405system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% # Class of executed instruction 406system.cpu.op_class::SimdAlu 0 0.00% 65.05% # Class of executed instruction 407system.cpu.op_class::SimdCmp 0 0.00% 65.05% # Class of executed instruction 408system.cpu.op_class::SimdCvt 0 0.00% 65.05% # Class of executed instruction 409system.cpu.op_class::SimdMisc 0 0.00% 65.05% # Class of executed instruction 410system.cpu.op_class::SimdMult 0 0.00% 65.05% # Class of executed instruction 411system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% # Class of executed instruction 412system.cpu.op_class::SimdShift 0 0.00% 65.05% # Class of executed instruction 413system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% # Class of executed instruction 414system.cpu.op_class::SimdSqrt 0 0.00% 65.05% # Class of executed instruction 415system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% # Class of executed instruction 416system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% # Class of executed instruction 417system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% # Class of executed instruction 418system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% # Class of executed instruction 419system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% # Class of executed instruction 420system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% # Class of executed instruction 421system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction 422system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction 423system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction 424system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction 425system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction 426system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 427system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 428system.cpu.op_class::total 5831 # Class of executed instruction 429system.cpu.dcache.tags.replacements 0 # number of replacements 430system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use 431system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. 432system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 433system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. 434system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 435system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor 436system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy 437system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy 438system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 439system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 440system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 441system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id 442system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses 443system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses 444system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits 445system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits 446system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits 447system.cpu.dcache.WriteReq_hits::total 882 # number of WriteReq hits 448system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 449system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 450system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 451system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 452system.cpu.dcache.demand_hits::cpu.data 1833 # number of demand (read+write) hits 453system.cpu.dcache.demand_hits::total 1833 # number of demand (read+write) hits 454system.cpu.dcache.overall_hits::cpu.data 1833 # number of overall hits 455system.cpu.dcache.overall_hits::total 1833 # number of overall hits 456system.cpu.dcache.ReadReq_misses::cpu.data 99 # number of ReadReq misses 457system.cpu.dcache.ReadReq_misses::total 99 # number of ReadReq misses 458system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 459system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 460system.cpu.dcache.demand_misses::cpu.data 142 # number of demand (read+write) misses 461system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses 462system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses 463system.cpu.dcache.overall_misses::total 142 # number of overall misses 464system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777000 # number of ReadReq miss cycles 465system.cpu.dcache.ReadReq_miss_latency::total 8777000 # number of ReadReq miss cycles 466system.cpu.dcache.WriteReq_miss_latency::cpu.data 4411000 # number of WriteReq miss cycles 467system.cpu.dcache.WriteReq_miss_latency::total 4411000 # number of WriteReq miss cycles 468system.cpu.dcache.demand_miss_latency::cpu.data 13188000 # number of demand (read+write) miss cycles 469system.cpu.dcache.demand_miss_latency::total 13188000 # number of demand (read+write) miss cycles 470system.cpu.dcache.overall_miss_latency::cpu.data 13188000 # number of overall miss cycles 471system.cpu.dcache.overall_miss_latency::total 13188000 # number of overall miss cycles 472system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) 473system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) 474system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 475system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 476system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 477system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 478system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 479system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 480system.cpu.dcache.demand_accesses::cpu.data 1975 # number of demand (read+write) accesses 481system.cpu.dcache.demand_accesses::total 1975 # number of demand (read+write) accesses 482system.cpu.dcache.overall_accesses::cpu.data 1975 # number of overall (read+write) accesses 483system.cpu.dcache.overall_accesses::total 1975 # number of overall (read+write) accesses 484system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094286 # miss rate for ReadReq accesses 485system.cpu.dcache.ReadReq_miss_rate::total 0.094286 # miss rate for ReadReq accesses 486system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046486 # miss rate for WriteReq accesses 487system.cpu.dcache.WriteReq_miss_rate::total 0.046486 # miss rate for WriteReq accesses 488system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 # miss rate for demand accesses 489system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses 490system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses 491system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses 492system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88656.565657 # average ReadReq miss latency 493system.cpu.dcache.ReadReq_avg_miss_latency::total 88656.565657 # average ReadReq miss latency 494system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102581.395349 # average WriteReq miss latency 495system.cpu.dcache.WriteReq_avg_miss_latency::total 102581.395349 # average WriteReq miss latency 496system.cpu.dcache.demand_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency 497system.cpu.dcache.demand_avg_miss_latency::total 92873.239437 # average overall miss latency 498system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency 499system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency 500system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 501system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 502system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 503system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 504system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 505system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 506system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses 507system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses 508system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 509system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 510system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 511system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 512system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 513system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses 514system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8579000 # number of ReadReq MSHR miss cycles 515system.cpu.dcache.ReadReq_mshr_miss_latency::total 8579000 # number of ReadReq MSHR miss cycles 516system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325000 # number of WriteReq MSHR miss cycles 517system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325000 # number of WriteReq MSHR miss cycles 518system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12904000 # number of demand (read+write) MSHR miss cycles 519system.cpu.dcache.demand_mshr_miss_latency::total 12904000 # number of demand (read+write) MSHR miss cycles 520system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12904000 # number of overall MSHR miss cycles 521system.cpu.dcache.overall_mshr_miss_latency::total 12904000 # number of overall MSHR miss cycles 522system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses 523system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses 524system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses 525system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046486 # mshr miss rate for WriteReq accesses 526system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for demand accesses 527system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses 528system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses 529system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses 530system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency 531system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency 532system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency 533system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency 534system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency 535system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency 536system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency 537system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency 538system.cpu.icache.tags.replacements 70 # number of replacements 539system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use 540system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. 541system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. 542system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. 543system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 544system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor 545system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy 546system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy 547system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id 548system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 549system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 550system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id 551system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses 552system.cpu.icache.tags.data_accesses 10305 # Number of data accesses 553system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits 554system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits 555system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits 556system.cpu.icache.demand_hits::total 4779 # number of demand (read+write) hits 557system.cpu.icache.overall_hits::cpu.inst 4779 # number of overall hits 558system.cpu.icache.overall_hits::total 4779 # number of overall hits 559system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses 560system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses 561system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses 562system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses 563system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses 564system.cpu.icache.overall_misses::total 249 # number of overall misses 565system.cpu.icache.ReadReq_miss_latency::cpu.inst 23411000 # number of ReadReq miss cycles 566system.cpu.icache.ReadReq_miss_latency::total 23411000 # number of ReadReq miss cycles 567system.cpu.icache.demand_miss_latency::cpu.inst 23411000 # number of demand (read+write) miss cycles 568system.cpu.icache.demand_miss_latency::total 23411000 # number of demand (read+write) miss cycles 569system.cpu.icache.overall_miss_latency::cpu.inst 23411000 # number of overall miss cycles 570system.cpu.icache.overall_miss_latency::total 23411000 # number of overall miss cycles 571system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) 572system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) 573system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses 574system.cpu.icache.demand_accesses::total 5028 # number of demand (read+write) accesses 575system.cpu.icache.overall_accesses::cpu.inst 5028 # number of overall (read+write) accesses 576system.cpu.icache.overall_accesses::total 5028 # number of overall (read+write) accesses 577system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.049523 # miss rate for ReadReq accesses 578system.cpu.icache.ReadReq_miss_rate::total 0.049523 # miss rate for ReadReq accesses 579system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 # miss rate for demand accesses 580system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses 581system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses 582system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses 583system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94020.080321 # average ReadReq miss latency 584system.cpu.icache.ReadReq_avg_miss_latency::total 94020.080321 # average ReadReq miss latency 585system.cpu.icache.demand_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency 586system.cpu.icache.demand_avg_miss_latency::total 94020.080321 # average overall miss latency 587system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency 588system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency 589system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 590system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 591system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 592system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 593system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 594system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 595system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses 596system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses 597system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses 598system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses 599system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses 600system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses 601system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles 602system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles 603system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22913000 # number of demand (read+write) MSHR miss cycles 604system.cpu.icache.demand_mshr_miss_latency::total 22913000 # number of demand (read+write) MSHR miss cycles 605system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22913000 # number of overall MSHR miss cycles 606system.cpu.icache.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles 607system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses 608system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses 609system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses 610system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses 611system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses 612system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses 613system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency 614system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency 615system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency 616system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency 617system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency 618system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency 619system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. 620system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. 621system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 622system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 623system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 624system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 625system.l2bus.trans_dist::ReadResp 348 # Transaction distribution 626system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution 627system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution 628system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution 629system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution 630system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 568 # Packet count per connected master and slave (bytes) 631system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 632system.l2bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) 633system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15936 # Cumulative packet size per connected master and slave (bytes) 634system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 635system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) 636system.l2bus.snoops 0 # Total snoops (count) 637system.l2bus.snoop_fanout::samples 391 # Request fanout histogram 638system.l2bus.snoop_fanout::mean 0.086957 # Request fanout histogram 639system.l2bus.snoop_fanout::stdev 0.282132 # Request fanout histogram 640system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 641system.l2bus.snoop_fanout::0 357 91.30% 91.30% # Request fanout histogram 642system.l2bus.snoop_fanout::1 34 8.70% 100.00% # Request fanout histogram 643system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 644system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 645system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 646system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 647system.l2bus.snoop_fanout::total 391 # Request fanout histogram 648system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) 649system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 650system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) 651system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) 652system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) 653system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) 654system.l2cache.tags.replacements 0 # number of replacements 655system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use 656system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. 657system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. 658system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks. 659system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 660system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor 661system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor 662system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy 663system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy 664system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy 665system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 666system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 667system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id 668system.l2cache.tags.occ_task_id_percent::1024 0.075195 # Percentage of cache occupancy per task id 669system.l2cache.tags.tag_accesses 3959 # Number of tag accesses 670system.l2cache.tags.data_accesses 3959 # Number of data accesses 671system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits 672system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits 673system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits 674system.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits 675system.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 676system.l2cache.demand_hits::total 40 # number of demand (read+write) hits 677system.l2cache.overall_hits::cpu.inst 24 # number of overall hits 678system.l2cache.overall_hits::cpu.data 16 # number of overall hits 679system.l2cache.overall_hits::total 40 # number of overall hits 680system.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 681system.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 682system.l2cache.ReadSharedReq_misses::cpu.inst 225 # number of ReadSharedReq misses 683system.l2cache.ReadSharedReq_misses::cpu.data 83 # number of ReadSharedReq misses 684system.l2cache.ReadSharedReq_misses::total 308 # number of ReadSharedReq misses 685system.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses 686system.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses 687system.l2cache.demand_misses::total 351 # number of demand (read+write) misses 688system.l2cache.overall_misses::cpu.inst 225 # number of overall misses 689system.l2cache.overall_misses::cpu.data 126 # number of overall misses 690system.l2cache.overall_misses::total 351 # number of overall misses 691system.l2cache.ReadExReq_miss_latency::cpu.data 4196000 # number of ReadExReq miss cycles 692system.l2cache.ReadExReq_miss_latency::total 4196000 # number of ReadExReq miss cycles 693system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21622000 # number of ReadSharedReq miss cycles 694system.l2cache.ReadSharedReq_miss_latency::cpu.data 7918000 # number of ReadSharedReq miss cycles 695system.l2cache.ReadSharedReq_miss_latency::total 29540000 # number of ReadSharedReq miss cycles 696system.l2cache.demand_miss_latency::cpu.inst 21622000 # number of demand (read+write) miss cycles 697system.l2cache.demand_miss_latency::cpu.data 12114000 # number of demand (read+write) miss cycles 698system.l2cache.demand_miss_latency::total 33736000 # number of demand (read+write) miss cycles 699system.l2cache.overall_miss_latency::cpu.inst 21622000 # number of overall miss cycles 700system.l2cache.overall_miss_latency::cpu.data 12114000 # number of overall miss cycles 701system.l2cache.overall_miss_latency::total 33736000 # number of overall miss cycles 702system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 703system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 704system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) 705system.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses) 706system.l2cache.ReadSharedReq_accesses::total 348 # number of ReadSharedReq accesses(hits+misses) 707system.l2cache.demand_accesses::cpu.inst 249 # number of demand (read+write) accesses 708system.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 709system.l2cache.demand_accesses::total 391 # number of demand (read+write) accesses 710system.l2cache.overall_accesses::cpu.inst 249 # number of overall (read+write) accesses 711system.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses 712system.l2cache.overall_accesses::total 391 # number of overall (read+write) accesses 713system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 714system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 715system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.903614 # miss rate for ReadSharedReq accesses 716system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.838384 # miss rate for ReadSharedReq accesses 717system.l2cache.ReadSharedReq_miss_rate::total 0.885057 # miss rate for ReadSharedReq accesses 718system.l2cache.demand_miss_rate::cpu.inst 0.903614 # miss rate for demand accesses 719system.l2cache.demand_miss_rate::cpu.data 0.887324 # miss rate for demand accesses 720system.l2cache.demand_miss_rate::total 0.897698 # miss rate for demand accesses 721system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses 722system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses 723system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses 724system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97581.395349 # average ReadExReq miss latency 725system.l2cache.ReadExReq_avg_miss_latency::total 97581.395349 # average ReadExReq miss latency 726system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96097.777778 # average ReadSharedReq miss latency 727system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95397.590361 # average ReadSharedReq miss latency 728system.l2cache.ReadSharedReq_avg_miss_latency::total 95909.090909 # average ReadSharedReq miss latency 729system.l2cache.demand_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency 730system.l2cache.demand_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency 731system.l2cache.demand_avg_miss_latency::total 96113.960114 # average overall miss latency 732system.l2cache.overall_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency 733system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency 734system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency 735system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 736system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 737system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 738system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 739system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 740system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 741system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 742system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 743system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses 744system.l2cache.ReadSharedReq_mshr_misses::cpu.data 83 # number of ReadSharedReq MSHR misses 745system.l2cache.ReadSharedReq_mshr_misses::total 308 # number of ReadSharedReq MSHR misses 746system.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 747system.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses 748system.l2cache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 749system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses 750system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses 751system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses 752system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3336000 # number of ReadExReq MSHR miss cycles 753system.l2cache.ReadExReq_mshr_miss_latency::total 3336000 # number of ReadExReq MSHR miss cycles 754system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17122000 # number of ReadSharedReq MSHR miss cycles 755system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6258000 # number of ReadSharedReq MSHR miss cycles 756system.l2cache.ReadSharedReq_mshr_miss_latency::total 23380000 # number of ReadSharedReq MSHR miss cycles 757system.l2cache.demand_mshr_miss_latency::cpu.inst 17122000 # number of demand (read+write) MSHR miss cycles 758system.l2cache.demand_mshr_miss_latency::cpu.data 9594000 # number of demand (read+write) MSHR miss cycles 759system.l2cache.demand_mshr_miss_latency::total 26716000 # number of demand (read+write) MSHR miss cycles 760system.l2cache.overall_mshr_miss_latency::cpu.inst 17122000 # number of overall MSHR miss cycles 761system.l2cache.overall_mshr_miss_latency::cpu.data 9594000 # number of overall MSHR miss cycles 762system.l2cache.overall_mshr_miss_latency::total 26716000 # number of overall MSHR miss cycles 763system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 764system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 765system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses 766system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.838384 # mshr miss rate for ReadSharedReq accesses 767system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.885057 # mshr miss rate for ReadSharedReq accesses 768system.l2cache.demand_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for demand accesses 769system.l2cache.demand_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for demand accesses 770system.l2cache.demand_mshr_miss_rate::total 0.897698 # mshr miss rate for demand accesses 771system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses 772system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses 773system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses 774system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77581.395349 # average ReadExReq mshr miss latency 775system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77581.395349 # average ReadExReq mshr miss latency 776system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76097.777778 # average ReadSharedReq mshr miss latency 777system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency 778system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency 779system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency 780system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency 781system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency 782system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency 783system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency 784system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency 785system.membus.trans_dist::ReadResp 308 # Transaction distribution 786system.membus.trans_dist::ReadExReq 43 # Transaction distribution 787system.membus.trans_dist::ReadExResp 43 # Transaction distribution 788system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution 789system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702 # Packet count per connected master and slave (bytes) 790system.membus.pkt_count::total 702 # Packet count per connected master and slave (bytes) 791system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464 # Cumulative packet size per connected master and slave (bytes) 792system.membus.pkt_size::total 22464 # Cumulative packet size per connected master and slave (bytes) 793system.membus.snoops 0 # Total snoops (count) 794system.membus.snoop_fanout::samples 351 # Request fanout histogram 795system.membus.snoop_fanout::mean 0 # Request fanout histogram 796system.membus.snoop_fanout::stdev 0 # Request fanout histogram 797system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 798system.membus.snoop_fanout::0 351 100.00% 100.00% # Request fanout histogram 799system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 800system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 801system.membus.snoop_fanout::min_value 0 # Request fanout histogram 802system.membus.snoop_fanout::max_value 0 # Request fanout histogram 803system.membus.snoop_fanout::total 351 # Request fanout histogram 804system.membus.reqLayer0.occupancy 351000 # Layer occupancy (ticks) 805system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) 806system.membus.respLayer0.occupancy 1865750 # Layer occupancy (ticks) 807system.membus.respLayer0.utilization 3.7 # Layer utilization (%) 808 809---------- End Simulation Statistics ---------- 810