config.ini revision 9885
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= 23symbolfile= 24work_begin_ckpt_count=0 25work_begin_cpu_id_exit=-1 26work_begin_exit_count=0 27work_cpus_ckpt_count=0 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 36voltage_domain=system.voltage_domain 37 38[system.cpu] 39type=TimingSimpleCPU 40children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload 41checker=Null 42clk_domain=system.cpu_clk_domain 43cpu_id=0 44do_checkpoint_insts=true 45do_quiesce=true 46do_statistics_insts=true 47dtb=system.cpu.dtb 48function_trace=false 49function_trace_start=0 50interrupts=system.cpu.interrupts 51isa=system.cpu.isa 52itb=system.cpu.itb 53max_insts_all_threads=0 54max_insts_any_thread=0 55max_loads_all_threads=0 56max_loads_any_thread=0 57numThreads=1 58profile=0 59progress_interval=0 60simpoint_start_insts= 61switched_out=false 62system=system 63tracer=system.cpu.tracer 64workload=system.cpu.workload 65dcache_port=system.cpu.dcache.cpu_side 66icache_port=system.cpu.icache.cpu_side 67 68[system.cpu.dcache] 69type=BaseCache 70children=tags 71addr_ranges=0:18446744073709551615 72assoc=2 73clk_domain=system.cpu_clk_domain 74forward_snoops=true 75hit_latency=2 76is_top_level=true 77max_miss_count=0 78mshrs=4 79prefetch_on_access=false 80prefetcher=Null 81response_latency=2 82size=262144 83system=system 84tags=system.cpu.dcache.tags 85tgts_per_mshr=20 86two_queue=false 87write_buffers=8 88cpu_side=system.cpu.dcache_port 89mem_side=system.cpu.toL2Bus.slave[1] 90 91[system.cpu.dcache.tags] 92type=LRU 93assoc=2 94block_size=64 95clk_domain=system.cpu_clk_domain 96hit_latency=2 97size=262144 98 99[system.cpu.dtb] 100type=SparcTLB 101size=64 102 103[system.cpu.icache] 104type=BaseCache 105children=tags 106addr_ranges=0:18446744073709551615 107assoc=2 108clk_domain=system.cpu_clk_domain 109forward_snoops=true 110hit_latency=2 111is_top_level=true 112max_miss_count=0 113mshrs=4 114prefetch_on_access=false 115prefetcher=Null 116response_latency=2 117size=131072 118system=system 119tags=system.cpu.icache.tags 120tgts_per_mshr=20 121two_queue=false 122write_buffers=8 123cpu_side=system.cpu.icache_port 124mem_side=system.cpu.toL2Bus.slave[0] 125 126[system.cpu.icache.tags] 127type=LRU 128assoc=2 129block_size=64 130clk_domain=system.cpu_clk_domain 131hit_latency=2 132size=131072 133 134[system.cpu.interrupts] 135type=SparcInterrupts 136 137[system.cpu.isa] 138type=SparcISA 139 140[system.cpu.itb] 141type=SparcTLB 142size=64 143 144[system.cpu.l2cache] 145type=BaseCache 146children=tags 147addr_ranges=0:18446744073709551615 148assoc=8 149clk_domain=system.cpu_clk_domain 150forward_snoops=true 151hit_latency=20 152is_top_level=false 153max_miss_count=0 154mshrs=20 155prefetch_on_access=false 156prefetcher=Null 157response_latency=20 158size=2097152 159system=system 160tags=system.cpu.l2cache.tags 161tgts_per_mshr=12 162two_queue=false 163write_buffers=8 164cpu_side=system.cpu.toL2Bus.master[0] 165mem_side=system.membus.slave[1] 166 167[system.cpu.l2cache.tags] 168type=LRU 169assoc=8 170block_size=64 171clk_domain=system.cpu_clk_domain 172hit_latency=20 173size=2097152 174 175[system.cpu.toL2Bus] 176type=CoherentBus 177clk_domain=system.cpu_clk_domain 178header_cycles=1 179system=system 180use_default_range=false 181width=32 182master=system.cpu.l2cache.cpu_side 183slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 184 185[system.cpu.tracer] 186type=ExeTracer 187 188[system.cpu.workload] 189type=LiveProcess 190cmd=insttest 191cwd= 192egid=100 193env= 194errout=cerr 195euid=100 196executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest 197gid=100 198input=cin 199max_stack_size=67108864 200output=cout 201pid=100 202ppid=99 203simpoint=0 204system=system 205uid=100 206 207[system.cpu_clk_domain] 208type=SrcClockDomain 209clock=500 210voltage_domain=system.voltage_domain 211 212[system.membus] 213type=CoherentBus 214clk_domain=system.clk_domain 215header_cycles=1 216system=system 217use_default_range=false 218width=8 219master=system.physmem.port 220slave=system.system_port system.cpu.l2cache.mem_side 221 222[system.physmem] 223type=SimpleMemory 224bandwidth=73.000000 225clk_domain=system.clk_domain 226conf_table_reported=true 227in_addr_map=true 228latency=30000 229latency_var=0 230null=false 231range=0:134217727 232port=system.membus.master[0] 233 234[system.voltage_domain] 235type=VoltageDomain 236voltage=1.000000 237 238