stats.txt revision 8835:7c68f84d7c4e
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000018 # Number of seconds simulated 4sim_ticks 18114000 # Number of ticks simulated 5final_tick 18114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 120891 # Simulator instruction rate (inst/s) 8host_op_rate 120873 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 151511225 # Simulator tick rate (ticks/s) 10host_mem_usage 211580 # Number of bytes of host memory used 11host_seconds 0.12 # Real time elapsed on the host 12sim_insts 14449 # Number of instructions simulated 13sim_ops 14449 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 30464 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 21120 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 476 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 1681793088 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 1165948990 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 1681793088 # Total bandwidth to/from this memory (bytes/s) 23system.cpu.workload.num_syscalls 18 # Number of system calls 24system.cpu.numCycles 36229 # number of cpu cycles simulated 25system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 26system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 27system.cpu.BPredUnit.lookups 5641 # Number of BP lookups 28system.cpu.BPredUnit.condPredicted 3757 # Number of conditional branches predicted 29system.cpu.BPredUnit.condIncorrect 847 # Number of conditional branches incorrect 30system.cpu.BPredUnit.BTBLookups 5015 # Number of BTB lookups 31system.cpu.BPredUnit.BTBHits 2638 # Number of BTB hits 32system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 33system.cpu.BPredUnit.usedRAS 357 # Number of times the RAS was used to get a target. 34system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. 35system.cpu.fetch.icacheStallCycles 10704 # Number of cycles fetch is stalled on an Icache miss 36system.cpu.fetch.Insts 25822 # Number of instructions fetch has processed 37system.cpu.fetch.Branches 5641 # Number of branches that fetch encountered 38system.cpu.fetch.predictedBranches 2995 # Number of branches that fetch has predicted taken 39system.cpu.fetch.Cycles 8176 # Number of cycles fetch has run and was not squashing or blocked 40system.cpu.fetch.SquashCycles 2307 # Number of cycles fetch has spent squashing 41system.cpu.fetch.BlockedCycles 6717 # Number of cycles fetch has spent blocked 42system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 43system.cpu.fetch.PendingTrapStallCycles 641 # Number of stall cycles due to pending traps 44system.cpu.fetch.CacheLines 4608 # Number of cache lines fetched 45system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed 46system.cpu.fetch.rateDist::samples 27606 # Number of instructions fetched each cycle (Total) 47system.cpu.fetch.rateDist::mean 0.935376 # Number of instructions fetched each cycle (Total) 48system.cpu.fetch.rateDist::stdev 2.035144 # Number of instructions fetched each cycle (Total) 49system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 50system.cpu.fetch.rateDist::0 19430 70.38% 70.38% # Number of instructions fetched each cycle (Total) 51system.cpu.fetch.rateDist::1 4056 14.69% 85.08% # Number of instructions fetched each cycle (Total) 52system.cpu.fetch.rateDist::2 538 1.95% 87.02% # Number of instructions fetched each cycle (Total) 53system.cpu.fetch.rateDist::3 472 1.71% 88.73% # Number of instructions fetched each cycle (Total) 54system.cpu.fetch.rateDist::4 725 2.63% 91.36% # Number of instructions fetched each cycle (Total) 55system.cpu.fetch.rateDist::5 639 2.31% 93.68% # Number of instructions fetched each cycle (Total) 56system.cpu.fetch.rateDist::6 274 0.99% 94.67% # Number of instructions fetched each cycle (Total) 57system.cpu.fetch.rateDist::7 241 0.87% 95.54% # Number of instructions fetched each cycle (Total) 58system.cpu.fetch.rateDist::8 1231 4.46% 100.00% # Number of instructions fetched each cycle (Total) 59system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 60system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 62system.cpu.fetch.rateDist::total 27606 # Number of instructions fetched each cycle (Total) 63system.cpu.fetch.branchRate 0.155704 # Number of branch fetches per cycle 64system.cpu.fetch.rate 0.712744 # Number of inst fetches per cycle 65system.cpu.decode.IdleCycles 11125 # Number of cycles decode is idle 66system.cpu.decode.BlockedCycles 7403 # Number of cycles decode is blocked 67system.cpu.decode.RunCycles 7524 # Number of cycles decode is running 68system.cpu.decode.UnblockCycles 190 # Number of cycles decode is unblocking 69system.cpu.decode.SquashCycles 1364 # Number of cycles decode is squashing 70system.cpu.decode.DecodedInsts 24270 # Number of instructions handled by decode 71system.cpu.rename.SquashCycles 1364 # Number of cycles rename is squashing 72system.cpu.rename.IdleCycles 11622 # Number of cycles rename is idle 73system.cpu.rename.BlockCycles 225 # Number of cycles rename is blocking 74system.cpu.rename.serializeStallCycles 6687 # count of cycles rename stalled for serializing inst 75system.cpu.rename.RunCycles 7253 # Number of cycles rename is running 76system.cpu.rename.UnblockCycles 455 # Number of cycles rename is unblocking 77system.cpu.rename.RenamedInsts 22509 # Number of instructions processed by rename 78system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full 79system.cpu.rename.LSQFullEvents 135 # Number of times rename has blocked due to LSQ full 80system.cpu.rename.RenamedOperands 20189 # Number of destination operands rename has renamed 81system.cpu.rename.RenameLookups 41765 # Number of register rename lookups that rename has made 82system.cpu.rename.int_rename_lookups 41765 # Number of integer rename lookups 83system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed 84system.cpu.rename.UndoneMaps 6357 # Number of HB maps that are undone due to squashing 85system.cpu.rename.serializingInsts 639 # count of serializing insts renamed 86system.cpu.rename.tempSerializingInsts 633 # count of temporary serializing insts renamed 87system.cpu.rename.skidInsts 2443 # count of insts added to the skid buffer 88system.cpu.memDep0.insertedLoads 3114 # Number of loads inserted to the mem dependence unit. 89system.cpu.memDep0.insertedStores 1976 # Number of stores inserted to the mem dependence unit. 90system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. 91system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 92system.cpu.iq.iqInstsAdded 19328 # Number of instructions added to the IQ (excludes non-spec) 93system.cpu.iq.iqNonSpecInstsAdded 615 # Number of non-speculative instructions added to the IQ 94system.cpu.iq.iqInstsIssued 18581 # Number of instructions issued 95system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued 96system.cpu.iq.iqSquashedInstsExamined 4856 # Number of squashed instructions iterated over during squash; mainly for profiling 97system.cpu.iq.iqSquashedOperandsExamined 3975 # Number of squashed operands that are examined and possibly removed from graph 98system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed 99system.cpu.iq.issued_per_cycle::samples 27606 # Number of insts issued each cycle 100system.cpu.iq.issued_per_cycle::mean 0.673078 # Number of insts issued each cycle 101system.cpu.iq.issued_per_cycle::stdev 1.254278 # Number of insts issued each cycle 102system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 103system.cpu.iq.issued_per_cycle::0 19117 69.25% 69.25% # Number of insts issued each cycle 104system.cpu.iq.issued_per_cycle::1 3446 12.48% 81.73% # Number of insts issued each cycle 105system.cpu.iq.issued_per_cycle::2 2219 8.04% 89.77% # Number of insts issued each cycle 106system.cpu.iq.issued_per_cycle::3 1536 5.56% 95.33% # Number of insts issued each cycle 107system.cpu.iq.issued_per_cycle::4 657 2.38% 97.71% # Number of insts issued each cycle 108system.cpu.iq.issued_per_cycle::5 384 1.39% 99.11% # Number of insts issued each cycle 109system.cpu.iq.issued_per_cycle::6 197 0.71% 99.82% # Number of insts issued each cycle 110system.cpu.iq.issued_per_cycle::7 41 0.15% 99.97% # Number of insts issued each cycle 111system.cpu.iq.issued_per_cycle::8 9 0.03% 100.00% # Number of insts issued each cycle 112system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 113system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 114system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 115system.cpu.iq.issued_per_cycle::total 27606 # Number of insts issued each cycle 116system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 117system.cpu.iq.fu_full::IntAlu 35 25.18% 25.18% # attempts to use FU when none available 118system.cpu.iq.fu_full::IntMult 0 0.00% 25.18% # attempts to use FU when none available 119system.cpu.iq.fu_full::IntDiv 0 0.00% 25.18% # attempts to use FU when none available 120system.cpu.iq.fu_full::FloatAdd 0 0.00% 25.18% # attempts to use FU when none available 121system.cpu.iq.fu_full::FloatCmp 0 0.00% 25.18% # attempts to use FU when none available 122system.cpu.iq.fu_full::FloatCvt 0 0.00% 25.18% # attempts to use FU when none available 123system.cpu.iq.fu_full::FloatMult 0 0.00% 25.18% # attempts to use FU when none available 124system.cpu.iq.fu_full::FloatDiv 0 0.00% 25.18% # attempts to use FU when none available 125system.cpu.iq.fu_full::FloatSqrt 0 0.00% 25.18% # attempts to use FU when none available 126system.cpu.iq.fu_full::SimdAdd 0 0.00% 25.18% # attempts to use FU when none available 127system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 25.18% # attempts to use FU when none available 128system.cpu.iq.fu_full::SimdAlu 0 0.00% 25.18% # attempts to use FU when none available 129system.cpu.iq.fu_full::SimdCmp 0 0.00% 25.18% # attempts to use FU when none available 130system.cpu.iq.fu_full::SimdCvt 0 0.00% 25.18% # attempts to use FU when none available 131system.cpu.iq.fu_full::SimdMisc 0 0.00% 25.18% # attempts to use FU when none available 132system.cpu.iq.fu_full::SimdMult 0 0.00% 25.18% # attempts to use FU when none available 133system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 25.18% # attempts to use FU when none available 134system.cpu.iq.fu_full::SimdShift 0 0.00% 25.18% # attempts to use FU when none available 135system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 25.18% # attempts to use FU when none available 136system.cpu.iq.fu_full::SimdSqrt 0 0.00% 25.18% # attempts to use FU when none available 137system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 25.18% # attempts to use FU when none available 138system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 25.18% # attempts to use FU when none available 139system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 25.18% # attempts to use FU when none available 140system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 25.18% # attempts to use FU when none available 141system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 25.18% # attempts to use FU when none available 142system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 25.18% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 25.18% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.18% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 25.18% # attempts to use FU when none available 146system.cpu.iq.fu_full::MemRead 26 18.71% 43.88% # attempts to use FU when none available 147system.cpu.iq.fu_full::MemWrite 78 56.12% 100.00% # attempts to use FU when none available 148system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 149system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 150system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 151system.cpu.iq.FU_type_0::IntAlu 13779 74.16% 74.16% # Type of FU issued 152system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.16% # Type of FU issued 153system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.16% # Type of FU issued 154system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.16% # Type of FU issued 155system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.16% # Type of FU issued 156system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.16% # Type of FU issued 157system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.16% # Type of FU issued 158system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.16% # Type of FU issued 159system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.16% # Type of FU issued 160system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.16% # Type of FU issued 161system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.16% # Type of FU issued 162system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.16% # Type of FU issued 163system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.16% # Type of FU issued 164system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.16% # Type of FU issued 165system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.16% # Type of FU issued 166system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.16% # Type of FU issued 167system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.16% # Type of FU issued 168system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.16% # Type of FU issued 169system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.16% # Type of FU issued 170system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.16% # Type of FU issued 171system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.16% # Type of FU issued 172system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.16% # Type of FU issued 173system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.16% # Type of FU issued 174system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.16% # Type of FU issued 175system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.16% # Type of FU issued 176system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.16% # Type of FU issued 177system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.16% # Type of FU issued 178system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.16% # Type of FU issued 179system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.16% # Type of FU issued 180system.cpu.iq.FU_type_0::MemRead 2952 15.89% 90.04% # Type of FU issued 181system.cpu.iq.FU_type_0::MemWrite 1850 9.96% 100.00% # Type of FU issued 182system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 183system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 184system.cpu.iq.FU_type_0::total 18581 # Type of FU issued 185system.cpu.iq.rate 0.512876 # Inst issue rate 186system.cpu.iq.fu_busy_cnt 139 # FU busy when requested 187system.cpu.iq.fu_busy_rate 0.007481 # FU busy rate (busy events/executed inst) 188system.cpu.iq.int_inst_queue_reads 64988 # Number of integer instruction queue reads 189system.cpu.iq.int_inst_queue_writes 24825 # Number of integer instruction queue writes 190system.cpu.iq.int_inst_queue_wakeup_accesses 17429 # Number of integer instruction queue wakeup accesses 191system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 192system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 193system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 194system.cpu.iq.int_alu_accesses 18720 # Number of integer alu accesses 195system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 196system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores 197system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 198system.cpu.iew.lsq.thread0.squashedLoads 888 # Number of loads squashed 199system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 200system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations 201system.cpu.iew.lsq.thread0.squashedStores 528 # Number of stores squashed 202system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 203system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 204system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 205system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 206system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 207system.cpu.iew.iewSquashCycles 1364 # Number of cycles IEW is squashing 208system.cpu.iew.iewBlockCycles 96 # Number of cycles IEW is blocking 209system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking 210system.cpu.iew.iewDispatchedInsts 21045 # Number of instructions dispatched to IQ 211system.cpu.iew.iewDispSquashedInsts 247 # Number of squashed instructions skipped by dispatch 212system.cpu.iew.iewDispLoadInsts 3114 # Number of dispatched load instructions 213system.cpu.iew.iewDispStoreInsts 1976 # Number of dispatched store instructions 214system.cpu.iew.iewDispNonSpecInsts 615 # Number of dispatched non-speculative instructions 215system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 216system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 217system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations 218system.cpu.iew.predictedTakenIncorrect 371 # Number of branches that were predicted taken incorrectly 219system.cpu.iew.predictedNotTakenIncorrect 573 # Number of branches that were predicted not taken incorrectly 220system.cpu.iew.branchMispredicts 944 # Number of branch mispredicts detected at execute 221system.cpu.iew.iewExecutedInsts 17855 # Number of executed instructions 222system.cpu.iew.iewExecLoadInsts 2862 # Number of load instructions executed 223system.cpu.iew.iewExecSquashedInsts 726 # Number of squashed instructions skipped in execute 224system.cpu.iew.exec_swp 0 # number of swp insts executed 225system.cpu.iew.exec_nop 1102 # number of nop insts executed 226system.cpu.iew.exec_refs 4620 # number of memory reference insts executed 227system.cpu.iew.exec_branches 3963 # Number of branches executed 228system.cpu.iew.exec_stores 1758 # Number of stores executed 229system.cpu.iew.exec_rate 0.492837 # Inst execution rate 230system.cpu.iew.wb_sent 17592 # cumulative count of insts sent to commit 231system.cpu.iew.wb_count 17429 # cumulative count of insts written-back 232system.cpu.iew.wb_producers 8123 # num instructions producing a value 233system.cpu.iew.wb_consumers 9726 # num instructions consuming a value 234system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 235system.cpu.iew.wb_rate 0.481079 # insts written-back per cycle 236system.cpu.iew.wb_fanout 0.835184 # average fanout of values written-back 237system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 238system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions 239system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions 240system.cpu.commit.commitSquashedInsts 5794 # The number of squashed insts skipped by commit 241system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards 242system.cpu.commit.branchMispredicts 847 # The number of times a branch was mispredicted 243system.cpu.commit.committed_per_cycle::samples 26259 # Number of insts commited each cycle 244system.cpu.commit.committed_per_cycle::mean 0.577897 # Number of insts commited each cycle 245system.cpu.commit.committed_per_cycle::stdev 1.280480 # Number of insts commited each cycle 246system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 247system.cpu.commit.committed_per_cycle::0 19069 72.62% 72.62% # Number of insts commited each cycle 248system.cpu.commit.committed_per_cycle::1 3994 15.21% 87.83% # Number of insts commited each cycle 249system.cpu.commit.committed_per_cycle::2 1208 4.60% 92.43% # Number of insts commited each cycle 250system.cpu.commit.committed_per_cycle::3 790 3.01% 95.44% # Number of insts commited each cycle 251system.cpu.commit.committed_per_cycle::4 369 1.41% 96.84% # Number of insts commited each cycle 252system.cpu.commit.committed_per_cycle::5 322 1.23% 98.07% # Number of insts commited each cycle 253system.cpu.commit.committed_per_cycle::6 345 1.31% 99.38% # Number of insts commited each cycle 254system.cpu.commit.committed_per_cycle::7 57 0.22% 99.60% # Number of insts commited each cycle 255system.cpu.commit.committed_per_cycle::8 105 0.40% 100.00% # Number of insts commited each cycle 256system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 257system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 258system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 259system.cpu.commit.committed_per_cycle::total 26259 # Number of insts commited each cycle 260system.cpu.commit.committedInsts 15175 # Number of instructions committed 261system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed 262system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 263system.cpu.commit.refs 3674 # Number of memory references committed 264system.cpu.commit.loads 2226 # Number of loads committed 265system.cpu.commit.membars 0 # Number of memory barriers committed 266system.cpu.commit.branches 3359 # Number of branches committed 267system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 268system.cpu.commit.int_insts 12186 # Number of committed integer instructions. 269system.cpu.commit.function_calls 187 # Number of function calls committed. 270system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached 271system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 272system.cpu.rob.rob_reads 46300 # The number of ROB reads 273system.cpu.rob.rob_writes 43308 # The number of ROB writes 274system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself 275system.cpu.idleCycles 8623 # Total number of cycles that the CPU has spent unscheduled due to idling 276system.cpu.committedInsts 14449 # Number of Instructions Simulated 277system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated 278system.cpu.committedInsts_total 14449 # Number of Instructions Simulated 279system.cpu.cpi 2.507371 # CPI: Cycles Per Instruction 280system.cpu.cpi_total 2.507371 # CPI: Total CPI of All Threads 281system.cpu.ipc 0.398824 # IPC: Instructions Per Cycle 282system.cpu.ipc_total 0.398824 # IPC: Total IPC of All Threads 283system.cpu.int_regfile_reads 28557 # number of integer regfile reads 284system.cpu.int_regfile_writes 15938 # number of integer regfile writes 285system.cpu.misc_regfile_reads 6251 # number of misc regfile reads 286system.cpu.misc_regfile_writes 569 # number of misc regfile writes 287system.cpu.icache.replacements 0 # number of replacements 288system.cpu.icache.tagsinuse 193.216525 # Cycle average of tags in use 289system.cpu.icache.total_refs 4151 # Total number of references to valid blocks. 290system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. 291system.cpu.icache.avg_refs 12.503012 # Average number of references to valid blocks. 292system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 293system.cpu.icache.occ_blocks::cpu.inst 193.216525 # Average occupied blocks per requestor 294system.cpu.icache.occ_percent::cpu.inst 0.094344 # Average percentage of cache occupancy 295system.cpu.icache.occ_percent::total 0.094344 # Average percentage of cache occupancy 296system.cpu.icache.ReadReq_hits::cpu.inst 4151 # number of ReadReq hits 297system.cpu.icache.ReadReq_hits::total 4151 # number of ReadReq hits 298system.cpu.icache.demand_hits::cpu.inst 4151 # number of demand (read+write) hits 299system.cpu.icache.demand_hits::total 4151 # number of demand (read+write) hits 300system.cpu.icache.overall_hits::cpu.inst 4151 # number of overall hits 301system.cpu.icache.overall_hits::total 4151 # number of overall hits 302system.cpu.icache.ReadReq_misses::cpu.inst 457 # number of ReadReq misses 303system.cpu.icache.ReadReq_misses::total 457 # number of ReadReq misses 304system.cpu.icache.demand_misses::cpu.inst 457 # number of demand (read+write) misses 305system.cpu.icache.demand_misses::total 457 # number of demand (read+write) misses 306system.cpu.icache.overall_misses::cpu.inst 457 # number of overall misses 307system.cpu.icache.overall_misses::total 457 # number of overall misses 308system.cpu.icache.ReadReq_miss_latency::cpu.inst 15956000 # number of ReadReq miss cycles 309system.cpu.icache.ReadReq_miss_latency::total 15956000 # number of ReadReq miss cycles 310system.cpu.icache.demand_miss_latency::cpu.inst 15956000 # number of demand (read+write) miss cycles 311system.cpu.icache.demand_miss_latency::total 15956000 # number of demand (read+write) miss cycles 312system.cpu.icache.overall_miss_latency::cpu.inst 15956000 # number of overall miss cycles 313system.cpu.icache.overall_miss_latency::total 15956000 # number of overall miss cycles 314system.cpu.icache.ReadReq_accesses::cpu.inst 4608 # number of ReadReq accesses(hits+misses) 315system.cpu.icache.ReadReq_accesses::total 4608 # number of ReadReq accesses(hits+misses) 316system.cpu.icache.demand_accesses::cpu.inst 4608 # number of demand (read+write) accesses 317system.cpu.icache.demand_accesses::total 4608 # number of demand (read+write) accesses 318system.cpu.icache.overall_accesses::cpu.inst 4608 # number of overall (read+write) accesses 319system.cpu.icache.overall_accesses::total 4608 # number of overall (read+write) accesses 320system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.099175 # miss rate for ReadReq accesses 321system.cpu.icache.demand_miss_rate::cpu.inst 0.099175 # miss rate for demand accesses 322system.cpu.icache.overall_miss_rate::cpu.inst 0.099175 # miss rate for overall accesses 323system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34914.660832 # average ReadReq miss latency 324system.cpu.icache.demand_avg_miss_latency::cpu.inst 34914.660832 # average overall miss latency 325system.cpu.icache.overall_avg_miss_latency::cpu.inst 34914.660832 # average overall miss latency 326system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 327system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 328system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 329system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 330system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 331system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 332system.cpu.icache.fast_writes 0 # number of fast writes performed 333system.cpu.icache.cache_copies 0 # number of cache copies performed 334system.cpu.icache.ReadReq_mshr_hits::cpu.inst 125 # number of ReadReq MSHR hits 335system.cpu.icache.ReadReq_mshr_hits::total 125 # number of ReadReq MSHR hits 336system.cpu.icache.demand_mshr_hits::cpu.inst 125 # number of demand (read+write) MSHR hits 337system.cpu.icache.demand_mshr_hits::total 125 # number of demand (read+write) MSHR hits 338system.cpu.icache.overall_mshr_hits::cpu.inst 125 # number of overall MSHR hits 339system.cpu.icache.overall_mshr_hits::total 125 # number of overall MSHR hits 340system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses 341system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses 342system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses 343system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses 344system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses 345system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses 346system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11653500 # number of ReadReq MSHR miss cycles 347system.cpu.icache.ReadReq_mshr_miss_latency::total 11653500 # number of ReadReq MSHR miss cycles 348system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11653500 # number of demand (read+write) MSHR miss cycles 349system.cpu.icache.demand_mshr_miss_latency::total 11653500 # number of demand (read+write) MSHR miss cycles 350system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11653500 # number of overall MSHR miss cycles 351system.cpu.icache.overall_mshr_miss_latency::total 11653500 # number of overall MSHR miss cycles 352system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for ReadReq accesses 353system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for demand accesses 354system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for overall accesses 355system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35100.903614 # average ReadReq mshr miss latency 356system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35100.903614 # average overall mshr miss latency 357system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35100.903614 # average overall mshr miss latency 358system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 359system.cpu.dcache.replacements 0 # number of replacements 360system.cpu.dcache.tagsinuse 102.149831 # Cycle average of tags in use 361system.cpu.dcache.total_refs 3712 # Total number of references to valid blocks. 362system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. 363system.cpu.dcache.avg_refs 25.424658 # Average number of references to valid blocks. 364system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 365system.cpu.dcache.occ_blocks::cpu.data 102.149831 # Average occupied blocks per requestor 366system.cpu.dcache.occ_percent::cpu.data 0.024939 # Average percentage of cache occupancy 367system.cpu.dcache.occ_percent::total 0.024939 # Average percentage of cache occupancy 368system.cpu.dcache.ReadReq_hits::cpu.data 2672 # number of ReadReq hits 369system.cpu.dcache.ReadReq_hits::total 2672 # number of ReadReq hits 370system.cpu.dcache.WriteReq_hits::cpu.data 1034 # number of WriteReq hits 371system.cpu.dcache.WriteReq_hits::total 1034 # number of WriteReq hits 372system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 373system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 374system.cpu.dcache.demand_hits::cpu.data 3706 # number of demand (read+write) hits 375system.cpu.dcache.demand_hits::total 3706 # number of demand (read+write) hits 376system.cpu.dcache.overall_hits::cpu.data 3706 # number of overall hits 377system.cpu.dcache.overall_hits::total 3706 # number of overall hits 378system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses 379system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses 380system.cpu.dcache.WriteReq_misses::cpu.data 408 # number of WriteReq misses 381system.cpu.dcache.WriteReq_misses::total 408 # number of WriteReq misses 382system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses 383system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses 384system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses 385system.cpu.dcache.overall_misses::total 522 # number of overall misses 386system.cpu.dcache.ReadReq_miss_latency::cpu.data 3994500 # number of ReadReq miss cycles 387system.cpu.dcache.ReadReq_miss_latency::total 3994500 # number of ReadReq miss cycles 388system.cpu.dcache.WriteReq_miss_latency::cpu.data 14649500 # number of WriteReq miss cycles 389system.cpu.dcache.WriteReq_miss_latency::total 14649500 # number of WriteReq miss cycles 390system.cpu.dcache.demand_miss_latency::cpu.data 18644000 # number of demand (read+write) miss cycles 391system.cpu.dcache.demand_miss_latency::total 18644000 # number of demand (read+write) miss cycles 392system.cpu.dcache.overall_miss_latency::cpu.data 18644000 # number of overall miss cycles 393system.cpu.dcache.overall_miss_latency::total 18644000 # number of overall miss cycles 394system.cpu.dcache.ReadReq_accesses::cpu.data 2786 # number of ReadReq accesses(hits+misses) 395system.cpu.dcache.ReadReq_accesses::total 2786 # number of ReadReq accesses(hits+misses) 396system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 397system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 398system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 399system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) 400system.cpu.dcache.demand_accesses::cpu.data 4228 # number of demand (read+write) accesses 401system.cpu.dcache.demand_accesses::total 4228 # number of demand (read+write) accesses 402system.cpu.dcache.overall_accesses::cpu.data 4228 # number of overall (read+write) accesses 403system.cpu.dcache.overall_accesses::total 4228 # number of overall (read+write) accesses 404system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040919 # miss rate for ReadReq accesses 405system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282940 # miss rate for WriteReq accesses 406system.cpu.dcache.demand_miss_rate::cpu.data 0.123463 # miss rate for demand accesses 407system.cpu.dcache.overall_miss_rate::cpu.data 0.123463 # miss rate for overall accesses 408system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35039.473684 # average ReadReq miss latency 409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35905.637255 # average WriteReq miss latency 410system.cpu.dcache.demand_avg_miss_latency::cpu.data 35716.475096 # average overall miss latency 411system.cpu.dcache.overall_avg_miss_latency::cpu.data 35716.475096 # average overall miss latency 412system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 413system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 414system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 416system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 417system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 418system.cpu.dcache.fast_writes 0 # number of fast writes performed 419system.cpu.dcache.cache_copies 0 # number of cache copies performed 420system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits 421system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits 422system.cpu.dcache.WriteReq_mshr_hits::cpu.data 325 # number of WriteReq MSHR hits 423system.cpu.dcache.WriteReq_mshr_hits::total 325 # number of WriteReq MSHR hits 424system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits 425system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits 426system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits 427system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits 428system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses 429system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses 430system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 431system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 432system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses 433system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 434system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses 435system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses 436system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2241500 # number of ReadReq MSHR miss cycles 437system.cpu.dcache.ReadReq_mshr_miss_latency::total 2241500 # number of ReadReq MSHR miss cycles 438system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2985000 # number of WriteReq MSHR miss cycles 439system.cpu.dcache.WriteReq_mshr_miss_latency::total 2985000 # number of WriteReq MSHR miss cycles 440system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5226500 # number of demand (read+write) MSHR miss cycles 441system.cpu.dcache.demand_mshr_miss_latency::total 5226500 # number of demand (read+write) MSHR miss cycles 442system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5226500 # number of overall MSHR miss cycles 443system.cpu.dcache.overall_mshr_miss_latency::total 5226500 # number of overall MSHR miss cycles 444system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022613 # mshr miss rate for ReadReq accesses 445system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 446system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034532 # mshr miss rate for demand accesses 447system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034532 # mshr miss rate for overall accesses 448system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35579.365079 # average ReadReq mshr miss latency 449system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35963.855422 # average WriteReq mshr miss latency 450system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35797.945205 # average overall mshr miss latency 451system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35797.945205 # average overall mshr miss latency 452system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 453system.cpu.l2cache.replacements 0 # number of replacements 454system.cpu.l2cache.tagsinuse 228.374360 # Cycle average of tags in use 455system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 456system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. 457system.cpu.l2cache.avg_refs 0.005089 # Average number of references to valid blocks. 458system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 459system.cpu.l2cache.occ_blocks::cpu.inst 192.484909 # Average occupied blocks per requestor 460system.cpu.l2cache.occ_blocks::cpu.data 35.889452 # Average occupied blocks per requestor 461system.cpu.l2cache.occ_percent::cpu.inst 0.005874 # Average percentage of cache occupancy 462system.cpu.l2cache.occ_percent::cpu.data 0.001095 # Average percentage of cache occupancy 463system.cpu.l2cache.occ_percent::total 0.006969 # Average percentage of cache occupancy 464system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 465system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 466system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 467system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 468system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 469system.cpu.l2cache.overall_hits::total 2 # number of overall hits 470system.cpu.l2cache.ReadReq_misses::cpu.inst 330 # number of ReadReq misses 471system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses 472system.cpu.l2cache.ReadReq_misses::total 393 # number of ReadReq misses 473system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 474system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses 475system.cpu.l2cache.demand_misses::cpu.inst 330 # number of demand (read+write) misses 476system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses 477system.cpu.l2cache.demand_misses::total 476 # number of demand (read+write) misses 478system.cpu.l2cache.overall_misses::cpu.inst 330 # number of overall misses 479system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses 480system.cpu.l2cache.overall_misses::total 476 # number of overall misses 481system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11308000 # number of ReadReq miss cycles 482system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2167000 # number of ReadReq miss cycles 483system.cpu.l2cache.ReadReq_miss_latency::total 13475000 # number of ReadReq miss cycles 484system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2872000 # number of ReadExReq miss cycles 485system.cpu.l2cache.ReadExReq_miss_latency::total 2872000 # number of ReadExReq miss cycles 486system.cpu.l2cache.demand_miss_latency::cpu.inst 11308000 # number of demand (read+write) miss cycles 487system.cpu.l2cache.demand_miss_latency::cpu.data 5039000 # number of demand (read+write) miss cycles 488system.cpu.l2cache.demand_miss_latency::total 16347000 # number of demand (read+write) miss cycles 489system.cpu.l2cache.overall_miss_latency::cpu.inst 11308000 # number of overall miss cycles 490system.cpu.l2cache.overall_miss_latency::cpu.data 5039000 # number of overall miss cycles 491system.cpu.l2cache.overall_miss_latency::total 16347000 # number of overall miss cycles 492system.cpu.l2cache.ReadReq_accesses::cpu.inst 332 # number of ReadReq accesses(hits+misses) 493system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses) 494system.cpu.l2cache.ReadReq_accesses::total 395 # number of ReadReq accesses(hits+misses) 495system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 496system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) 497system.cpu.l2cache.demand_accesses::cpu.inst 332 # number of demand (read+write) accesses 498system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses 499system.cpu.l2cache.demand_accesses::total 478 # number of demand (read+write) accesses 500system.cpu.l2cache.overall_accesses::cpu.inst 332 # number of overall (read+write) accesses 501system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses 502system.cpu.l2cache.overall_accesses::total 478 # number of overall (read+write) accesses 503system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993976 # miss rate for ReadReq accesses 504system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 505system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 506system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993976 # miss rate for demand accesses 507system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 508system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993976 # miss rate for overall accesses 509system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 510system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34266.666667 # average ReadReq miss latency 511system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34396.825397 # average ReadReq miss latency 512system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34602.409639 # average ReadExReq miss latency 513system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34266.666667 # average overall miss latency 514system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34513.698630 # average overall miss latency 515system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34266.666667 # average overall miss latency 516system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34513.698630 # average overall miss latency 517system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 518system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 519system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 520system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 521system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 522system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 523system.cpu.l2cache.fast_writes 0 # number of fast writes performed 524system.cpu.l2cache.cache_copies 0 # number of cache copies performed 525system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 330 # number of ReadReq MSHR misses 526system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses 527system.cpu.l2cache.ReadReq_mshr_misses::total 393 # number of ReadReq MSHR misses 528system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 529system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 530system.cpu.l2cache.demand_mshr_misses::cpu.inst 330 # number of demand (read+write) MSHR misses 531system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses 532system.cpu.l2cache.demand_mshr_misses::total 476 # number of demand (read+write) MSHR misses 533system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses 534system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses 535system.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses 536system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10246500 # number of ReadReq MSHR miss cycles 537system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1968500 # number of ReadReq MSHR miss cycles 538system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12215000 # number of ReadReq MSHR miss cycles 539system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2608500 # number of ReadExReq MSHR miss cycles 540system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2608500 # number of ReadExReq MSHR miss cycles 541system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10246500 # number of demand (read+write) MSHR miss cycles 542system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4577000 # number of demand (read+write) MSHR miss cycles 543system.cpu.l2cache.demand_mshr_miss_latency::total 14823500 # number of demand (read+write) MSHR miss cycles 544system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10246500 # number of overall MSHR miss cycles 545system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4577000 # number of overall MSHR miss cycles 546system.cpu.l2cache.overall_mshr_miss_latency::total 14823500 # number of overall MSHR miss cycles 547system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for ReadReq accesses 548system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 549system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 550system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for demand accesses 551system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 552system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for overall accesses 553system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 554system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31050 # average ReadReq mshr miss latency 555system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746 # average ReadReq mshr miss latency 556system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31427.710843 # average ReadExReq mshr miss latency 557system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31050 # average overall mshr miss latency 558system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency 559system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31050 # average overall mshr miss latency 560system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency 561system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 562 563---------- End Simulation Statistics ---------- 564