config.ini revision 9481:b0fa6b872f40
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=timing 18mem_ranges= 19memories=system.physmem 20num_work_ids=16 21readfile= 22symbolfile= 23work_begin_ckpt_count=0 24work_begin_cpu_id_exit=-1 25work_begin_exit_count=0 26work_cpus_ckpt_count=0 27work_end_ckpt_count=0 28work_end_exit_count=0 29work_item_id=-1 30system_port=system.membus.slave[0] 31 32[system.cpu] 33type=DerivO3CPU 34children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 35LFSTSize=1024 36LQEntries=32 37LSQCheckLoads=true 38LSQDepCheckShift=4 39SQEntries=32 40SSITSize=1024 41activity=0 42backComSize=5 43branchPred=system.cpu.branchPred 44cachePorts=200 45checker=Null 46clock=500 47commitToDecodeDelay=1 48commitToFetchDelay=1 49commitToIEWDelay=1 50commitToRenameDelay=1 51commitWidth=8 52cpu_id=0 53decodeToFetchDelay=1 54decodeToRenameDelay=1 55decodeWidth=8 56dispatchWidth=8 57do_checkpoint_insts=true 58do_quiesce=true 59do_statistics_insts=true 60dtb=system.cpu.dtb 61fetchToDecodeDelay=1 62fetchTrapLatency=1 63fetchWidth=8 64forwardComSize=5 65fuPool=system.cpu.fuPool 66function_trace=false 67function_trace_start=0 68iewToCommitDelay=1 69iewToDecodeDelay=1 70iewToFetchDelay=1 71iewToRenameDelay=1 72interrupts=system.cpu.interrupts 73isa=system.cpu.isa 74issueToExecuteDelay=1 75issueWidth=8 76itb=system.cpu.itb 77max_insts_all_threads=0 78max_insts_any_thread=0 79max_loads_all_threads=0 80max_loads_any_thread=0 81needsTSO=false 82numIQEntries=64 83numPhysFloatRegs=256 84numPhysIntRegs=256 85numROBEntries=192 86numRobs=1 87numThreads=1 88profile=0 89progress_interval=0 90renameToDecodeDelay=1 91renameToFetchDelay=1 92renameToIEWDelay=2 93renameToROBDelay=1 94renameWidth=8 95smtCommitPolicy=RoundRobin 96smtFetchPolicy=SingleThread 97smtIQPolicy=Partitioned 98smtIQThreshold=100 99smtLSQPolicy=Partitioned 100smtLSQThreshold=100 101smtNumFetchingThreads=1 102smtROBPolicy=Partitioned 103smtROBThreshold=100 104squashWidth=8 105store_set_clear_period=250000 106switched_out=false 107system=system 108tracer=system.cpu.tracer 109trapLatency=13 110wbDepth=1 111wbWidth=8 112workload=system.cpu.workload 113dcache_port=system.cpu.dcache.cpu_side 114icache_port=system.cpu.icache.cpu_side 115 116[system.cpu.branchPred] 117type=BranchPredictor 118BTBEntries=4096 119BTBTagSize=16 120RASSize=16 121choiceCtrBits=2 122choicePredictorSize=8192 123globalCtrBits=2 124globalHistoryBits=13 125globalPredictorSize=8192 126instShiftAmt=2 127localCtrBits=2 128localHistoryBits=11 129localHistoryTableSize=2048 130localPredictorSize=2048 131numThreads=1 132predType=tournament 133 134[system.cpu.dcache] 135type=BaseCache 136addr_ranges=0:18446744073709551615 137assoc=2 138block_size=64 139clock=500 140forward_snoops=true 141hit_latency=2 142is_top_level=true 143max_miss_count=0 144mshrs=4 145prefetch_on_access=false 146prefetcher=Null 147response_latency=2 148size=262144 149system=system 150tgts_per_mshr=20 151two_queue=false 152write_buffers=8 153cpu_side=system.cpu.dcache_port 154mem_side=system.cpu.toL2Bus.slave[1] 155 156[system.cpu.dtb] 157type=SparcTLB 158size=64 159 160[system.cpu.fuPool] 161type=FUPool 162children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 163FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 164 165[system.cpu.fuPool.FUList0] 166type=FUDesc 167children=opList 168count=6 169opList=system.cpu.fuPool.FUList0.opList 170 171[system.cpu.fuPool.FUList0.opList] 172type=OpDesc 173issueLat=1 174opClass=IntAlu 175opLat=1 176 177[system.cpu.fuPool.FUList1] 178type=FUDesc 179children=opList0 opList1 180count=2 181opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 182 183[system.cpu.fuPool.FUList1.opList0] 184type=OpDesc 185issueLat=1 186opClass=IntMult 187opLat=3 188 189[system.cpu.fuPool.FUList1.opList1] 190type=OpDesc 191issueLat=19 192opClass=IntDiv 193opLat=20 194 195[system.cpu.fuPool.FUList2] 196type=FUDesc 197children=opList0 opList1 opList2 198count=4 199opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 200 201[system.cpu.fuPool.FUList2.opList0] 202type=OpDesc 203issueLat=1 204opClass=FloatAdd 205opLat=2 206 207[system.cpu.fuPool.FUList2.opList1] 208type=OpDesc 209issueLat=1 210opClass=FloatCmp 211opLat=2 212 213[system.cpu.fuPool.FUList2.opList2] 214type=OpDesc 215issueLat=1 216opClass=FloatCvt 217opLat=2 218 219[system.cpu.fuPool.FUList3] 220type=FUDesc 221children=opList0 opList1 opList2 222count=2 223opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 224 225[system.cpu.fuPool.FUList3.opList0] 226type=OpDesc 227issueLat=1 228opClass=FloatMult 229opLat=4 230 231[system.cpu.fuPool.FUList3.opList1] 232type=OpDesc 233issueLat=12 234opClass=FloatDiv 235opLat=12 236 237[system.cpu.fuPool.FUList3.opList2] 238type=OpDesc 239issueLat=24 240opClass=FloatSqrt 241opLat=24 242 243[system.cpu.fuPool.FUList4] 244type=FUDesc 245children=opList 246count=0 247opList=system.cpu.fuPool.FUList4.opList 248 249[system.cpu.fuPool.FUList4.opList] 250type=OpDesc 251issueLat=1 252opClass=MemRead 253opLat=1 254 255[system.cpu.fuPool.FUList5] 256type=FUDesc 257children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 258count=4 259opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 260 261[system.cpu.fuPool.FUList5.opList00] 262type=OpDesc 263issueLat=1 264opClass=SimdAdd 265opLat=1 266 267[system.cpu.fuPool.FUList5.opList01] 268type=OpDesc 269issueLat=1 270opClass=SimdAddAcc 271opLat=1 272 273[system.cpu.fuPool.FUList5.opList02] 274type=OpDesc 275issueLat=1 276opClass=SimdAlu 277opLat=1 278 279[system.cpu.fuPool.FUList5.opList03] 280type=OpDesc 281issueLat=1 282opClass=SimdCmp 283opLat=1 284 285[system.cpu.fuPool.FUList5.opList04] 286type=OpDesc 287issueLat=1 288opClass=SimdCvt 289opLat=1 290 291[system.cpu.fuPool.FUList5.opList05] 292type=OpDesc 293issueLat=1 294opClass=SimdMisc 295opLat=1 296 297[system.cpu.fuPool.FUList5.opList06] 298type=OpDesc 299issueLat=1 300opClass=SimdMult 301opLat=1 302 303[system.cpu.fuPool.FUList5.opList07] 304type=OpDesc 305issueLat=1 306opClass=SimdMultAcc 307opLat=1 308 309[system.cpu.fuPool.FUList5.opList08] 310type=OpDesc 311issueLat=1 312opClass=SimdShift 313opLat=1 314 315[system.cpu.fuPool.FUList5.opList09] 316type=OpDesc 317issueLat=1 318opClass=SimdShiftAcc 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList10] 322type=OpDesc 323issueLat=1 324opClass=SimdSqrt 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList11] 328type=OpDesc 329issueLat=1 330opClass=SimdFloatAdd 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList12] 334type=OpDesc 335issueLat=1 336opClass=SimdFloatAlu 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList13] 340type=OpDesc 341issueLat=1 342opClass=SimdFloatCmp 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList14] 346type=OpDesc 347issueLat=1 348opClass=SimdFloatCvt 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList15] 352type=OpDesc 353issueLat=1 354opClass=SimdFloatDiv 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList16] 358type=OpDesc 359issueLat=1 360opClass=SimdFloatMisc 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList17] 364type=OpDesc 365issueLat=1 366opClass=SimdFloatMult 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList18] 370type=OpDesc 371issueLat=1 372opClass=SimdFloatMultAcc 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList19] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatSqrt 379opLat=1 380 381[system.cpu.fuPool.FUList6] 382type=FUDesc 383children=opList 384count=0 385opList=system.cpu.fuPool.FUList6.opList 386 387[system.cpu.fuPool.FUList6.opList] 388type=OpDesc 389issueLat=1 390opClass=MemWrite 391opLat=1 392 393[system.cpu.fuPool.FUList7] 394type=FUDesc 395children=opList0 opList1 396count=4 397opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 398 399[system.cpu.fuPool.FUList7.opList0] 400type=OpDesc 401issueLat=1 402opClass=MemRead 403opLat=1 404 405[system.cpu.fuPool.FUList7.opList1] 406type=OpDesc 407issueLat=1 408opClass=MemWrite 409opLat=1 410 411[system.cpu.fuPool.FUList8] 412type=FUDesc 413children=opList 414count=1 415opList=system.cpu.fuPool.FUList8.opList 416 417[system.cpu.fuPool.FUList8.opList] 418type=OpDesc 419issueLat=3 420opClass=IprAccess 421opLat=3 422 423[system.cpu.icache] 424type=BaseCache 425addr_ranges=0:18446744073709551615 426assoc=2 427block_size=64 428clock=500 429forward_snoops=true 430hit_latency=2 431is_top_level=true 432max_miss_count=0 433mshrs=4 434prefetch_on_access=false 435prefetcher=Null 436response_latency=2 437size=131072 438system=system 439tgts_per_mshr=20 440two_queue=false 441write_buffers=8 442cpu_side=system.cpu.icache_port 443mem_side=system.cpu.toL2Bus.slave[0] 444 445[system.cpu.interrupts] 446type=SparcInterrupts 447 448[system.cpu.isa] 449type=SparcISA 450 451[system.cpu.itb] 452type=SparcTLB 453size=64 454 455[system.cpu.l2cache] 456type=BaseCache 457addr_ranges=0:18446744073709551615 458assoc=8 459block_size=64 460clock=500 461forward_snoops=true 462hit_latency=20 463is_top_level=false 464max_miss_count=0 465mshrs=20 466prefetch_on_access=false 467prefetcher=Null 468response_latency=20 469size=2097152 470system=system 471tgts_per_mshr=12 472two_queue=false 473write_buffers=8 474cpu_side=system.cpu.toL2Bus.master[0] 475mem_side=system.membus.slave[1] 476 477[system.cpu.toL2Bus] 478type=CoherentBus 479block_size=64 480clock=500 481header_cycles=1 482use_default_range=false 483width=32 484master=system.cpu.l2cache.cpu_side 485slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 486 487[system.cpu.tracer] 488type=ExeTracer 489 490[system.cpu.workload] 491type=LiveProcess 492cmd=insttest 493cwd= 494egid=100 495env= 496errout=cerr 497euid=100 498executable=tests/test-progs/insttest/bin/sparc/linux/insttest 499gid=100 500input=cin 501max_stack_size=67108864 502output=cout 503pid=100 504ppid=99 505simpoint=0 506system=system 507uid=100 508 509[system.membus] 510type=CoherentBus 511block_size=64 512clock=1000 513header_cycles=1 514use_default_range=false 515width=8 516master=system.physmem.port 517slave=system.system_port system.cpu.l2cache.mem_side 518 519[system.physmem] 520type=SimpleDRAM 521addr_mapping=openmap 522banks_per_rank=8 523clock=1000 524conf_table_reported=false 525in_addr_map=true 526lines_per_rowbuffer=64 527mem_sched_policy=fcfs 528null=false 529page_policy=open 530range=0:134217727 531ranks_per_channel=2 532read_buffer_size=32 533tBURST=4000 534tCL=14000 535tRCD=14000 536tREFI=7800000 537tRFC=300000 538tRP=14000 539tWTR=1000 540write_buffer_size=32 541write_thresh_perc=70 542zero=false 543port=system.membus.master[0] 544 545