config.ini revision 8721
16313Sgblack@eecs.umich.edu[root] 26313Sgblack@eecs.umich.edutype=Root 36313Sgblack@eecs.umich.educhildren=system 46313Sgblack@eecs.umich.edutime_sync_enable=false 56313Sgblack@eecs.umich.edutime_sync_period=100000000000 66313Sgblack@eecs.umich.edutime_sync_spin_threshold=100000000 76313Sgblack@eecs.umich.edu 86313Sgblack@eecs.umich.edu[system] 96313Sgblack@eecs.umich.edutype=System 106313Sgblack@eecs.umich.educhildren=cpu membus physmem 116313Sgblack@eecs.umich.edumem_mode=atomic 126313Sgblack@eecs.umich.edumemories=system.physmem 136313Sgblack@eecs.umich.edunum_work_ids=16 146313Sgblack@eecs.umich.eduphysmem=system.physmem 156313Sgblack@eecs.umich.eduwork_begin_ckpt_count=0 166313Sgblack@eecs.umich.eduwork_begin_cpu_id_exit=-1 176313Sgblack@eecs.umich.eduwork_begin_exit_count=0 186313Sgblack@eecs.umich.eduwork_cpus_ckpt_count=0 196313Sgblack@eecs.umich.eduwork_end_ckpt_count=0 206313Sgblack@eecs.umich.eduwork_end_exit_count=0 216313Sgblack@eecs.umich.eduwork_item_id=-1 226313Sgblack@eecs.umich.edusystem_port=system.membus.port[0] 236313Sgblack@eecs.umich.edu 246313Sgblack@eecs.umich.edu[system.cpu] 256313Sgblack@eecs.umich.edutype=DerivO3CPU 266313Sgblack@eecs.umich.educhildren=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload 276313Sgblack@eecs.umich.eduBTBEntries=4096 286313Sgblack@eecs.umich.eduBTBTagSize=16 296313Sgblack@eecs.umich.eduLFSTSize=1024 306313Sgblack@eecs.umich.eduLQEntries=32 316313Sgblack@eecs.umich.eduLSQCheckLoads=true 326330Sgblack@eecs.umich.eduLSQDepCheckShift=4 336313Sgblack@eecs.umich.eduRASSize=16 346313Sgblack@eecs.umich.eduSQEntries=32 356313Sgblack@eecs.umich.eduSSITSize=1024 366313Sgblack@eecs.umich.eduactivity=0 376313Sgblack@eecs.umich.edubackComSize=5 386313Sgblack@eecs.umich.educachePorts=200 396678Sgblack@eecs.umich.educhecker=Null 406313Sgblack@eecs.umich.educhoiceCtrBits=2 416330Sgblack@eecs.umich.educhoicePredictorSize=8192 426330Sgblack@eecs.umich.educlock=500 436330Sgblack@eecs.umich.educommitToDecodeDelay=1 446330Sgblack@eecs.umich.educommitToFetchDelay=1 456330Sgblack@eecs.umich.educommitToIEWDelay=1 466313Sgblack@eecs.umich.educommitToRenameDelay=1 476313Sgblack@eecs.umich.educommitWidth=8 486313Sgblack@eecs.umich.educpu_id=0 496678Sgblack@eecs.umich.edudecodeToFetchDelay=1 506313Sgblack@eecs.umich.edudecodeToRenameDelay=1 516330Sgblack@eecs.umich.edudecodeWidth=8 526330Sgblack@eecs.umich.edudefer_registration=false 536330Sgblack@eecs.umich.edudispatchWidth=8 546330Sgblack@eecs.umich.edudo_checkpoint_insts=true 556330Sgblack@eecs.umich.edudo_statistics_insts=true 566330Sgblack@eecs.umich.edudtb=system.cpu.dtb 576330Sgblack@eecs.umich.edufetchToDecodeDelay=1 586330Sgblack@eecs.umich.edufetchTrapLatency=1 596330Sgblack@eecs.umich.edufetchWidth=8 606330Sgblack@eecs.umich.eduforwardComSize=5 616330Sgblack@eecs.umich.edufuPool=system.cpu.fuPool 626330Sgblack@eecs.umich.edufunction_trace=false 636330Sgblack@eecs.umich.edufunction_trace_start=0 646330Sgblack@eecs.umich.eduglobalCtrBits=2 656330Sgblack@eecs.umich.eduglobalHistoryBits=13 666330Sgblack@eecs.umich.eduglobalPredictorSize=8192 676330Sgblack@eecs.umich.eduiewToCommitDelay=1 686330Sgblack@eecs.umich.eduiewToDecodeDelay=1 696330Sgblack@eecs.umich.eduiewToFetchDelay=1 706330Sgblack@eecs.umich.eduiewToRenameDelay=1 716330Sgblack@eecs.umich.eduinstShiftAmt=2 726330Sgblack@eecs.umich.eduissueToExecuteDelay=1 736330Sgblack@eecs.umich.eduissueWidth=8 746330Sgblack@eecs.umich.eduitb=system.cpu.itb 756330Sgblack@eecs.umich.edulocalCtrBits=2 766330Sgblack@eecs.umich.edulocalHistoryBits=11 776330Sgblack@eecs.umich.edulocalHistoryTableSize=2048 786330Sgblack@eecs.umich.edulocalPredictorSize=2048 796330Sgblack@eecs.umich.edumax_insts_all_threads=0 806330Sgblack@eecs.umich.edumax_insts_any_thread=0 816330Sgblack@eecs.umich.edumax_loads_all_threads=0 826330Sgblack@eecs.umich.edumax_loads_any_thread=0 836330Sgblack@eecs.umich.edunumIQEntries=64 846330Sgblack@eecs.umich.edunumPhysFloatRegs=256 856330Sgblack@eecs.umich.edunumPhysIntRegs=256 866330Sgblack@eecs.umich.edunumROBEntries=192 876330Sgblack@eecs.umich.edunumRobs=1 886330Sgblack@eecs.umich.edunumThreads=1 896330Sgblack@eecs.umich.eduphase=0 906330Sgblack@eecs.umich.edupredType=tournament 916330Sgblack@eecs.umich.eduprogress_interval=0 926330Sgblack@eecs.umich.edurenameToDecodeDelay=1 936330Sgblack@eecs.umich.edurenameToFetchDelay=1 946330Sgblack@eecs.umich.edurenameToIEWDelay=2 956330Sgblack@eecs.umich.edurenameToROBDelay=1 966330Sgblack@eecs.umich.edurenameWidth=8 976330Sgblack@eecs.umich.edusmtCommitPolicy=RoundRobin 986330Sgblack@eecs.umich.edusmtFetchPolicy=SingleThread 996330Sgblack@eecs.umich.edusmtIQPolicy=Partitioned 1006330Sgblack@eecs.umich.edusmtIQThreshold=100 1016330Sgblack@eecs.umich.edusmtLSQPolicy=Partitioned 1026330Sgblack@eecs.umich.edusmtLSQThreshold=100 1036330Sgblack@eecs.umich.edusmtNumFetchingThreads=1 1046330Sgblack@eecs.umich.edusmtROBPolicy=Partitioned 1056330Sgblack@eecs.umich.edusmtROBThreshold=100 1066330Sgblack@eecs.umich.edusquashWidth=8 1076330Sgblack@eecs.umich.edustore_set_clear_period=250000 1086330Sgblack@eecs.umich.edusystem=system 1096330Sgblack@eecs.umich.edutracer=system.cpu.tracer 1106330Sgblack@eecs.umich.edutrapLatency=13 1116330Sgblack@eecs.umich.eduwbDepth=1 1126330Sgblack@eecs.umich.eduwbWidth=8 1136330Sgblack@eecs.umich.eduworkload=system.cpu.workload 1146330Sgblack@eecs.umich.edudcache_port=system.cpu.dcache.cpu_side 1156330Sgblack@eecs.umich.eduicache_port=system.cpu.icache.cpu_side 1166330Sgblack@eecs.umich.edu 1176330Sgblack@eecs.umich.edu[system.cpu.dcache] 1186330Sgblack@eecs.umich.edutype=BaseCache 1196330Sgblack@eecs.umich.eduaddr_range=0:18446744073709551615 1206330Sgblack@eecs.umich.eduassoc=2 1216330Sgblack@eecs.umich.edublock_size=64 1226330Sgblack@eecs.umich.eduforward_snoops=true 1236330Sgblack@eecs.umich.eduhash_delay=1 1246330Sgblack@eecs.umich.eduis_top_level=true 1256330Sgblack@eecs.umich.edulatency=1000 1266330Sgblack@eecs.umich.edumax_miss_count=0 1276330Sgblack@eecs.umich.edumshrs=10 1286330Sgblack@eecs.umich.edunum_cpus=1 1296330Sgblack@eecs.umich.eduprefetch_data_accesses_only=false 1306330Sgblack@eecs.umich.eduprefetch_degree=1 1316330Sgblack@eecs.umich.eduprefetch_latency=10000 1326330Sgblack@eecs.umich.eduprefetch_on_access=false 1336330Sgblack@eecs.umich.eduprefetch_past_page=false 1346330Sgblack@eecs.umich.eduprefetch_policy=none 1356330Sgblack@eecs.umich.eduprefetch_serial_squash=false 1366330Sgblack@eecs.umich.eduprefetch_use_cpu_id=true 1376330Sgblack@eecs.umich.eduprefetcher_size=100 1386330Sgblack@eecs.umich.eduprioritizeRequests=false 1396330Sgblack@eecs.umich.edurepl=Null 1406330Sgblack@eecs.umich.edusize=262144 1416330Sgblack@eecs.umich.edusubblock_size=0 1426330Sgblack@eecs.umich.edutgts_per_mshr=20 1436330Sgblack@eecs.umich.edutrace_addr=0 1446330Sgblack@eecs.umich.edutwo_queue=false 1456330Sgblack@eecs.umich.eduwrite_buffers=8 1466330Sgblack@eecs.umich.educpu_side=system.cpu.dcache_port 1476330Sgblack@eecs.umich.edumem_side=system.cpu.toL2Bus.port[1] 1486313Sgblack@eecs.umich.edu 1496313Sgblack@eecs.umich.edu[system.cpu.dtb] 1506313Sgblack@eecs.umich.edutype=SparcTLB 151size=64 152 153[system.cpu.fuPool] 154type=FUPool 155children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 156FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 157 158[system.cpu.fuPool.FUList0] 159type=FUDesc 160children=opList 161count=6 162opList=system.cpu.fuPool.FUList0.opList 163 164[system.cpu.fuPool.FUList0.opList] 165type=OpDesc 166issueLat=1 167opClass=IntAlu 168opLat=1 169 170[system.cpu.fuPool.FUList1] 171type=FUDesc 172children=opList0 opList1 173count=2 174opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 175 176[system.cpu.fuPool.FUList1.opList0] 177type=OpDesc 178issueLat=1 179opClass=IntMult 180opLat=3 181 182[system.cpu.fuPool.FUList1.opList1] 183type=OpDesc 184issueLat=19 185opClass=IntDiv 186opLat=20 187 188[system.cpu.fuPool.FUList2] 189type=FUDesc 190children=opList0 opList1 opList2 191count=4 192opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 193 194[system.cpu.fuPool.FUList2.opList0] 195type=OpDesc 196issueLat=1 197opClass=FloatAdd 198opLat=2 199 200[system.cpu.fuPool.FUList2.opList1] 201type=OpDesc 202issueLat=1 203opClass=FloatCmp 204opLat=2 205 206[system.cpu.fuPool.FUList2.opList2] 207type=OpDesc 208issueLat=1 209opClass=FloatCvt 210opLat=2 211 212[system.cpu.fuPool.FUList3] 213type=FUDesc 214children=opList0 opList1 opList2 215count=2 216opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 217 218[system.cpu.fuPool.FUList3.opList0] 219type=OpDesc 220issueLat=1 221opClass=FloatMult 222opLat=4 223 224[system.cpu.fuPool.FUList3.opList1] 225type=OpDesc 226issueLat=12 227opClass=FloatDiv 228opLat=12 229 230[system.cpu.fuPool.FUList3.opList2] 231type=OpDesc 232issueLat=24 233opClass=FloatSqrt 234opLat=24 235 236[system.cpu.fuPool.FUList4] 237type=FUDesc 238children=opList 239count=0 240opList=system.cpu.fuPool.FUList4.opList 241 242[system.cpu.fuPool.FUList4.opList] 243type=OpDesc 244issueLat=1 245opClass=MemRead 246opLat=1 247 248[system.cpu.fuPool.FUList5] 249type=FUDesc 250children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 251count=4 252opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 253 254[system.cpu.fuPool.FUList5.opList00] 255type=OpDesc 256issueLat=1 257opClass=SimdAdd 258opLat=1 259 260[system.cpu.fuPool.FUList5.opList01] 261type=OpDesc 262issueLat=1 263opClass=SimdAddAcc 264opLat=1 265 266[system.cpu.fuPool.FUList5.opList02] 267type=OpDesc 268issueLat=1 269opClass=SimdAlu 270opLat=1 271 272[system.cpu.fuPool.FUList5.opList03] 273type=OpDesc 274issueLat=1 275opClass=SimdCmp 276opLat=1 277 278[system.cpu.fuPool.FUList5.opList04] 279type=OpDesc 280issueLat=1 281opClass=SimdCvt 282opLat=1 283 284[system.cpu.fuPool.FUList5.opList05] 285type=OpDesc 286issueLat=1 287opClass=SimdMisc 288opLat=1 289 290[system.cpu.fuPool.FUList5.opList06] 291type=OpDesc 292issueLat=1 293opClass=SimdMult 294opLat=1 295 296[system.cpu.fuPool.FUList5.opList07] 297type=OpDesc 298issueLat=1 299opClass=SimdMultAcc 300opLat=1 301 302[system.cpu.fuPool.FUList5.opList08] 303type=OpDesc 304issueLat=1 305opClass=SimdShift 306opLat=1 307 308[system.cpu.fuPool.FUList5.opList09] 309type=OpDesc 310issueLat=1 311opClass=SimdShiftAcc 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList10] 315type=OpDesc 316issueLat=1 317opClass=SimdSqrt 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList11] 321type=OpDesc 322issueLat=1 323opClass=SimdFloatAdd 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList12] 327type=OpDesc 328issueLat=1 329opClass=SimdFloatAlu 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList13] 333type=OpDesc 334issueLat=1 335opClass=SimdFloatCmp 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList14] 339type=OpDesc 340issueLat=1 341opClass=SimdFloatCvt 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList15] 345type=OpDesc 346issueLat=1 347opClass=SimdFloatDiv 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList16] 351type=OpDesc 352issueLat=1 353opClass=SimdFloatMisc 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList17] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatMult 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList18] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatMultAcc 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList19] 369type=OpDesc 370issueLat=1 371opClass=SimdFloatSqrt 372opLat=1 373 374[system.cpu.fuPool.FUList6] 375type=FUDesc 376children=opList 377count=0 378opList=system.cpu.fuPool.FUList6.opList 379 380[system.cpu.fuPool.FUList6.opList] 381type=OpDesc 382issueLat=1 383opClass=MemWrite 384opLat=1 385 386[system.cpu.fuPool.FUList7] 387type=FUDesc 388children=opList0 opList1 389count=4 390opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 391 392[system.cpu.fuPool.FUList7.opList0] 393type=OpDesc 394issueLat=1 395opClass=MemRead 396opLat=1 397 398[system.cpu.fuPool.FUList7.opList1] 399type=OpDesc 400issueLat=1 401opClass=MemWrite 402opLat=1 403 404[system.cpu.fuPool.FUList8] 405type=FUDesc 406children=opList 407count=1 408opList=system.cpu.fuPool.FUList8.opList 409 410[system.cpu.fuPool.FUList8.opList] 411type=OpDesc 412issueLat=3 413opClass=IprAccess 414opLat=3 415 416[system.cpu.icache] 417type=BaseCache 418addr_range=0:18446744073709551615 419assoc=2 420block_size=64 421forward_snoops=true 422hash_delay=1 423is_top_level=true 424latency=1000 425max_miss_count=0 426mshrs=10 427num_cpus=1 428prefetch_data_accesses_only=false 429prefetch_degree=1 430prefetch_latency=10000 431prefetch_on_access=false 432prefetch_past_page=false 433prefetch_policy=none 434prefetch_serial_squash=false 435prefetch_use_cpu_id=true 436prefetcher_size=100 437prioritizeRequests=false 438repl=Null 439size=131072 440subblock_size=0 441tgts_per_mshr=20 442trace_addr=0 443two_queue=false 444write_buffers=8 445cpu_side=system.cpu.icache_port 446mem_side=system.cpu.toL2Bus.port[0] 447 448[system.cpu.itb] 449type=SparcTLB 450size=64 451 452[system.cpu.l2cache] 453type=BaseCache 454addr_range=0:18446744073709551615 455assoc=2 456block_size=64 457forward_snoops=true 458hash_delay=1 459is_top_level=false 460latency=1000 461max_miss_count=0 462mshrs=10 463num_cpus=1 464prefetch_data_accesses_only=false 465prefetch_degree=1 466prefetch_latency=10000 467prefetch_on_access=false 468prefetch_past_page=false 469prefetch_policy=none 470prefetch_serial_squash=false 471prefetch_use_cpu_id=true 472prefetcher_size=100 473prioritizeRequests=false 474repl=Null 475size=2097152 476subblock_size=0 477tgts_per_mshr=5 478trace_addr=0 479two_queue=false 480write_buffers=8 481cpu_side=system.cpu.toL2Bus.port[2] 482mem_side=system.membus.port[2] 483 484[system.cpu.toL2Bus] 485type=Bus 486block_size=64 487bus_id=0 488clock=1000 489header_cycles=1 490use_default_range=false 491width=64 492port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 493 494[system.cpu.tracer] 495type=ExeTracer 496 497[system.cpu.workload] 498type=LiveProcess 499cmd=insttest 500cwd= 501egid=100 502env= 503errout=cerr 504euid=100 505executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest 506gid=100 507input=cin 508max_stack_size=67108864 509output=cout 510pid=100 511ppid=99 512simpoint=0 513system=system 514uid=100 515 516[system.membus] 517type=Bus 518block_size=64 519bus_id=0 520clock=1000 521header_cycles=1 522use_default_range=false 523width=64 524port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side 525 526[system.physmem] 527type=PhysicalMemory 528file= 529latency=30000 530latency_var=0 531null=false 532range=0:134217727 533zero=false 534port=system.membus.port[1] 535 536