config.ini revision 11066
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=Null 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dtb=system.cpu.dtb 76eventq_index=0 77fetchBufferSize=64 78fetchQueueSize=32 79fetchToDecodeDelay=1 80fetchTrapLatency=1 81fetchWidth=8 82forwardComSize=5 83fuPool=system.cpu.fuPool 84function_trace=false 85function_trace_start=0 86iewToCommitDelay=1 87iewToDecodeDelay=1 88iewToFetchDelay=1 89iewToRenameDelay=1 90interrupts=system.cpu.interrupts 91isa=system.cpu.isa 92issueToExecuteDelay=1 93issueWidth=8 94itb=system.cpu.itb 95max_insts_all_threads=0 96max_insts_any_thread=0 97max_loads_all_threads=0 98max_loads_any_thread=0 99needsTSO=false 100numIQEntries=64 101numPhysCCRegs=0 102numPhysFloatRegs=256 103numPhysIntRegs=256 104numROBEntries=192 105numRobs=1 106numThreads=1 107profile=0 108progress_interval=0 109renameToDecodeDelay=1 110renameToFetchDelay=1 111renameToIEWDelay=2 112renameToROBDelay=1 113renameWidth=8 114simpoint_start_insts= 115smtCommitPolicy=RoundRobin 116smtFetchPolicy=SingleThread 117smtIQPolicy=Partitioned 118smtIQThreshold=100 119smtLSQPolicy=Partitioned 120smtLSQThreshold=100 121smtNumFetchingThreads=1 122smtROBPolicy=Partitioned 123smtROBThreshold=100 124socket_id=0 125squashWidth=8 126store_set_clear_period=250000 127switched_out=false 128system=system 129tracer=system.cpu.tracer 130trapLatency=13 131wbWidth=8 132workload=system.cpu.workload 133dcache_port=system.cpu.dcache.cpu_side 134icache_port=system.cpu.icache.cpu_side 135 136[system.cpu.branchPred] 137type=TournamentBP 138BTBEntries=4096 139BTBTagSize=16 140RASSize=16 141choiceCtrBits=2 142choicePredictorSize=8192 143eventq_index=0 144globalCtrBits=2 145globalPredictorSize=8192 146instShiftAmt=2 147localCtrBits=2 148localHistoryTableSize=2048 149localPredictorSize=2048 150numThreads=1 151 152[system.cpu.dcache] 153type=Cache 154children=tags 155addr_ranges=0:18446744073709551615 156assoc=2 157clk_domain=system.cpu_clk_domain 158demand_mshr_reserve=1 159eventq_index=0 160forward_snoops=true 161hit_latency=2 162is_read_only=false 163max_miss_count=0 164mshrs=4 165prefetch_on_access=false 166prefetcher=Null 167response_latency=2 168sequential_access=false 169size=262144 170system=system 171tags=system.cpu.dcache.tags 172tgts_per_mshr=20 173write_buffers=8 174cpu_side=system.cpu.dcache_port 175mem_side=system.cpu.toL2Bus.slave[1] 176 177[system.cpu.dcache.tags] 178type=LRU 179assoc=2 180block_size=64 181clk_domain=system.cpu_clk_domain 182eventq_index=0 183hit_latency=2 184sequential_access=false 185size=262144 186 187[system.cpu.dtb] 188type=SparcTLB 189eventq_index=0 190size=64 191 192[system.cpu.fuPool] 193type=FUPool 194children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 195FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 196eventq_index=0 197 198[system.cpu.fuPool.FUList0] 199type=FUDesc 200children=opList 201count=6 202eventq_index=0 203opList=system.cpu.fuPool.FUList0.opList 204 205[system.cpu.fuPool.FUList0.opList] 206type=OpDesc 207eventq_index=0 208opClass=IntAlu 209opLat=1 210pipelined=true 211 212[system.cpu.fuPool.FUList1] 213type=FUDesc 214children=opList0 opList1 215count=2 216eventq_index=0 217opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 218 219[system.cpu.fuPool.FUList1.opList0] 220type=OpDesc 221eventq_index=0 222opClass=IntMult 223opLat=3 224pipelined=true 225 226[system.cpu.fuPool.FUList1.opList1] 227type=OpDesc 228eventq_index=0 229opClass=IntDiv 230opLat=20 231pipelined=false 232 233[system.cpu.fuPool.FUList2] 234type=FUDesc 235children=opList0 opList1 opList2 236count=4 237eventq_index=0 238opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 239 240[system.cpu.fuPool.FUList2.opList0] 241type=OpDesc 242eventq_index=0 243opClass=FloatAdd 244opLat=2 245pipelined=true 246 247[system.cpu.fuPool.FUList2.opList1] 248type=OpDesc 249eventq_index=0 250opClass=FloatCmp 251opLat=2 252pipelined=true 253 254[system.cpu.fuPool.FUList2.opList2] 255type=OpDesc 256eventq_index=0 257opClass=FloatCvt 258opLat=2 259pipelined=true 260 261[system.cpu.fuPool.FUList3] 262type=FUDesc 263children=opList0 opList1 opList2 264count=2 265eventq_index=0 266opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 267 268[system.cpu.fuPool.FUList3.opList0] 269type=OpDesc 270eventq_index=0 271opClass=FloatMult 272opLat=4 273pipelined=true 274 275[system.cpu.fuPool.FUList3.opList1] 276type=OpDesc 277eventq_index=0 278opClass=FloatDiv 279opLat=12 280pipelined=false 281 282[system.cpu.fuPool.FUList3.opList2] 283type=OpDesc 284eventq_index=0 285opClass=FloatSqrt 286opLat=24 287pipelined=false 288 289[system.cpu.fuPool.FUList4] 290type=FUDesc 291children=opList 292count=0 293eventq_index=0 294opList=system.cpu.fuPool.FUList4.opList 295 296[system.cpu.fuPool.FUList4.opList] 297type=OpDesc 298eventq_index=0 299opClass=MemRead 300opLat=1 301pipelined=true 302 303[system.cpu.fuPool.FUList5] 304type=FUDesc 305children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 306count=4 307eventq_index=0 308opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 309 310[system.cpu.fuPool.FUList5.opList00] 311type=OpDesc 312eventq_index=0 313opClass=SimdAdd 314opLat=1 315pipelined=true 316 317[system.cpu.fuPool.FUList5.opList01] 318type=OpDesc 319eventq_index=0 320opClass=SimdAddAcc 321opLat=1 322pipelined=true 323 324[system.cpu.fuPool.FUList5.opList02] 325type=OpDesc 326eventq_index=0 327opClass=SimdAlu 328opLat=1 329pipelined=true 330 331[system.cpu.fuPool.FUList5.opList03] 332type=OpDesc 333eventq_index=0 334opClass=SimdCmp 335opLat=1 336pipelined=true 337 338[system.cpu.fuPool.FUList5.opList04] 339type=OpDesc 340eventq_index=0 341opClass=SimdCvt 342opLat=1 343pipelined=true 344 345[system.cpu.fuPool.FUList5.opList05] 346type=OpDesc 347eventq_index=0 348opClass=SimdMisc 349opLat=1 350pipelined=true 351 352[system.cpu.fuPool.FUList5.opList06] 353type=OpDesc 354eventq_index=0 355opClass=SimdMult 356opLat=1 357pipelined=true 358 359[system.cpu.fuPool.FUList5.opList07] 360type=OpDesc 361eventq_index=0 362opClass=SimdMultAcc 363opLat=1 364pipelined=true 365 366[system.cpu.fuPool.FUList5.opList08] 367type=OpDesc 368eventq_index=0 369opClass=SimdShift 370opLat=1 371pipelined=true 372 373[system.cpu.fuPool.FUList5.opList09] 374type=OpDesc 375eventq_index=0 376opClass=SimdShiftAcc 377opLat=1 378pipelined=true 379 380[system.cpu.fuPool.FUList5.opList10] 381type=OpDesc 382eventq_index=0 383opClass=SimdSqrt 384opLat=1 385pipelined=true 386 387[system.cpu.fuPool.FUList5.opList11] 388type=OpDesc 389eventq_index=0 390opClass=SimdFloatAdd 391opLat=1 392pipelined=true 393 394[system.cpu.fuPool.FUList5.opList12] 395type=OpDesc 396eventq_index=0 397opClass=SimdFloatAlu 398opLat=1 399pipelined=true 400 401[system.cpu.fuPool.FUList5.opList13] 402type=OpDesc 403eventq_index=0 404opClass=SimdFloatCmp 405opLat=1 406pipelined=true 407 408[system.cpu.fuPool.FUList5.opList14] 409type=OpDesc 410eventq_index=0 411opClass=SimdFloatCvt 412opLat=1 413pipelined=true 414 415[system.cpu.fuPool.FUList5.opList15] 416type=OpDesc 417eventq_index=0 418opClass=SimdFloatDiv 419opLat=1 420pipelined=true 421 422[system.cpu.fuPool.FUList5.opList16] 423type=OpDesc 424eventq_index=0 425opClass=SimdFloatMisc 426opLat=1 427pipelined=true 428 429[system.cpu.fuPool.FUList5.opList17] 430type=OpDesc 431eventq_index=0 432opClass=SimdFloatMult 433opLat=1 434pipelined=true 435 436[system.cpu.fuPool.FUList5.opList18] 437type=OpDesc 438eventq_index=0 439opClass=SimdFloatMultAcc 440opLat=1 441pipelined=true 442 443[system.cpu.fuPool.FUList5.opList19] 444type=OpDesc 445eventq_index=0 446opClass=SimdFloatSqrt 447opLat=1 448pipelined=true 449 450[system.cpu.fuPool.FUList6] 451type=FUDesc 452children=opList 453count=0 454eventq_index=0 455opList=system.cpu.fuPool.FUList6.opList 456 457[system.cpu.fuPool.FUList6.opList] 458type=OpDesc 459eventq_index=0 460opClass=MemWrite 461opLat=1 462pipelined=true 463 464[system.cpu.fuPool.FUList7] 465type=FUDesc 466children=opList0 opList1 467count=4 468eventq_index=0 469opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 470 471[system.cpu.fuPool.FUList7.opList0] 472type=OpDesc 473eventq_index=0 474opClass=MemRead 475opLat=1 476pipelined=true 477 478[system.cpu.fuPool.FUList7.opList1] 479type=OpDesc 480eventq_index=0 481opClass=MemWrite 482opLat=1 483pipelined=true 484 485[system.cpu.fuPool.FUList8] 486type=FUDesc 487children=opList 488count=1 489eventq_index=0 490opList=system.cpu.fuPool.FUList8.opList 491 492[system.cpu.fuPool.FUList8.opList] 493type=OpDesc 494eventq_index=0 495opClass=IprAccess 496opLat=3 497pipelined=false 498 499[system.cpu.icache] 500type=Cache 501children=tags 502addr_ranges=0:18446744073709551615 503assoc=2 504clk_domain=system.cpu_clk_domain 505demand_mshr_reserve=1 506eventq_index=0 507forward_snoops=true 508hit_latency=2 509is_read_only=true 510max_miss_count=0 511mshrs=4 512prefetch_on_access=false 513prefetcher=Null 514response_latency=2 515sequential_access=false 516size=131072 517system=system 518tags=system.cpu.icache.tags 519tgts_per_mshr=20 520write_buffers=8 521cpu_side=system.cpu.icache_port 522mem_side=system.cpu.toL2Bus.slave[0] 523 524[system.cpu.icache.tags] 525type=LRU 526assoc=2 527block_size=64 528clk_domain=system.cpu_clk_domain 529eventq_index=0 530hit_latency=2 531sequential_access=false 532size=131072 533 534[system.cpu.interrupts] 535type=SparcInterrupts 536eventq_index=0 537 538[system.cpu.isa] 539type=SparcISA 540eventq_index=0 541 542[system.cpu.itb] 543type=SparcTLB 544eventq_index=0 545size=64 546 547[system.cpu.l2cache] 548type=Cache 549children=tags 550addr_ranges=0:18446744073709551615 551assoc=8 552clk_domain=system.cpu_clk_domain 553demand_mshr_reserve=1 554eventq_index=0 555forward_snoops=true 556hit_latency=20 557is_read_only=false 558max_miss_count=0 559mshrs=20 560prefetch_on_access=false 561prefetcher=Null 562response_latency=20 563sequential_access=false 564size=2097152 565system=system 566tags=system.cpu.l2cache.tags 567tgts_per_mshr=12 568write_buffers=8 569cpu_side=system.cpu.toL2Bus.master[0] 570mem_side=system.membus.slave[1] 571 572[system.cpu.l2cache.tags] 573type=LRU 574assoc=8 575block_size=64 576clk_domain=system.cpu_clk_domain 577eventq_index=0 578hit_latency=20 579sequential_access=false 580size=2097152 581 582[system.cpu.toL2Bus] 583type=CoherentXBar 584clk_domain=system.cpu_clk_domain 585eventq_index=0 586forward_latency=0 587frontend_latency=1 588response_latency=1 589snoop_filter=Null 590snoop_response_latency=1 591system=system 592use_default_range=false 593width=32 594master=system.cpu.l2cache.cpu_side 595slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 596 597[system.cpu.tracer] 598type=ExeTracer 599eventq_index=0 600 601[system.cpu.workload] 602type=LiveProcess 603cmd=insttest 604cwd= 605drivers= 606egid=100 607env= 608errout=cerr 609euid=100 610eventq_index=0 611executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest 612gid=100 613input=cin 614kvmInSE=false 615max_stack_size=67108864 616output=cout 617pid=100 618ppid=99 619simpoint=0 620system=system 621uid=100 622useArchPT=false 623 624[system.cpu_clk_domain] 625type=SrcClockDomain 626clock=500 627domain_id=-1 628eventq_index=0 629init_perf_level=0 630voltage_domain=system.voltage_domain 631 632[system.dvfs_handler] 633type=DVFSHandler 634domains= 635enable=false 636eventq_index=0 637sys_clk_domain=system.clk_domain 638transition_latency=100000000 639 640[system.membus] 641type=CoherentXBar 642clk_domain=system.clk_domain 643eventq_index=0 644forward_latency=4 645frontend_latency=3 646response_latency=2 647snoop_filter=Null 648snoop_response_latency=4 649system=system 650use_default_range=false 651width=16 652master=system.physmem.port 653slave=system.system_port system.cpu.l2cache.mem_side 654 655[system.physmem] 656type=DRAMCtrl 657IDD0=0.075000 658IDD02=0.000000 659IDD2N=0.050000 660IDD2N2=0.000000 661IDD2P0=0.000000 662IDD2P02=0.000000 663IDD2P1=0.000000 664IDD2P12=0.000000 665IDD3N=0.057000 666IDD3N2=0.000000 667IDD3P0=0.000000 668IDD3P02=0.000000 669IDD3P1=0.000000 670IDD3P12=0.000000 671IDD4R=0.187000 672IDD4R2=0.000000 673IDD4W=0.165000 674IDD4W2=0.000000 675IDD5=0.220000 676IDD52=0.000000 677IDD6=0.000000 678IDD62=0.000000 679VDD=1.500000 680VDD2=0.000000 681activation_limit=4 682addr_mapping=RoRaBaCoCh 683bank_groups_per_rank=0 684banks_per_rank=8 685burst_length=8 686channels=1 687clk_domain=system.clk_domain 688conf_table_reported=true 689device_bus_width=8 690device_rowbuffer_size=1024 691device_size=536870912 692devices_per_rank=8 693dll=true 694eventq_index=0 695in_addr_map=true 696max_accesses_per_row=16 697mem_sched_policy=frfcfs 698min_writes_per_switch=16 699null=false 700page_policy=open_adaptive 701range=0:134217727 702ranks_per_channel=2 703read_buffer_size=32 704static_backend_latency=10000 705static_frontend_latency=10000 706tBURST=5000 707tCCD_L=0 708tCK=1250 709tCL=13750 710tCS=2500 711tRAS=35000 712tRCD=13750 713tREFI=7800000 714tRFC=260000 715tRP=13750 716tRRD=6000 717tRRD_L=0 718tRTP=7500 719tRTW=2500 720tWR=15000 721tWTR=7500 722tXAW=30000 723tXP=0 724tXPDLL=0 725tXS=0 726tXSDLL=0 727write_buffer_size=64 728write_high_thresh_perc=85 729write_low_thresh_perc=50 730port=system.membus.master[0] 731 732[system.voltage_domain] 733type=VoltageDomain 734eventq_index=0 735voltage=1.000000 736 737