config.ini revision 10451
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu] 47type=DerivO3CPU 48children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 49LFSTSize=1024 50LQEntries=32 51LSQCheckLoads=true 52LSQDepCheckShift=4 53SQEntries=32 54SSITSize=1024 55activity=0 56backComSize=5 57branchPred=system.cpu.branchPred 58cachePorts=200 59checker=Null 60clk_domain=system.cpu_clk_domain 61commitToDecodeDelay=1 62commitToFetchDelay=1 63commitToIEWDelay=1 64commitToRenameDelay=1 65commitWidth=8 66cpu_id=0 67decodeToFetchDelay=1 68decodeToRenameDelay=1 69decodeWidth=8 70dispatchWidth=8 71do_checkpoint_insts=true 72do_quiesce=true 73do_statistics_insts=true 74dtb=system.cpu.dtb 75eventq_index=0 76fetchBufferSize=64 77fetchQueueSize=32 78fetchToDecodeDelay=1 79fetchTrapLatency=1 80fetchWidth=8 81forwardComSize=5 82fuPool=system.cpu.fuPool 83function_trace=false 84function_trace_start=0 85iewToCommitDelay=1 86iewToDecodeDelay=1 87iewToFetchDelay=1 88iewToRenameDelay=1 89interrupts=system.cpu.interrupts 90isa=system.cpu.isa 91issueToExecuteDelay=1 92issueWidth=8 93itb=system.cpu.itb 94max_insts_all_threads=0 95max_insts_any_thread=0 96max_loads_all_threads=0 97max_loads_any_thread=0 98needsTSO=false 99numIQEntries=64 100numPhysCCRegs=0 101numPhysFloatRegs=256 102numPhysIntRegs=256 103numROBEntries=192 104numRobs=1 105numThreads=1 106profile=0 107progress_interval=0 108renameToDecodeDelay=1 109renameToFetchDelay=1 110renameToIEWDelay=2 111renameToROBDelay=1 112renameWidth=8 113simpoint_start_insts= 114smtCommitPolicy=RoundRobin 115smtFetchPolicy=SingleThread 116smtIQPolicy=Partitioned 117smtIQThreshold=100 118smtLSQPolicy=Partitioned 119smtLSQThreshold=100 120smtNumFetchingThreads=1 121smtROBPolicy=Partitioned 122smtROBThreshold=100 123socket_id=0 124squashWidth=8 125store_set_clear_period=250000 126switched_out=false 127system=system 128tracer=system.cpu.tracer 129trapLatency=13 130wbWidth=8 131workload=system.cpu.workload 132dcache_port=system.cpu.dcache.cpu_side 133icache_port=system.cpu.icache.cpu_side 134 135[system.cpu.branchPred] 136type=BranchPredictor 137BTBEntries=4096 138BTBTagSize=16 139RASSize=16 140choiceCtrBits=2 141choicePredictorSize=8192 142eventq_index=0 143globalCtrBits=2 144globalPredictorSize=8192 145instShiftAmt=2 146localCtrBits=2 147localHistoryTableSize=2048 148localPredictorSize=2048 149numThreads=1 150predType=tournament 151 152[system.cpu.dcache] 153type=BaseCache 154children=tags 155addr_ranges=0:18446744073709551615 156assoc=2 157clk_domain=system.cpu_clk_domain 158eventq_index=0 159forward_snoops=true 160hit_latency=2 161is_top_level=true 162max_miss_count=0 163mshrs=4 164prefetch_on_access=false 165prefetcher=Null 166response_latency=2 167sequential_access=false 168size=262144 169system=system 170tags=system.cpu.dcache.tags 171tgts_per_mshr=20 172two_queue=false 173write_buffers=8 174cpu_side=system.cpu.dcache_port 175mem_side=system.cpu.toL2Bus.slave[1] 176 177[system.cpu.dcache.tags] 178type=LRU 179assoc=2 180block_size=64 181clk_domain=system.cpu_clk_domain 182eventq_index=0 183hit_latency=2 184sequential_access=false 185size=262144 186 187[system.cpu.dtb] 188type=SparcTLB 189eventq_index=0 190size=64 191 192[system.cpu.fuPool] 193type=FUPool 194children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 195FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 196eventq_index=0 197 198[system.cpu.fuPool.FUList0] 199type=FUDesc 200children=opList 201count=6 202eventq_index=0 203opList=system.cpu.fuPool.FUList0.opList 204 205[system.cpu.fuPool.FUList0.opList] 206type=OpDesc 207eventq_index=0 208issueLat=1 209opClass=IntAlu 210opLat=1 211 212[system.cpu.fuPool.FUList1] 213type=FUDesc 214children=opList0 opList1 215count=2 216eventq_index=0 217opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 218 219[system.cpu.fuPool.FUList1.opList0] 220type=OpDesc 221eventq_index=0 222issueLat=1 223opClass=IntMult 224opLat=3 225 226[system.cpu.fuPool.FUList1.opList1] 227type=OpDesc 228eventq_index=0 229issueLat=19 230opClass=IntDiv 231opLat=20 232 233[system.cpu.fuPool.FUList2] 234type=FUDesc 235children=opList0 opList1 opList2 236count=4 237eventq_index=0 238opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 239 240[system.cpu.fuPool.FUList2.opList0] 241type=OpDesc 242eventq_index=0 243issueLat=1 244opClass=FloatAdd 245opLat=2 246 247[system.cpu.fuPool.FUList2.opList1] 248type=OpDesc 249eventq_index=0 250issueLat=1 251opClass=FloatCmp 252opLat=2 253 254[system.cpu.fuPool.FUList2.opList2] 255type=OpDesc 256eventq_index=0 257issueLat=1 258opClass=FloatCvt 259opLat=2 260 261[system.cpu.fuPool.FUList3] 262type=FUDesc 263children=opList0 opList1 opList2 264count=2 265eventq_index=0 266opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 267 268[system.cpu.fuPool.FUList3.opList0] 269type=OpDesc 270eventq_index=0 271issueLat=1 272opClass=FloatMult 273opLat=4 274 275[system.cpu.fuPool.FUList3.opList1] 276type=OpDesc 277eventq_index=0 278issueLat=12 279opClass=FloatDiv 280opLat=12 281 282[system.cpu.fuPool.FUList3.opList2] 283type=OpDesc 284eventq_index=0 285issueLat=24 286opClass=FloatSqrt 287opLat=24 288 289[system.cpu.fuPool.FUList4] 290type=FUDesc 291children=opList 292count=0 293eventq_index=0 294opList=system.cpu.fuPool.FUList4.opList 295 296[system.cpu.fuPool.FUList4.opList] 297type=OpDesc 298eventq_index=0 299issueLat=1 300opClass=MemRead 301opLat=1 302 303[system.cpu.fuPool.FUList5] 304type=FUDesc 305children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 306count=4 307eventq_index=0 308opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 309 310[system.cpu.fuPool.FUList5.opList00] 311type=OpDesc 312eventq_index=0 313issueLat=1 314opClass=SimdAdd 315opLat=1 316 317[system.cpu.fuPool.FUList5.opList01] 318type=OpDesc 319eventq_index=0 320issueLat=1 321opClass=SimdAddAcc 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList02] 325type=OpDesc 326eventq_index=0 327issueLat=1 328opClass=SimdAlu 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList03] 332type=OpDesc 333eventq_index=0 334issueLat=1 335opClass=SimdCmp 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList04] 339type=OpDesc 340eventq_index=0 341issueLat=1 342opClass=SimdCvt 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList05] 346type=OpDesc 347eventq_index=0 348issueLat=1 349opClass=SimdMisc 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList06] 353type=OpDesc 354eventq_index=0 355issueLat=1 356opClass=SimdMult 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList07] 360type=OpDesc 361eventq_index=0 362issueLat=1 363opClass=SimdMultAcc 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList08] 367type=OpDesc 368eventq_index=0 369issueLat=1 370opClass=SimdShift 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList09] 374type=OpDesc 375eventq_index=0 376issueLat=1 377opClass=SimdShiftAcc 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList10] 381type=OpDesc 382eventq_index=0 383issueLat=1 384opClass=SimdSqrt 385opLat=1 386 387[system.cpu.fuPool.FUList5.opList11] 388type=OpDesc 389eventq_index=0 390issueLat=1 391opClass=SimdFloatAdd 392opLat=1 393 394[system.cpu.fuPool.FUList5.opList12] 395type=OpDesc 396eventq_index=0 397issueLat=1 398opClass=SimdFloatAlu 399opLat=1 400 401[system.cpu.fuPool.FUList5.opList13] 402type=OpDesc 403eventq_index=0 404issueLat=1 405opClass=SimdFloatCmp 406opLat=1 407 408[system.cpu.fuPool.FUList5.opList14] 409type=OpDesc 410eventq_index=0 411issueLat=1 412opClass=SimdFloatCvt 413opLat=1 414 415[system.cpu.fuPool.FUList5.opList15] 416type=OpDesc 417eventq_index=0 418issueLat=1 419opClass=SimdFloatDiv 420opLat=1 421 422[system.cpu.fuPool.FUList5.opList16] 423type=OpDesc 424eventq_index=0 425issueLat=1 426opClass=SimdFloatMisc 427opLat=1 428 429[system.cpu.fuPool.FUList5.opList17] 430type=OpDesc 431eventq_index=0 432issueLat=1 433opClass=SimdFloatMult 434opLat=1 435 436[system.cpu.fuPool.FUList5.opList18] 437type=OpDesc 438eventq_index=0 439issueLat=1 440opClass=SimdFloatMultAcc 441opLat=1 442 443[system.cpu.fuPool.FUList5.opList19] 444type=OpDesc 445eventq_index=0 446issueLat=1 447opClass=SimdFloatSqrt 448opLat=1 449 450[system.cpu.fuPool.FUList6] 451type=FUDesc 452children=opList 453count=0 454eventq_index=0 455opList=system.cpu.fuPool.FUList6.opList 456 457[system.cpu.fuPool.FUList6.opList] 458type=OpDesc 459eventq_index=0 460issueLat=1 461opClass=MemWrite 462opLat=1 463 464[system.cpu.fuPool.FUList7] 465type=FUDesc 466children=opList0 opList1 467count=4 468eventq_index=0 469opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 470 471[system.cpu.fuPool.FUList7.opList0] 472type=OpDesc 473eventq_index=0 474issueLat=1 475opClass=MemRead 476opLat=1 477 478[system.cpu.fuPool.FUList7.opList1] 479type=OpDesc 480eventq_index=0 481issueLat=1 482opClass=MemWrite 483opLat=1 484 485[system.cpu.fuPool.FUList8] 486type=FUDesc 487children=opList 488count=1 489eventq_index=0 490opList=system.cpu.fuPool.FUList8.opList 491 492[system.cpu.fuPool.FUList8.opList] 493type=OpDesc 494eventq_index=0 495issueLat=3 496opClass=IprAccess 497opLat=3 498 499[system.cpu.icache] 500type=BaseCache 501children=tags 502addr_ranges=0:18446744073709551615 503assoc=2 504clk_domain=system.cpu_clk_domain 505eventq_index=0 506forward_snoops=true 507hit_latency=2 508is_top_level=true 509max_miss_count=0 510mshrs=4 511prefetch_on_access=false 512prefetcher=Null 513response_latency=2 514sequential_access=false 515size=131072 516system=system 517tags=system.cpu.icache.tags 518tgts_per_mshr=20 519two_queue=false 520write_buffers=8 521cpu_side=system.cpu.icache_port 522mem_side=system.cpu.toL2Bus.slave[0] 523 524[system.cpu.icache.tags] 525type=LRU 526assoc=2 527block_size=64 528clk_domain=system.cpu_clk_domain 529eventq_index=0 530hit_latency=2 531sequential_access=false 532size=131072 533 534[system.cpu.interrupts] 535type=SparcInterrupts 536eventq_index=0 537 538[system.cpu.isa] 539type=SparcISA 540eventq_index=0 541 542[system.cpu.itb] 543type=SparcTLB 544eventq_index=0 545size=64 546 547[system.cpu.l2cache] 548type=BaseCache 549children=tags 550addr_ranges=0:18446744073709551615 551assoc=8 552clk_domain=system.cpu_clk_domain 553eventq_index=0 554forward_snoops=true 555hit_latency=20 556is_top_level=false 557max_miss_count=0 558mshrs=20 559prefetch_on_access=false 560prefetcher=Null 561response_latency=20 562sequential_access=false 563size=2097152 564system=system 565tags=system.cpu.l2cache.tags 566tgts_per_mshr=12 567two_queue=false 568write_buffers=8 569cpu_side=system.cpu.toL2Bus.master[0] 570mem_side=system.membus.slave[1] 571 572[system.cpu.l2cache.tags] 573type=LRU 574assoc=8 575block_size=64 576clk_domain=system.cpu_clk_domain 577eventq_index=0 578hit_latency=20 579sequential_access=false 580size=2097152 581 582[system.cpu.toL2Bus] 583type=CoherentXBar 584clk_domain=system.cpu_clk_domain 585eventq_index=0 586header_cycles=1 587snoop_filter=Null 588system=system 589use_default_range=false 590width=32 591master=system.cpu.l2cache.cpu_side 592slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 593 594[system.cpu.tracer] 595type=ExeTracer 596eventq_index=0 597 598[system.cpu.workload] 599type=LiveProcess 600cmd=insttest 601cwd= 602egid=100 603env= 604errout=cerr 605euid=100 606eventq_index=0 607executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest 608gid=100 609input=cin 610max_stack_size=67108864 611output=cout 612pid=100 613ppid=99 614simpoint=0 615system=system 616uid=100 617useArchPT=false 618 619[system.cpu_clk_domain] 620type=SrcClockDomain 621clock=500 622domain_id=-1 623eventq_index=0 624init_perf_level=0 625voltage_domain=system.voltage_domain 626 627[system.dvfs_handler] 628type=DVFSHandler 629domains= 630enable=false 631eventq_index=0 632sys_clk_domain=system.clk_domain 633transition_latency=100000000 634 635[system.membus] 636type=CoherentXBar 637clk_domain=system.clk_domain 638eventq_index=0 639header_cycles=1 640snoop_filter=Null 641system=system 642use_default_range=false 643width=8 644master=system.physmem.port 645slave=system.system_port system.cpu.l2cache.mem_side 646 647[system.physmem] 648type=DRAMCtrl 649IDD0=0.075000 650IDD02=0.000000 651IDD2N=0.050000 652IDD2N2=0.000000 653IDD2P0=0.000000 654IDD2P02=0.000000 655IDD2P1=0.000000 656IDD2P12=0.000000 657IDD3N=0.057000 658IDD3N2=0.000000 659IDD3P0=0.000000 660IDD3P02=0.000000 661IDD3P1=0.000000 662IDD3P12=0.000000 663IDD4R=0.187000 664IDD4R2=0.000000 665IDD4W=0.165000 666IDD4W2=0.000000 667IDD5=0.220000 668IDD52=0.000000 669IDD6=0.000000 670IDD62=0.000000 671VDD=1.500000 672VDD2=0.000000 673activation_limit=4 674addr_mapping=RoRaBaChCo 675bank_groups_per_rank=0 676banks_per_rank=8 677burst_length=8 678channels=1 679clk_domain=system.clk_domain 680conf_table_reported=true 681device_bus_width=8 682device_rowbuffer_size=1024 683devices_per_rank=8 684dll=true 685eventq_index=0 686in_addr_map=true 687max_accesses_per_row=16 688mem_sched_policy=frfcfs 689min_writes_per_switch=16 690null=false 691page_policy=open_adaptive 692range=0:134217727 693ranks_per_channel=2 694read_buffer_size=32 695static_backend_latency=10000 696static_frontend_latency=10000 697tBURST=5000 698tCCD_L=0 699tCK=1250 700tCL=13750 701tCS=2500 702tRAS=35000 703tRCD=13750 704tREFI=7800000 705tRFC=260000 706tRP=13750 707tRRD=6000 708tRRD_L=0 709tRTP=7500 710tRTW=2500 711tWR=15000 712tWTR=7500 713tXAW=30000 714tXP=0 715tXPDLL=0 716tXS=0 717tXSDLL=0 718write_buffer_size=64 719write_high_thresh_perc=85 720write_low_thresh_perc=50 721port=system.membus.master[0] 722 723[system.voltage_domain] 724type=VoltageDomain 725eventq_index=0 726voltage=1.000000 727 728