config.ini revision 7524
1[root] 2type=Root 3children=system 4dummy=0 5 6[system] 7type=System 8children=cpu membus physmem 9mem_mode=atomic 10physmem=system.physmem 11 12[system.cpu] 13type=DerivO3CPU 14children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload 15BTBEntries=4096 16BTBTagSize=16 17LFSTSize=1024 18LQEntries=32 19RASSize=16 20SQEntries=32 21SSITSize=1024 22activity=0 23backComSize=5 24cachePorts=200 25checker=Null 26choiceCtrBits=2 27choicePredictorSize=8192 28clock=500 29commitToDecodeDelay=1 30commitToFetchDelay=1 31commitToIEWDelay=1 32commitToRenameDelay=1 33commitWidth=8 34cpu_id=0 35decodeToFetchDelay=1 36decodeToRenameDelay=1 37decodeWidth=8 38defer_registration=false 39dispatchWidth=8 40do_checkpoint_insts=true 41do_statistics_insts=true 42dtb=system.cpu.dtb 43fetchToDecodeDelay=1 44fetchTrapLatency=1 45fetchWidth=8 46forwardComSize=5 47fuPool=system.cpu.fuPool 48function_trace=false 49function_trace_start=0 50globalCtrBits=2 51globalHistoryBits=13 52globalPredictorSize=8192 53iewToCommitDelay=1 54iewToDecodeDelay=1 55iewToFetchDelay=1 56iewToRenameDelay=1 57instShiftAmt=2 58issueToExecuteDelay=1 59issueWidth=8 60itb=system.cpu.itb 61localCtrBits=2 62localHistoryBits=11 63localHistoryTableSize=2048 64localPredictorSize=2048 65max_insts_all_threads=0 66max_insts_any_thread=0 67max_loads_all_threads=0 68max_loads_any_thread=0 69numIQEntries=64 70numPhysFloatRegs=256 71numPhysIntRegs=256 72numROBEntries=192 73numRobs=1 74numThreads=1 75phase=0 76predType=tournament 77progress_interval=0 78renameToDecodeDelay=1 79renameToFetchDelay=1 80renameToIEWDelay=2 81renameToROBDelay=1 82renameWidth=8 83smtCommitPolicy=RoundRobin 84smtFetchPolicy=SingleThread 85smtIQPolicy=Partitioned 86smtIQThreshold=100 87smtLSQPolicy=Partitioned 88smtLSQThreshold=100 89smtNumFetchingThreads=1 90smtROBPolicy=Partitioned 91smtROBThreshold=100 92squashWidth=8 93system=system 94tracer=system.cpu.tracer 95trapLatency=13 96wbDepth=1 97wbWidth=8 98workload=system.cpu.workload 99dcache_port=system.cpu.dcache.cpu_side 100icache_port=system.cpu.icache.cpu_side 101 102[system.cpu.dcache] 103type=BaseCache 104addr_range=0:18446744073709551615 105assoc=2 106block_size=64 107forward_snoops=true 108hash_delay=1 109latency=1000 110max_miss_count=0 111mshrs=10 112num_cpus=1 113prefetch_data_accesses_only=false 114prefetch_degree=1 115prefetch_latency=10000 116prefetch_on_access=false 117prefetch_past_page=false 118prefetch_policy=none 119prefetch_serial_squash=false 120prefetch_use_cpu_id=true 121prefetcher_size=100 122prioritizeRequests=false 123repl=Null 124size=262144 125subblock_size=0 126tgts_per_mshr=20 127trace_addr=0 128two_queue=false 129write_buffers=8 130cpu_side=system.cpu.dcache_port 131mem_side=system.cpu.toL2Bus.port[1] 132 133[system.cpu.dtb] 134type=SparcTLB 135size=64 136 137[system.cpu.fuPool] 138type=FUPool 139children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 140FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 141 142[system.cpu.fuPool.FUList0] 143type=FUDesc 144children=opList 145count=6 146opList=system.cpu.fuPool.FUList0.opList 147 148[system.cpu.fuPool.FUList0.opList] 149type=OpDesc 150issueLat=1 151opClass=IntAlu 152opLat=1 153 154[system.cpu.fuPool.FUList1] 155type=FUDesc 156children=opList0 opList1 157count=2 158opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 159 160[system.cpu.fuPool.FUList1.opList0] 161type=OpDesc 162issueLat=1 163opClass=IntMult 164opLat=3 165 166[system.cpu.fuPool.FUList1.opList1] 167type=OpDesc 168issueLat=19 169opClass=IntDiv 170opLat=20 171 172[system.cpu.fuPool.FUList2] 173type=FUDesc 174children=opList0 opList1 opList2 175count=4 176opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 177 178[system.cpu.fuPool.FUList2.opList0] 179type=OpDesc 180issueLat=1 181opClass=FloatAdd 182opLat=2 183 184[system.cpu.fuPool.FUList2.opList1] 185type=OpDesc 186issueLat=1 187opClass=FloatCmp 188opLat=2 189 190[system.cpu.fuPool.FUList2.opList2] 191type=OpDesc 192issueLat=1 193opClass=FloatCvt 194opLat=2 195 196[system.cpu.fuPool.FUList3] 197type=FUDesc 198children=opList0 opList1 opList2 199count=2 200opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 201 202[system.cpu.fuPool.FUList3.opList0] 203type=OpDesc 204issueLat=1 205opClass=FloatMult 206opLat=4 207 208[system.cpu.fuPool.FUList3.opList1] 209type=OpDesc 210issueLat=12 211opClass=FloatDiv 212opLat=12 213 214[system.cpu.fuPool.FUList3.opList2] 215type=OpDesc 216issueLat=24 217opClass=FloatSqrt 218opLat=24 219 220[system.cpu.fuPool.FUList4] 221type=FUDesc 222children=opList 223count=0 224opList=system.cpu.fuPool.FUList4.opList 225 226[system.cpu.fuPool.FUList4.opList] 227type=OpDesc 228issueLat=1 229opClass=MemRead 230opLat=1 231 232[system.cpu.fuPool.FUList5] 233type=FUDesc 234children=opList 235count=0 236opList=system.cpu.fuPool.FUList5.opList 237 238[system.cpu.fuPool.FUList5.opList] 239type=OpDesc 240issueLat=1 241opClass=MemWrite 242opLat=1 243 244[system.cpu.fuPool.FUList6] 245type=FUDesc 246children=opList0 opList1 247count=4 248opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 249 250[system.cpu.fuPool.FUList6.opList0] 251type=OpDesc 252issueLat=1 253opClass=MemRead 254opLat=1 255 256[system.cpu.fuPool.FUList6.opList1] 257type=OpDesc 258issueLat=1 259opClass=MemWrite 260opLat=1 261 262[system.cpu.fuPool.FUList7] 263type=FUDesc 264children=opList 265count=1 266opList=system.cpu.fuPool.FUList7.opList 267 268[system.cpu.fuPool.FUList7.opList] 269type=OpDesc 270issueLat=3 271opClass=IprAccess 272opLat=3 273 274[system.cpu.icache] 275type=BaseCache 276addr_range=0:18446744073709551615 277assoc=2 278block_size=64 279forward_snoops=true 280hash_delay=1 281latency=1000 282max_miss_count=0 283mshrs=10 284num_cpus=1 285prefetch_data_accesses_only=false 286prefetch_degree=1 287prefetch_latency=10000 288prefetch_on_access=false 289prefetch_past_page=false 290prefetch_policy=none 291prefetch_serial_squash=false 292prefetch_use_cpu_id=true 293prefetcher_size=100 294prioritizeRequests=false 295repl=Null 296size=131072 297subblock_size=0 298tgts_per_mshr=20 299trace_addr=0 300two_queue=false 301write_buffers=8 302cpu_side=system.cpu.icache_port 303mem_side=system.cpu.toL2Bus.port[0] 304 305[system.cpu.itb] 306type=SparcTLB 307size=64 308 309[system.cpu.l2cache] 310type=BaseCache 311addr_range=0:18446744073709551615 312assoc=2 313block_size=64 314forward_snoops=true 315hash_delay=1 316latency=1000 317max_miss_count=0 318mshrs=10 319num_cpus=1 320prefetch_data_accesses_only=false 321prefetch_degree=1 322prefetch_latency=10000 323prefetch_on_access=false 324prefetch_past_page=false 325prefetch_policy=none 326prefetch_serial_squash=false 327prefetch_use_cpu_id=true 328prefetcher_size=100 329prioritizeRequests=false 330repl=Null 331size=2097152 332subblock_size=0 333tgts_per_mshr=5 334trace_addr=0 335two_queue=false 336write_buffers=8 337cpu_side=system.cpu.toL2Bus.port[2] 338mem_side=system.membus.port[1] 339 340[system.cpu.toL2Bus] 341type=Bus 342block_size=64 343bus_id=0 344clock=1000 345header_cycles=1 346use_default_range=false 347width=64 348port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 349 350[system.cpu.tracer] 351type=ExeTracer 352 353[system.cpu.workload] 354type=LiveProcess 355cmd=insttest 356cwd= 357egid=100 358env= 359errout=cerr 360euid=100 361executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest 362gid=100 363input=cin 364max_stack_size=67108864 365output=cout 366pid=100 367ppid=99 368simpoint=0 369system=system 370uid=100 371 372[system.membus] 373type=Bus 374block_size=64 375bus_id=0 376clock=1000 377header_cycles=1 378use_default_range=false 379width=64 380port=system.physmem.port[0] system.cpu.l2cache.mem_side 381 382[system.physmem] 383type=PhysicalMemory 384file= 385latency=30000 386latency_var=0 387null=false 388range=0:134217727 389zero=false 390port=system.membus.port[0] 391 392