config.ini revision 4463
1[root] 2type=Root 3children=system 4dummy=0 5 6[system] 7type=System 8children=cpu membus physmem 9mem_mode=atomic 10physmem=system.physmem 11 12[system.cpu] 13type=DerivO3CPU 14children=dcache fuPool icache l2cache toL2Bus workload 15BTBEntries=4096 16BTBTagSize=16 17LFSTSize=1024 18LQEntries=32 19RASSize=16 20SQEntries=32 21SSITSize=1024 22activity=0 23backComSize=5 24choiceCtrBits=2 25choicePredictorSize=8192 26clock=500 27commitToDecodeDelay=1 28commitToFetchDelay=1 29commitToIEWDelay=1 30commitToRenameDelay=1 31commitWidth=8 32cpu_id=0 33decodeToFetchDelay=1 34decodeToRenameDelay=1 35decodeWidth=8 36defer_registration=false 37dispatchWidth=8 38fetchToDecodeDelay=1 39fetchTrapLatency=1 40fetchWidth=8 41forwardComSize=5 42fuPool=system.cpu.fuPool 43function_trace=false 44function_trace_start=0 45globalCtrBits=2 46globalHistoryBits=13 47globalPredictorSize=8192 48iewToCommitDelay=1 49iewToDecodeDelay=1 50iewToFetchDelay=1 51iewToRenameDelay=1 52instShiftAmt=2 53issueToExecuteDelay=1 54issueWidth=8 55localCtrBits=2 56localHistoryBits=11 57localHistoryTableSize=2048 58localPredictorSize=2048 59max_insts_all_threads=0 60max_insts_any_thread=0 61max_loads_all_threads=0 62max_loads_any_thread=0 63numIQEntries=64 64numPhysFloatRegs=256 65numPhysIntRegs=256 66numROBEntries=192 67numRobs=1 68numThreads=1 69phase=0 70predType=tournament 71progress_interval=0 72renameToDecodeDelay=1 73renameToFetchDelay=1 74renameToIEWDelay=2 75renameToROBDelay=1 76renameWidth=8 77squashWidth=8 78system=system 79trapLatency=13 80wbDepth=1 81wbWidth=8 82workload=system.cpu.workload 83dcache_port=system.cpu.dcache.cpu_side 84icache_port=system.cpu.icache.cpu_side 85 86[system.cpu.dcache] 87type=BaseCache 88adaptive_compression=false 89assoc=2 90block_size=64 91compressed_bus=false 92compression_latency=0 93hash_delay=1 94latency=1000 95lifo=false 96max_miss_count=0 97mshrs=10 98prefetch_access=false 99prefetch_cache_check_push=true 100prefetch_data_accesses_only=false 101prefetch_degree=1 102prefetch_latency=10 103prefetch_miss=false 104prefetch_past_page=false 105prefetch_policy=none 106prefetch_serial_squash=false 107prefetch_use_cpu_id=true 108prefetcher_size=100 109prioritizeRequests=false 110protocol=Null 111repl=Null 112size=262144 113split=false 114split_size=0 115store_compressed=false 116subblock_size=0 117tgts_per_mshr=20 118trace_addr=0 119two_queue=false 120write_buffers=8 121cpu_side=system.cpu.dcache_port 122mem_side=system.cpu.toL2Bus.port[1] 123 124[system.cpu.fuPool] 125type=FUPool 126children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 127FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 128 129[system.cpu.fuPool.FUList0] 130type=FUDesc 131children=opList0 132count=6 133opList=system.cpu.fuPool.FUList0.opList0 134 135[system.cpu.fuPool.FUList0.opList0] 136type=OpDesc 137issueLat=1 138opClass=IntAlu 139opLat=1 140 141[system.cpu.fuPool.FUList1] 142type=FUDesc 143children=opList0 opList1 144count=2 145opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 146 147[system.cpu.fuPool.FUList1.opList0] 148type=OpDesc 149issueLat=1 150opClass=IntMult 151opLat=3 152 153[system.cpu.fuPool.FUList1.opList1] 154type=OpDesc 155issueLat=19 156opClass=IntDiv 157opLat=20 158 159[system.cpu.fuPool.FUList2] 160type=FUDesc 161children=opList0 opList1 opList2 162count=4 163opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 164 165[system.cpu.fuPool.FUList2.opList0] 166type=OpDesc 167issueLat=1 168opClass=FloatAdd 169opLat=2 170 171[system.cpu.fuPool.FUList2.opList1] 172type=OpDesc 173issueLat=1 174opClass=FloatCmp 175opLat=2 176 177[system.cpu.fuPool.FUList2.opList2] 178type=OpDesc 179issueLat=1 180opClass=FloatCvt 181opLat=2 182 183[system.cpu.fuPool.FUList3] 184type=FUDesc 185children=opList0 opList1 opList2 186count=2 187opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 188 189[system.cpu.fuPool.FUList3.opList0] 190type=OpDesc 191issueLat=1 192opClass=FloatMult 193opLat=4 194 195[system.cpu.fuPool.FUList3.opList1] 196type=OpDesc 197issueLat=12 198opClass=FloatDiv 199opLat=12 200 201[system.cpu.fuPool.FUList3.opList2] 202type=OpDesc 203issueLat=24 204opClass=FloatSqrt 205opLat=24 206 207[system.cpu.fuPool.FUList4] 208type=FUDesc 209children=opList0 210count=0 211opList=system.cpu.fuPool.FUList4.opList0 212 213[system.cpu.fuPool.FUList4.opList0] 214type=OpDesc 215issueLat=1 216opClass=MemRead 217opLat=1 218 219[system.cpu.fuPool.FUList5] 220type=FUDesc 221children=opList0 222count=0 223opList=system.cpu.fuPool.FUList5.opList0 224 225[system.cpu.fuPool.FUList5.opList0] 226type=OpDesc 227issueLat=1 228opClass=MemWrite 229opLat=1 230 231[system.cpu.fuPool.FUList6] 232type=FUDesc 233children=opList0 opList1 234count=4 235opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 236 237[system.cpu.fuPool.FUList6.opList0] 238type=OpDesc 239issueLat=1 240opClass=MemRead 241opLat=1 242 243[system.cpu.fuPool.FUList6.opList1] 244type=OpDesc 245issueLat=1 246opClass=MemWrite 247opLat=1 248 249[system.cpu.fuPool.FUList7] 250type=FUDesc 251children=opList0 252count=1 253opList=system.cpu.fuPool.FUList7.opList0 254 255[system.cpu.fuPool.FUList7.opList0] 256type=OpDesc 257issueLat=3 258opClass=IprAccess 259opLat=3 260 261[system.cpu.icache] 262type=BaseCache 263adaptive_compression=false 264assoc=2 265block_size=64 266compressed_bus=false 267compression_latency=0 268hash_delay=1 269latency=1000 270lifo=false 271max_miss_count=0 272mshrs=10 273prefetch_access=false 274prefetch_cache_check_push=true 275prefetch_data_accesses_only=false 276prefetch_degree=1 277prefetch_latency=10 278prefetch_miss=false 279prefetch_past_page=false 280prefetch_policy=none 281prefetch_serial_squash=false 282prefetch_use_cpu_id=true 283prefetcher_size=100 284prioritizeRequests=false 285protocol=Null 286repl=Null 287size=131072 288split=false 289split_size=0 290store_compressed=false 291subblock_size=0 292tgts_per_mshr=20 293trace_addr=0 294two_queue=false 295write_buffers=8 296cpu_side=system.cpu.icache_port 297mem_side=system.cpu.toL2Bus.port[0] 298 299[system.cpu.l2cache] 300type=BaseCache 301adaptive_compression=false 302assoc=2 303block_size=64 304compressed_bus=false 305compression_latency=0 306hash_delay=1 307latency=1000 308lifo=false 309max_miss_count=0 310mshrs=10 311prefetch_access=false 312prefetch_cache_check_push=true 313prefetch_data_accesses_only=false 314prefetch_degree=1 315prefetch_latency=10 316prefetch_miss=false 317prefetch_past_page=false 318prefetch_policy=none 319prefetch_serial_squash=false 320prefetch_use_cpu_id=true 321prefetcher_size=100 322prioritizeRequests=false 323protocol=Null 324repl=Null 325size=2097152 326split=false 327split_size=0 328store_compressed=false 329subblock_size=0 330tgts_per_mshr=5 331trace_addr=0 332two_queue=false 333write_buffers=8 334cpu_side=system.cpu.toL2Bus.port[2] 335mem_side=system.membus.port[1] 336 337[system.cpu.toL2Bus] 338type=Bus 339block_size=64 340bus_id=0 341clock=1000 342responder_set=false 343width=64 344port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 345 346[system.cpu.workload] 347type=LiveProcess 348cmd=insttest 349cwd= 350egid=100 351env= 352euid=100 353executable=tests/test-progs/insttest/bin/sparc/linux/insttest 354gid=100 355input=cin 356output=cout 357pid=100 358ppid=99 359system=system 360uid=100 361 362[system.membus] 363type=Bus 364block_size=64 365bus_id=0 366clock=1000 367responder_set=false 368width=64 369port=system.physmem.port system.cpu.l2cache.mem_side 370 371[system.physmem] 372type=PhysicalMemory 373file= 374latency=1 375range=0:134217727 376zero=false 377port=system.membus.port[0] 378 379