stats.txt revision 11731
111731Sjason@lowepower.com 211731Sjason@lowepower.com---------- Begin Simulation Statistics ---------- 311731Sjason@lowepower.comsim_seconds 0.000210 # Number of seconds simulated 411731Sjason@lowepower.comsim_ticks 209715500 # Number of ticks simulated 511731Sjason@lowepower.comfinal_tick 209715500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611731Sjason@lowepower.comsim_freq 1000000000000 # Frequency of simulated ticks 711731Sjason@lowepower.comhost_inst_rate 42175 # Simulator instruction rate (inst/s) 811731Sjason@lowepower.comhost_op_rate 42174 # Simulator op (including micro ops) rate (op/s) 911731Sjason@lowepower.comhost_tick_rate 78069260 # Simulator tick rate (ticks/s) 1011731Sjason@lowepower.comhost_mem_usage 242960 # Number of bytes of host memory used 1111731Sjason@lowepower.comhost_seconds 2.69 # Real time elapsed on the host 1211731Sjason@lowepower.comsim_insts 113291 # Number of instructions simulated 1311731Sjason@lowepower.comsim_ops 113291 # Number of ops (including micro ops) simulated 1411731Sjason@lowepower.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511731Sjason@lowepower.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611731Sjason@lowepower.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states 1711731Sjason@lowepower.comsystem.physmem.bytes_read::cpu.inst 37952 # Number of bytes read from this memory 1811731Sjason@lowepower.comsystem.physmem.bytes_read::cpu.data 16640 # Number of bytes read from this memory 1911731Sjason@lowepower.comsystem.physmem.bytes_read::total 54592 # Number of bytes read from this memory 2011731Sjason@lowepower.comsystem.physmem.bytes_inst_read::cpu.inst 37952 # Number of instructions bytes read from this memory 2111731Sjason@lowepower.comsystem.physmem.bytes_inst_read::total 37952 # Number of instructions bytes read from this memory 2211731Sjason@lowepower.comsystem.physmem.num_reads::cpu.inst 593 # Number of read requests responded to by this memory 2311731Sjason@lowepower.comsystem.physmem.num_reads::cpu.data 260 # Number of read requests responded to by this memory 2411731Sjason@lowepower.comsystem.physmem.num_reads::total 853 # Number of read requests responded to by this memory 2511731Sjason@lowepower.comsystem.physmem.bw_read::cpu.inst 180968979 # Total read bandwidth from this memory (bytes/s) 2611731Sjason@lowepower.comsystem.physmem.bw_read::cpu.data 79345590 # Total read bandwidth from this memory (bytes/s) 2711731Sjason@lowepower.comsystem.physmem.bw_read::total 260314569 # Total read bandwidth from this memory (bytes/s) 2811731Sjason@lowepower.comsystem.physmem.bw_inst_read::cpu.inst 180968979 # Instruction read bandwidth from this memory (bytes/s) 2911731Sjason@lowepower.comsystem.physmem.bw_inst_read::total 180968979 # Instruction read bandwidth from this memory (bytes/s) 3011731Sjason@lowepower.comsystem.physmem.bw_total::cpu.inst 180968979 # Total bandwidth to/from this memory (bytes/s) 3111731Sjason@lowepower.comsystem.physmem.bw_total::cpu.data 79345590 # Total bandwidth to/from this memory (bytes/s) 3211731Sjason@lowepower.comsystem.physmem.bw_total::total 260314569 # Total bandwidth to/from this memory (bytes/s) 3311731Sjason@lowepower.comsystem.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states 3411731Sjason@lowepower.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 3511731Sjason@lowepower.comsystem.cpu.dtb.read_hits 0 # DTB read hits 3611731Sjason@lowepower.comsystem.cpu.dtb.read_misses 0 # DTB read misses 3711731Sjason@lowepower.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 3811731Sjason@lowepower.comsystem.cpu.dtb.write_hits 0 # DTB write hits 3911731Sjason@lowepower.comsystem.cpu.dtb.write_misses 0 # DTB write misses 4011731Sjason@lowepower.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 4111731Sjason@lowepower.comsystem.cpu.dtb.hits 0 # DTB hits 4211731Sjason@lowepower.comsystem.cpu.dtb.misses 0 # DTB misses 4311731Sjason@lowepower.comsystem.cpu.dtb.accesses 0 # DTB accesses 4411731Sjason@lowepower.comsystem.cpu.itb.read_hits 0 # DTB read hits 4511731Sjason@lowepower.comsystem.cpu.itb.read_misses 0 # DTB read misses 4611731Sjason@lowepower.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 4711731Sjason@lowepower.comsystem.cpu.itb.write_hits 0 # DTB write hits 4811731Sjason@lowepower.comsystem.cpu.itb.write_misses 0 # DTB write misses 4911731Sjason@lowepower.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 5011731Sjason@lowepower.comsystem.cpu.itb.hits 0 # DTB hits 5111731Sjason@lowepower.comsystem.cpu.itb.misses 0 # DTB misses 5211731Sjason@lowepower.comsystem.cpu.itb.accesses 0 # DTB accesses 5311731Sjason@lowepower.comsystem.cpu.workload.num_syscalls 45 # Number of system calls 5411731Sjason@lowepower.comsystem.cpu.pwrStateResidencyTicks::ON 209715500 # Cumulative time (in ticks) in various power states 5511731Sjason@lowepower.comsystem.cpu.numCycles 419431 # number of cpu cycles simulated 5611731Sjason@lowepower.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 5711731Sjason@lowepower.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 5811731Sjason@lowepower.comsystem.cpu.committedInsts 113291 # Number of instructions committed 5911731Sjason@lowepower.comsystem.cpu.committedOps 113291 # Number of ops (including micro ops) committed 6011731Sjason@lowepower.comsystem.cpu.num_int_alu_accesses 113292 # Number of integer alu accesses 6111731Sjason@lowepower.comsystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 6211731Sjason@lowepower.comsystem.cpu.num_func_calls 8529 # number of times a function call or return occured 6311731Sjason@lowepower.comsystem.cpu.num_conditional_control_insts 17391 # number of instructions that are conditional controls 6411731Sjason@lowepower.comsystem.cpu.num_int_insts 113292 # number of integer instructions 6511731Sjason@lowepower.comsystem.cpu.num_fp_insts 0 # number of float instructions 6611731Sjason@lowepower.comsystem.cpu.num_int_register_reads 151096 # number of times the integer registers were read 6711731Sjason@lowepower.comsystem.cpu.num_int_register_writes 76188 # number of times the integer registers were written 6811731Sjason@lowepower.comsystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 6911731Sjason@lowepower.comsystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 7011731Sjason@lowepower.comsystem.cpu.num_mem_refs 43493 # number of memory refs 7111731Sjason@lowepower.comsystem.cpu.num_load_insts 23780 # Number of load instructions 7211731Sjason@lowepower.comsystem.cpu.num_store_insts 19713 # Number of store instructions 7311731Sjason@lowepower.comsystem.cpu.num_idle_cycles 0 # Number of idle cycles 7411731Sjason@lowepower.comsystem.cpu.num_busy_cycles 419431 # Number of busy cycles 7511731Sjason@lowepower.comsystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 7611731Sjason@lowepower.comsystem.cpu.idle_fraction 0 # Percentage of idle cycles 7711731Sjason@lowepower.comsystem.cpu.Branches 25920 # Number of branches fetched 7811731Sjason@lowepower.comsystem.cpu.op_class::No_OpClass 45 0.04% 0.04% # Class of executed instruction 7911731Sjason@lowepower.comsystem.cpu.op_class::IntAlu 69651 61.45% 61.49% # Class of executed instruction 8011731Sjason@lowepower.comsystem.cpu.op_class::IntMult 122 0.11% 61.60% # Class of executed instruction 8111731Sjason@lowepower.comsystem.cpu.op_class::IntDiv 26 0.02% 61.63% # Class of executed instruction 8211731Sjason@lowepower.comsystem.cpu.op_class::FloatAdd 0 0.00% 61.63% # Class of executed instruction 8311731Sjason@lowepower.comsystem.cpu.op_class::FloatCmp 0 0.00% 61.63% # Class of executed instruction 8411731Sjason@lowepower.comsystem.cpu.op_class::FloatCvt 0 0.00% 61.63% # Class of executed instruction 8511731Sjason@lowepower.comsystem.cpu.op_class::FloatMult 0 0.00% 61.63% # Class of executed instruction 8611731Sjason@lowepower.comsystem.cpu.op_class::FloatMultAcc 0 0.00% 61.63% # Class of executed instruction 8711731Sjason@lowepower.comsystem.cpu.op_class::FloatDiv 0 0.00% 61.63% # Class of executed instruction 8811731Sjason@lowepower.comsystem.cpu.op_class::FloatMisc 0 0.00% 61.63% # Class of executed instruction 8911731Sjason@lowepower.comsystem.cpu.op_class::FloatSqrt 0 0.00% 61.63% # Class of executed instruction 9011731Sjason@lowepower.comsystem.cpu.op_class::SimdAdd 0 0.00% 61.63% # Class of executed instruction 9111731Sjason@lowepower.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 61.63% # Class of executed instruction 9211731Sjason@lowepower.comsystem.cpu.op_class::SimdAlu 0 0.00% 61.63% # Class of executed instruction 9311731Sjason@lowepower.comsystem.cpu.op_class::SimdCmp 0 0.00% 61.63% # Class of executed instruction 9411731Sjason@lowepower.comsystem.cpu.op_class::SimdCvt 0 0.00% 61.63% # Class of executed instruction 9511731Sjason@lowepower.comsystem.cpu.op_class::SimdMisc 0 0.00% 61.63% # Class of executed instruction 9611731Sjason@lowepower.comsystem.cpu.op_class::SimdMult 0 0.00% 61.63% # Class of executed instruction 9711731Sjason@lowepower.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 61.63% # Class of executed instruction 9811731Sjason@lowepower.comsystem.cpu.op_class::SimdShift 0 0.00% 61.63% # Class of executed instruction 9911731Sjason@lowepower.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 61.63% # Class of executed instruction 10011731Sjason@lowepower.comsystem.cpu.op_class::SimdSqrt 0 0.00% 61.63% # Class of executed instruction 10111731Sjason@lowepower.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 61.63% # Class of executed instruction 10211731Sjason@lowepower.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 61.63% # Class of executed instruction 10311731Sjason@lowepower.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 61.63% # Class of executed instruction 10411731Sjason@lowepower.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 61.63% # Class of executed instruction 10511731Sjason@lowepower.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 61.63% # Class of executed instruction 10611731Sjason@lowepower.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 61.63% # Class of executed instruction 10711731Sjason@lowepower.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 61.63% # Class of executed instruction 10811731Sjason@lowepower.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.63% # Class of executed instruction 10911731Sjason@lowepower.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 61.63% # Class of executed instruction 11011731Sjason@lowepower.comsystem.cpu.op_class::MemRead 23780 20.98% 82.61% # Class of executed instruction 11111731Sjason@lowepower.comsystem.cpu.op_class::MemWrite 19713 17.39% 100.00% # Class of executed instruction 11211731Sjason@lowepower.comsystem.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 11311731Sjason@lowepower.comsystem.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 11411731Sjason@lowepower.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 11511731Sjason@lowepower.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 11611731Sjason@lowepower.comsystem.cpu.op_class::total 113337 # Class of executed instruction 11711731Sjason@lowepower.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states 11811731Sjason@lowepower.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 11911731Sjason@lowepower.comsystem.cpu.dcache.tags.tagsinuse 215.473039 # Cycle average of tags in use 12011731Sjason@lowepower.comsystem.cpu.dcache.tags.total_refs 43232 # Total number of references to valid blocks. 12111731Sjason@lowepower.comsystem.cpu.dcache.tags.sampled_refs 260 # Sample count of references to valid blocks. 12211731Sjason@lowepower.comsystem.cpu.dcache.tags.avg_refs 166.276923 # Average number of references to valid blocks. 12311731Sjason@lowepower.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 12411731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 215.473039 # Average occupied blocks per requestor 12511731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.052606 # Average percentage of cache occupancy 12611731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_percent::total 0.052606 # Average percentage of cache occupancy 12711731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 260 # Occupied blocks per task id 12811731Sjason@lowepower.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 12911731Sjason@lowepower.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id 13011731Sjason@lowepower.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id 13111731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.063477 # Percentage of cache occupancy per task id 13211731Sjason@lowepower.comsystem.cpu.dcache.tags.tag_accesses 87244 # Number of tag accesses 13311731Sjason@lowepower.comsystem.cpu.dcache.tags.data_accesses 87244 # Number of data accesses 13411731Sjason@lowepower.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states 13511731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_hits::cpu.data 23719 # number of ReadReq hits 13611731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_hits::total 23719 # number of ReadReq hits 13711731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_hits::cpu.data 19513 # number of WriteReq hits 13811731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_hits::total 19513 # number of WriteReq hits 13911731Sjason@lowepower.comsystem.cpu.dcache.demand_hits::cpu.data 43232 # number of demand (read+write) hits 14011731Sjason@lowepower.comsystem.cpu.dcache.demand_hits::total 43232 # number of demand (read+write) hits 14111731Sjason@lowepower.comsystem.cpu.dcache.overall_hits::cpu.data 43232 # number of overall hits 14211731Sjason@lowepower.comsystem.cpu.dcache.overall_hits::total 43232 # number of overall hits 14311731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses 14411731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses 14511731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_misses::cpu.data 199 # number of WriteReq misses 14611731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_misses::total 199 # number of WriteReq misses 14711731Sjason@lowepower.comsystem.cpu.dcache.demand_misses::cpu.data 260 # number of demand (read+write) misses 14811731Sjason@lowepower.comsystem.cpu.dcache.demand_misses::total 260 # number of demand (read+write) misses 14911731Sjason@lowepower.comsystem.cpu.dcache.overall_misses::cpu.data 260 # number of overall misses 15011731Sjason@lowepower.comsystem.cpu.dcache.overall_misses::total 260 # number of overall misses 15111731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 3843000 # number of ReadReq miss cycles 15211731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_latency::total 3843000 # number of ReadReq miss cycles 15311731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 12537000 # number of WriteReq miss cycles 15411731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_latency::total 12537000 # number of WriteReq miss cycles 15511731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_latency::cpu.data 16380000 # number of demand (read+write) miss cycles 15611731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_latency::total 16380000 # number of demand (read+write) miss cycles 15711731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_latency::cpu.data 16380000 # number of overall miss cycles 15811731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_latency::total 16380000 # number of overall miss cycles 15911731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 23780 # number of ReadReq accesses(hits+misses) 16011731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_accesses::total 23780 # number of ReadReq accesses(hits+misses) 16111731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses) 16211731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses) 16311731Sjason@lowepower.comsystem.cpu.dcache.demand_accesses::cpu.data 43492 # number of demand (read+write) accesses 16411731Sjason@lowepower.comsystem.cpu.dcache.demand_accesses::total 43492 # number of demand (read+write) accesses 16511731Sjason@lowepower.comsystem.cpu.dcache.overall_accesses::cpu.data 43492 # number of overall (read+write) accesses 16611731Sjason@lowepower.comsystem.cpu.dcache.overall_accesses::total 43492 # number of overall (read+write) accesses 16711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002565 # miss rate for ReadReq accesses 16811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.002565 # miss rate for ReadReq accesses 16911731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010095 # miss rate for WriteReq accesses 17011731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.010095 # miss rate for WriteReq accesses 17111731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.005978 # miss rate for demand accesses 17211731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_rate::total 0.005978 # miss rate for demand accesses 17311731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.005978 # miss rate for overall accesses 17411731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_rate::total 0.005978 # miss rate for overall accesses 17511731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency 17611731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency 17711731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency 17811731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency 17911731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency 18011731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency 18111731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency 18211731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency 18311731Sjason@lowepower.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 18411731Sjason@lowepower.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 18511731Sjason@lowepower.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 18611731Sjason@lowepower.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 18711731Sjason@lowepower.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 18811731Sjason@lowepower.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 18911731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses 19011731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses 19111731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 199 # number of WriteReq MSHR misses 19211731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_misses::total 199 # number of WriteReq MSHR misses 19311731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 260 # number of demand (read+write) MSHR misses 19411731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses 19511731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 260 # number of overall MSHR misses 19611731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses 19711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3782000 # number of ReadReq MSHR miss cycles 19811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 3782000 # number of ReadReq MSHR miss cycles 19911731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12338000 # number of WriteReq MSHR miss cycles 20011731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 12338000 # number of WriteReq MSHR miss cycles 20111731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 16120000 # number of demand (read+write) MSHR miss cycles 20211731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_latency::total 16120000 # number of demand (read+write) MSHR miss cycles 20311731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 16120000 # number of overall MSHR miss cycles 20411731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_latency::total 16120000 # number of overall MSHR miss cycles 20511731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002565 # mshr miss rate for ReadReq accesses 20611731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002565 # mshr miss rate for ReadReq accesses 20711731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010095 # mshr miss rate for WriteReq accesses 20811731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010095 # mshr miss rate for WriteReq accesses 20911731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005978 # mshr miss rate for demand accesses 21011731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.005978 # mshr miss rate for demand accesses 21111731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005978 # mshr miss rate for overall accesses 21211731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.005978 # mshr miss rate for overall accesses 21311731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency 21411731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency 21511731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency 21611731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency 21711731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency 21811731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency 21911731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency 22011731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency 22111731Sjason@lowepower.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states 22211731Sjason@lowepower.comsystem.cpu.icache.tags.replacements 6 # number of replacements 22311731Sjason@lowepower.comsystem.cpu.icache.tags.tagsinuse 302.746737 # Cycle average of tags in use 22411731Sjason@lowepower.comsystem.cpu.icache.tags.total_refs 112745 # Total number of references to valid blocks. 22511731Sjason@lowepower.comsystem.cpu.icache.tags.sampled_refs 593 # Sample count of references to valid blocks. 22611731Sjason@lowepower.comsystem.cpu.icache.tags.avg_refs 190.126476 # Average number of references to valid blocks. 22711731Sjason@lowepower.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 22811731Sjason@lowepower.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 302.746737 # Average occupied blocks per requestor 22911731Sjason@lowepower.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.147826 # Average percentage of cache occupancy 23011731Sjason@lowepower.comsystem.cpu.icache.tags.occ_percent::total 0.147826 # Average percentage of cache occupancy 23111731Sjason@lowepower.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 587 # Occupied blocks per task id 23211731Sjason@lowepower.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 23311731Sjason@lowepower.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id 23411731Sjason@lowepower.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id 23511731Sjason@lowepower.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.286621 # Percentage of cache occupancy per task id 23611731Sjason@lowepower.comsystem.cpu.icache.tags.tag_accesses 227269 # Number of tag accesses 23711731Sjason@lowepower.comsystem.cpu.icache.tags.data_accesses 227269 # Number of data accesses 23811731Sjason@lowepower.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states 23911731Sjason@lowepower.comsystem.cpu.icache.ReadReq_hits::cpu.inst 112745 # number of ReadReq hits 24011731Sjason@lowepower.comsystem.cpu.icache.ReadReq_hits::total 112745 # number of ReadReq hits 24111731Sjason@lowepower.comsystem.cpu.icache.demand_hits::cpu.inst 112745 # number of demand (read+write) hits 24211731Sjason@lowepower.comsystem.cpu.icache.demand_hits::total 112745 # number of demand (read+write) hits 24311731Sjason@lowepower.comsystem.cpu.icache.overall_hits::cpu.inst 112745 # number of overall hits 24411731Sjason@lowepower.comsystem.cpu.icache.overall_hits::total 112745 # number of overall hits 24511731Sjason@lowepower.comsystem.cpu.icache.ReadReq_misses::cpu.inst 593 # number of ReadReq misses 24611731Sjason@lowepower.comsystem.cpu.icache.ReadReq_misses::total 593 # number of ReadReq misses 24711731Sjason@lowepower.comsystem.cpu.icache.demand_misses::cpu.inst 593 # number of demand (read+write) misses 24811731Sjason@lowepower.comsystem.cpu.icache.demand_misses::total 593 # number of demand (read+write) misses 24911731Sjason@lowepower.comsystem.cpu.icache.overall_misses::cpu.inst 593 # number of overall misses 25011731Sjason@lowepower.comsystem.cpu.icache.overall_misses::total 593 # number of overall misses 25111731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 37359500 # number of ReadReq miss cycles 25211731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_latency::total 37359500 # number of ReadReq miss cycles 25311731Sjason@lowepower.comsystem.cpu.icache.demand_miss_latency::cpu.inst 37359500 # number of demand (read+write) miss cycles 25411731Sjason@lowepower.comsystem.cpu.icache.demand_miss_latency::total 37359500 # number of demand (read+write) miss cycles 25511731Sjason@lowepower.comsystem.cpu.icache.overall_miss_latency::cpu.inst 37359500 # number of overall miss cycles 25611731Sjason@lowepower.comsystem.cpu.icache.overall_miss_latency::total 37359500 # number of overall miss cycles 25711731Sjason@lowepower.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 113338 # number of ReadReq accesses(hits+misses) 25811731Sjason@lowepower.comsystem.cpu.icache.ReadReq_accesses::total 113338 # number of ReadReq accesses(hits+misses) 25911731Sjason@lowepower.comsystem.cpu.icache.demand_accesses::cpu.inst 113338 # number of demand (read+write) accesses 26011731Sjason@lowepower.comsystem.cpu.icache.demand_accesses::total 113338 # number of demand (read+write) accesses 26111731Sjason@lowepower.comsystem.cpu.icache.overall_accesses::cpu.inst 113338 # number of overall (read+write) accesses 26211731Sjason@lowepower.comsystem.cpu.icache.overall_accesses::total 113338 # number of overall (read+write) accesses 26311731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005232 # miss rate for ReadReq accesses 26411731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_rate::total 0.005232 # miss rate for ReadReq accesses 26511731Sjason@lowepower.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.005232 # miss rate for demand accesses 26611731Sjason@lowepower.comsystem.cpu.icache.demand_miss_rate::total 0.005232 # miss rate for demand accesses 26711731Sjason@lowepower.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.005232 # miss rate for overall accesses 26811731Sjason@lowepower.comsystem.cpu.icache.overall_miss_rate::total 0.005232 # miss rate for overall accesses 26911731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63000.843170 # average ReadReq miss latency 27011731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 63000.843170 # average ReadReq miss latency 27111731Sjason@lowepower.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 63000.843170 # average overall miss latency 27211731Sjason@lowepower.comsystem.cpu.icache.demand_avg_miss_latency::total 63000.843170 # average overall miss latency 27311731Sjason@lowepower.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 63000.843170 # average overall miss latency 27411731Sjason@lowepower.comsystem.cpu.icache.overall_avg_miss_latency::total 63000.843170 # average overall miss latency 27511731Sjason@lowepower.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 27611731Sjason@lowepower.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 27711731Sjason@lowepower.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 27811731Sjason@lowepower.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 27911731Sjason@lowepower.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 28011731Sjason@lowepower.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 28111731Sjason@lowepower.comsystem.cpu.icache.writebacks::writebacks 6 # number of writebacks 28211731Sjason@lowepower.comsystem.cpu.icache.writebacks::total 6 # number of writebacks 28311731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 593 # number of ReadReq MSHR misses 28411731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_misses::total 593 # number of ReadReq MSHR misses 28511731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 593 # number of demand (read+write) MSHR misses 28611731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_misses::total 593 # number of demand (read+write) MSHR misses 28711731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 593 # number of overall MSHR misses 28811731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_misses::total 593 # number of overall MSHR misses 28911731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36766500 # number of ReadReq MSHR miss cycles 29011731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 36766500 # number of ReadReq MSHR miss cycles 29111731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 36766500 # number of demand (read+write) MSHR miss cycles 29211731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_latency::total 36766500 # number of demand (read+write) MSHR miss cycles 29311731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 36766500 # number of overall MSHR miss cycles 29411731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_latency::total 36766500 # number of overall MSHR miss cycles 29511731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005232 # mshr miss rate for ReadReq accesses 29611731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.005232 # mshr miss rate for ReadReq accesses 29711731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005232 # mshr miss rate for demand accesses 29811731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.005232 # mshr miss rate for demand accesses 29911731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005232 # mshr miss rate for overall accesses 30011731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.005232 # mshr miss rate for overall accesses 30111731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62000.843170 # average ReadReq mshr miss latency 30211731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62000.843170 # average ReadReq mshr miss latency 30311731Sjason@lowepower.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62000.843170 # average overall mshr miss latency 30411731Sjason@lowepower.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 62000.843170 # average overall mshr miss latency 30511731Sjason@lowepower.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62000.843170 # average overall mshr miss latency 30611731Sjason@lowepower.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 62000.843170 # average overall mshr miss latency 30711731Sjason@lowepower.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states 30811731Sjason@lowepower.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 30911731Sjason@lowepower.comsystem.cpu.l2cache.tags.tagsinuse 520.331439 # Cycle average of tags in use 31011731Sjason@lowepower.comsystem.cpu.l2cache.tags.total_refs 6 # Total number of references to valid blocks. 31111731Sjason@lowepower.comsystem.cpu.l2cache.tags.sampled_refs 853 # Sample count of references to valid blocks. 31211731Sjason@lowepower.comsystem.cpu.l2cache.tags.avg_refs 0.007034 # Average number of references to valid blocks. 31311731Sjason@lowepower.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 31411731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 304.845382 # Average occupied blocks per requestor 31511731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 215.486056 # Average occupied blocks per requestor 31611731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.009303 # Average percentage of cache occupancy 31711731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.006576 # Average percentage of cache occupancy 31811731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::total 0.015879 # Average percentage of cache occupancy 31911731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 853 # Occupied blocks per task id 32011731Sjason@lowepower.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 32111731Sjason@lowepower.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 32211731Sjason@lowepower.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 552 # Occupied blocks per task id 32311731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.026031 # Percentage of cache occupancy per task id 32411731Sjason@lowepower.comsystem.cpu.l2cache.tags.tag_accesses 7725 # Number of tag accesses 32511731Sjason@lowepower.comsystem.cpu.l2cache.tags.data_accesses 7725 # Number of data accesses 32611731Sjason@lowepower.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states 32711731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 6 # number of WritebackClean hits 32811731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_hits::total 6 # number of WritebackClean hits 32911731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 199 # number of ReadExReq misses 33011731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_misses::total 199 # number of ReadExReq misses 33111731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 593 # number of ReadCleanReq misses 33211731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_misses::total 593 # number of ReadCleanReq misses 33311731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 61 # number of ReadSharedReq misses 33411731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_misses::total 61 # number of ReadSharedReq misses 33511731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::cpu.inst 593 # number of demand (read+write) misses 33611731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::cpu.data 260 # number of demand (read+write) misses 33711731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::total 853 # number of demand (read+write) misses 33811731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::cpu.inst 593 # number of overall misses 33911731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::cpu.data 260 # number of overall misses 34011731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::total 853 # number of overall misses 34111731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12039500 # number of ReadExReq miss cycles 34211731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 12039500 # number of ReadExReq miss cycles 34311731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 35877000 # number of ReadCleanReq miss cycles 34411731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 35877000 # number of ReadCleanReq miss cycles 34511731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3690500 # number of ReadSharedReq miss cycles 34611731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 3690500 # number of ReadSharedReq miss cycles 34711731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 35877000 # number of demand (read+write) miss cycles 34811731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 15730000 # number of demand (read+write) miss cycles 34911731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::total 51607000 # number of demand (read+write) miss cycles 35011731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 35877000 # number of overall miss cycles 35111731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 15730000 # number of overall miss cycles 35211731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::total 51607000 # number of overall miss cycles 35311731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 6 # number of WritebackClean accesses(hits+misses) 35411731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_accesses::total 6 # number of WritebackClean accesses(hits+misses) 35511731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 199 # number of ReadExReq accesses(hits+misses) 35611731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_accesses::total 199 # number of ReadExReq accesses(hits+misses) 35711731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 593 # number of ReadCleanReq accesses(hits+misses) 35811731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 593 # number of ReadCleanReq accesses(hits+misses) 35911731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61 # number of ReadSharedReq accesses(hits+misses) 36011731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 61 # number of ReadSharedReq accesses(hits+misses) 36111731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::cpu.inst 593 # number of demand (read+write) accesses 36211731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::cpu.data 260 # number of demand (read+write) accesses 36311731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::total 853 # number of demand (read+write) accesses 36411731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::cpu.inst 593 # number of overall (read+write) accesses 36511731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::cpu.data 260 # number of overall (read+write) accesses 36611731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::total 853 # number of overall (read+write) accesses 36711731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 36811731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 36911731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses 37011731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses 37111731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 37211731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 37311731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 37411731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 37511731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses 37611731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 37711731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 37811731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses 37911731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency 38011731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency 38111731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.843170 # average ReadCleanReq miss latency 38211731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.843170 # average ReadCleanReq miss latency 38311731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency 38411731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency 38511731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.843170 # average overall miss latency 38611731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency 38711731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::total 60500.586166 # average overall miss latency 38811731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.843170 # average overall miss latency 38911731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency 39011731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::total 60500.586166 # average overall miss latency 39111731Sjason@lowepower.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 39211731Sjason@lowepower.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 39311731Sjason@lowepower.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 39411731Sjason@lowepower.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 39511731Sjason@lowepower.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39611731Sjason@lowepower.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39711731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 199 # number of ReadExReq MSHR misses 39811731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 199 # number of ReadExReq MSHR misses 39911731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 593 # number of ReadCleanReq MSHR misses 40011731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 593 # number of ReadCleanReq MSHR misses 40111731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 61 # number of ReadSharedReq MSHR misses 40211731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 61 # number of ReadSharedReq MSHR misses 40311731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 593 # number of demand (read+write) MSHR misses 40411731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 260 # number of demand (read+write) MSHR misses 40511731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::total 853 # number of demand (read+write) MSHR misses 40611731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 593 # number of overall MSHR misses 40711731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 260 # number of overall MSHR misses 40811731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::total 853 # number of overall MSHR misses 40911731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10049500 # number of ReadExReq MSHR miss cycles 41011731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10049500 # number of ReadExReq MSHR miss cycles 41111731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 29947000 # number of ReadCleanReq MSHR miss cycles 41211731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 29947000 # number of ReadCleanReq MSHR miss cycles 41311731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3080500 # number of ReadSharedReq MSHR miss cycles 41411731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3080500 # number of ReadSharedReq MSHR miss cycles 41511731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29947000 # number of demand (read+write) MSHR miss cycles 41611731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13130000 # number of demand (read+write) MSHR miss cycles 41711731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 43077000 # number of demand (read+write) MSHR miss cycles 41811731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29947000 # number of overall MSHR miss cycles 41911731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13130000 # number of overall MSHR miss cycles 42011731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 43077000 # number of overall MSHR miss cycles 42111731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 42211731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 42311731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses 42411731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses 42511731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 42611731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 42711731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 42811731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 42911731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 43011731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 43111731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 43211731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 43311731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency 43411731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency 43511731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.843170 # average ReadCleanReq mshr miss latency 43611731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.843170 # average ReadCleanReq mshr miss latency 43711731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency 43811731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency 43911731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.843170 # average overall mshr miss latency 44011731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 44111731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.586166 # average overall mshr miss latency 44211731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.843170 # average overall mshr miss latency 44311731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 44411731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.586166 # average overall mshr miss latency 44511731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 859 # Total number of requests made to the snoop filter. 44611731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 6 # Number of requests hitting in the snoop filter with a single holder of the requested data. 44711731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 44811731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 44911731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 45011731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 45111731Sjason@lowepower.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states 45211731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadResp 654 # Transaction distribution 45311731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 6 # Transaction distribution 45411731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution 45511731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 199 # Transaction distribution 45611731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 593 # Transaction distribution 45711731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 61 # Transaction distribution 45811731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1192 # Packet count per connected master and slave (bytes) 45911731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 520 # Packet count per connected master and slave (bytes) 46011731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count::total 1712 # Packet count per connected master and slave (bytes) 46111731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes) 46211731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16640 # Cumulative packet size per connected master and slave (bytes) 46311731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size::total 54976 # Cumulative packet size per connected master and slave (bytes) 46411731Sjason@lowepower.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 46511731Sjason@lowepower.comsystem.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 46611731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::samples 853 # Request fanout histogram 46711731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram 46811731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 46911731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 47011731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::0 853 100.00% 100.00% # Request fanout histogram 47111731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 47211731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 47311731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 47411731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 47511731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram 47611731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::total 853 # Request fanout histogram 47711731Sjason@lowepower.comsystem.cpu.toL2Bus.reqLayer0.occupancy 435500 # Layer occupancy (ticks) 47811731Sjason@lowepower.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 47911731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer0.occupancy 889500 # Layer occupancy (ticks) 48011731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) 48111731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer1.occupancy 390000 # Layer occupancy (ticks) 48211731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 48311731Sjason@lowepower.comsystem.membus.snoop_filter.tot_requests 853 # Total number of requests made to the snoop filter. 48411731Sjason@lowepower.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 48511731Sjason@lowepower.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 48611731Sjason@lowepower.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 48711731Sjason@lowepower.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 48811731Sjason@lowepower.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 48911731Sjason@lowepower.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states 49011731Sjason@lowepower.comsystem.membus.trans_dist::ReadResp 654 # Transaction distribution 49111731Sjason@lowepower.comsystem.membus.trans_dist::ReadExReq 199 # Transaction distribution 49211731Sjason@lowepower.comsystem.membus.trans_dist::ReadExResp 199 # Transaction distribution 49311731Sjason@lowepower.comsystem.membus.trans_dist::ReadSharedReq 654 # Transaction distribution 49411731Sjason@lowepower.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1706 # Packet count per connected master and slave (bytes) 49511731Sjason@lowepower.comsystem.membus.pkt_count::total 1706 # Packet count per connected master and slave (bytes) 49611731Sjason@lowepower.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54592 # Cumulative packet size per connected master and slave (bytes) 49711731Sjason@lowepower.comsystem.membus.pkt_size::total 54592 # Cumulative packet size per connected master and slave (bytes) 49811731Sjason@lowepower.comsystem.membus.snoops 0 # Total snoops (count) 49911731Sjason@lowepower.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 50011731Sjason@lowepower.comsystem.membus.snoop_fanout::samples 853 # Request fanout histogram 50111731Sjason@lowepower.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 50211731Sjason@lowepower.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 50311731Sjason@lowepower.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 50411731Sjason@lowepower.comsystem.membus.snoop_fanout::0 853 100.00% 100.00% # Request fanout histogram 50511731Sjason@lowepower.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 50611731Sjason@lowepower.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 50711731Sjason@lowepower.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 50811731Sjason@lowepower.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 50911731Sjason@lowepower.comsystem.membus.snoop_fanout::total 853 # Request fanout histogram 51011731Sjason@lowepower.comsystem.membus.reqLayer0.occupancy 853500 # Layer occupancy (ticks) 51111731Sjason@lowepower.comsystem.membus.reqLayer0.utilization 0.4 # Layer utilization (%) 51211731Sjason@lowepower.comsystem.membus.respLayer1.occupancy 4265000 # Layer occupancy (ticks) 51311731Sjason@lowepower.comsystem.membus.respLayer1.utilization 2.0 # Layer utilization (%) 51411731Sjason@lowepower.com 51511731Sjason@lowepower.com---------- End Simulation Statistics ---------- 516