simout revision 11731:c473ca7cc650 
1Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic/simout
2Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic/simerr
3gem5 Simulator System.  http://gem5.org
4gem5 is copyrighted software; use the --copyright option for details.
5
6gem5 compiled Nov 30 2016 14:33:35
7gem5 started Nov 30 2016 16:18:49
8gem5 executing on zizzer, pid 34098
9command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-atomic
10
11Global frequency set at 1000000000000 ticks per second
12info: Entering event queue @ 0.  Starting simulation...
13info: Increasing stack size by one page.
14mul: PASS
15mul, overflow: PASS
16mulh: PASS
17mulh, negative: PASS
18mulh, all bits set: PASS
19mulhsu, all bits set: PASS
20mulhsu: PASS
21mulhu: PASS
22mulhu, all bits set: PASS
23div: PASS
24div/0: PASS
25div, overflow: PASS
26divu: PASS
27divu/0: PASS
28divu, "overflow": PASS
29rem: PASS
30rem/0: PASS
31rem, overflow: PASS
32remu: PASS
33remu/0: PASS
34remu, "overflow": PASS
35mulw, truncate: PASS
36mulw, overflow: PASS
37divw, truncate: PASS
38divw/0: PASS
39divw, overflow: PASS
40divuw, truncate: PASS
41divuw/0: PASS
42divuw, "overflow": PASS
43divuw, sign extend: PASS
44remw, truncate: PASS
45remw/0: PASS
46remw, overflow: PASS
47remuw, truncate: PASS
48remuw/0: PASS
49remuw, "overflow": PASS
50remuw, sign extend: PASS
51Exiting @ tick 56668000 because target called exit()
52