stats.txt revision 11731
111731Sjason@lowepower.com 211731Sjason@lowepower.com---------- Begin Simulation Statistics ---------- 311731Sjason@lowepower.comsim_seconds 0.000067 # Number of seconds simulated 411731Sjason@lowepower.comsim_ticks 66726000 # Number of ticks simulated 511731Sjason@lowepower.comfinal_tick 66726000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611731Sjason@lowepower.comsim_freq 1000000000000 # Frequency of simulated ticks 711731Sjason@lowepower.comhost_inst_rate 30660 # Simulator instruction rate (inst/s) 811731Sjason@lowepower.comhost_op_rate 30660 # Simulator op (including micro ops) rate (op/s) 911731Sjason@lowepower.comhost_tick_rate 18058105 # Simulator tick rate (ticks/s) 1011731Sjason@lowepower.comhost_mem_usage 245440 # Number of bytes of host memory used 1111731Sjason@lowepower.comhost_seconds 3.70 # Real time elapsed on the host 1211731Sjason@lowepower.comsim_insts 113291 # Number of instructions simulated 1311731Sjason@lowepower.comsim_ops 113291 # Number of ops (including micro ops) simulated 1411731Sjason@lowepower.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511731Sjason@lowepower.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611731Sjason@lowepower.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states 1711731Sjason@lowepower.comsystem.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory 1811731Sjason@lowepower.comsystem.physmem.bytes_read::cpu.data 16960 # Number of bytes read from this memory 1911731Sjason@lowepower.comsystem.physmem.bytes_read::total 66432 # Number of bytes read from this memory 2011731Sjason@lowepower.comsystem.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory 2111731Sjason@lowepower.comsystem.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory 2211731Sjason@lowepower.comsystem.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory 2311731Sjason@lowepower.comsystem.physmem.num_reads::cpu.data 265 # Number of read requests responded to by this memory 2411731Sjason@lowepower.comsystem.physmem.num_reads::total 1038 # Number of read requests responded to by this memory 2511731Sjason@lowepower.comsystem.physmem.bw_read::cpu.inst 741420136 # Total read bandwidth from this memory (bytes/s) 2611731Sjason@lowepower.comsystem.physmem.bw_read::cpu.data 254173785 # Total read bandwidth from this memory (bytes/s) 2711731Sjason@lowepower.comsystem.physmem.bw_read::total 995593921 # Total read bandwidth from this memory (bytes/s) 2811731Sjason@lowepower.comsystem.physmem.bw_inst_read::cpu.inst 741420136 # Instruction read bandwidth from this memory (bytes/s) 2911731Sjason@lowepower.comsystem.physmem.bw_inst_read::total 741420136 # Instruction read bandwidth from this memory (bytes/s) 3011731Sjason@lowepower.comsystem.physmem.bw_total::cpu.inst 741420136 # Total bandwidth to/from this memory (bytes/s) 3111731Sjason@lowepower.comsystem.physmem.bw_total::cpu.data 254173785 # Total bandwidth to/from this memory (bytes/s) 3211731Sjason@lowepower.comsystem.physmem.bw_total::total 995593921 # Total bandwidth to/from this memory (bytes/s) 3311731Sjason@lowepower.comsystem.physmem.readReqs 1039 # Number of read requests accepted 3411731Sjason@lowepower.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511731Sjason@lowepower.comsystem.physmem.readBursts 1039 # Number of DRAM read bursts, including those serviced by the write queue 3611731Sjason@lowepower.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711731Sjason@lowepower.comsystem.physmem.bytesReadDRAM 66496 # Total number of bytes read from DRAM 3811731Sjason@lowepower.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 3911731Sjason@lowepower.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011731Sjason@lowepower.comsystem.physmem.bytesReadSys 66496 # Total read bytes from the system interface side 4111731Sjason@lowepower.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 4211731Sjason@lowepower.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 4311731Sjason@lowepower.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 4411731Sjason@lowepower.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4511731Sjason@lowepower.comsystem.physmem.perBankRdBursts::0 89 # Per bank write bursts 4611731Sjason@lowepower.comsystem.physmem.perBankRdBursts::1 8 # Per bank write bursts 4711731Sjason@lowepower.comsystem.physmem.perBankRdBursts::2 16 # Per bank write bursts 4811731Sjason@lowepower.comsystem.physmem.perBankRdBursts::3 108 # Per bank write bursts 4911731Sjason@lowepower.comsystem.physmem.perBankRdBursts::4 64 # Per bank write bursts 5011731Sjason@lowepower.comsystem.physmem.perBankRdBursts::5 91 # Per bank write bursts 5111731Sjason@lowepower.comsystem.physmem.perBankRdBursts::6 61 # Per bank write bursts 5211731Sjason@lowepower.comsystem.physmem.perBankRdBursts::7 30 # Per bank write bursts 5311731Sjason@lowepower.comsystem.physmem.perBankRdBursts::8 56 # Per bank write bursts 5411731Sjason@lowepower.comsystem.physmem.perBankRdBursts::9 76 # Per bank write bursts 5511731Sjason@lowepower.comsystem.physmem.perBankRdBursts::10 79 # Per bank write bursts 5611731Sjason@lowepower.comsystem.physmem.perBankRdBursts::11 53 # Per bank write bursts 5711731Sjason@lowepower.comsystem.physmem.perBankRdBursts::12 133 # Per bank write bursts 5811731Sjason@lowepower.comsystem.physmem.perBankRdBursts::13 64 # Per bank write bursts 5911731Sjason@lowepower.comsystem.physmem.perBankRdBursts::14 104 # Per bank write bursts 6011731Sjason@lowepower.comsystem.physmem.perBankRdBursts::15 7 # Per bank write bursts 6111731Sjason@lowepower.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 6211731Sjason@lowepower.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 6311731Sjason@lowepower.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 6411731Sjason@lowepower.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 6511731Sjason@lowepower.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 6611731Sjason@lowepower.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 6711731Sjason@lowepower.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 6811731Sjason@lowepower.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 6911731Sjason@lowepower.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 7011731Sjason@lowepower.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 7111731Sjason@lowepower.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 7211731Sjason@lowepower.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 7311731Sjason@lowepower.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 7411731Sjason@lowepower.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 7511731Sjason@lowepower.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 7611731Sjason@lowepower.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 7711731Sjason@lowepower.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 7811731Sjason@lowepower.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911731Sjason@lowepower.comsystem.physmem.totGap 66707000 # Total gap between requests 8011731Sjason@lowepower.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8111731Sjason@lowepower.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8211731Sjason@lowepower.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 8311731Sjason@lowepower.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 8411731Sjason@lowepower.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 8511731Sjason@lowepower.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611731Sjason@lowepower.comsystem.physmem.readPktSize::6 1039 # Read request sizes (log2) 8711731Sjason@lowepower.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 8811731Sjason@lowepower.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 8911731Sjason@lowepower.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9011731Sjason@lowepower.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9111731Sjason@lowepower.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9211731Sjason@lowepower.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 9311731Sjason@lowepower.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::0 580 # What read queue length does an incoming req see 9511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::1 293 # What read queue length does an incoming req see 9611731Sjason@lowepower.comsystem.physmem.rdQLenPdf::2 111 # What read queue length does an incoming req see 9711731Sjason@lowepower.comsystem.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see 9811731Sjason@lowepower.comsystem.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 9911731Sjason@lowepower.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10011731Sjason@lowepower.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10111731Sjason@lowepower.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10211731Sjason@lowepower.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 10311731Sjason@lowepower.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 10411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 10511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 10611731Sjason@lowepower.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 10711731Sjason@lowepower.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 10811731Sjason@lowepower.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 10911731Sjason@lowepower.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11011731Sjason@lowepower.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11111731Sjason@lowepower.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11211731Sjason@lowepower.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 11311731Sjason@lowepower.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 11411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 11511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 11611731Sjason@lowepower.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 11711731Sjason@lowepower.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 11811731Sjason@lowepower.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 11911731Sjason@lowepower.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12011731Sjason@lowepower.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12111731Sjason@lowepower.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12211731Sjason@lowepower.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 12311731Sjason@lowepower.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 12411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 12511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 12611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 12711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 12811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 12911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 13011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 13111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 13211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 13311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 13411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 13511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 13611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 13711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 13811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 13911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 14011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 14111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 14211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 14311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 14411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 14511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 14611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 14711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 14811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 14911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 15011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 15111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 15211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 15311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 15411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 15511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 15611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 15711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011731Sjason@lowepower.comsystem.physmem.bytesPerActivate::samples 205 # Bytes accessed per row activation 19111731Sjason@lowepower.comsystem.physmem.bytesPerActivate::mean 313.131707 # Bytes accessed per row activation 19211731Sjason@lowepower.comsystem.physmem.bytesPerActivate::gmean 191.178317 # Bytes accessed per row activation 19311731Sjason@lowepower.comsystem.physmem.bytesPerActivate::stdev 319.046077 # Bytes accessed per row activation 19411731Sjason@lowepower.comsystem.physmem.bytesPerActivate::0-127 71 34.63% 34.63% # Bytes accessed per row activation 19511731Sjason@lowepower.comsystem.physmem.bytesPerActivate::128-255 47 22.93% 57.56% # Bytes accessed per row activation 19611731Sjason@lowepower.comsystem.physmem.bytesPerActivate::256-383 29 14.15% 71.71% # Bytes accessed per row activation 19711731Sjason@lowepower.comsystem.physmem.bytesPerActivate::384-511 11 5.37% 77.07% # Bytes accessed per row activation 19811731Sjason@lowepower.comsystem.physmem.bytesPerActivate::512-639 11 5.37% 82.44% # Bytes accessed per row activation 19911731Sjason@lowepower.comsystem.physmem.bytesPerActivate::640-767 6 2.93% 85.37% # Bytes accessed per row activation 20011731Sjason@lowepower.comsystem.physmem.bytesPerActivate::768-895 3 1.46% 86.83% # Bytes accessed per row activation 20111731Sjason@lowepower.comsystem.physmem.bytesPerActivate::896-1023 5 2.44% 89.27% # Bytes accessed per row activation 20211731Sjason@lowepower.comsystem.physmem.bytesPerActivate::1024-1151 22 10.73% 100.00% # Bytes accessed per row activation 20311731Sjason@lowepower.comsystem.physmem.bytesPerActivate::total 205 # Bytes accessed per row activation 20411731Sjason@lowepower.comsystem.physmem.totQLat 13576000 # Total ticks spent queuing 20511731Sjason@lowepower.comsystem.physmem.totMemAccLat 33057250 # Total ticks spent from burst creation until serviced by the DRAM 20611731Sjason@lowepower.comsystem.physmem.totBusLat 5195000 # Total ticks spent in databus transfers 20711731Sjason@lowepower.comsystem.physmem.avgQLat 13066.41 # Average queueing delay per DRAM burst 20811731Sjason@lowepower.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20911731Sjason@lowepower.comsystem.physmem.avgMemAccLat 31816.41 # Average memory access latency per DRAM burst 21011731Sjason@lowepower.comsystem.physmem.avgRdBW 996.55 # Average DRAM read bandwidth in MiByte/s 21111731Sjason@lowepower.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21211731Sjason@lowepower.comsystem.physmem.avgRdBWSys 996.55 # Average system read bandwidth in MiByte/s 21311731Sjason@lowepower.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 21411731Sjason@lowepower.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21511731Sjason@lowepower.comsystem.physmem.busUtil 7.79 # Data bus utilization in percentage 21611731Sjason@lowepower.comsystem.physmem.busUtilRead 7.79 # Data bus utilization in percentage for reads 21711731Sjason@lowepower.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21811731Sjason@lowepower.comsystem.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing 21911731Sjason@lowepower.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22011731Sjason@lowepower.comsystem.physmem.readRowHits 821 # Number of row buffer hits during reads 22111731Sjason@lowepower.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22211731Sjason@lowepower.comsystem.physmem.readRowHitRate 79.02 # Row buffer hit rate for reads 22311731Sjason@lowepower.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22411731Sjason@lowepower.comsystem.physmem.avgGap 64203.08 # Average gap between requests 22511731Sjason@lowepower.comsystem.physmem.pageHitRate 79.02 # Row buffer hit rate, read and write combined 22611731Sjason@lowepower.comsystem.physmem_0.actEnergy 835380 # Energy for activate commands per rank (pJ) 22711731Sjason@lowepower.comsystem.physmem_0.preEnergy 413655 # Energy for precharge commands per rank (pJ) 22811731Sjason@lowepower.comsystem.physmem_0.readEnergy 3334380 # Energy for read commands per rank (pJ) 22911731Sjason@lowepower.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 23011731Sjason@lowepower.comsystem.physmem_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) 23111731Sjason@lowepower.comsystem.physmem_0.actBackEnergy 6568110 # Energy for active background per rank (pJ) 23211731Sjason@lowepower.comsystem.physmem_0.preBackEnergy 113280 # Energy for precharge background per rank (pJ) 23311731Sjason@lowepower.comsystem.physmem_0.actPowerDownEnergy 22288140 # Energy for active power-down per rank (pJ) 23411731Sjason@lowepower.comsystem.physmem_0.prePowerDownEnergy 1209600 # Energy for precharge power-down per rank (pJ) 23511731Sjason@lowepower.comsystem.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 23611731Sjason@lowepower.comsystem.physmem_0.totalEnergy 39679665 # Total energy per rank (pJ) 23711731Sjason@lowepower.comsystem.physmem_0.averagePower 594.663495 # Core power per rank (mW) 23811731Sjason@lowepower.comsystem.physmem_0.totalIdleTime 51714500 # Total Idle time Per DRAM Rank 23911731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::IDLE 59500 # Time in different power states 24011731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::REF 2080000 # Time in different power states 24111731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::SREF 0 # Time in different power states 24211731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::PRE_PDN 3148750 # Time in different power states 24311731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::ACT 12569500 # Time in different power states 24411731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::ACT_PDN 48868250 # Time in different power states 24511731Sjason@lowepower.comsystem.physmem_1.actEnergy 721140 # Energy for activate commands per rank (pJ) 24611731Sjason@lowepower.comsystem.physmem_1.preEnergy 364320 # Energy for precharge commands per rank (pJ) 24711731Sjason@lowepower.comsystem.physmem_1.readEnergy 4084080 # Energy for read commands per rank (pJ) 24811731Sjason@lowepower.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24911731Sjason@lowepower.comsystem.physmem_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) 25011731Sjason@lowepower.comsystem.physmem_1.actBackEnergy 6353220 # Energy for active background per rank (pJ) 25111731Sjason@lowepower.comsystem.physmem_1.preBackEnergy 143040 # Energy for precharge background per rank (pJ) 25211731Sjason@lowepower.comsystem.physmem_1.actPowerDownEnergy 20623170 # Energy for active power-down per rank (pJ) 25311731Sjason@lowepower.comsystem.physmem_1.prePowerDownEnergy 2762880 # Energy for precharge power-down per rank (pJ) 25411731Sjason@lowepower.comsystem.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 25511731Sjason@lowepower.comsystem.physmem_1.totalEnergy 39968970 # Total energy per rank (pJ) 25611731Sjason@lowepower.comsystem.physmem_1.averagePower 598.999194 # Core power per rank (mW) 25711731Sjason@lowepower.comsystem.physmem_1.totalIdleTime 52416000 # Total Idle time Per DRAM Rank 25811731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::IDLE 150500 # Time in different power states 25911731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::REF 2080000 # Time in different power states 26011731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::SREF 0 # Time in different power states 26111731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::PRE_PDN 7195250 # Time in different power states 26211731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::ACT 12079500 # Time in different power states 26311731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::ACT_PDN 45220750 # Time in different power states 26411731Sjason@lowepower.comsystem.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states 26511731Sjason@lowepower.comsystem.cpu.branchPred.lookups 39966 # Number of BP lookups 26611731Sjason@lowepower.comsystem.cpu.branchPred.condPredicted 24999 # Number of conditional branches predicted 26711731Sjason@lowepower.comsystem.cpu.branchPred.condIncorrect 2671 # Number of conditional branches incorrect 26811731Sjason@lowepower.comsystem.cpu.branchPred.BTBLookups 33955 # Number of BTB lookups 26911731Sjason@lowepower.comsystem.cpu.branchPred.BTBHits 19441 # Number of BTB hits 27011731Sjason@lowepower.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 27111731Sjason@lowepower.comsystem.cpu.branchPred.BTBHitPct 57.255191 # BTB Hit Percentage 27211731Sjason@lowepower.comsystem.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 27311731Sjason@lowepower.comsystem.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 27411731Sjason@lowepower.comsystem.cpu.branchPred.indirectLookups 7662 # Number of indirect predictor lookups. 27511731Sjason@lowepower.comsystem.cpu.branchPred.indirectHits 3924 # Number of indirect target hits. 27611731Sjason@lowepower.comsystem.cpu.branchPred.indirectMisses 3738 # Number of indirect misses. 27711731Sjason@lowepower.comsystem.cpu.branchPredindirectMispredicted 1190 # Number of mispredicted indirect branches. 27811731Sjason@lowepower.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 27911731Sjason@lowepower.comsystem.cpu.dtb.read_hits 0 # DTB read hits 28011731Sjason@lowepower.comsystem.cpu.dtb.read_misses 0 # DTB read misses 28111731Sjason@lowepower.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 28211731Sjason@lowepower.comsystem.cpu.dtb.write_hits 0 # DTB write hits 28311731Sjason@lowepower.comsystem.cpu.dtb.write_misses 0 # DTB write misses 28411731Sjason@lowepower.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 28511731Sjason@lowepower.comsystem.cpu.dtb.hits 0 # DTB hits 28611731Sjason@lowepower.comsystem.cpu.dtb.misses 0 # DTB misses 28711731Sjason@lowepower.comsystem.cpu.dtb.accesses 0 # DTB accesses 28811731Sjason@lowepower.comsystem.cpu.itb.read_hits 0 # DTB read hits 28911731Sjason@lowepower.comsystem.cpu.itb.read_misses 0 # DTB read misses 29011731Sjason@lowepower.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 29111731Sjason@lowepower.comsystem.cpu.itb.write_hits 0 # DTB write hits 29211731Sjason@lowepower.comsystem.cpu.itb.write_misses 0 # DTB write misses 29311731Sjason@lowepower.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 29411731Sjason@lowepower.comsystem.cpu.itb.hits 0 # DTB hits 29511731Sjason@lowepower.comsystem.cpu.itb.misses 0 # DTB misses 29611731Sjason@lowepower.comsystem.cpu.itb.accesses 0 # DTB accesses 29711731Sjason@lowepower.comsystem.cpu.workload.num_syscalls 45 # Number of system calls 29811731Sjason@lowepower.comsystem.cpu.pwrStateResidencyTicks::ON 66726000 # Cumulative time (in ticks) in various power states 29911731Sjason@lowepower.comsystem.cpu.numCycles 133453 # number of cpu cycles simulated 30011731Sjason@lowepower.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 30111731Sjason@lowepower.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 30211731Sjason@lowepower.comsystem.cpu.fetch.icacheStallCycles 32838 # Number of cycles fetch is stalled on an Icache miss 30311731Sjason@lowepower.comsystem.cpu.fetch.Insts 168786 # Number of instructions fetch has processed 30411731Sjason@lowepower.comsystem.cpu.fetch.Branches 39966 # Number of branches that fetch encountered 30511731Sjason@lowepower.comsystem.cpu.fetch.predictedBranches 23365 # Number of branches that fetch has predicted taken 30611731Sjason@lowepower.comsystem.cpu.fetch.Cycles 44071 # Number of cycles fetch has run and was not squashing or blocked 30711731Sjason@lowepower.comsystem.cpu.fetch.SquashCycles 5482 # Number of cycles fetch has spent squashing 30811731Sjason@lowepower.comsystem.cpu.fetch.MiscStallCycles 503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 30911731Sjason@lowepower.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 181 # Number of stall cycles due to full MSHR 31011731Sjason@lowepower.comsystem.cpu.fetch.CacheLines 22322 # Number of cache lines fetched 31111731Sjason@lowepower.comsystem.cpu.fetch.IcacheSquashes 1285 # Number of outstanding Icache misses that were squashed 31211731Sjason@lowepower.comsystem.cpu.fetch.rateDist::samples 80334 # Number of instructions fetched each cycle (Total) 31311731Sjason@lowepower.comsystem.cpu.fetch.rateDist::mean 2.101053 # Number of instructions fetched each cycle (Total) 31411731Sjason@lowepower.comsystem.cpu.fetch.rateDist::stdev 2.833149 # Number of instructions fetched each cycle (Total) 31511731Sjason@lowepower.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 31611731Sjason@lowepower.comsystem.cpu.fetch.rateDist::0 43916 54.67% 54.67% # Number of instructions fetched each cycle (Total) 31711731Sjason@lowepower.comsystem.cpu.fetch.rateDist::1 3396 4.23% 58.89% # Number of instructions fetched each cycle (Total) 31811731Sjason@lowepower.comsystem.cpu.fetch.rateDist::2 6102 7.60% 66.49% # Number of instructions fetched each cycle (Total) 31911731Sjason@lowepower.comsystem.cpu.fetch.rateDist::3 5424 6.75% 73.24% # Number of instructions fetched each cycle (Total) 32011731Sjason@lowepower.comsystem.cpu.fetch.rateDist::4 2470 3.07% 76.32% # Number of instructions fetched each cycle (Total) 32111731Sjason@lowepower.comsystem.cpu.fetch.rateDist::5 6562 8.17% 84.48% # Number of instructions fetched each cycle (Total) 32211731Sjason@lowepower.comsystem.cpu.fetch.rateDist::6 1937 2.41% 86.90% # Number of instructions fetched each cycle (Total) 32311731Sjason@lowepower.comsystem.cpu.fetch.rateDist::7 1614 2.01% 88.91% # Number of instructions fetched each cycle (Total) 32411731Sjason@lowepower.comsystem.cpu.fetch.rateDist::8 8913 11.09% 100.00% # Number of instructions fetched each cycle (Total) 32511731Sjason@lowepower.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 32611731Sjason@lowepower.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 32711731Sjason@lowepower.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 32811731Sjason@lowepower.comsystem.cpu.fetch.rateDist::total 80334 # Number of instructions fetched each cycle (Total) 32911731Sjason@lowepower.comsystem.cpu.fetch.branchRate 0.299476 # Number of branch fetches per cycle 33011731Sjason@lowepower.comsystem.cpu.fetch.rate 1.264760 # Number of inst fetches per cycle 33111731Sjason@lowepower.comsystem.cpu.decode.IdleCycles 33037 # Number of cycles decode is idle 33211731Sjason@lowepower.comsystem.cpu.decode.BlockedCycles 11879 # Number of cycles decode is blocked 33311731Sjason@lowepower.comsystem.cpu.decode.RunCycles 32363 # Number of cycles decode is running 33411731Sjason@lowepower.comsystem.cpu.decode.UnblockCycles 923 # Number of cycles decode is unblocking 33511731Sjason@lowepower.comsystem.cpu.decode.SquashCycles 2132 # Number of cycles decode is squashing 33611731Sjason@lowepower.comsystem.cpu.decode.BranchResolved 6308 # Number of times decode resolved a branch 33711731Sjason@lowepower.comsystem.cpu.decode.BranchMispred 640 # Number of times decode detected a branch misprediction 33811731Sjason@lowepower.comsystem.cpu.decode.DecodedInsts 154953 # Number of instructions handled by decode 33911731Sjason@lowepower.comsystem.cpu.decode.SquashedInsts 1928 # Number of squashed instructions handled by decode 34011731Sjason@lowepower.comsystem.cpu.rename.SquashCycles 2132 # Number of cycles rename is squashing 34111731Sjason@lowepower.comsystem.cpu.rename.IdleCycles 34625 # Number of cycles rename is idle 34211731Sjason@lowepower.comsystem.cpu.rename.BlockCycles 3379 # Number of cycles rename is blocking 34311731Sjason@lowepower.comsystem.cpu.rename.serializeStallCycles 1413 # count of cycles rename stalled for serializing inst 34411731Sjason@lowepower.comsystem.cpu.rename.RunCycles 31599 # Number of cycles rename is running 34511731Sjason@lowepower.comsystem.cpu.rename.UnblockCycles 7186 # Number of cycles rename is unblocking 34611731Sjason@lowepower.comsystem.cpu.rename.RenamedInsts 148471 # Number of instructions processed by rename 34711731Sjason@lowepower.comsystem.cpu.rename.ROBFullEvents 97 # Number of times rename has blocked due to ROB full 34811731Sjason@lowepower.comsystem.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 34911731Sjason@lowepower.comsystem.cpu.rename.LQFullEvents 431 # Number of times rename has blocked due to LQ full 35011731Sjason@lowepower.comsystem.cpu.rename.SQFullEvents 6512 # Number of times rename has blocked due to SQ full 35111731Sjason@lowepower.comsystem.cpu.rename.RenamedOperands 101480 # Number of destination operands rename has renamed 35211731Sjason@lowepower.comsystem.cpu.rename.RenameLookups 195404 # Number of register rename lookups that rename has made 35311731Sjason@lowepower.comsystem.cpu.rename.int_rename_lookups 195404 # Number of integer rename lookups 35411731Sjason@lowepower.comsystem.cpu.rename.CommittedMaps 76188 # Number of HB maps that are committed 35511731Sjason@lowepower.comsystem.cpu.rename.UndoneMaps 25292 # Number of HB maps that are undone due to squashing 35611731Sjason@lowepower.comsystem.cpu.rename.serializingInsts 58 # count of serializing insts renamed 35711731Sjason@lowepower.comsystem.cpu.rename.tempSerializingInsts 58 # count of temporary serializing insts renamed 35811731Sjason@lowepower.comsystem.cpu.rename.skidInsts 3325 # count of insts added to the skid buffer 35911731Sjason@lowepower.comsystem.cpu.memDep0.insertedLoads 28879 # Number of loads inserted to the mem dependence unit. 36011731Sjason@lowepower.comsystem.cpu.memDep0.insertedStores 22638 # Number of stores inserted to the mem dependence unit. 36111731Sjason@lowepower.comsystem.cpu.memDep0.conflictingLoads 630 # Number of conflicting loads. 36211731Sjason@lowepower.comsystem.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. 36311731Sjason@lowepower.comsystem.cpu.iq.iqInstsAdded 137222 # Number of instructions added to the IQ (excludes non-spec) 36411731Sjason@lowepower.comsystem.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ 36511731Sjason@lowepower.comsystem.cpu.iq.iqInstsIssued 131068 # Number of instructions issued 36611731Sjason@lowepower.comsystem.cpu.iq.iqSquashedInstsIssued 381 # Number of squashed instructions issued 36711731Sjason@lowepower.comsystem.cpu.iq.iqSquashedInstsExamined 23997 # Number of squashed instructions iterated over during squash; mainly for profiling 36811731Sjason@lowepower.comsystem.cpu.iq.iqSquashedOperandsExamined 13432 # Number of squashed operands that are examined and possibly removed from graph 36911731Sjason@lowepower.comsystem.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed 37011731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::samples 80334 # Number of insts issued each cycle 37111731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::mean 1.631538 # Number of insts issued each cycle 37211731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::stdev 2.013515 # Number of insts issued each cycle 37311731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 37411731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::0 38041 47.35% 47.35% # Number of insts issued each cycle 37511731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::1 10252 12.76% 60.12% # Number of insts issued each cycle 37611731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::2 8094 10.08% 70.19% # Number of insts issued each cycle 37711731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::3 8074 10.05% 80.24% # Number of insts issued each cycle 37811731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::4 5916 7.36% 87.61% # Number of insts issued each cycle 37911731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::5 4749 5.91% 93.52% # Number of insts issued each cycle 38011731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::6 3775 4.70% 98.22% # Number of insts issued each cycle 38111731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::7 1117 1.39% 99.61% # Number of insts issued each cycle 38211731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::8 316 0.39% 100.00% # Number of insts issued each cycle 38311731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 38411731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 38511731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 38611731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::total 80334 # Number of insts issued each cycle 38711731Sjason@lowepower.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 38811731Sjason@lowepower.comsystem.cpu.iq.fu_full::IntAlu 175 6.09% 6.09% # attempts to use FU when none available 38911731Sjason@lowepower.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 6.09% # attempts to use FU when none available 39011731Sjason@lowepower.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 6.09% # attempts to use FU when none available 39111731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 6.09% # attempts to use FU when none available 39211731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 6.09% # attempts to use FU when none available 39311731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 6.09% # attempts to use FU when none available 39411731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 6.09% # attempts to use FU when none available 39511731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.09% # attempts to use FU when none available 39611731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 6.09% # attempts to use FU when none available 39711731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatMisc 0 0.00% 6.09% # attempts to use FU when none available 39811731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.09% # attempts to use FU when none available 39911731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 6.09% # attempts to use FU when none available 40011731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.09% # attempts to use FU when none available 40111731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 6.09% # attempts to use FU when none available 40211731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 6.09% # attempts to use FU when none available 40311731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 6.09% # attempts to use FU when none available 40411731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 6.09% # attempts to use FU when none available 40511731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 6.09% # attempts to use FU when none available 40611731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.09% # attempts to use FU when none available 40711731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 6.09% # attempts to use FU when none available 40811731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.09% # attempts to use FU when none available 40911731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.09% # attempts to use FU when none available 41011731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.09% # attempts to use FU when none available 41111731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.09% # attempts to use FU when none available 41211731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.09% # attempts to use FU when none available 41311731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.09% # attempts to use FU when none available 41411731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.09% # attempts to use FU when none available 41511731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.09% # attempts to use FU when none available 41611731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.09% # attempts to use FU when none available 41711731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.09% # attempts to use FU when none available 41811731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.09% # attempts to use FU when none available 41911731Sjason@lowepower.comsystem.cpu.iq.fu_full::MemRead 1363 47.43% 53.51% # attempts to use FU when none available 42011731Sjason@lowepower.comsystem.cpu.iq.fu_full::MemWrite 1336 46.49% 100.00% # attempts to use FU when none available 42111731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available 42211731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available 42311731Sjason@lowepower.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 42411731Sjason@lowepower.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 42511731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::No_OpClass 45 0.03% 0.03% # Type of FU issued 42611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::IntAlu 81693 62.33% 62.36% # Type of FU issued 42711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::IntMult 129 0.10% 62.46% # Type of FU issued 42811731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::IntDiv 30 0.02% 62.48% # Type of FU issued 42911731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued 43011731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued 43111731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.48% # Type of FU issued 43211731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.48% # Type of FU issued 43311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.48% # Type of FU issued 43411731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.48% # Type of FU issued 43511731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.48% # Type of FU issued 43611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.48% # Type of FU issued 43711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.48% # Type of FU issued 43811731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.48% # Type of FU issued 43911731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.48% # Type of FU issued 44011731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.48% # Type of FU issued 44111731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.48% # Type of FU issued 44211731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.48% # Type of FU issued 44311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.48% # Type of FU issued 44411731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.48% # Type of FU issued 44511731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.48% # Type of FU issued 44611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.48% # Type of FU issued 44711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.48% # Type of FU issued 44811731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.48% # Type of FU issued 44911731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.48% # Type of FU issued 45011731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.48% # Type of FU issued 45111731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.48% # Type of FU issued 45211731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.48% # Type of FU issued 45311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.48% # Type of FU issued 45411731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued 45511731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued 45611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued 45711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::MemRead 27948 21.32% 83.81% # Type of FU issued 45811731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::MemWrite 21223 16.19% 100.00% # Type of FU issued 45911731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued 46011731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued 46111731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 46211731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 46311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::total 131068 # Type of FU issued 46411731Sjason@lowepower.comsystem.cpu.iq.rate 0.982129 # Inst issue rate 46511731Sjason@lowepower.comsystem.cpu.iq.fu_busy_cnt 2874 # FU busy when requested 46611731Sjason@lowepower.comsystem.cpu.iq.fu_busy_rate 0.021928 # FU busy rate (busy events/executed inst) 46711731Sjason@lowepower.comsystem.cpu.iq.int_inst_queue_reads 345725 # Number of integer instruction queue reads 46811731Sjason@lowepower.comsystem.cpu.iq.int_inst_queue_writes 161326 # Number of integer instruction queue writes 46911731Sjason@lowepower.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 125053 # Number of integer instruction queue wakeup accesses 47011731Sjason@lowepower.comsystem.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 47111731Sjason@lowepower.comsystem.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 47211731Sjason@lowepower.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 47311731Sjason@lowepower.comsystem.cpu.iq.int_alu_accesses 133897 # Number of integer alu accesses 47411731Sjason@lowepower.comsystem.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 47511731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.forwLoads 2531 # Number of loads that had data forwarded from stores 47611731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 47711731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.squashedLoads 5099 # Number of loads squashed 47811731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 47911731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations 48011731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.squashedStores 2926 # Number of stores squashed 48111731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 48211731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 48311731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled 48411731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.cacheBlocked 101 # Number of times an access to memory failed due to the cache being blocked 48511731Sjason@lowepower.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 48611731Sjason@lowepower.comsystem.cpu.iew.iewSquashCycles 2132 # Number of cycles IEW is squashing 48711731Sjason@lowepower.comsystem.cpu.iew.iewBlockCycles 2287 # Number of cycles IEW is blocking 48811731Sjason@lowepower.comsystem.cpu.iew.iewUnblockCycles 246 # Number of cycles IEW is unblocking 48911731Sjason@lowepower.comsystem.cpu.iew.iewDispatchedInsts 137289 # Number of instructions dispatched to IQ 49011731Sjason@lowepower.comsystem.cpu.iew.iewDispSquashedInsts 950 # Number of squashed instructions skipped by dispatch 49111731Sjason@lowepower.comsystem.cpu.iew.iewDispLoadInsts 28879 # Number of dispatched load instructions 49211731Sjason@lowepower.comsystem.cpu.iew.iewDispStoreInsts 22638 # Number of dispatched store instructions 49311731Sjason@lowepower.comsystem.cpu.iew.iewDispNonSpecInsts 67 # Number of dispatched non-speculative instructions 49411731Sjason@lowepower.comsystem.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 49511731Sjason@lowepower.comsystem.cpu.iew.iewLSQFullEvents 254 # Number of times the LSQ has become full, causing a stall 49611731Sjason@lowepower.comsystem.cpu.iew.memOrderViolationEvents 35 # Number of memory order violations 49711731Sjason@lowepower.comsystem.cpu.iew.predictedTakenIncorrect 498 # Number of branches that were predicted taken incorrectly 49811731Sjason@lowepower.comsystem.cpu.iew.predictedNotTakenIncorrect 1893 # Number of branches that were predicted not taken incorrectly 49911731Sjason@lowepower.comsystem.cpu.iew.branchMispredicts 2391 # Number of branch mispredicts detected at execute 50011731Sjason@lowepower.comsystem.cpu.iew.iewExecutedInsts 126811 # Number of executed instructions 50111731Sjason@lowepower.comsystem.cpu.iew.iewExecLoadInsts 27146 # Number of load instructions executed 50211731Sjason@lowepower.comsystem.cpu.iew.iewExecSquashedInsts 4257 # Number of squashed instructions skipped in execute 50311731Sjason@lowepower.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 50411731Sjason@lowepower.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 50511731Sjason@lowepower.comsystem.cpu.iew.exec_refs 47872 # number of memory reference insts executed 50611731Sjason@lowepower.comsystem.cpu.iew.exec_branches 29089 # Number of branches executed 50711731Sjason@lowepower.comsystem.cpu.iew.exec_stores 20726 # Number of stores executed 50811731Sjason@lowepower.comsystem.cpu.iew.exec_rate 0.950230 # Inst execution rate 50911731Sjason@lowepower.comsystem.cpu.iew.wb_sent 125714 # cumulative count of insts sent to commit 51011731Sjason@lowepower.comsystem.cpu.iew.wb_count 125053 # cumulative count of insts written-back 51111731Sjason@lowepower.comsystem.cpu.iew.wb_producers 49299 # num instructions producing a value 51211731Sjason@lowepower.comsystem.cpu.iew.wb_consumers 72928 # num instructions consuming a value 51311731Sjason@lowepower.comsystem.cpu.iew.wb_rate 0.937056 # insts written-back per cycle 51411731Sjason@lowepower.comsystem.cpu.iew.wb_fanout 0.675996 # average fanout of values written-back 51511731Sjason@lowepower.comsystem.cpu.commit.commitSquashedInsts 24018 # The number of squashed insts skipped by commit 51611731Sjason@lowepower.comsystem.cpu.commit.commitNonSpecStalls 45 # The number of times commit has been forced to stall to communicate backwards 51711731Sjason@lowepower.comsystem.cpu.commit.branchMispredicts 2062 # The number of times a branch was mispredicted 51811731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::samples 75915 # Number of insts commited each cycle 51911731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::mean 1.492340 # Number of insts commited each cycle 52011731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::stdev 2.298348 # Number of insts commited each cycle 52111731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 52211731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::0 42174 55.55% 55.55% # Number of insts commited each cycle 52311731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::1 10802 14.23% 69.78% # Number of insts commited each cycle 52411731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::2 5429 7.15% 76.93% # Number of insts commited each cycle 52511731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::3 4052 5.34% 82.27% # Number of insts commited each cycle 52611731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::4 3273 4.31% 86.58% # Number of insts commited each cycle 52711731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::5 3050 4.02% 90.60% # Number of insts commited each cycle 52811731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::6 2519 3.32% 93.92% # Number of insts commited each cycle 52911731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::7 909 1.20% 95.12% # Number of insts commited each cycle 53011731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::8 3707 4.88% 100.00% # Number of insts commited each cycle 53111731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 53211731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 53311731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 53411731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::total 75915 # Number of insts commited each cycle 53511731Sjason@lowepower.comsystem.cpu.commit.committedInsts 113291 # Number of instructions committed 53611731Sjason@lowepower.comsystem.cpu.commit.committedOps 113291 # Number of ops (including micro ops) committed 53711731Sjason@lowepower.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 53811731Sjason@lowepower.comsystem.cpu.commit.refs 43492 # Number of memory references committed 53911731Sjason@lowepower.comsystem.cpu.commit.loads 23780 # Number of loads committed 54011731Sjason@lowepower.comsystem.cpu.commit.membars 0 # Number of memory barriers committed 54111731Sjason@lowepower.comsystem.cpu.commit.branches 25920 # Number of branches committed 54211731Sjason@lowepower.comsystem.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 54311731Sjason@lowepower.comsystem.cpu.commit.int_insts 113291 # Number of committed integer instructions. 54411731Sjason@lowepower.comsystem.cpu.commit.function_calls 8529 # Number of function calls committed. 54511731Sjason@lowepower.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 54611731Sjason@lowepower.comsystem.cpu.commit.op_class_0::IntAlu 69651 61.48% 61.48% # Class of committed instruction 54711731Sjason@lowepower.comsystem.cpu.commit.op_class_0::IntMult 122 0.11% 61.59% # Class of committed instruction 54811731Sjason@lowepower.comsystem.cpu.commit.op_class_0::IntDiv 26 0.02% 61.61% # Class of committed instruction 54911731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.61% # Class of committed instruction 55011731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.61% # Class of committed instruction 55111731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.61% # Class of committed instruction 55211731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 61.61% # Class of committed instruction 55311731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 61.61% # Class of committed instruction 55411731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.61% # Class of committed instruction 55511731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatMisc 0 0.00% 61.61% # Class of committed instruction 55611731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.61% # Class of committed instruction 55711731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.61% # Class of committed instruction 55811731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.61% # Class of committed instruction 55911731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.61% # Class of committed instruction 56011731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.61% # Class of committed instruction 56111731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.61% # Class of committed instruction 56211731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.61% # Class of committed instruction 56311731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 61.61% # Class of committed instruction 56411731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.61% # Class of committed instruction 56511731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 61.61% # Class of committed instruction 56611731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.61% # Class of committed instruction 56711731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.61% # Class of committed instruction 56811731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.61% # Class of committed instruction 56911731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.61% # Class of committed instruction 57011731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.61% # Class of committed instruction 57111731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.61% # Class of committed instruction 57211731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.61% # Class of committed instruction 57311731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 61.61% # Class of committed instruction 57411731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.61% # Class of committed instruction 57511731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.61% # Class of committed instruction 57611731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.61% # Class of committed instruction 57711731Sjason@lowepower.comsystem.cpu.commit.op_class_0::MemRead 23780 20.99% 82.60% # Class of committed instruction 57811731Sjason@lowepower.comsystem.cpu.commit.op_class_0::MemWrite 19712 17.40% 100.00% # Class of committed instruction 57911731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 58011731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction 58111731Sjason@lowepower.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 58211731Sjason@lowepower.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 58311731Sjason@lowepower.comsystem.cpu.commit.op_class_0::total 113291 # Class of committed instruction 58411731Sjason@lowepower.comsystem.cpu.commit.bw_lim_events 3707 # number cycles where commit BW limit reached 58511731Sjason@lowepower.comsystem.cpu.rob.rob_reads 208932 # The number of ROB reads 58611731Sjason@lowepower.comsystem.cpu.rob.rob_writes 279096 # The number of ROB writes 58711731Sjason@lowepower.comsystem.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself 58811731Sjason@lowepower.comsystem.cpu.idleCycles 53119 # Total number of cycles that the CPU has spent unscheduled due to idling 58911731Sjason@lowepower.comsystem.cpu.committedInsts 113291 # Number of Instructions Simulated 59011731Sjason@lowepower.comsystem.cpu.committedOps 113291 # Number of Ops (including micro ops) Simulated 59111731Sjason@lowepower.comsystem.cpu.cpi 1.177966 # CPI: Cycles Per Instruction 59211731Sjason@lowepower.comsystem.cpu.cpi_total 1.177966 # CPI: Total CPI of All Threads 59311731Sjason@lowepower.comsystem.cpu.ipc 0.848921 # IPC: Instructions Per Cycle 59411731Sjason@lowepower.comsystem.cpu.ipc_total 0.848921 # IPC: Total IPC of All Threads 59511731Sjason@lowepower.comsystem.cpu.int_regfile_reads 166154 # number of integer regfile reads 59611731Sjason@lowepower.comsystem.cpu.int_regfile_writes 85972 # number of integer regfile writes 59711731Sjason@lowepower.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states 59811731Sjason@lowepower.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 59911731Sjason@lowepower.comsystem.cpu.dcache.tags.tagsinuse 217.973737 # Cycle average of tags in use 60011731Sjason@lowepower.comsystem.cpu.dcache.tags.total_refs 42393 # Total number of references to valid blocks. 60111731Sjason@lowepower.comsystem.cpu.dcache.tags.sampled_refs 265 # Sample count of references to valid blocks. 60211731Sjason@lowepower.comsystem.cpu.dcache.tags.avg_refs 159.973585 # Average number of references to valid blocks. 60311731Sjason@lowepower.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 60411731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 217.973737 # Average occupied blocks per requestor 60511731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.053216 # Average percentage of cache occupancy 60611731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_percent::total 0.053216 # Average percentage of cache occupancy 60711731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 265 # Occupied blocks per task id 60811731Sjason@lowepower.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 60911731Sjason@lowepower.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 61011731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.064697 # Percentage of cache occupancy per task id 61111731Sjason@lowepower.comsystem.cpu.dcache.tags.tag_accesses 88473 # Number of tag accesses 61211731Sjason@lowepower.comsystem.cpu.dcache.tags.data_accesses 88473 # Number of data accesses 61311731Sjason@lowepower.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states 61411731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_hits::cpu.data 24147 # number of ReadReq hits 61511731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_hits::total 24147 # number of ReadReq hits 61611731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_hits::cpu.data 18246 # number of WriteReq hits 61711731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_hits::total 18246 # number of WriteReq hits 61811731Sjason@lowepower.comsystem.cpu.dcache.demand_hits::cpu.data 42393 # number of demand (read+write) hits 61911731Sjason@lowepower.comsystem.cpu.dcache.demand_hits::total 42393 # number of demand (read+write) hits 62011731Sjason@lowepower.comsystem.cpu.dcache.overall_hits::cpu.data 42393 # number of overall hits 62111731Sjason@lowepower.comsystem.cpu.dcache.overall_hits::total 42393 # number of overall hits 62211731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_misses::cpu.data 245 # number of ReadReq misses 62311731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_misses::total 245 # number of ReadReq misses 62411731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1466 # number of WriteReq misses 62511731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_misses::total 1466 # number of WriteReq misses 62611731Sjason@lowepower.comsystem.cpu.dcache.demand_misses::cpu.data 1711 # number of demand (read+write) misses 62711731Sjason@lowepower.comsystem.cpu.dcache.demand_misses::total 1711 # number of demand (read+write) misses 62811731Sjason@lowepower.comsystem.cpu.dcache.overall_misses::cpu.data 1711 # number of overall misses 62911731Sjason@lowepower.comsystem.cpu.dcache.overall_misses::total 1711 # number of overall misses 63011731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 20376500 # number of ReadReq miss cycles 63111731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_latency::total 20376500 # number of ReadReq miss cycles 63211731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 95969940 # number of WriteReq miss cycles 63311731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_latency::total 95969940 # number of WriteReq miss cycles 63411731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_latency::cpu.data 116346440 # number of demand (read+write) miss cycles 63511731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_latency::total 116346440 # number of demand (read+write) miss cycles 63611731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_latency::cpu.data 116346440 # number of overall miss cycles 63711731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_latency::total 116346440 # number of overall miss cycles 63811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 24392 # number of ReadReq accesses(hits+misses) 63911731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_accesses::total 24392 # number of ReadReq accesses(hits+misses) 64011731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses) 64111731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses) 64211731Sjason@lowepower.comsystem.cpu.dcache.demand_accesses::cpu.data 44104 # number of demand (read+write) accesses 64311731Sjason@lowepower.comsystem.cpu.dcache.demand_accesses::total 44104 # number of demand (read+write) accesses 64411731Sjason@lowepower.comsystem.cpu.dcache.overall_accesses::cpu.data 44104 # number of overall (read+write) accesses 64511731Sjason@lowepower.comsystem.cpu.dcache.overall_accesses::total 44104 # number of overall (read+write) accesses 64611731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010044 # miss rate for ReadReq accesses 64711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.010044 # miss rate for ReadReq accesses 64811731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.074371 # miss rate for WriteReq accesses 64911731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.074371 # miss rate for WriteReq accesses 65011731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.038795 # miss rate for demand accesses 65111731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_rate::total 0.038795 # miss rate for demand accesses 65211731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.038795 # miss rate for overall accesses 65311731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_rate::total 0.038795 # miss rate for overall accesses 65411731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83169.387755 # average ReadReq miss latency 65511731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 83169.387755 # average ReadReq miss latency 65611731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65463.806276 # average WriteReq miss latency 65711731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 65463.806276 # average WriteReq miss latency 65811731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 67999.088252 # average overall miss latency 65911731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_miss_latency::total 67999.088252 # average overall miss latency 66011731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 67999.088252 # average overall miss latency 66111731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_miss_latency::total 67999.088252 # average overall miss latency 66211731Sjason@lowepower.comsystem.cpu.dcache.blocked_cycles::no_mshrs 5526 # number of cycles access was blocked 66311731Sjason@lowepower.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 66411731Sjason@lowepower.comsystem.cpu.dcache.blocked::no_mshrs 63 # number of cycles access was blocked 66511731Sjason@lowepower.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 66611731Sjason@lowepower.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 87.714286 # average number of cycles each access was blocked 66711731Sjason@lowepower.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 66811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 175 # number of ReadReq MSHR hits 66911731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits 67011731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1269 # number of WriteReq MSHR hits 67111731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1269 # number of WriteReq MSHR hits 67211731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 1444 # number of demand (read+write) MSHR hits 67311731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_hits::total 1444 # number of demand (read+write) MSHR hits 67411731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 1444 # number of overall MSHR hits 67511731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_hits::total 1444 # number of overall MSHR hits 67611731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses 67711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses 67811731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 197 # number of WriteReq MSHR misses 67911731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_misses::total 197 # number of WriteReq MSHR misses 68011731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses 68111731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses 68211731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses 68311731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses 68411731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6394500 # number of ReadReq MSHR miss cycles 68511731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 6394500 # number of ReadReq MSHR miss cycles 68611731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15710500 # number of WriteReq MSHR miss cycles 68711731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 15710500 # number of WriteReq MSHR miss cycles 68811731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 22105000 # number of demand (read+write) MSHR miss cycles 68911731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_latency::total 22105000 # number of demand (read+write) MSHR miss cycles 69011731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 22105000 # number of overall MSHR miss cycles 69111731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_latency::total 22105000 # number of overall MSHR miss cycles 69211731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002870 # mshr miss rate for ReadReq accesses 69311731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002870 # mshr miss rate for ReadReq accesses 69411731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009994 # mshr miss rate for WriteReq accesses 69511731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009994 # mshr miss rate for WriteReq accesses 69611731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006054 # mshr miss rate for demand accesses 69711731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.006054 # mshr miss rate for demand accesses 69811731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006054 # mshr miss rate for overall accesses 69911731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.006054 # mshr miss rate for overall accesses 70011731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91350 # average ReadReq mshr miss latency 70111731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91350 # average ReadReq mshr miss latency 70211731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79748.730964 # average WriteReq mshr miss latency 70311731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79748.730964 # average WriteReq mshr miss latency 70411731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82790.262172 # average overall mshr miss latency 70511731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 82790.262172 # average overall mshr miss latency 70611731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82790.262172 # average overall mshr miss latency 70711731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 82790.262172 # average overall mshr miss latency 70811731Sjason@lowepower.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states 70911731Sjason@lowepower.comsystem.cpu.icache.tags.replacements 16 # number of replacements 71011731Sjason@lowepower.comsystem.cpu.icache.tags.tagsinuse 390.097209 # Cycle average of tags in use 71111731Sjason@lowepower.comsystem.cpu.icache.tags.total_refs 21273 # Total number of references to valid blocks. 71211731Sjason@lowepower.comsystem.cpu.icache.tags.sampled_refs 775 # Sample count of references to valid blocks. 71311731Sjason@lowepower.comsystem.cpu.icache.tags.avg_refs 27.449032 # Average number of references to valid blocks. 71411731Sjason@lowepower.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 71511731Sjason@lowepower.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 390.097209 # Average occupied blocks per requestor 71611731Sjason@lowepower.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.190477 # Average percentage of cache occupancy 71711731Sjason@lowepower.comsystem.cpu.icache.tags.occ_percent::total 0.190477 # Average percentage of cache occupancy 71811731Sjason@lowepower.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 759 # Occupied blocks per task id 71911731Sjason@lowepower.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 72011731Sjason@lowepower.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 680 # Occupied blocks per task id 72111731Sjason@lowepower.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.370605 # Percentage of cache occupancy per task id 72211731Sjason@lowepower.comsystem.cpu.icache.tags.tag_accesses 45403 # Number of tag accesses 72311731Sjason@lowepower.comsystem.cpu.icache.tags.data_accesses 45403 # Number of data accesses 72411731Sjason@lowepower.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states 72511731Sjason@lowepower.comsystem.cpu.icache.ReadReq_hits::cpu.inst 21273 # number of ReadReq hits 72611731Sjason@lowepower.comsystem.cpu.icache.ReadReq_hits::total 21273 # number of ReadReq hits 72711731Sjason@lowepower.comsystem.cpu.icache.demand_hits::cpu.inst 21273 # number of demand (read+write) hits 72811731Sjason@lowepower.comsystem.cpu.icache.demand_hits::total 21273 # number of demand (read+write) hits 72911731Sjason@lowepower.comsystem.cpu.icache.overall_hits::cpu.inst 21273 # number of overall hits 73011731Sjason@lowepower.comsystem.cpu.icache.overall_hits::total 21273 # number of overall hits 73111731Sjason@lowepower.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1041 # number of ReadReq misses 73211731Sjason@lowepower.comsystem.cpu.icache.ReadReq_misses::total 1041 # number of ReadReq misses 73311731Sjason@lowepower.comsystem.cpu.icache.demand_misses::cpu.inst 1041 # number of demand (read+write) misses 73411731Sjason@lowepower.comsystem.cpu.icache.demand_misses::total 1041 # number of demand (read+write) misses 73511731Sjason@lowepower.comsystem.cpu.icache.overall_misses::cpu.inst 1041 # number of overall misses 73611731Sjason@lowepower.comsystem.cpu.icache.overall_misses::total 1041 # number of overall misses 73711731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 81501497 # number of ReadReq miss cycles 73811731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_latency::total 81501497 # number of ReadReq miss cycles 73911731Sjason@lowepower.comsystem.cpu.icache.demand_miss_latency::cpu.inst 81501497 # number of demand (read+write) miss cycles 74011731Sjason@lowepower.comsystem.cpu.icache.demand_miss_latency::total 81501497 # number of demand (read+write) miss cycles 74111731Sjason@lowepower.comsystem.cpu.icache.overall_miss_latency::cpu.inst 81501497 # number of overall miss cycles 74211731Sjason@lowepower.comsystem.cpu.icache.overall_miss_latency::total 81501497 # number of overall miss cycles 74311731Sjason@lowepower.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 22314 # number of ReadReq accesses(hits+misses) 74411731Sjason@lowepower.comsystem.cpu.icache.ReadReq_accesses::total 22314 # number of ReadReq accesses(hits+misses) 74511731Sjason@lowepower.comsystem.cpu.icache.demand_accesses::cpu.inst 22314 # number of demand (read+write) accesses 74611731Sjason@lowepower.comsystem.cpu.icache.demand_accesses::total 22314 # number of demand (read+write) accesses 74711731Sjason@lowepower.comsystem.cpu.icache.overall_accesses::cpu.inst 22314 # number of overall (read+write) accesses 74811731Sjason@lowepower.comsystem.cpu.icache.overall_accesses::total 22314 # number of overall (read+write) accesses 74911731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046652 # miss rate for ReadReq accesses 75011731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_rate::total 0.046652 # miss rate for ReadReq accesses 75111731Sjason@lowepower.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.046652 # miss rate for demand accesses 75211731Sjason@lowepower.comsystem.cpu.icache.demand_miss_rate::total 0.046652 # miss rate for demand accesses 75311731Sjason@lowepower.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.046652 # miss rate for overall accesses 75411731Sjason@lowepower.comsystem.cpu.icache.overall_miss_rate::total 0.046652 # miss rate for overall accesses 75511731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78291.543708 # average ReadReq miss latency 75611731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 78291.543708 # average ReadReq miss latency 75711731Sjason@lowepower.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 78291.543708 # average overall miss latency 75811731Sjason@lowepower.comsystem.cpu.icache.demand_avg_miss_latency::total 78291.543708 # average overall miss latency 75911731Sjason@lowepower.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 78291.543708 # average overall miss latency 76011731Sjason@lowepower.comsystem.cpu.icache.overall_avg_miss_latency::total 78291.543708 # average overall miss latency 76111731Sjason@lowepower.comsystem.cpu.icache.blocked_cycles::no_mshrs 2316 # number of cycles access was blocked 76211731Sjason@lowepower.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 76311731Sjason@lowepower.comsystem.cpu.icache.blocked::no_mshrs 36 # number of cycles access was blocked 76411731Sjason@lowepower.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 76511731Sjason@lowepower.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 64.333333 # average number of cycles each access was blocked 76611731Sjason@lowepower.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 76711731Sjason@lowepower.comsystem.cpu.icache.writebacks::writebacks 16 # number of writebacks 76811731Sjason@lowepower.comsystem.cpu.icache.writebacks::total 16 # number of writebacks 76911731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 266 # number of ReadReq MSHR hits 77011731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits 77111731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 266 # number of demand (read+write) MSHR hits 77211731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_hits::total 266 # number of demand (read+write) MSHR hits 77311731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 266 # number of overall MSHR hits 77411731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_hits::total 266 # number of overall MSHR hits 77511731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses 77611731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses 77711731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses 77811731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_misses::total 775 # number of demand (read+write) MSHR misses 77911731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses 78011731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_misses::total 775 # number of overall MSHR misses 78111731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65524999 # number of ReadReq MSHR miss cycles 78211731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 65524999 # number of ReadReq MSHR miss cycles 78311731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 65524999 # number of demand (read+write) MSHR miss cycles 78411731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_latency::total 65524999 # number of demand (read+write) MSHR miss cycles 78511731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 65524999 # number of overall MSHR miss cycles 78611731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_latency::total 65524999 # number of overall MSHR miss cycles 78711731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.034732 # mshr miss rate for ReadReq accesses 78811731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.034732 # mshr miss rate for ReadReq accesses 78911731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.034732 # mshr miss rate for demand accesses 79011731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.034732 # mshr miss rate for demand accesses 79111731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.034732 # mshr miss rate for overall accesses 79211731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.034732 # mshr miss rate for overall accesses 79311731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84548.385806 # average ReadReq mshr miss latency 79411731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84548.385806 # average ReadReq mshr miss latency 79511731Sjason@lowepower.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84548.385806 # average overall mshr miss latency 79611731Sjason@lowepower.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 84548.385806 # average overall mshr miss latency 79711731Sjason@lowepower.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84548.385806 # average overall mshr miss latency 79811731Sjason@lowepower.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 84548.385806 # average overall mshr miss latency 79911731Sjason@lowepower.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states 80011731Sjason@lowepower.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 80111731Sjason@lowepower.comsystem.cpu.l2cache.tags.tagsinuse 612.345284 # Cycle average of tags in use 80211731Sjason@lowepower.comsystem.cpu.l2cache.tags.total_refs 16 # Total number of references to valid blocks. 80311731Sjason@lowepower.comsystem.cpu.l2cache.tags.sampled_refs 1038 # Sample count of references to valid blocks. 80411731Sjason@lowepower.comsystem.cpu.l2cache.tags.avg_refs 0.015414 # Average number of references to valid blocks. 80511731Sjason@lowepower.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 80611731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 394.329847 # Average occupied blocks per requestor 80711731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 218.015437 # Average occupied blocks per requestor 80811731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.012034 # Average percentage of cache occupancy 80911731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.006653 # Average percentage of cache occupancy 81011731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::total 0.018687 # Average percentage of cache occupancy 81111731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 1038 # Occupied blocks per task id 81211731Sjason@lowepower.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 81311731Sjason@lowepower.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 951 # Occupied blocks per task id 81411731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.031677 # Percentage of cache occupancy per task id 81511731Sjason@lowepower.comsystem.cpu.l2cache.tags.tag_accesses 9486 # Number of tag accesses 81611731Sjason@lowepower.comsystem.cpu.l2cache.tags.data_accesses 9486 # Number of data accesses 81711731Sjason@lowepower.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states 81811731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 16 # number of WritebackClean hits 81911731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_hits::total 16 # number of WritebackClean hits 82011731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 197 # number of ReadExReq misses 82111731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_misses::total 197 # number of ReadExReq misses 82211731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 773 # number of ReadCleanReq misses 82311731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_misses::total 773 # number of ReadCleanReq misses 82411731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 70 # number of ReadSharedReq misses 82511731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_misses::total 70 # number of ReadSharedReq misses 82611731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::cpu.inst 773 # number of demand (read+write) misses 82711731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::cpu.data 267 # number of demand (read+write) misses 82811731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::total 1040 # number of demand (read+write) misses 82911731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::cpu.inst 773 # number of overall misses 83011731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::cpu.data 267 # number of overall misses 83111731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::total 1040 # number of overall misses 83211731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15415000 # number of ReadExReq miss cycles 83311731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 15415000 # number of ReadExReq miss cycles 83411731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 64356500 # number of ReadCleanReq miss cycles 83511731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 64356500 # number of ReadCleanReq miss cycles 83611731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6291000 # number of ReadSharedReq miss cycles 83711731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 6291000 # number of ReadSharedReq miss cycles 83811731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 64356500 # number of demand (read+write) miss cycles 83911731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 21706000 # number of demand (read+write) miss cycles 84011731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::total 86062500 # number of demand (read+write) miss cycles 84111731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 64356500 # number of overall miss cycles 84211731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 21706000 # number of overall miss cycles 84311731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::total 86062500 # number of overall miss cycles 84411731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 16 # number of WritebackClean accesses(hits+misses) 84511731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_accesses::total 16 # number of WritebackClean accesses(hits+misses) 84611731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 197 # number of ReadExReq accesses(hits+misses) 84711731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_accesses::total 197 # number of ReadExReq accesses(hits+misses) 84811731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 773 # number of ReadCleanReq accesses(hits+misses) 84911731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 773 # number of ReadCleanReq accesses(hits+misses) 85011731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 70 # number of ReadSharedReq accesses(hits+misses) 85111731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 70 # number of ReadSharedReq accesses(hits+misses) 85211731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::cpu.inst 773 # number of demand (read+write) accesses 85311731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::cpu.data 267 # number of demand (read+write) accesses 85411731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::total 1040 # number of demand (read+write) accesses 85511731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::cpu.inst 773 # number of overall (read+write) accesses 85611731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::cpu.data 267 # number of overall (read+write) accesses 85711731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::total 1040 # number of overall (read+write) accesses 85811731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 85911731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 86011731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses 86111731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses 86211731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 86311731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 86411731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 86511731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 86611731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses 86711731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 86811731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 86911731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses 87011731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78248.730964 # average ReadExReq miss latency 87111731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 78248.730964 # average ReadExReq miss latency 87211731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83255.498060 # average ReadCleanReq miss latency 87311731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83255.498060 # average ReadCleanReq miss latency 87411731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89871.428571 # average ReadSharedReq miss latency 87511731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89871.428571 # average ReadSharedReq miss latency 87611731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83255.498060 # average overall miss latency 87711731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 81295.880150 # average overall miss latency 87811731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::total 82752.403846 # average overall miss latency 87911731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83255.498060 # average overall miss latency 88011731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 81295.880150 # average overall miss latency 88111731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::total 82752.403846 # average overall miss latency 88211731Sjason@lowepower.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 88311731Sjason@lowepower.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88411731Sjason@lowepower.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 88511731Sjason@lowepower.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 88611731Sjason@lowepower.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 88711731Sjason@lowepower.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 88811731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 197 # number of ReadExReq MSHR misses 88911731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 197 # number of ReadExReq MSHR misses 89011731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 773 # number of ReadCleanReq MSHR misses 89111731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 773 # number of ReadCleanReq MSHR misses 89211731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 70 # number of ReadSharedReq MSHR misses 89311731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 70 # number of ReadSharedReq MSHR misses 89411731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses 89511731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses 89611731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::total 1040 # number of demand (read+write) MSHR misses 89711731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses 89811731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses 89911731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::total 1040 # number of overall MSHR misses 90011731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13445000 # number of ReadExReq MSHR miss cycles 90111731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13445000 # number of ReadExReq MSHR miss cycles 90211731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 56626500 # number of ReadCleanReq MSHR miss cycles 90311731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 56626500 # number of ReadCleanReq MSHR miss cycles 90411731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5611000 # number of ReadSharedReq MSHR miss cycles 90511731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5611000 # number of ReadSharedReq MSHR miss cycles 90611731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 56626500 # number of demand (read+write) MSHR miss cycles 90711731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19056000 # number of demand (read+write) MSHR miss cycles 90811731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 75682500 # number of demand (read+write) MSHR miss cycles 90911731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 56626500 # number of overall MSHR miss cycles 91011731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19056000 # number of overall MSHR miss cycles 91111731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 75682500 # number of overall MSHR miss cycles 91211731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 91311731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 91411731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses 91511731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses 91611731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 91711731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 91811731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 91911731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 92011731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 92111731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 92211731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 92311731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 92411731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68248.730964 # average ReadExReq mshr miss latency 92511731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68248.730964 # average ReadExReq mshr miss latency 92611731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73255.498060 # average ReadCleanReq mshr miss latency 92711731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73255.498060 # average ReadCleanReq mshr miss latency 92811731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80157.142857 # average ReadSharedReq mshr miss latency 92911731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80157.142857 # average ReadSharedReq mshr miss latency 93011731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73255.498060 # average overall mshr miss latency 93111731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71370.786517 # average overall mshr miss latency 93211731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 72771.634615 # average overall mshr miss latency 93311731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73255.498060 # average overall mshr miss latency 93411731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71370.786517 # average overall mshr miss latency 93511731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 72771.634615 # average overall mshr miss latency 93611731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 1058 # Total number of requests made to the snoop filter. 93711731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 18 # Number of requests hitting in the snoop filter with a single holder of the requested data. 93811731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 93911731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 94011731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 94111731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 94211731Sjason@lowepower.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states 94311731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadResp 843 # Transaction distribution 94411731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 16 # Transaction distribution 94511731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 197 # Transaction distribution 94611731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 197 # Transaction distribution 94711731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 775 # Transaction distribution 94811731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 70 # Transaction distribution 94911731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes) 95011731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 532 # Packet count per connected master and slave (bytes) 95111731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count::total 2096 # Packet count per connected master and slave (bytes) 95211731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50496 # Cumulative packet size per connected master and slave (bytes) 95311731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16960 # Cumulative packet size per connected master and slave (bytes) 95411731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size::total 67456 # Cumulative packet size per connected master and slave (bytes) 95511731Sjason@lowepower.comsystem.cpu.toL2Bus.snoops 2 # Total snoops (count) 95611731Sjason@lowepower.comsystem.cpu.toL2Bus.snoopTraffic 128 # Total snoop traffic (bytes) 95711731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::samples 1042 # Request fanout histogram 95811731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.001919 # Request fanout histogram 95911731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.043790 # Request fanout histogram 96011731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 96111731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::0 1040 99.81% 99.81% # Request fanout histogram 96211731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::1 2 0.19% 100.00% # Request fanout histogram 96311731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 96411731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 96511731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 96611731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 96711731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::total 1042 # Request fanout histogram 96811731Sjason@lowepower.comsystem.cpu.toL2Bus.reqLayer0.occupancy 545000 # Layer occupancy (ticks) 96911731Sjason@lowepower.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 97011731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer0.occupancy 1162500 # Layer occupancy (ticks) 97111731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) 97211731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer1.occupancy 397500 # Layer occupancy (ticks) 97311731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) 97411731Sjason@lowepower.comsystem.membus.snoop_filter.tot_requests 1039 # Total number of requests made to the snoop filter. 97511731Sjason@lowepower.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 97611731Sjason@lowepower.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 97711731Sjason@lowepower.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 97811731Sjason@lowepower.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 97911731Sjason@lowepower.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 98011731Sjason@lowepower.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states 98111731Sjason@lowepower.comsystem.membus.trans_dist::ReadResp 841 # Transaction distribution 98211731Sjason@lowepower.comsystem.membus.trans_dist::ReadExReq 197 # Transaction distribution 98311731Sjason@lowepower.comsystem.membus.trans_dist::ReadExResp 197 # Transaction distribution 98411731Sjason@lowepower.comsystem.membus.trans_dist::ReadSharedReq 842 # Transaction distribution 98511731Sjason@lowepower.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2077 # Packet count per connected master and slave (bytes) 98611731Sjason@lowepower.comsystem.membus.pkt_count::total 2077 # Packet count per connected master and slave (bytes) 98711731Sjason@lowepower.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66432 # Cumulative packet size per connected master and slave (bytes) 98811731Sjason@lowepower.comsystem.membus.pkt_size::total 66432 # Cumulative packet size per connected master and slave (bytes) 98911731Sjason@lowepower.comsystem.membus.snoops 0 # Total snoops (count) 99011731Sjason@lowepower.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 99111731Sjason@lowepower.comsystem.membus.snoop_fanout::samples 1039 # Request fanout histogram 99211731Sjason@lowepower.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 99311731Sjason@lowepower.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 99411731Sjason@lowepower.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 99511731Sjason@lowepower.comsystem.membus.snoop_fanout::0 1039 100.00% 100.00% # Request fanout histogram 99611731Sjason@lowepower.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 99711731Sjason@lowepower.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 99811731Sjason@lowepower.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 99911731Sjason@lowepower.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 100011731Sjason@lowepower.comsystem.membus.snoop_fanout::total 1039 # Request fanout histogram 100111731Sjason@lowepower.comsystem.membus.reqLayer0.occupancy 1253500 # Layer occupancy (ticks) 100211731Sjason@lowepower.comsystem.membus.reqLayer0.utilization 1.9 # Layer utilization (%) 100311731Sjason@lowepower.comsystem.membus.respLayer1.occupancy 5477500 # Layer occupancy (ticks) 100411731Sjason@lowepower.comsystem.membus.respLayer1.utilization 8.2 # Layer utilization (%) 100511731Sjason@lowepower.com 100611731Sjason@lowepower.com---------- End Simulation Statistics ---------- 1007